Combinational

Circuit
Memory
elements
Inputs
Outputs
Block diagram of a Sequential Logic
Circuit
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
Q
Q
S (set)
R (reset)
1
0
1
0
1
2
S R Q Q
1 0 1 0
0 0 1 0
0 1 0 1
0 0 0 1
1 1 0 0
(after S=1 R=0)
(after S=0 R=1)
Basic flip-flop circuit with NOR gates
(Asnchronous Sequential Circuits!
(a) !o"ic #ia"ram
(b) $rut% $able
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
Q
Q
S (set)
R (reset)
1
2
1
0
1
0
S R Q Q
1 0 0 1
1 1 0 1
0 1 1 0
1 1 1 0
0 0 1 1
(after S=1 R=0)
(after S=0 R=1)
Basic flip-flop circuit with NAN" gates
(Asnchronous Sequential Circuits!
(a) !o"ic #ia"ram
(b) $rut% $able
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
1
1
Q
Q
1
2
(a) !o"ic &ia"ram
Q S R Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 Indeterminate
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 indeterminate
(c) C%aracteristic table
Q Q
R S
X 1
1 X 1
00 01 11 10
Q
0
1
SR
S
R
Q(t'1) = S'RQ
(b) (rap%ical Symbol
(&) C%aracteristic e)uation
Clocked RS flip-flop
SR = 0
R
C*
S
C*
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
+
,
Q
Q
1
2
-
(a) !o"ic &ia"ram .it% /0/# "ates
Q Q
#
(b) (rap%ical Symbol
Q D Q(t+1)
0 0 0
0 1 1
1 0 0
1 1 1
1
1
0
1
0 1
Q(t'1) = #
(c) C%aracteristic table
(&) C%aracteristic e)uation
Clocked D flip-flop
#
C*
R
S
C*
Q
#
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
(a) !o"ic &ia"ram
Q
Q
Clocked JK
flip-flop
Q Q
1 2
Q J K Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
1 1
1 1
00 01 11 10 Q
0
1
21
2
1
Q(t'1) = 2Q'1Q
(&) C%aracteristic e)uation
(b) (rap%ical Symbol
(c) C%aracteristic table
1
C*
2
C*
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
(a) !o"ic &ia"ram
Q
Q
Clocked T
flip-flop
C*
$
Q Q
$
(b) (rap%ical Symbol
C*
Q T Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0
(c) C%aracteristic table
1
1
0
1
0 1
Q
$
Q(t'1) = $Q'$Q
(&) C%aracteristic e)uation
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
#ositi$e #ulse Negati$e #ulse
#ositi$e-
edge
Negati$e-
edge
Negati$e-
edge
#ositi$e-
edge
"efinition of clock pulse transition
1
0
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
Master
S
R
Sla3e
S
R
S
R
Q
Q
C*
M0S$4R5S!064 7!I*57!O*
!o"ic &ia"ram of master5sla3e flip5flop
8
8
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
$imin" relations%ips in a master5sla3e flip5flop
S
Q
8
C*
S=1 R=0
S=0 R=1
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
1
+
,
2
-
9
Q
Q
:
;
<
1
C*
2
8
8
Cloc=e& master5sla3e 21 flip5flop
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
1
2
+
,
-
9
C*
S
R
#
Q
Q
S R Q Q
1 0 0 1
1 1 0 1
0 1 1 0
1 1 1 0
0 0 1 1
(/C)
(/C)
>
S=R=1 for stea&y state 3alues
> ?%en S=1 @ R=0 A Q=0
> ?%en S=0 @ R=1 A Q=1
#5type positi3e5e&"e5tri""ere& flip5flop
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
1
2
+
,
C*=0
S
R
#=0
1
2
+
,
C*=0
S
R
#=1
0
1
1
1
1
1
1
0
/o C%an"e at t%e outputs of t%e flip flop .%et%er # = 0 or 1
(a) ?it% C* = 0
Operation of the D-type edge-triggered flip-flop
So Q = 0 @ Q = 1
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
1
2
+
,
C*=1
S
R
#=0
1
2
+
,
C*=1
S
R
#=1
0
1
0
1
1
0
1
0
Operation of the D-type edge-triggered flip-flop
(b) ?it% C* = 1
So Q = 0 @ Q = 1
So Q = 1 @ Q = 0 So Q = 1 @ Q = 0
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
Q Q
1 2
7unction $able
Inputs Outputs
Clear Cloc= 2 1 Q Q
0 B B B 0 1
1 0 0 /o C%an"e
1 0 1 0 1
1 1 0 1 0
1 1 1 $o""le
C*
#irect Inputs
0sync%ronous
21 flip5flop .it% &irect clear
Clear
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
y
B
0
C
R Q
S Q
B
0
B
0
C
C
R Q
S Q
B
C
B
C
0
0
C*
4Bample of cloc=e& se)uential circuit
(0nalysis)
Input = B (4Bternal)
Output = y
Cloc=e& RS flip5flop
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
/eBt State Output
*resent State B=0 B=1 B=0 B=1
0C 0C 0C y y
00 00 01 0 0
01 11 01 0 0
10 10 00 0 1
11 10 11 0 0
State table for circuit
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
00
11
01 10
0D0
0D0
0D0
0D0
1D0
1D0
1D0
1D1
State &ia"ram for t%e circuit
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
1 1 1
1
0
0
1
CB
C
B
00 01 11 10
0
1
1 1 1
0
0
1
CB
C
B
0
00 01 11 10
0(t'1) = CB'(C'B)0 C(t'1) = 0B'(0'B)C
(a! 0(t'1) % B&' ( (B'&!' A ()! C(t'1) % A'& ( (A&'!' B
0(t'1) = S' R0 C(t'1) = S' RC
State e)uations for flip5flops 0 an& C
Q(t'1) = S' RQ
SR=0
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
S0 = C B R0 = CB
SC = 0B
RC = 0B y =
0CB
0nalysis of cloc=e& se)uential circuit
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
y
B
0
C
R Q
S Q
B
0
B
0
C
C
R Q
S Q
B
C
B
C
0
0
C*
Cloc=e& se)uential circuit
Input = B (4Bternal)
Output = y
Cloc=e& RS flip5flop
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
1 Q
2 Q
0
0
C
C
B
C
C
B
C
y
C*
20 = CCB ' CCB an& 10 = C'y
Implementation of t%e flip5flop input functions
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
a
b
&
f
c
e
"
0D0
1D0
1D1
0D0
0D0
0D0
0D0
0D0
0D0
1D0
1D0
1D1
1D1
1D1
*resent State a a b c & e f f " f " a
Input 6alue 0 1 0 1 0 1 1 0 1 0 0
Output 6alue 0 0 0 0 0 1 1 0 1 0 0
State &ia"ram

$%e problem of state5

re&uction is to fin& .ays of
re&ucin" t%e number of
states in a se)uential circuit
.it%out alterin" t%e input5
output relations%ipsE

minimiFes t%e cost of

circuit by re&ucin" flip5
flops @ "atesE

Consi&er t%e input

se)uence 01010110100
startin" from present state aE

?e are intereste& only in

output se)uences cause& by
input se)uencesEE
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
/eBt State Output
*resent State B=0 B=1 B=0 B=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1
State *a)le
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
Ne&t State Output
#resent State &%+ &%, &%+ &%,
a a b + +
b c d + +
c a d + +
d e f + ,
e a f + ,
f g f + ,
g a f + ,
Reducing the State *a)le
State
a a b c & e & & e & e a
Input
0 1 0 1 0 1 1 0 1 0 0
Output
0 0 0 0 0 1 1 0 1 0 0
d
d
e
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
/eBt State Output
*resent State B=0 B=1 B=0 B=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1
Reduced State *a)le
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
001
a
010
b
100
&
011
c
101
e
0D0
1D0
1D1
0D0
0D0
0D0
0D0
1D1
1D0
1D0
Re&uce& State &ia"ram

m flip5flops can represent

up to 2
m
&istinct states (iEeE
if m=+ ; states =G 0005
111)

7or fi3e states + flip5

flops are re)uire&E

7e.er states &o not

"uarantee a sa3in" in t%e
number of flip5flops or
number of "atesE
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
1 0 100 001 101
1 0 100 101 100
0 0 100 001 011
0 0 100 011 010
0 0 010 001 001
B=1 B=0
B=1 B=0
*resent State
Output /eBt State
Reduced State *a)le with )inar assignment ,
011 111 101 e
101 101 100 &
010 011 011 c
100 010 010 b
000 000 001 a
0ssi"nment+ 0ssi"nment2 0ssi"nment 1 State
*hree possi)le )inar state assignments
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
S R Q(t'1) 2 1 Q(t'1)
0 0 Q(t) /C 0 0 Q(t) /C
0 1 0 0 1 0
1 0 1 1 0 1
1 1 H 1 1 Q(t)
# Q(t'1) $ Q(t'1)
0 0 0 Q(t) /C
1 1 1 Q(t)
(a) RS (b) 21
(c) # (&) $
-lip-flop characteristic ta)les
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
Q(t) Q(t'1) S R Q(t) Q(t'1) 2 1
0 0 0 I 0 0 0 I
0 1 1 0 0 1 1 I
1 0 0 1 1 0 I 1
1 1 I 0 1 1 I 0
Q(t) Q(t'1) # Q(t) Q(t'1) $
0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0
(a) RS (b) 21
(c) #
(&) $
-lip-flop e&citation ta)les
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
#esi"n *roce&ure for Se)uential !o"ic Circuits
1E $%e .or& &escription of t%e circuits be%a3ior is state&E $%is may be
accompanie& by a state &ia"ram a timin" &ia"ram or ot%er pertinent
informationE
2E 7rom t%e "i3en information about t%e circuit obtain t%e state tableE
+E $%e number of states may be re&uce& by state re&uction met%o&s if t%e
se)uential circuit can be c%aracteriFe& by input5output relations%ips
in&epen&ent of t%e number of statesE
,E 0ssi"n binary 3alues to eac% state if t%e state table obtaine& in step 2 or
+ contains letter symbolsE
-E #etermine t%e number of flip5flops nee&e& an& assi"n a letter symbol to
eac%E
9E C%oose t%e type of flip5flop to be use&E
:E 7rom t%e state table &eri3e t%e circuit eBcitation an& output tablesE
;E Jsin" t%e 15Map or any ot%er simplification met%o& &eri3e t%e circuit
output functions an& t%e flip5flop input functionsE
<E #ra. t%e lo"ic &ia"ramE
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
00
10
01 11
0
1
1
1
1
0
0
0
State &ia"ram
"esign the clocked sequential circuit
using ./ flip-flops from the gi$en state
diagram0
/eBt State Output
*resent State B=0 B=1
0 C 0 C 0 C
0 0 0 0 0 1
0 1 1 0 0 1
1 0 1 0 1 1
1 1 1 1 0 0
State *a)le
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
1nputs of Com)inational
Circuit
Ne&t state
Outputs of Com)inational circuit
#resent state 1nput -lip-flop inputs
A B & A B .A /A .B /B
+ + + + + + 2 + 2
+ + , + , + 2 , 2
+ , + , + , 2 2 ,
+ , , + , + 2 2 +
, + + , + 2 + + 2
, + , , , 2 + , 2
, , + , , 2 + 2 +
, , , + + 2 , 2 ,
3(t! 3(t(,! . /
+ + + 2
+ , , 2
, + 2 ,
, , 2 +
4&citation ta)le
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
Combinational Circuit
0
0
C
C
Q Q
1 2
Q Q
1 2
0 0 C C
10 20 1C 2C
C*
4Bternal
outputs
(none)
4Bternal Inputs
Cloc= &ia"ram of se)uential circuit
B
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
1
X X X X
00 01 11 10
0
0
1
CB
C
B
0
X X X X
1
00 01 11 10
0
0
1
CB
C
1 X X
1 X X
00 01 11 10
0
0
1
CB
C
X X 1
X X 1
00 01 11 10
0
0
1
CB
C
20 = CB
10 = CB
2C = B 1C = 0 E I = 0B ' 0B
Maps for combinational circuit
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
Q Q
1 2
Q Q
1 2
0
C
C*
B
!o"ic &ia"ram of Se)uential !o"ic Circuit
20 = CB
10 = CB
2C = B
1C = 0 B
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
#resent state 1nput Ne&t State -lip-flop 1nputs Output
A B C & A B C SA RA SB RB SC RC
+ + , + + + , + 2 + 2 2 + +
+ + , , + , + + 2 , + + , +
+ , + + + , , + 2 2 + , + +
+ , + , , + + , + + , + 2 +
+ , , + + + , + 2 + , 2 + +
+ , , , , + + , + + , + , +
, + + + , + , 2 + + 2 , + +
, + + , , + + 2 + + 2 + 2 ,
, + , + + + , + , + 2 2 + +
, + , , , + + 2 + + 2 + , ,
4&citation ta)le
35 "esign a sequential circuit using state ta)le with assignment , emploing
RS flip-flops0
3(t! 3(t(,! S R
0 0 0 I
0 1 1 0
1 0 0 1
1 1 I 0
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
x x
1 1
x x x x
x x x
00 01 11 10
00
01
11
10
0C
0
C
x x x x
x x
x x x x
1
x x 1
x
x x x x
x x x
1 1 1
x x x x
x x x x
x x x
1 x
x x x x
1 x
x x 1
x 1
x x x x
x 1
x x
x x x x
1 1
S0=CB
R0=CB SC=0CB
RC=CC'CB
SC=B y=0B RC=B
Maps for simplifyin" t%e se)uential circuit
CB
CB
0C
00 01 11 10 0C
00 01 11 10 0C
00 01 11 10 0C
00 01 11 10 0C 00 01 11 10 0C
00 01 11 10
CB CB
CB
CB
00
01
11
10
00
01
11
10
00
01
11
10
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
S Q
R Q
S Q
R Q
S Q
R Q
y
0
0
C
C
C
C*
B
Logic diagram
S0 = CB R0 = CB SC = 0CB RC = CC ' CB SC = B RC =B @ y = 0B
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
4&ample5 Analse the sequential circuit and determine the effect of unused states0
001
011
100
010 101
0D0
1D0
1D1
0D0
0D0
0D0
0D0
1D1
1D0
1D0
000
110
111
0D0
0D0
0D0
1D0
1D1
1D1
A B C X
000 0 0 0 0
0 0 0 1
110 1 1 0 0
1 1 0 1
111 1 1 1 0
1 1 1 1
Jnuse& states
$%e circuit is
self5startin" an&
self5correctin"
since it
e3entually "oes
to a 3ali& state
from .%ic% it
continues to
operate as
re)uire&E
State &ia"ram of t%e circuit
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
000
111
110
101
100
011
010
001
State diagram of a 6 )it )inar counter
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
Count se)uence 7lip5flop inputs
0
2
0
1
0
0
$0
2
$0
1
$0
0
0 0 0 0 0 1
0 0 1 0 1 1
0 1 0 0 0 1
0 1 1 1 1 1
1 0 0 0 0 1
1 0 1 0 1 1
1 1 0 0 0 1
1 1 1 1 1 1
1
1
0
1
00 01 11 10
A
2
1 1
1 1
A
1
A
0
1 1 1 1
1 1 1 1
0
1
A
2
0
0
$0
2
= 0
1
0
0
$0
1
= 0
0
$0
0
= 1
7aps for a 6-)it )inar counter
4&citation ta)le for a 6-)it )inar counter
Q(t) Q(t+1) T
0 0 0
0 1 1
1 0 1
1 1 0
0
A
2
1
0
A
2
1
00 01 11 10
A
1
A
0
00 01 11 10
A
1
A
0
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
!o"ic &ia"ram 0f a +5bit binary counter
C#
0
2
0
1
0
0
$0
2
= 0
1
0
0
$0
1
= 0
0
$0
0
= 1
Q
$
Q
$
Q
$
1
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
0 C C
0 0 0
0 0 1
0 1 0
- 0 0
1 0 1
: 1 0
20
0
0
1
I
I
I
10
I
I
I
0
0
1
2C
0
1
I
0
1
I
1C
I
I
1
I
I
1
2C
1
I
0
1
I
0
1C
I
1
I
I
1
I
-lip-flop inputs Count sequence
4&citation ta)le
Q(t) Q(t'1) 2 1
0 0 0 I
0 1 1 I
1 0 I 1
1 1 I 0
#ont care
011
111
Q: Desin a !"#nter t$at !"#nts a re%eated se&#en!e as
s$"'n (e)"' #sin JK *)i%+*)"%
Countin" Se)uence A 0 1 2 , - an& 9
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
B 1
B B B B
0
0
1
00
B B B B
B 1
0
0
1
1 B B
1 B B
0
0
1
B B B 1
B B B 1
0
0
1
1 B B
1 B B
0
0
1
B 1 B B
B 1 B B
0
0
1
01
11 10 00
01
11 10
00 01
11 10 00
01
11 10
00
01
11 10
00
01
11 10
10 = C
1C = 1
1C = 1
20 = C
2C = C
2C = C
#ont careA 011 @ 111
CC
CC
CC
CC
CC
CC
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
0 C C
1
Q Q
1 2
Q Q
1 2
Q Q
1 2
C
Count
*ulses
(a! Logic "iagram
of Counter
000
001 110
010 101
100
111
011
()! Logic "iagram
of Counter
Jsin" 15maps
20 = C
10 = C
2C = C
1C = 1
2C = C
1C = 1
Counter is self5startin"
Jnuse& states
011
111
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
#esi"n .it% State 4)uation
*resent
State
Input /eBt
State
0 C B 0 C
0 0 0 0 0
0 0 1 0 1
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 1 1
1 1 0 1 1
1 1 1 0 0

?it% # 7lip 7lops

C%aracteristic e)uation
Q(t'1) = #
4&ample 8 ,5 State e)uations from t%e "i3en table areA
0(t'1) = #0(0CB) = K (2,-9)
C(t'1) = #C(0CB) = K (1+-9)
#0 = 0C ' CB
#C = 0B ' CB '0CB
1
1 1 1
0
1
00 01 11 10
A
Bx
1 1
1 1
0
1
00 01 11 10
A
Bx
Q Q
t
D
0 0 0
0 1 1
1 0 0
1 1 1
#0 = 0C ' CB
#C = 0B ' CB
'0CB
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
# Q
# Q
0
0
C
C
C*
B
#0 = 0C ' CB
#C = 0B ' CB '0CB
Logic diagram
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
4&ample 8 9 A #esi"n a se)uential Circuit as per "i3en con&itions usin" # flip flopsA5
0(t'1) = C ' #
C(t'1) = 0
C(t'1) = C
#(t'1) = C
So
#0 = C ' #
#C = 0
#C = C
## = C
Q # Q # Q # Q #
0
C
C*
C
#
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
Example # 3:- Desin a Se&#entia) Cir!#it 'it$ JK *)i%+*)"%s t" satis*,
t$e i-en e&#ati"ns:+
State Equations [Characteristic equation of JK flip-flops = Q(t!" = (J" Q# ($#" Q %
A(t+1) . ABCD + ABC + ACD + ACD
B(t+1) . AC + CD + ABC
C(t+1) . B
D(t+1) . D
A)e(rai! mani%#)ati"ns *"r mat!$in !$ara!teristi! e&#ati"n "* JK *)i%+
*)"%s:
A(t+1) . (BCD + BC) A + (CD + CD)A
. (J)A + (K) A
J . BCD + BC . BC ++++++++++++(i)
(K) . (CD +CD) . CD + CD++++++(ii)
B(t+1) . (AC +CD) + (AC)B
B(t+1) . (AC + CD)(B+B) + (AC)B
. (AC + CD) B + (AC + CD + AC) B
. (J)B + (K) B
J . AC + CD +++++++++++++(iii)
(K) . (AC + CD + AC) . AC + AD ++++++++++ (i-)
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m
C(t'1) = C = C(C ' C) = CC ' CC
= (2) C ' (1) C
2 = C 5555555555(3)
(1) = C 5555555(3i)
#(t'1) = # = 1E# ' 0E#
= (2) # ' (1) #
2 = 1 = 1
2 = 15555555555(3ii)
(1) = (O) = (1) = 155555555555(3iii)
20 = CC 5555555555(i) 10 = C# ' C#55555555555(ii)
2C = 0C ' C# 55555555(iii) 1C = 0C ' 0# 5555555(i3)
2C = C 555555555(3) 1C = C 5555555555(3i)
2# = 1 5555555555(3ii) 1# = 1 555555555555(3iii)
F
a
a
D
o
O
E
n
g
i
n
e
e
r
s
.
c
o
m