CS221:

VHDLExamples
Dr.A.Sahu
Dept of Comp. Sc. & Engg. DeptofComp.Sc.&Engg.
IndianInstituteofTechnologyGuwahati
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Outline Outline
VHDL
Test benches Packages and Library Testbenches,PackagesandLibrary
GenericandGenerates
VHDL Edit VHDLEditor:emacs
Examples
Assignments:Pleaselookatcourse
website
OnlineDemoinClass
Examples,GHDL,GTKWAVE p , ,
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Test Benches TestBenches
Purpose test correctness of Design Under Purpose testcorrectnessofDesignUnder
Test(DUT)
provide input stimulus provideinputstimulus
observeoutputs
compare against expected outputs compareagainstexpectedoutputs
TestBenchisalsoaVHDLmodel
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TestbenchforAdder
Testbench
For ( i =0; i <8; i ++) {
i t 10 wai t 10ns
Read ( Tr ut h Tabl e)
Send r ead A, B, Ci
A
Adder
Recei ve S, Co f r omadder
Compar e wi t h expect ed
i f ( er r or f ound)
B
Ci
S
Co
i f ( er r or f ound)
Repor t Er r or
}
Compare
result
ExpectedS
ExpectedCo
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TestBenchModelling
TestBench
DesignUnder
Test
Test bench a separate VHDL entity
(DUT)
Signals
TestbenchaseparateVHDLentity
PortsareconnectedtoDUTsports
i/p port corresponding to DUTs o/p port i/pportcorrespondingtoDUT so/pport
o/pportcorrespondingtoDUTsi/pport
Test bench instantiates the DUT TestbenchinstantiatestheDUT
Stimulusgenerationandoutputmonitoringina
separate VHDL process separateVHDLprocess
SignalsareconnectedtoDUTsports
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Libraries and Packages LibrariesandPackages
PACKAGE collection of PACKAGE collectionof
Components
data types datatypes
functions/procedures
LIBRARY ll ti f PACKAGE LIBRARY collectionofPACKAGEs
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Packages
PACKAGE util IS PACKAGE util IS
COMPONENT cIS
PORT (a:INBIT,b:OUTBIT);
Package
ENDCOMPONENT
TYPE my_int ISINTEGERRANGE7TO 7;
FUNCTION comp(a:BIT VECTOR)
Package
Declaration
p ( _ )
RETURNBIT_VECTOR;
END util;
PACKAGEBODYutil IS
FUNCTIONcomp(a:BIT_VECTOR) RETURN Package
BIT_VECTORIS
BEGIN
RETURNNOTa;
Body
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;
END comp;
END util;
Using a Package UsingaPackage
Library
Name
Package
Name
All
Contents
PACKAGE util IS
COMPONENT c IS
Name Name
COMPONENT cIS
PORT (a:INBIT,b:OUTBIT);
ENDCOMPONENT
USEWORK.UTIL.ALL;
...
SIGNAL x:my int;
TYPE my_int ISINTEGERRANGE7TO 7;
FUNCTION comp(a:BIT_VECTOR)
RETURNBIT_VECTOR;
y_ ;
a=comp(b);
_ ;
END util;
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Libraries Libraries
STD STD
STANDARD:types/utilities(BIT,TIME,INTEGER,...)
TEXTIO TEXTIO
interfacetotextfiles
WORK
defaultlibraryforstoringuserdesigns
STD_LOGIC_1164
multivaluedlogic g
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TEXTIO Package TEXTIOPackage
Data types and functions for Datatypesandfunctionsfor
readingfromtextfiles
writing out text files writingouttextfiles
FILE f:TEXTISfile_name;
VARIABLE one line: line; VARIABLE one_line:line;
VARIABLE str:STRING;
...
READLINE (f,one_line); readonelinefromfile
READ (str,one_line); readawordfromline
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WRITELINE (g,one_line); writeonelinetofile
WRITE (str,one_line); writeawordintoline
DesignParameterization:
GENERIC&GENERATE
ENTITY eIS
GENERIC (delay:TIME :=2NS;
width:INTEGER :=4);
PORT (a: IN BIT VECTOR (0 TO width); PORT (a:INBIT_VECTOR(0TO width);
b:OUTBIT_VECTOR(0TO width));
END e;
Default
Value
ARCHITECTURE aOF eIS
BEGIN
b<=NOT aAFTER delay;
END a;
Generic
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Generic
Parameters
PassingGENERICParameters
ENTITY IS
;
ENTITY cIS
GENERIC (delay:TIME :=4ns);PORT(a:INBIT;b:OUTBIT);
END c;
ARCHITECTUREaOFeIS
COMPONENTc
GENERIC (t: TIME:= 4 NS);
ARCHITECTUREdefOFeIS
COMPONENTc
GENERIC (t: TIME:= 4 NS);
GENERIC(t:TIME:=4NS);
PORT(a:INBIT,b:OUTBIT);
ENDCOMPONENT;
SIGNALx,y:BIT;
GENERIC(t:TIME: 4NS);
PORT(a:INBIT,b:OUTBIT);
ENDCOMPONENT;
SIGNALx,y:BIT;
, y ;
FORALL:cUSEwork.c (arc);
BEGIN
FORALL:cUSEwork.c (arc);
BEGIN
c1:cGENERICMAP(3ns)
PORTMAP(x,y);
END a;
c1:cPORTMAP(x,y);
END def;
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DelayParameter3ns
DelayDefaultValue4ns
GENERATE:ConditionalandLooped
Instantiation
Number of instances of DFF determined by NumberofinstancesofDFFdeterminedby
GenericParametern
Inp
Outp
DD_F
0
DD_F
1
DD_F
2
DD_F
N1
Inp
Outp
CLK
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GENERATE:ConditionalandLooped
Instantiation
GENERIC (n:INTEGER)...
Need intermediate
...
SIGNAL t:BIT_VECTOR (0TO n1);
Needintermediate
signalt(0ton1)
Inp
Outp
t(0) t(1) t(2) t(n1)
DD_F
0
DD_F
1
DD_F
2
DD_F
N1
Inp
Outp
CLK
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GENERATE Statement GENERATEStatement
SIGNAL t:BIT_VECTOR (0TO n1);
...
dff_0:DFFPORTMAP(Inp,Clk,t(0));
dff_n:DFFPORTMAP(t(n1),Clk,Outp);
FOR i IN 1TO n1GENERATE
dff_i:DFFPORTMAP (t(i1),Clk,t(i));
ENDGENERATE;
Outp
DD_F
0
DD_F
1
DD_F
2
DD_F
N
Inp
Outp
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CLK
N Bit Ripple Carry Adder: FA NBitRippleCarryAdder:FA
ENTITYfull_adder IS
PORT (a,b,c_in:IN std_logic;
Sum,Carry:OUT std_logic );
END full_adder;
ARCHITECTURE full_adder_arch_1OF full_adder IS
SIGNAL S1,S2,S3:std_logic;
BEGIN BEGIN
s3<=(aAND b)after5ns;
s2<=(c_in AND s1)after5ns;
s1<=(aXORb)after15ns;
Carry<=(s2OR s3)after5ns;
Sum<=(s1XOR c in )after15ns;
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( _ ) ;
END full_adder_arch_1;
N Bit Ripple Carry Adder NBitRippleCarryAdder
ENTITYadder_bits_n IS
GENERIC(n:INTEGER :=2);
PORT (
Cin:IN std_logic;
a,b:IN std_logic_vector(n1downto 0);
S:OUT std_logic_vector(n1downto 0);
Cout: OUT std logic Cout:OUT std_logic
);
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END;
N Bit Ripple Carry Adder NBitRippleCarryAdder
ARCHITECTURE ripple_n_arch OFadder_bits_n IS
COMPONENTfull_adder
PORT (x,y,z:IN std_logic;Sum,Carry:OUT std_logic);
END COMPONENT; ENDCOMPONENT;
SIGNAL t:std_logic_vector(ndownto 0);
BEGIN
t(0)<=Cin;Cout <=t(n); ( ) ; ( );
FA:FOR i in 0to n1GENERATE
FA_i:full_adder PORTMAP(t(i),a(i),b(i),S(i),t(i+1));
end generate;
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endgenerate;
END;
Testbenchesfor4bitadder:Stimulusonly
ARCHITECTURE tb OFtb_adder_4IS
COMPONENT adder bits n GENERIC(n: INTEGER := 2); COMPONENT adder_bits_n GENERIC(n:INTEGER :=2);
PORT (Cin:IN std_logic;a,b:IN std_logic_vector(n1downto 0);
S:OUTstd_logic_vector(n1downto 0);Cout:OUT std_logic);
END COMPONENT; ENDCOMPONENT;
SIGNAL x,y,Sum:std_logic_vector(ndownto 0);
SIGNAL c Cout: std logic; SIGNAL c,Cout:std_logic;
BEGIN
x<=0000,0001after200ns,0101,after400ns;
< 0010 0011 ft 200 1010 ft 400 y<=0010,0011after200ns,1010,after400ns;
c<=1,0after200ns;
UUT_ADDER_4:adder_bits_n GENERICMAP(4)
PORT MAP ( S C )
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PORTMAP(c,x,y,Sum,Cout);
END
4bitmultiplexor4x1
4x1
I0
I1
I2
Y
4Bit:3 downto 0
4x1
Mux
I2
I3
S1 S0
entity Mux is
port(I3:instd_logic_vector(3downto 0);
I2:in std logic vector(3downto 0); _ g _ ( );
I1:in std_logic_vector(3downto 0);
I0:in std_logic_vector(3downto 0);
S: in std logic vector(1 downto 0); S:in std_logic_vector(1downto 0);
O: out std_logic_vector(3downto 0)
);
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end Mux;
Architecture of 4x1 Mux Architectureof4x1Mux
architecture behvioral ofMux is
Begin
process(I3,I2,I1,I0,S)
begin usecasestatement g
case Sis
when "00"=>O<=I0;
when "01" => O <= I1; when 01 =>O<=I1;
when "10"=>O<=I2;
when "11"=>O<=I3;
h h O "ZZZ" when others=>O<="ZZZ";
endcase;
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endprocess;
endbehvioural;
Resister
entity regis is
port(rst,clk,load:in std_logic;
input: in std logic vector( 3 downto 0 ); input:in std_logic_vector(3downto 0);
output:out std_logic_vector(3downto 0)
);
d i end regis;
architectureregis_arc of regis is
begin
process(rst,clk,load,input)
begin
if( rst = '1' ) then output <= "0000"; if(rst 1 )then output< 0000 ;
elsif(clk'event and clk ='1')then
if(load='1')then output<=input;
d if d if
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endif;endif;
endprocess;
endregis_arc;
How to Write FSM is VHDL HowtoWriteFSMisVHDL
S3
01010
S0 S1 S2 Init
C=
10
C
00000 00011
xxx00
01010
S4
C=
01
C=
11
entity fsm is
S5
11111
00101
entityfsm is
port(rst,clk,proceed :in std_logic;
comparison:in std_logic_vector(1downto 0);
bl l l ld ld t td l i
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;
enable,xsel,ysel,xld,yld:out std_logic
);
endfsm;
FSM Architecture FSMArchitecture
architecturefsm_arc offsm is
i ( i i 0 2 3 ) typestatesis(init,s0,s1,s2,s3,s4,s5);
signalnState,cState:states;
begin g
Process1:process(rst,clk )
begin
if( rst = '1' ) then if(rst = 1 )then
cState <=init;
elsif(clk'event andclk ='1')then
S S cState <=nState;
endif;
endprocess;
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FSMArchitecture
process(proceed,comparison,cState )
begin
variable:OP:std_loic_vector (4downto 0);
casecState is
wheninit=>if(proceed='0')thennState <=init;
elsenState <=s0;endif;
whens0=>OP<=00000;nState <=s1;
h 1 > OP < 00001 St t < 2 whens1=>OP<=00001;nState <=s2;
whens2=>OP<=XXX01;
if(comparison="10")thennState <=s3;
elsif( comparison = "01" ) then nState <= s4; elsif(comparison= 01 )thennState <=s4;
elsif(comparison="11")thennState <=s5;endif;
whens3=>OP<=01010nState <=s2;
whens4=>OP<=00101;nState <=s2; ; ;
whens5=>OP<=11111;nState <=s0;
whenothers=>nState <=s0;
endcase;
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enable<=OP(4);xsel <=OP(3);ysel <=OP(2);xld <=OP(1);yld <=OP(0);
endprocess;
endfsm_arc;
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