Apple Macbook Pro A1386 K19

8
1
CK
APPD
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
REV
SCHEM,CORNHOLE,K19
ZONE
ECN
ENG
APPD
DESCRIPTION OF CHANGE
DATE
DATE
PVT 04/24/2009
(.csa)
Page
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
24
25
26
28
29
31
32
33
34
35
37
38
39
41
42
43
45
46
48
49
50
51
52
Date
Contents
Sync
Table of Contents
System Block Diagram
Power Block Diagram
Power Block Diagram
BOM Configuration
JTAG Scan Chain
Functional / ICT Test
Power Aliases
Signal Aliases
CPU FSB
CPU Power & Ground
CPU Decoupling & VID
eXtended Debug Port(MiniXDP)
MCP CPU Interface
MCP Memory Interface
MCP Memory Misc
MCP PCIe Interfaces
MCP Ethernet & Graphics
MCP PCI & LPC
MCP SATA & USB
MCP HDA & MISC
MCP Power & Ground
MCP79 A01 Silicon Support
MCP Standard Decoupling
MCP Graphics Support
SB Misc
FSB/DDR3/FRAMEBUF Vref Margining
DDR3 SO-DIMM Connector A
DDR3 SO-DIMM Connector B
DDR3 Support
Right Clutch Connector
SECUREDIGITAL CARD READER
Ethernet PHY (RTL8211CL)
Ethernet & AirPort Support
Ethernet Connector
FireWire LLC/PHY (FW643)
FireWire Port Power
FireWire Ports
SATA Connectors
External USB Connectors
Front Flex Support
SMC
SMC Support
LPC+SPI Debug Connector
K19 SMBUS CONNECTIONS
12/05/2008
(.csa)
Page
DDR
12/12/2007
T18_MLB
12/12/2007
T18_MLB
N/A
N/A
12/18/2008
DDR
07/22/2008
DDR
N/A
N/A
(MASTER)
(MASTER)
(MASTER)
(MASTER)
11/12/2008
M98_MLB
11/12/2008
M98_MLB
10/17/2007
M87_MLB
11/12/2008
M98_MLB
12/12/2008
T18_MLB
12/12/2008
T18_MLB
12/12/2008
T18_MLB
04/04/2008
T18_MLB
12/12/2008
T18_MLB
12/12/2008
T18_MLB
12/12/2008
T18_MLB
12/12/2008
T18_MLB
12/12/2008
T18_MLB
03/31/2008
T18_MLB
06/18/2008
T18_MLB
06/18/2008
AMASON_M98_MLB
12/15/2008
DDR
12/05/2008
DDR
07/22/2008
DDR
07/22/2008
DDR
12/12/2008
T18_MLB
12/08/2008
MUXGFX
01/30/2009
VEMURI
07/01/2008
SUMA_M98_MLB
07/01/2008
SUMA_M98_MLB
12/16/2008
AMASON_M98_MLB
08/14/2008
SENSOR
12/22/2008
YUN_K19_MLB
08/14/2008
SENSOR
12/04/2008
PWRSQNC
11/14/2008
M98_MLB
12/04/2008
PWRSQNC
12/12/2008
T18_MLB
12/19/2008
DDR
05/09/2008
CHANGZHANG
12/19/2008
DDR
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
53
54
55
56
57
58
59
60
61
62
63
65
66
67
68
69
70
71
72
73
75
76
77
78
79
80
81
82
84
85
86
87
88
89
90
93
94
95
96
97
98
99
100
101
102
Date
Contents
Current & Voltage Sensing
Current Sensing
Thermal Sensors
Fan Connectors
WELLSPRING 1
WELLSPRING 2
Sudden Motion Sensor (SMS)
DEBUG SENSORS AND ADC
SPI ROM
AUDIO: CODEC/REGULATOR
AUDIO: LINE INPUT FILTER
AUDIO: HEADPHONE FILTER
AUDIO: SPEAKER AMP
AUDIO: JACKS
AUDIO: JACK TRANSLATORS
DC-In & Battery Connectors
PBus Supply & Battery Charger
IMVP6 CPU VCore Regulator
5V / 3.3V Power Supply
1.5V DDR3 Supply
MCP CORE REGULATOR
CPU VTT / 1V05 S0 Power Supply
Misc Power Supplies
Power Control
Power FETs
NV G96 PCI-E
NV G96 Core/FB Power
NV G96 Frame Buffer I/F
GDDR3 Frame Buffer A (Top)
GDDR3 Frame Buffer B (Top)
NV G96 GPIO/MIO/Misc
G96 GPIOs & Straps
NV G96 Video Interfaces
GPU (G96) CORE SUPPLY
LVDS Display Connector
Muxed Graphics Support
DisplayPort Connector
1.1V / 1V8 FB Power Supply
Graphics MUX (GMUX)
LCD BACKLIGHT DRIVER
LCD Backlight Support
Misc Power Supplies
CPU/FSB Constraints
Memory Constraints
MCP Constraints 1
Page
08/14/2008
SENSOR
12/10/2008
YUN_K19_MLB
12/22/2008
YUN_K19_MLB
10/17/2007
M87_MLB
06/18/2008
AMASON_M98_MLB
01/05/2009
PWRSQNC
08/14/2008
SENSOR
12/19/2008
DDR
07/01/2008
CHANG_M98_MLB
03/16/2009
AUDIO
03/16/2009
AUDIO
03/16/2009
AUDIO
03/16/2009
AUDIO
03/16/2009
AUDIO
03/16/2009
AUDIO
12/16/2008
YUN_K19_MLB
12/10/2007
M99_MLB
10/17/2007
M87_MLB
12/17/2008
PWRSQNC
12/05/2008
DDR
11/14/2008
M98_MLB
12/14/2007
M99_MLB
12/14/2007
M99_MLB
12/17/2008
PWRSQNC
12/05/2008
DDR
07/10/2008
MUXGFX
07/10/2008
MUXGFX
07/10/2008
MUXGFX
07/10/2008
MUXGFX
07/10/2008
MUXGFX
07/10/2008
MUXGFX
07/09/2008
MUXGFX
07/10/2008
MUXGFX
10/17/2007
M87_MLB
12/19/2008
DDR
12/05/2008
AMASON_M98_MLB
07/10/2008
MUXGFX
07/10/2008
MUXGFX
07/10/2008
MUXGFX
12/12/2008
DDR
07/02/2008
YITE_M98_MLB
02/01/2008
MUXGFX
02/18/2008
MUXGFX
02/18/2008
MUXGFX
02/18/2008
MUXGFX
91
92
93
94
95
96
97
103
104
105
106
107
108
109
Contents
MCP Constraints 2
Ethernet Constraints
FireWire Constraints
SMC Constraints
GPU (G96) CONSTRAINTS
Project Specific Constraints
PCB Rule Definitions
Date
Sync
02/18/2008
MUXGFX
02/18/2008
MUXGFX
02/18/2008
MUXGFX
02/18/2008
MUXGFX
02/18/2008
MUXGFX
02/21/2008
MUXGFX
01/22/2008
M99_MLB
ALIASES RESOLVED
(.csa)
Sync
Schematic / PCB #s
PART NUMBER
DIMENSIONS ARE IN MILLIMETERS
APPLE INC.
METRIC
XX
X.XX
DRAFTER
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ENG APPD
MFG APPD
QA APPD
DESIGNER
RELEASE
SCALE
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
ANGLES
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
051-7892
SCHEM,CORNHOLE,K19
SCH
CRITICAL
820-2523
PCBF,CORNHOLE,K19
PCB
CRITICAL
NOTICE OF PROPRIETARY PROPERTY
DESIGN CK
X.XXX
BOM OPTION
TITLE
DO NOT SCALE DRAWING
DRAWING
SIZE
ABBREV=DRAWING
TITLE=MLB
LAST_MODIFIED=Fri Apr 24 15:23:24 2009

THIRD ANGLE PROJECTION
SCHEM,MBP 15MLB
NONE
MATERIAL/FINISH
NOTED AS
APPLICABLE
DRAWING NUMBER
REV.
051-7892
SHT
A.0.0
OF
97
U1000
U1300
INTEL CPU
XDP CONN
2.X OR 3.X GHZ
PG 12
PENRYN
PG 9
FSB
J6950
64-Bit
800/1067/1333 MHz
DC/BATT
POWER SUPPLY
PG 13
PG 60
J2900
2 UDIMMs
MAIN
FSB INTERFACE
GPIOs
DDR2-800MHZ
DDR3-1067/1333MHZ
MEMORY
DIMM
PG 14
U4900
PG 25,26
TEMP SENSOR
PG 41
Misc
CLK
PG 24
U6100
SYNTH
POWER SENSE
PG 45
SPI
Boot ROM
J4510
J5650,5600,5610,5611,5660,5720,5730,5750
FAN CONN AND CONTROL
SPI
SATA
PG 52
Conn
1.05V/3GHZ.
PG 48,49
PG 20
PG 38
HD
NVIDIA
J4520
J4900
B,0
SATA
Conn
PG 38
ADC
BSB
Fan
Ser
J5100
MCP79
SATA
1.05V/3GHZ.
Prt
SMC
LPC Conn
LPC
PG 19
ODD
Port80,serial
PG 41
PG 43
PG 18
U1400
J9000
PWR
LVDS
CONN
CTRL
LVDS OUT
PG 71
RGB OUT
J4720
DP OUT
IR
J3900,4635,4655
CAMERA
HDMI OUT
EXTERNAL
USB
Connectors
PG 40
PG 40
PG 40
PG 40
8
7
6
5
4
USB
PG 16
PCI-E
UP TO 20 LANES3
PG 17
PG 19
TMDS OUT
PG 39
DVI OUT
PG 71
J4710
J4710
TRACKPAD/
KEYBOARD
DISPLAY PORT
CONN
J4700
Bluetooth
(UP TO 12 DEVICES)
J9400
B
SMB
SMB
PG 20
CONN
RGMII
HDA
PCI
PG 44
DIMMs
(UP TO FOUR PORTS)

PG 17
PG 18
PG 20
U6200
Audio
Codec
PG 53
U6301
U6400
U6500
System Block Diagram
U6600,6605,6610,6620
U3700
GB
Line In
Line Out
Speaker
E-NET
Amp
Amp
Amp
Amps
PG 54
PG 55
PG 56
PG 57
HEADPHONE
SYNC_MASTER=T18_MLB
SYNC_DATE=12/12/2007
88E1116
PG 31

J3400
U3900
Mini PCI-E
J6800,6801,6802,6803
E-NET
AirPort
Conn
PG 28
Audio
SIZE
Conns
PG 33
PG 59
APPLE INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
2
97
M98 POWER SYSTEM ARCHITECTURE
SMC PWRGD
RN5VD30A-F
U5000
(PAGE 43)
D6905
PP3V42_G3H_REG
LT3470
U6990
(PAGE 59)
Q5315
VIN
CPUVTTS0_EN
PPBUS_G3H
CHGR_EN
(S5)
6A FUSE
DCIN(16.5V)
ENABLES
PM_GPUVCORE_EN
VIN
LIO_DCIN_ISENSE
VIN
ISL6263B
U8900
EN_PSV
(PAGE 60)
PBUS SUPPLY/
BATTERY CHARGER
VOUT
PGOOD
CPUVTTS0_PGOOD
GPUVCORE_PGOOD
MCP79
CK_PWRGD
U2830
VR_PWRGD_CLKEN
U5400
MCP_PS_PWRGD
U1400
(PAGE 14~22)
U2850
VR_PWRGD_CLKEN_L
VR_PWRGOOD_DELAY
PGOOD
Q7920
(PAGE 61)
PP5V_S0_FET
CPU
PPBUS_G3H
EN1
PP1V1_S0GPU_REG
VIN
PWRGOOD
U1000
(PAGE 10,11)
P5VS0_SS
P1V1GPU_EN
P3V3S3_EN
CPU_PWRGD
PWROK
CPUPWRGD(GPIO49)
PPVCORE_CPU_S0
VR_ON
PPVBAT_G3H_CHGR_R
CHGR_BGATE
PLT_RST_L
RSMRST*
SMC_CPU_VSENSE
A CPUVCORE_IOUT
VOUT
U7100
IMVP_VR_ON_R
Q7055
MCP79
PWRBTN#
VRMPWRGD
PLTRST*
VIN
ISL9504B
(18A MAX CURRENT)
U5715
A SMC_BATT_ISENSE
J6950
BATT_POS_F
TPS51117
U7600
(PAG 66)
(PAGE 78)
CPU VCORE
(9 TO 12.6V)
1.05V
PPVCORE_GPU_REG
GPUVCORE_IOUT
PGOOD
ISL6258A
U7000
3S2P
VOUT
VOUT
(6A MAX CURRENT)
U5498
PPCPUVTT_S0_REG
EN_PSV
SMC_GPU_VSENSE
GPU VCORE
AC
ADAPTER
IN
SMC_RESET_L
3.425V G3HOT
PBUSB_VSENSE
8A FUSE
PPVBAT_G3H_CHGR_REG
U5705
ENABLE
PPVIN_G3H_P3V42G3H
D6905
RESET*
Q7900
VOUT1
PP5V_S3_FET
1.103V(L/H)
SLP_S5#(H17)
P5VS3_EN
LIO_S3_EN
SLP_S3#(G17)
P1V8FB_EN
U4900
P60
(PAGE 14~22)
EN2
1.8V(R/H)
SMC
U1400
(PAGE 42)
PP1V8_GPU_REG
VOUT2
P5VS3_SS
TPS51124
U9500
(PAGE 82)
U7859
SMC_PM_G2_EN
VIN
5V
VOUT1
(S5)
3.3V
VOUT2
(R/H)
P3V3S5_EN
VIN
P5V_RT_EN
U7400
PP5V_RT_REG
VOUT
EN/PSV
SC417
(PAGE 64)
P5V_RT_PGOOD
ENL
PGOOD
PP5V_S5_REG
PP5V_S3
(8A MAX CURRENT)
(L/H)
PP3V3_S5_REG
PP3V3_S5
ISL8009
V4
Q7910
TPS51125
U7201
(PAGE 62)
PGOOD1,2
VREG3
PP3V3_S3_FET
EN0
U7750
(PAGE 66)
P3V3S3_SS
P5V3V3_S5_PGOOD
Q7930
Q3805
PP1V05_S5_MCP
(5.5A MAX CURRENT)
SMC
PP3V3_S0GPU_FET
PM_RSMRST_L
RSMRST_OUT(P15)
PM_WLAN_EN_L
ALL_SYS_PWRGD
WOW_EN
PWRGD(P12)
VIN
P3V3S0_SS
GOSHAWK6P
Q3801
BKLT_EN
PM_ENET_EN
RSMRST_PWRGD
PPVOUT_S0_LCDBKLT
PP3V3_S0_FET
ENA
VOUT
(PAGE 84)
PLT_RST*
SMC_ONOFF_L
PWR_BUTTON(P90)
P17(BTN_OUT)
P1V05S0_PGOOD
P5VRIGHT_PGOOD
P3V3GPU_SS
VIN LTC3407
P1V2ENET_EN
RUN2
ENETAVDD_EN
Q3810
PP1V9_ENET_REG
VOUT1
P3V3_ENET_FET
U3850
(PAGE 33)
RUN1
VOUT2
PM_ENET_EN_L
MCPCORES0_PGOOD
CPUVTTS0_PGOOD
PP1V2_ENET_REG
RST*
PM_SLP_S5_L
PM_PWRBTN_L
SMC_RESET_L
SLP_S5_L(P95)
PM_SLP_S4_L
SLP_S4_L(P94)
P1V8S0_PGOOD
P3V3ENET_EN_L
PM_SLP_S3_L
SLP_S3_L(P93)
P1V5S0_PGOOD
Q3800
IMVP_VR_ON
RSMRST_IN(P13)
Q7970
U9701
99ms DLY
IMVP_VR_ON(P16)
PPVIN_S0_DDRREG_LDO
U4900
(PAGE 42)
S0PGOOD_PWROK
WOL_EN
PM_ENET_EN_L
SMC_ADAPTER_EN
RC
DELAY
P5VRIGHT_EN
RC
DELAY
P1V8S0_EN
MCPDDR_EN
RC
DELAY
CPUVTTS0_EN
RC
DELAY
MCPCORES0_EN
VLDOIN
1.8V
VOUT1
PPDDR_S3_REG
S3 0.9V
VOUT2
RST*
PPVTT_S0_DDR_LDO
TPS51116
U7300
(PAGE 63)
P5VS0_EN
RC
DELAY
S5
(12A MAX CURRENT)
DDRVTT_EN
PM_SLP_S3_L
RC
DELAY
VIN
DDRREG_EN
(S0)
P3V3S0_EN
(S0)
PBUSVSENS_EN
(S0)
PP5V_S0
V1
PP3V3_S0
V2
V3
PP1V5_S0_REG
MCP_CORE
MCPCORES0_EN
P1V05S0_EN
VIN
U7870

(PAGE 68)
(25A MAX CURRENT)
PP5V_RT_REG
VOUT1
(5A MAX CURRENT)

SIZE
ISL6236
U7500
DRAWING NUMBER
(PAGE 65)
(S0)
LTC2900
VOUT2
1.1V
EN1
PM_SLP_S3_DELAY_L
MCPCPCORE_S0_REG
EN2
V4
Power Block Diagram

SYNC_MASTER=T18_MLB
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
3
97
Power Block Diagram
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
4
97
BOM Variants
TABLE_ALT_HEAD
TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
PART NUMBER
ALTERNATE FOR
PART NUMBER
138S0603
BOM OPTION
REF DES
COMMENTS:
138S0602
ALL
Murata alt to Samsung
353S1681
353S1294
ALL
LMV2011,OPAMP. GBW
152S0276
152S0683
ALL
Maglayers alt to Dale/Vishay
341S2367
341S2366
ALL
Macronix alt to SST
152S1034
152S0867
ALL
Toko alt to Delta
157S0058
157S0055
ALL
Delta alt to TDK Magnetics
152S0915
152S0796
ALL
Maglayers alt to Cyntec IND
128S0220
128S0262
ALL
KEMET ALT TO SANYO
127S0062
127S0108
ALL
ROHM ALT TO KEMET
152S0968
152S0966
ALL
Maglayer alt to Delta
311S0447
311S0406
ALL
NXP alt to TI
338S0714
338S0554
ALL
Low Leakage G96 GPU
107S0138
107S0074
ALL
CYNTEC alt to YDS
107S0139
107S0075
ALL
CYNTEC alt to YDS
TABLE_BOMGROUP_ITEM
630-9965
PCBA,2.66GHZ,256SAM_VRAM,HB_AUDIO,K19
TABLE_ALT_ITEM
K19_COMMON,DEVEL_BOM,EEE_6XN,CPU_2_66GHZ,FB_256_SAMSUNG
TABLE_BOMGROUP_ITEM
630-9966
PCBA,2.66GHZ,256HYN_VRAM,HB_AUDIO,K19
TABLE_ALT_ITEM
K19_COMMON,DEVEL_BOM,EEE_6XP,CPU_2_66GHZ,FB_256_HYNIX
TABLE_BOMGROUP_ITEM
630-9967
TABLE_ALT_ITEM
K19_COMMON,DEVEL_BOM,EEE_6XQ,CPU_2_80GHZ,FB_512_SAMSUNG
TABLE_BOMGROUP_ITEM
630-9968
TABLE_ALT_ITEM
K19_COMMON,DEVEL_BOM,EEE_6XR,CPU_2_80GHZ,FB_512_HYNIX
TABLE_BOMGROUP_ITEM
630-9969
TABLE_ALT_ITEM
K19_COMMON,DEVEL_BOM,EEE_6XS,CPU_3_06GHZ,FB_512_SAMSUNG
TABLE_BOMGROUP_ITEM
630-9970
TABLE_ALT_ITEM
K19_COMMON,DEVEL_BOM,EEE_6XT,CPU_3_06GHZ,FB_512_HYNIX
TABLE_BOMGROUP_ITEM
085-0736
K19 MLB DEVELOPMENT
TABLE_ALT_ITEM
K19_DEVEL_PVT
TABLE_ALT_ITEM
K19 BOM Groups
TABLE_ALT_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
K19_COMMON
ALTERNATE,COMMON,K19,K19_COMMON1,K19_COMMON2,K19_PROGPARTS
K19_COMMON1
BOOT_MODE_USER,DPMUX_EN_S0,DP_CA_DET_EG_PLD,DP_ESD,EG_PWRSEQ_HW,EXTRACT_BUFF
K19_COMMON2
GMUX_1V8,GPUVID_1P00V,GPU_SS_INT,ISL6258A,MCP_B03,MCPSEQ_SMC,MIKEY,MUXGFX,SMC_DEBUG_YES,XDP
K19_DEVEL_ENG
BMON_ENG,DEBUG_ADC,GMUX_JTAG,LPCPLUS,VREFMRGN,XDP_CONN
K19_DEVEL_PVT
BMON_PROD,LPCPLUS,NO_VREFMRGN,XDP_CONN
K19_PROD
BMON_PROD,LPCPLUS_NOT,NO_VREFMRGN
K19_PROGPARTS
GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG
BOM GROUP
BOM OPTIONS
FB_256_SAMSUNG
VRAM4,VRAM_256_SAMSUNG
FB_256_HYNIX
VRAM4,VRAM_256_HYNIX
FB_512_SAMSUNG
VRAM4,VRAM_512_SAMSUNG
FB_512_HYNIX
VRAM4,VRAM_512_HYNIX
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
C Bar Code Labels / EEE #s

PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
826-4393
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:6XN]
CRITICAL
EEE_6XN
826-4393
[EEE:6XP]
CRITICAL
EEE_6XP
826-4393
[EEE:6XQ]
CRITICAL
EEE_6XQ
826-4393
[EEE:6XR]
CRITICAL
EEE_6XR
826-4393
[EEE:6XS]
CRITICAL
EEE_6XS
826-4393
[EEE:6XT]
CRITICAL
EEE_6XT
DESCRIPTION
REFERENCE DES
Module Parts
PART NUMBER
QTY
CRITICAL
BOM OPTION
337S3761
IC,PDC,SLGLA,PRQ,2.66G,25W,1066,R0,3M,BGA
U1000
CRITICAL
CPU_2_66GHZ
337S3682
IC,PDC,SLGEM,PRQ,2.80G,35W,1066,E0,6M,BGA
U1000
CRITICAL
CPU_2_80GHZ
337S3744
IC,PDC,SLGKH,QS,3.06G,35W,1066,E0,6M,BGA
U1000
CRITICAL
CPU_3_06GHZ
338S0710
IC,MCP79MXT-B3,35X35MM,BGA1437
U1400
CRITICAL
MCP_B03
338S0694
IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P LQFP
U3700
CRITICAL
338S0654
IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12
U4100
CRITICAL
341S2384
IR,ENCORE II, CY7C63803-LQXC
U4800
CRITICAL
338S0563
IC,SMC,HS8/2117,9MMX9MM,TLP
U4900
CRITICAL
341S2462
IC,SMC,DEVELOPMENT,K19
U4900
CRITICAL
SMC_PROG
341S2503
IC,PSOC +W/USB,56PIN,MLF,K19
U5701
CRITICAL
TPAD_PROG
335S0384
IC,32MBIT 8-PIN SPI SERIAL FLASH,SOIC8
U6100
CRITICAL
BOOTROM_BLANK
341S2456
IC,EFI ROM,DEVELOPMENT,K19
U6100
CRITICAL
BOOTROM_PROG
338S0554
IC,GPU,55nm,NV G96-GS,BGA969,LF
U8000
CRITICAL
333S0507
IC,SGRAM,GDDR3,16Mx32,1000MHZ,136 FBGA
U8400,U8450,U8500,U8550
CRITICAL
333S0483
U8400,U8450,U8500,U8550
CRITICAL
VRAM_256_HYNIX
333S0511
U8400,U8450,U8500,U8550
CRITICAL
VRAM_512_SAMSUNG
333S0506
U8400,U8450,U8500,U8550
CRITICAL
VRAM_512_HYNIX
B
SMC_BLANK
VRAM_256_SAMSUNG
Development BOM
PART NUMBER
085-0736
QTY
1
DESCRIPTION
REFERENCE DES
K19 MLB DEVELOPMENT
DEVEL
CRITICAL
CRITICAL
BOM OPTION
DEVEL_BOM
BOM Configuration
SYNC_MASTER=DDR

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
5
97
1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE)
82 81 80 77 70 69 68 63 60 59 PP3V3_S0
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84
U1000
CPU
From XDP connector

JTAG_ALLDEV
1
JTAG_ALLDEV
C0601
C0602
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
88 13 10 6
IN
88 13 10
IN
88 13 10 6
IN
88 13 10 6
IN
XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST_L
To XDP connector
and/or level translator
PPCPUVTT_S0
20 18 17 14 13 12 11 10 9 8 7
67 63 25 24 22
XDP
R0603
88 10
XDP_TDO
PLACEMENT_NOTE=Place near pin U1000.AB3

XDP_TDO_CONN
5%
1/16W
MF-LF
402
13
OUT
XDP connector
JTAG_ALLDEV
R0601 1
11
10K
5%
1/16W
MF-LF
402
From XDP connector

or via level translator
VCCA VCCB
U0600
U1400
MCP
NLSV4T244
XDP_TCK
88 13 10 6
2
3
NOSTUFF
R0602
0
5%
1/16W
MF-LF
402
XDP_TMS
XDP_TRST_L
88 13 10 6
88 13 10 6
4
5
A1
A2
A3
A4
UQFN
JTAG_ALLDEV
B1
B2
B3
B4
10
MAKE_BASE=TRUE
9
8
7
MAKE_BASE=TRUE
1
2
JTAG_LVL_TRANS_EN_L
12
OE*
6 13 21 76
XDP
13 21
R0604
13 21
21
6 13 21 76
JTAG_MCP_TDO
PLACEMENT_NOTE=Place near pin U1400.F19

JTAG_MCP_TDO_CONN
5%
1/16W
MF-LF
402
R0606
10K
GND
JTAG_MCP_TCK
JTAG_MCP_TDI
JTAG_MCP_TMS
JTAG_MCP_TRST_L
5%
1/16W
MF-LF
402
13
OUT
XDP connector
R0607
1
5%
1/16W
MF-LF
402
NOSTUFF
U8000
GPU
VCC
U0601
JTAG_MCP_TCK
GPU_JTAG_TDI
GPU_JTAG_TMS
JTAG_MCP_TRST_L
74LVC1G07
GMUX CPLD Programming Port
NC
NC
SOT886
NC
R0605
81 79 77 76 70 69 8
PP3V3_S0GPU
10K
PLACEMENT_NOTE=Place close to U8000

GPU_JTAG_TMS
6 76
5%
1/16W
MF-LF
402
6 13 21 76
76
6 76
6 13 21 76
76 6
TP_GPU_JTAG_TDO
TP_GPU_JTAG_TDO
NC
6 76
MAKE_BASE=TRUE
GND
3
GMUX_JTAG
CRITICAL
J0600
1909782
M-RT-SM
7
1
2
3
4
PP3V3_S0
TDO
TDI
TMS
59 60 63 68 69 70 77 80 81 82
6 7 8 13 18 19 21 22 24 25 28
29 37 39 43 45 47 48 49 51 55
84 85 96
U9200
GMUX
TCK
JTAG_GMUX_TCK
JTAG_GMUX_TDI
JTAG_GMUX_TMS
84
9 19 84
9 19 84
84 17 9
JTAG_GMUX_TDO
JTAG Scan Chain
SYNC_MASTER=DDR

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
6
97
Fan Connectors
PP5V_S0
TRUE
TRUE
TRUE
TRUE
FAN_LT_PWM
FAN_LT_TACH
FAN_RT_PWM
FAN_RT_TACH
TRUE
GND
66 67 70
8 39 44
49 51 63
83 85
3 TPs
49
SATA ODD Connectors
49
FUNC_TEST
49
5 TPs
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_CONN_A_DATA_N<0>
LVDS_CONN_A_DATA_P<0>
LVDS_CONN_A_CLK_F_N
LVDS_CONN_A_CLK_F_P
LVDS_CONN_B_DATA_N<0>
LVDS_CONN_B_DATA_P<0>
LVDS_CONN_B_CLK_F_N
LVDS_CONN_B_CLK_F_P
LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6
BKL_ISEN1
BKL_ISEN2
BKL_ISEN3
BKL_ISEN4
BKL_ISEN5
BKL_ISEN6
TRUE
59 60 63 68 69 70 77 80 81 82
6 7 8 13 18 19 21 22 24 25 28
29 37 39 43 45 47 48 49 51 55
84 85 96
80
TRUE
TRUE
GND
80 81
80 81 95
80 81 95
80 81 95
80 81 95
80 81 95
80 95
80 95
80 81 95
80 81 95
80 81 95
80 81 95
80 81 95
80 81 95
80 95
80 95
80 85
80 85
80 85
80 85
80 85
80 85
85
85
85
85
85
85
5 TPs
55 7
61
55 7
20 7
GND
TRUE
39 90
3 TPs
7 51
7 51
50 51
50 51
50 51
50 51
50 51
51
50 51
50 51
50 51
50 51
50 51
50 51
50 51
7 31 42 45 51 94
7 31 42 45 51 94
50 51
50 51
2 TPs
18 7
Battery Connector
39 90
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
7 8 21 27 31 32 45 50 52 70
TRUE
GND
50
50
FUNC_TEST
50
PP3V42_G3H
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMC_BIL_BUTTON_L
SMC_LID_R
GND
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
50
50
50
50
50
TRUE
GND
19 7
61
6 TPs
15 7
16 7
16 7
16 7
45 46 50 61 62 64 69
44
43
40 42
7 8 21
22 26
16 7
3 TPs
7 42 45 61 62 94
16 7
42 43 61
16 7
61
16 7
3 TPs
16 7
Power Nets
50
50
50
16 7
16 7
21 7
FUNC_TEST
50
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
50
50
50
50
50
50
50
50
50
50
50
50
50
7 51
2 TPs
17 31 90
17 31 90
31 90 96
31 90 96
31 96
31 96
31
PPVCORE_S0_CPU
PPVCORE_S0_MCP_REG
PP0V9R0V75_S0_DDRVTT
PPCPUVTT_S0
PP1V8R1V5_S0_FET
PP1V8_S0
PP3V3_S0
PP1V8R1V5_S3
PP3V3_S3
PP1V2R1V05_S5
PP3V3_S5
PP3V42_G3H
PPBUS_G3H
PP3V3_ENET_PHY
PP1V2R1V05_ENET
PP5V_S3
PP3V3_S5_AVREF_SMC
PP18V5_S3
PP3V3_S3_LDO
PPVOUT_S0_LCDBKLT
PP4V5_AUDIO_ANALOG
SMC_PM_G2_EN
PM_SLP_S4_L
PM_SLP_S3_L
PP1V05_S0_MCP_PLL_UF
PP5V_SW_ODD
PP5V_S0_HDD_FLT
BKL_VLDO
50 7
8 11 12 46 63
TRUE
GND
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
32
2 TPs
6 8 9 10 11 12 13 14 17 18 20
22 24 25 63 67
8 11 12 16 24 28 29 39 68 69 70
8 18 25 55 69 70 84 87
59 60 63 68 69 70 77 80 81 82
6 7 8 13 18 19 21 22 24 25 28
29 37 39 43 45 47 48 49 51 55
84 85 96
8
28 29 30 65 70
7 8 21 27 31 32 45 50 52 70
19 7
8 22 24 34 68
19 7
8 18 20 22 24 26 30 34 37 38 44
54 64 68 69 70 82 87 96
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
19 7
8 37 46 61 62 64 65 66 67 79 83
86
8 18 24 33 34
19 7
8 18 24 33 34 37
19 7
8 9 31 39 40 41 43 51 53 55 64
65 70 79
42 43
19 7
7 51
19 7
7 51
19 7
7 53 80 85
19 7
55
17 7
42 64 69
17 7
21 40 42 43 69 70
17 7
21 34 37 42 69 82 84
17 7
8 24 68
17 7
7 39 53
17 7
7 39
17 7
85
17 7
19 7
19 7
19 7
19 7
19 7
19 7
50 7
6 TPs
31
20 7
31
20 7
31
20 7
7 31 42 45 51 94
20 7
7 31 42 45 51 94
20 7
31 96
21 7
7 20
7 18
7 18
PP5V_S0_HDD_FLT
PP5V_S3_IR_R
NC_PCI_C_BE_L<3..0>
NC_PCI_CLK0
NC_PCI_CLK1
NC_PCI_DEVSEL_L
NC_PCI_FRAME_L
NC_PCI_GNT0_L
NC_PCI_GNT1_L
NC_PCI_INTW_L
NC_PCI_INTX_L
NC_PCI_INTZ_L
NC_PCI_IRDY_L
NC_PCI_PERR_L
NC_PCI_RESET1_L
NC_PCI_SERR_L
NC_PCI_STOP_L
NC_PCI_TRDY_L
NC_PCIE_CLK100M_PE4N
NC_PCIE_CLK100M_PE4P
NC_PCIE_PE4_D2RN
NC_PCIE_PE4_R2D_CN
NC_PE4_PRSNT_L
NC_PSOC_P1_3
NC_PSOC_SDA
NC_SATA_C_D2RP
NC_SATA_C_R2D_CN
NC_SATA_C_R2D_CP
NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SB_A20GATE
NC_PCI_CLK0
NC_PCI_CLK1
NC_PCI_DEVSEL_L
NC_PCI_FRAME_L
NC_PCI_GNT0_L
NC_PCI_GNT1_L
NC_PCI_INTW_L
NC_PCI_INTX_L
NC_PCI_INTZ_L
NC_PCI_IRDY_L
NC_PCI_PERR_L
NC_PCI_RESET1_L
NC_PCI_SERR_L
NC_PCI_STOP_L
NC_PCI_TRDY_L
NC_PCIE_PE4_D2RN
NC_PCIE_PE4_R2D_CN
NC_PE4_PRSNT_L
NC_PSOC_P1_3
NC_PSOC_SDA
NC_SATA_C_D2RP
NC_SATA_C_R2D_CN
NC_SATA_C_R2D_CP
NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SB_A20GATE
7 39
4 TPs
TRUE
TRUE
TRUE
FSB_A_L<31..3>
FSB_ADS_L
FSB_ADSTB_L<1..0>
10 14 88
TRUE
FSB_D_L<63..0>
10 14 88
TRUE
FSB_DINV_L<3..0>
10 14 88
TRUE
TRUE
TRUE
TRUE
TRUE
FSB_DSTB_L_N<3..0>
FSB_DSTB_L_P<3..0>
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
USB_BT_N
USB_BT_P
USB_CAMERA_N
USB_CAMERA_P
SATA_ODD_D2R_UF_N
SATA_ODD_D2R_UF_P
DP_ML_C_P<3..0>
TRUE
GND
10 14 88
10 14 88
7 16
7 16
7 16
7 16
16
7 16
7 16
7 16
7 16
7 16
7 16
7 21
7 50
19
19
7 19
7 19
7 19
7 19
7 19
7 19
7 19
7 19
7 19
7 19
7 19
7 19
7 19
7 19
7 19
7 17
7 17
7 17
7 17
7 17
7 17
7 17
7 17
7 50
7 50
7 20
7 20
7 20
7 20
7 20
7 21
Note.
NO_TEST properties are also on page9,26,43,50
39 90
39 90
39 90
10 14 88
10 14 88
10 14 88
10 14 88
10 14 88
39 90
Functional / ICT Test
39 41
39
6 TPs
20 31 91
SYNC_MASTER=N/A
SYNC_DATE=N/A
20 31 91
20 31 91
20 31 91

39 96
39 96

82 95
TRUE
TRUE
KBDLED_ANODE
SMC_KDBLED_PRESENT_L
TRUE
GND
7 51
2 TPs
51
SIZE
58 59 96
58 59 96
7 15
39
FUNC_TEST
58 59 96
TP_PCI_C_BE_L<3..0>
16
NO_TEST
10 TPs
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
IR_RX_OUT
SYS_LED_ANODE_R
58 59 96
NC_MEM_B_CKE<2>
NC_MEM_B_CLK3P
NC_MEM_B_CLK4N
NC_MEM_B_CLK4P
NC_MEM_B_CLK5N
NC_MEM_B_ODT<2>
NC_MLB_RAM_SIZE
NC_P7_7
NC_PCI_AD<31..8>
7 19
31 96
KBD Backlight Conn.
58 59 96
DRAWING NUMBER
6 TPs
7 20
31 96
59 60
58 59 96
NC_MEM_B_CKE<2>
NC_MEM_B_CLK3P
NC_MEM_B_CLK4N
NC_MEM_B_CLK4P
NC_MEM_B_CLK5N
NC_MEM_B_ODT<2>
NC_MLB_RAM_SIZE
NC_P7_7
TP_PCI_AD<31..8>
31 96
59 60
59 60
NC_MEM_A_CKE<3..2>
NC_MEM_A_CLK2N
NC_MEM_A_CLK3N
NC_MEM_A_CLK3P
NC_MEM_A_CLK4P
NC_MEM_A_CS_L<3>
NC_MEM_A_ODT<3..2>
APPLE INC.
REV.
051-7892
SCALE
SHT
NONE
7 55
8 28 29 65 70
50 7
GND
32
NC_LPC_DRQ0_L
8 22 24 46 66
17 31
31
NC_LPC_DRQ0_L
TP_MEM_A_CKE<3..2>
NC_MEM_A_CLK2N
NC_MEM_A_CLK3N
NC_MEM_A_CLK3P
NC_MEM_A_CLK4P
NC_MEM_A_CS_L<3>
TP_MEM_A_ODT<3..2>
7 42 45 61 62 94
50
32 93
FUNC_TEST
BI_MIC_LO
BI_MIC_SHIELD
BI_MIC_HI
SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
SPKRCONN_R_OUT_P
SPKRCONN_R_OUT_N
SPKRCONN_S_OUT_P
SPKRCONN_S_OUT_N
7 55
7 42 45 61 62 94
32 93
Speaker Connectors
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
NC_AUD_LO1_N_L
NC_AUD_LO1_P_L
NC_USB_10N
NC_USB_10P
NC_ENET_INTR_L
NC_ENET_PWRDWN_L
3 TPs
7 42 45 61 62 94
Batt Signal Connector
GND
TRUE
TRUE
32 93
61 62
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
50
FUNC_TEST
PCIE_MINI_D2R_P
TRUE
PCIE_MINI_D2R_N
TRUE
PCIE_MINI_R2D_P
TRUE
PCIE_MINI_R2D_N
TRUE
PCIE_CLK100M_MINI_CONN_P
TRUE
PCIE_CLK100M_MINI_CONN_N
TRUE
MINI_CLKREQ_Q_L
TRUE
PCIE_WAKE_L
TRUE
MINI_RESET_CONN_L
TRUE
PP5V_WLAN
TRUE
PP3V3_S3_BT_F
TRUE
PP5V_S3_BTCAMERA_F
TRUE
SMBUS_SMC_A_S3_SDA
TRUE
SMBUS_SMC_A_S3_SCL
TRUE
USB_CAMERA_CONN_P
TRUE
USB_CAMERA_CONN_N
TRUE
CONN_USB2_BT_P
TRUE
CONN_USB2_BT_N
TRUE
TRUE
PPVBAT_G3H_CONN
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SYS_DETECT_L
GND
TRUE
TRUE
TRUE
TRUE
TRUE
FUNC_TEST
SD_D<7..0>
SD_CMD
SD_CLK
SD_CD_L
SD_WP
18 7
NC_AUD_LO1_N_L
NC_AUD_LO1_P_L
NC_USB_10N
NC_USB_10P
NC_ENET_INTR_L
NC_ENET_PWRDWN_L
3 TPs
SATA HDD Connector
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
20 7
39 90
PP3V3_S3
PP3V42_G3H
WS_KBD1
WS_KBD2
WS_KBD3
WS_KBD4
WS_KBD5
WS_KBD6
WS_KBD7
WS_KBD8
WS_KBD9
WS_KBD10
WS_KBD11
WS_KBD12
WS_KBD13
WS_KBD14
WS_KBD15_CAP
WS_KBD16_NUM
WS_KBD17
WS_KBD18
WS_KBD19
WS_KBD20
WS_KBD21
WS_KBD22
WS_KBD23
WS_KBD_ONOFF_L
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
KBDLED_ANODE
TRUE
GND
3 TPs
39 90
Airport/BT/Camera Conn.
PP3V3_S3_LDO
PP18V5_S3
Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_BOOST_EN
Z2_HOST_INTN
Z2_CLKIN
Z2_KEY_ACT_L
Z2_RESET
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
PSOC_F_CS_L
PICKB_L
61
39 42
FUNC_TEST
80 81 95
GND
NO_TEST
PP18V5_DCIN_FUSE
ADAPTER_SENSE
TRUE
TRUE
FUNC_TEST
SD Card Connector
SMC_ODD_DETECT
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_C_N
SATA_ODD_D2R_C_P
4 TPs
Keyboard Connector
80 81
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
7 39 53
7 53 80 85
IPD Flex Connector

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
FUNC_TEST
PP5V_SW_ODD
TRUE
FUNC_TEST
PP3V3_S0
PP3V3_SW_LCD
PPVOUT_S0_LCDBKLT
ICT Test Points
DC Power Connector
49
LVDS Connector
TRUE
TRUE
TRUE
Functional Test Points
FUNC_TEST
TRUE
A.0.0
OF
7
97
8
86
66 65 64
37 8 7
62 61 46
83 79 67
PPBUS_G3H
"G3Hot" (Always-Present) Rails

PPBUS_G3H
PP3V3_S5
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE
PPBUS_G3H
7 8 37 46 61 62 64 65 66 67 79
83 86
7 8 37 46 61 62 64 65 66 67 79
83 86
7 8 37 46 61 62 64 65 66 67 79
83 86
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_CPU_IMVP_ISNS
7 8 37 46 61 62 64 65 66 67 79
83 86
7 8 37 46 61 62 64 65 66 67 79
83 86
7 8 37 46 61 62 64 65 66 67 79
83 86
7 8 37 46 61 62 64 65 66 67 79
83 86
7 8 37 46 61 62 64 65 66 67 79
83 86
7 8 37 46 61 62 64 65 66 67 79
83 86
PPBUS_CPU_IMVP_ISNS
VOLTAGE=12.6V
MAKE_BASE=TRUE
PPBUS_CPU_IMVP_ISNS
8 46 63
PPDCIN_G3H
PPDCIN_G3H
VOLTAGE=16.5V
MAKE_BASE=TRUE
PPDCIN_G3H
61
44
26 22 21 8
42
46
64
69
50
43
7
40
45
62
VOLTAGE=3.42V
MAKE_BASE=TRUE
PP3V42_G3H
PP3V42_G3H
PP1V8R1V5_S0_FET
7 8 18 20 22 24 26 30 34 37 38
44 54 64 68 69 70 82 87 96
130 mA
7 8 18 20 22 24 26 30 34 37 38
44 54 64 68 69 70 82 87 96
500 mA
4771 mA
7 8 21 27 31 32 45 50 52 70
PP1V0_FW
7 8 21 27 31 32
24 17 8 45 50 52 70
7 8 21 27 31 32 45
50 52 70
7 8 28 29 30 65 70
PP3V3_FW_FWPHY
7 8 28 38 37 36 8
29 30 65 70
PP3V3_FW_FWPHY
PP3V3_FW_FWPHY
PP3V3_FW_FWPHY
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
7 8 9 31 39 40 41 43 51 53 55
64 65 70 79
7 8 9 31 39 40 41 43 51 53 55
64 65 70 79
7 8 9 31 39 40 41 43 51 53 55
64 65 70 79
7 8 9
64 65
7 8 9
64 65
31
70
31
70
39 40 41 43 51 53 55
79
39 40 41 43 51 53 55
79
7 8 9 31 39 40 41 43 51 53 55
64 65 70 79
7 8 9
64 65
7 8 9
64 65
31
70
31
70
39 40 41 43 51 53 55
79
39 40 41 43 51 53 55
79
7 8 9 31 39 40 41 43 51 53 55
64 65 70 79
7 8 9 31 39 40 41 43 51 53 55
64 65 70 79
7 8 9 31 39 40 41 43 51 53 55
64 65 70 79
7 8 9 31 39 40 41 43 51 53 55
64 65 70 79
7 8 9 31 39 40 41 43 51 53 55
64 65 70 79
7 8 9 31 39 40 41 43 51 53 55
64 65 70 79
7 8 9 31 39 40 41 43 51 53 55
64 65 70 79
7 8 9 31 39 40 41 43 51 53 55
64 65 70 79
7 8 9 31 39 40 41 43 51 53 55
64 65 70 79
7 8 39 44 49 51 63 66 67 70 83
85
7 8 39 44 49 51 63 66 67 70 83
85
7 8 39 44 49 51 63 66 67 70 83
85
7 8 39 44 49 51 63 66 67 70 83
85
7 8 39 44 49 51 63 66 67 70 83
85
7 8 39 44 49 51 63 66 67 70 83
85
7 8 39 44 49 51 63 66 67 70 83
85
7 8 39 44 49 51 63 66 67 70 83
85
7 8 39 44 49 51 63 66 67 70 83
85
7 8 39 44 49 51 63 66 67 70 83
85
7 8 39 44 49 51 63 66 67 70 83
85
7 8 39 44 49 51 63 66 67 70 83
85
Chipset "VCore" Rails

PPVCORE_S0_CPU
VOLTAGE=1.25V
MAKE_BASE=TRUE
PPVCORE_S0_CPU
8 36 37 38
7 8 11 12 16 24 28 29 39 68 69
70
7 8 11 12 16 24 28
29 39 68 69 70
7 8 11 12 16 24 28 29 39 68 69
70
7 8 11 12 16 24 28 29 39 68 69
70
7 8 11 12 16 24 28
29 39 68 69 70 6
81 79 77 76 70 69 8
"GPU" Rails
PP3V3_S0GPU
PP3V3_S0GPU
6 8 69 70 76 77 79 81
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
6 7 8 9 10 11 12 13 14 17 18 20
22 24 25 63 67
PP3V3_S0GPU
PP3V3_S0GPU
6 7 8 9 10 11 12 13 14 17 18 20
22 24 25 63 67
PP1V05_S0_MCP_PEX_AVDD
7 8 24 68
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm
VOLTAGE=1.05V
MAKE_BASE=TRUE
7 8 11 12 16 24 28 29 39 68 69
70
8 17 24
6 8 69 70 76 77 79 81
6 8 69 70 76 77 79 81
PP3V3_S0GPU
6 8 69 70 76 77 79 81
8 17 24
7 8 21 27 31 32 45 50 52 70
PPCPUVTT_S0
7 8 21 27 31
32 45 50 52 70
PPCPUVTT_S0
PP3V3_S0GPU
PP3V3_S0GPU
6 7 8 9 10 11 12 13 14 17 18 20
22 24 25 63 67
7 8 21 27 31 32 45 50 52 70
PP1V05_S0_MCP_SATA_AVDD
PP3V3_S0
6 8 69 70 76 77 79 81
6 8 69 70 76 77 79 81
8 20 24
59 60 63 68 69 70 77 80 81 82
6 7 8 13 18 19 21 22 24 25 28
29 37 39 43 45 47 48 49 51 55
84 85 96
18 17 14 13 12 11 10 9 8 7 6
67 63 25 24 22 20
PPCPUVTT_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
59 60
6 7 8
29 37
84 85
82 84
51 55
6 7 8
85 96
59 60
25 28
19 21
6 7 8
63
13
39
96
85
59
13
29
63
29
22
13
68 69 70 77 80 81 82
18 19 21 22 24 25 28
43 45 47 48 49 51 55
59 60
6 7 8
29 37
84 85
77 80
43 45
6 7 8
29 37
68 69
59 60
29 37
6 7 8
63
13
39
96
81
47
13
39
70
63
39
13
68 69 70 77 80 81 82
18 19 21 22 24 25 28
43 45 47 48 49 51 55
PP3V3_S0
59 60
6 7 8
29 37
84 85
59 60
6 7 8
29 37
84 85
63
13
39
96
63
13
39
96
70 77
47 48
21 22
6 7 8
68 34
59 60
6 7 8
29 37
84 85
59 60
29 37
6 7 8
59 60
6 7 8
29 37
84 85
80
49
24
13
24
63
13
39
96
63
39
13
63
13
39
96
96
60
18
37
68
37
24
18
63
19
39
69
39
68
21
43
70
43
PPVCORE_S0_MCP_REG
69
22
45
77
45
70
24
47
80
47
6600 MA
77
25
48
81
48
51
82
PP1V1_S0GPU_REG
PPCPUVTT_S0
80
28
49
81
49
55
84
4500 mA
PPCPUVTT_S0
1182 mA
PPCPUVTT_S0
1034 mA
241 mA max load

84 85 96
68 69 70 77 80 81 82
43 45 47 48 49 51 55
18 19 21 22 24 25 28
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
6 7 8 9 10 11 12 13 14 17 18 20
22 24 25 63 67
6 7 8
22 24
6 7 8
22 24
9 10 11 12 13 14 17 18 20
25 63 67
9 10 11 12 13 14 17 18 20
25 63 67
6 7 8 9 10 11 12 13 14 17 18 20
22 24 25 63 67
78 70 8
81
51
25
18
22
68
18
43
84
68
43
18
68
18
43
82
55
28
19
8 7
69
19
45
85
69
45
19
69
19
45
59 60
6 7 8
29 37
84 85
59 60
6 7 8
29 37
84 85
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
63
13
39
96
63
13
39
96
PP1V2R1V05_S5
70
21
47
96
70
47
21
70
21
47
PP1V2R1V05_S5
8 71 73 76 78 83
8 71 73 76 78 83
8 71 73 76 78 83
8 71 73 76 78 83
8 71 73 76 78 83
PP1V8_GPUIFPX
8 70 78
8 70 78
77
48
22
77
22
48
80
49
24
80
24
49
81
51
25
81
25
51
82
55
28
82
28
55
7 8 22 24 34 68
VOLTAGE=1.05V
MAKE_BASE=TRUE
77 80 81 82
22 24 25 28
48 49 51 55
105 mA/241 mA
139 mA/
0 mA
75 74 73 72 47 9 8
PP1V2R1V05_S5
PP1V2R1V05_S5
PP1V8_S0GPU_ISNS
PP1V8_S0GPU_ISNS
PP1V8_S0GPU_ISNS
PP1V8_S0GPU_ISNS
PP1V8_S0GPU_ISNS
8 27 65
MIN_LINE_WIDTH=2 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE
79 72 46 8
PPVCORE_GPU
8 9 47 72 73 74 75
8 9 47 72 73 74 75
8 9 47 72 73 74 75
PPVCORE_GPU
8 46 72 79
PPVCORE_GPU
8 46 72 79
PP1V8_S0GPU_ISNS_R
8 47 83
7 8 28 29 65 70
7 8 28 29 65 70
7 8 28 29 65 70
83 47 8
PP1V8_S0GPU_ISNS_R
VOLTAGE=1.8V
MAKE_BASE=TRUE
ENET Rails
PP1V8_S0GPU_ISNS_R
PP1V2R1V05_ENET
8 47 83
7 8 18 24 33 34 37
MIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
80 81 82 84 85 96
37 39 43 45 47 48 49 51 55
13 18 19 21 22 24 25 28 29
8
59 60 63 68 69 70 77
84 685 96
59 760 63 68 69 70 77 80 81 82
29 37 39 43 45 47 48 49 51 55
6 7 8 13 18 19 21 22 24 25 28
59 60 63 68 69 70 77 80 81 82
6 7 8 13 18 19 21 22 24 25 28
29 37 39 43 45 47 48 49 51 55
84 85 96
8 9 47 72 73 74 75
VOLTAGE=1.0V
MAKE_BASE=TRUE
7 8 28 29 65 70
OR 0.75V
68 69 70 77 80 81 82
18 19 21 22 24 25 28
43 45 47 48 49 51 55
8 9 47 72 73 74 75
VOLTAGE=1.8V
MAKE_BASE=TRUE
7 8 22 24 34 68
VOLTAGE=0.75V
MAKE_BASE=TRUE
68 69 70 77 80 81 82
18 19 21 22 24 25 28
43 45 47 48 49 51 55
B
PP1V8_S0GPU_ISNS
7 8 22 24 34 68
PPVTTDDR_S3
PP1V2R1V05_ENET
PP1V2R1V05_ENET
7 8 18 24 33 34 37
PP1V2R1V05_ENET
PP1V2R1V05_ENET
PP1V2R1V05_ENET
PP1V2R1V05_ENET
Power Aliases
7 8 18 24 33 34 37
SYNC_MASTER=(MASTER)
7 8 18 24 33 34 37
SYNC_DATE=(MASTER)
7 8 18 24 33 34 37
7 8 18 24 33 34 37

7 8 11 12 46 63
PP3V3_ENET_PHY
7 8 22 24 46 66
87 84 8
PP1V2_S0
PP1V2_S0
8 84 87
VOLTAGE=1.2V
MAKE_BASE=TRUE
7 8 22 24 46 66
PP1V2_S0
PP3V3_ENET_PHY
7 8 18 24 33 34
VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_ENET_PHY
7 8 18 24 33 34
PP3V3_ENET_PHY
7 8 18 24 33 34
SIZE
DRAWING NUMBER
8 84 87
APPLE INC.
REV.
051-7892
SCALE
SHT
NONE
8 71 73 76 78 83
PP1V8_GPUIFPX
85 96
47 48 49 51 55 59
6 7 8 13 18 19
21 22 24 25 28 29 37 39 43 45
60 63 68 69 70 77 80 81 82 84
7 8 11 12 46 63
8 71 73 76 78 83
84 85 96
59 60 63 68 69
29 37 39 43 45
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
8 71 73 76 78 83
VOLTAGE=1.8V
MAKE_BASE=TRUE
68 69 70 77 80 81 82
18 19 21 22 24 25 28
43 45 47 48 49 51 55
PPVTTDDR_S3
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP1V8_GPUIFPX
68 69 70 77 80 81 82
18 19 21 22 24 25 28
43 45 47 48 49 51 55
80 81 82 84 85 96
47 48 49 51 55 59 60 63 68 69
6 7 8 13 18 19 21 22 24 25 28
29 37 39 43 45
70 77
65 27 8
59 60 63 68 69 70 77 80 81 82
6 7 8 13 18 19 21 22 24 25 28
29 37 39 43 45 47 48 49 51 55
84 85 96
68 69 70 77 80 81 84
39 43 45 47 48 49 51 55 59 60
8 13 18 19 21 22 24 25 28 29
6 85 96 85 96
7 80 81 82 84
37 37 39 43 45 47 48 49 51 55
63 13 18 19 21 22 24 25 28 29
82 8
59 60 63 68 69 70 77
84 685 96
59 760 63 68 69 70 77 80 81 82
29 37 39 43 45 47 48 49 51 55
6 7 8 13 18 19 21 22 24 25 28
59 60 63 68 69 70 77 80 81 82
6 7 8 13 18 19 21 22 24 25 28
29 37 39 43 45 47 48 49 51 55
84 85 96
PP3V3_S0
PP1V1_S0GPU_REG
PP1V1_S0GPU_REG
PP1V1_S0GPU_REG
PP1V1_S0GPU_REG
PP1V1_S0GPU_REG
PP1V1_S0GPU_REG
PP1V1_S0GPU_REG
PP1V1_S0GPU_REG
6 7 8 9 10 11 12 13 14 17 18 20
22 24 25 63 67
PPCPUVTT_S0
PPCPUVTT_S0
PPCPUVTT_S0
PPCPUVTT_S0
8 71 73 76 78 83
VOLTAGE=1.1V
MAKE_BASE=TRUE
6 7 8 9 10 11 12 13 14 17 18 20
22 24 25 63 67
59 60 63 68 69 70 77 80 81 82
6 7 8 13 18 19 21 22 24 25 28
29 37 39 43 45 47 48 49 51 55
84 85 96
PP3V3_S0
PP3V3_S0
PP1V1_S0GPU_REG
83 78 76 73 71
6 7 8 9 10 11 12 8
13 14 17 18 20 22 24 25 63 67
VOLTAGE=1.05V
MAKE_BASE=TRUE
82 84 85 96
48 49 51 55 59 60 63
18 19 21 22 24 25 28
34 33 24 18 8 7
PPVCORE_S0_MCP_REG
VOLTAGE=1.05V
MAKE_BASE=TRUE
8 36 37 38
7 8 11 12 16 24 28 29 39 68 69
70
PPCPUVTT_S0
MAKE_BASE=TRUE
8 36 37 38
VOLTAGE=3.3V
MAKE_BASE=TRUE
7 8 11 12 16 24 28 29 39 68 69
70
PPCPUVTT_S0
8 36 37
7 8 28 29 30 65 70
PP1V8R1V5_S0_FET
PP1V8R1V5_S0_FET
PP1V8R1V5_S0_FET
PP1V8R1V5_S0_FET
PP1V8R1V5_S0_FET
PP1V8R1V5_S0_FET
PPCPUVTT_S0
PP1V0_FW
7 8 28 29 30 65 70
PP1V8R1V5_S0_FET
7 8 21 27 31 32 45 50 52 70
8 36 37
VOLTAGE=1.05V
MAKE_BASE=TRUE
7 8 21 27 31 32 45 50 52 70
50 52 70
7 8 21 27 31 32
18 17 14 13 12 11 10 9 8 7 6 45
67 63 25 24 22 20
8 37 38
PP1V0_FW
7 8 28 29 30 65 70
7 8 21 27 31 32 45 50 52 70
VOLTAGE=3.3V
MAKE_BASE=TRUE
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE
PPVCORE_S0_MCP_REG
7 8 28 29 30 65 70
37 36 8
8 37 38
MAKE_BASE=TRUE
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
22 8 7
66 46 24
PPVP_FW
PPVP_FW
7 8 18 25 55 69 70 84 87
VOLTAGE=1.5V
MAKE_BASE=TRUE
7 8 18 20 22 24 26 30 34 37 38
44 54 64 68 69 70 82 87 96
8 37 38
VOLTAGE=12.6V
MAKE_BASE=TRUE
7 8 18 25 55 69 70 84 87
PP1V8R1V5_S0_FET
7 8 18 20 22 24 26 30 34 37 38
44 54 64 68 69 70 82 87 96
7 8 18 20 22 24 26 30 34 37 38
44 54 64 68 69 70 82 87 96
24 20 8
PP3V3_S0
PP5V_S0
PPVCORE_S0_CPU
7 8 18 20 22 24 26 30 34 37 38
44 54 64 68 69 70 82 87 96
82 87 96
30 34 37 38 44 54 64 68 69 70
7 8 18 20 22 24
68 39 29 28 24 16 12 11 8 7 26
70 69
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
11 8 7
63 46 12
7 8 18 20 22 24 26 30 34 37 38
44 54 64 68 69 70 82 87 96
7 8 18 20 22 24 26 30 34 37 38
44 54 64 68 69 70 82 87 96
PPVP_FW
PPVP_FW
7 8 18 25 55 69 70 84 87
PP1V8R1V5_S3
PP1V8R1V5_S3
PP1V8R1V5_S3
PP1V8R1V5_S3
PP1V8R1V5_S3
7 8 18 20 22 24 26 30 34 37 38
44 54 64 68 69 70 82 87 96
PP3V3_S3
7 8 18 25 55 69 70 84 87
8
38 37
PP1V8R1V5_S3
7 8 18 20 22 24 26 30 34 37 38
44 54 64 68 69 70 82 87 96
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP1V8_S0
PP1V8_S0
PP1V8_S0
PP1V8_S0
VOLTAGE=1.5V
MAKE_BASE=TRUE
7 8 18 20 22 24 26 30 34 37 38
44 54 64 68 69 70 82 87 96
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
7 8 21 22 26 40
42 43 44 45 46 50 61 62 64 69
PP5V_S3
PP1V8R1V5_S3
PP3V3_S3
PP3V3_S3
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
PP5V_S3
PP5V_S0
96
18 20 22 24 26 30 34 37 38
7
44 54 64 68 69 70 82 87
82 887 96
30 34 37 38 44 54 64 68 69 70
7 8 18 20 22 24
70 65 30 29 28 8 7 26
7 8 18 20 22 24 26 30 34 37 38
44 54 64 68 69 70 82 87 96
PP3V3_S5
"FW" (FireWire) Rails
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
85 83 70
51 49 44 39 8 7
67 66 63
500 mA max supply
7 8 18 25 55 69 70 84 87
VOLTAGE=1.8V
MAKE_BASE=TRUE
7 8 18 20 22 24 26 30 34 37 38
44 54 64 68 69 70 82 87 96
PP3V3_S3
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
VOLTAGE=5.0V
MAKE_BASE=TRUE
8 61 62
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
5V Rails
PP5V_S3
1.8V/DDR 1.5V Rails

PP1V8_S0
190 mA
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
VOLTAGE=3.3V
MAKE_BASE=TRUE
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
79 70
53 51 43
31 9 8 7
41 40 39
65 64 55
PP3V3_S3
8 61 62
PP3V42_G3H
PP3V42_G3H
PP1V8_S0
69 70 82 87 96
7 8 18 20 22
24 26 30 34 37 38 44 54 64 68
8 46 63
70 52 50 45 32 31 27 21 8 7
62 61 8
3.3V-2.5V Rails
PP3V3_S5
VOLTAGE=3.3V
MAKE_BASE=TRUE
7 8 37 46 61 62 64 65 66 67 79
83 86
PPBUS_G3H
PPBUS_G3H
7 8 37 46 61
62 64 65 66 67 79 83 86
7 8 37 46 61 62 64 65 66 67 79
83 86
PPBUS_G3H
PPBUS_G3H
63 46 8
A.0.0
OF
8
97
CPU signals
Thermal Module Holes
ZT0981
63 9
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
88 11
2.0DIA-TALL-EMI-MLB-M97-M98
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0982
ZT0985
SH0900
SM
88 10
70 65 26
STDOFF-4.5OD.98H-1.1-3.48-TH
SM
Left CPU
TM Hole
ZT0930
SH0916
STDOFF-4.5OD.98H-1.1-3.48-TH
SM
10
90 71
PEG_R2D_C_N<0..15>
10
GPU_FB_B_VREF_DIV
MAKE_BASE=TRUE
GPU_FB_B_VREF_DIV
LCD_BKLT_EN
86 84 9
R09701
R09901
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
200
R0960
62
5%
1/16W
MF-LF
2 402
3R2P5
OUT
88 14 10
OUT
29 9
DP_IG_ML_P<3>
DP_IG_ML_N<3>
DP_IG_ML_P<2..0>
150
DP_IG_ML_N<2..0>
DP_IG_DDC_CLK
TP_MEM_B_A<15>
NC_USB_EXTCP
90 18 9
NC_LVDS_IG_B_CLKN
STDOFF-4.0OD3.0H-TH
18 9
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_BKL_PWM
NO_TEST=TRUE
MAKE_BASE=TRUE
150
1%
1/16W
MF-LF
2 402
DP_IG_DDC_DATA
DP_IG_HPD
MAKE_BASE=TRUE
9 29
NC_USB_EXTCP
9 20 91
NC_USB_EXTCN
9 20 91
TP_CPU_PECI_MCP
9 14
MAKE_BASE=TRUE
37 19 9
FW_PLUG_DET_L
37 36 9
FW643_WAKE_L
PM_ALL_GPU_PGOOD
EG_RESET_L
84 19 9 6
JTAG_GMUX_TDI
84 19 9 6
JTAG_GMUX_TMS
84 17 9 6
JTAG_GMUX_TDO
GND_CHASSIS_AUDIO_JACK
9 17 90
90 17 9
TP_PCIE_EXCARD_D2R_N
90 17 9
TP_PCIE_EXCARD_R2D_C_P
9 17 90
9 17 90
MAKE_BASE=TRUE
90 17 9
TP_PCIE_EXCARD_R2D_C_N
17 9
TP_PCIE_EXCARD_PRSNT_L
9 17 90
MAKE_BASE=TRUE
9 18 77 81
9 17
MAKE_BASE=TRUE
9 18 81
TP_EXCARD_CLKREQ_L
TP_EXCARD_CLKREQ_L
90 17 9
TP_PCIE_CLK100M_EXCARD_P
90 17 9
TP_PCIE_CLK100M_EXCARD_N
17 9
9 69 83 84
9 17
MAKE_BASE=TRUE
9 17 90
MAKE_BASE=TRUE
9 84
9 17 90
MAKE_BASE=TRUE
9 71 84
JTAG_GMUX_TDI
6 9 19 84
JTAG_GMUX_TMS
6 9 19 84
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AUDIO ALIASES
SM
JTAG_GMUX_TDO
6 9 17 84
55 53 51 43 41 40 39 31 8 7
79 70 65 64
MAKE_BASE=TRUE
LVDS_IG_BKL_ON
LVDS_IG_BKL_ON
PP5V_S3
PP5V_S3_AUDIO_AMP
ETHERNET ALIASES
LVDS_IG_PANEL_PWR
LVDS_IG_PANEL_PWR
58
VOLTAGE=5V
XW0901
9 18 84
MAKE_BASE=TRUE
84 18 9
TP_PCIE_EXCARD_D2R_P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
EG_RESET_L
9 36 37
9 18 77 81
TP_LVDS_MUX_SEL_EG
MAKE_BASE=TRUE
9 19 37
FW643_WAKE_L
MAKE_BASE=TRUE
PM_ALL_GPU_PGOOD
TP_LVDS_MUX_SEL_EG
FW_PLUG_DET_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
R0980
18
DP_IG_HPD
84 71 9
9 18 84
MAKE_BASE=TRUE
34 21 9
34 21 9
PM_SLP_RMGT_L
PM_SLP_RMGT_L
9 21 34
MAKE_BASE=TRUE
TP_PP3V3_ENET_PHY_VDDREG TP_PP3V3_ENET_PHY_VDDREG
9 33
MAKE_BASE=TRUE
NC_LVDS_IG_B_CLKP
9 18 90
NC_LVDS_IG_B_CLKN
9 18 90
MCP79 PCIe PRSNT# Straps

These need work.
NC_LVDS_IG_BKL_PWM
NC_RTL8211_REGOUT
NC_RTL8211_REGOUT
MAKE_BASE=TRUE
9 33
NO_TEST=TRUE
GND
Add other PRSNT# straps if needed. .
9 18
NO STUFF
90 18 9
ZT0935
NC_LVDS_IG_A_DATAP<3>
MAKE_BASE=TRUE
STDOFF-4.0OD3.0H-TH
90 18 9
90 18 9
90 18 9
NO_TEST=TRUE
NC_LVDS_IG_A_DATAN<3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_B_DATAN<3>
NO_TEST=TRUE
MAKE_BASE=TRUE
9 18 90
9 18 90
NC_LVDS_IG_B_DATAP<3>
9 18 90
9 18 90
NO_TEST=TRUE
MAKE_BASE=TRUE
ZT0951
4.0OD1.85H-M1.6X0.35
R0925
Bosses
ZT0952
GND
PCIE_FW_PRSNT_L
5%
1/16W
MF-LF
402
NO STUFF
ZT0988
ZT0954
4.0OD1.85H-M1.6X0.35
18 9
MCP_MII_PD
OUT
GND
17
VOLTAGE=0V
R0926
1
EG_CLKREQ_OUT_L
IN
84
5%
1/16W
MF-LF
402
MCP_MII_PD
9 18
MCP_MII_PD
9 18
MAKE_BASE=TRUE
ZT0989
GND
Digital Ground
PEG_PRSNT_L
MAKE_BASE=TRUE
17 37
R0927
4.0OD1.5H-M1.6X0.35
ZT0953
STDOFF-4.5OD.98H-1.1-3.48-TH
OUT
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
4.0OD1.5H-M1.6X0.35
Signal Aliases
SYNC_MASTER=(MASTER)
STDOFF-4.5OD.98H-1.1-3.48-TH
R0930
MCP_MII_PD
9 18
5%
1/16W
MF-LF
2 402
ZT0991
STDOFF-4.5OD.98H-1.1-3.48-TH
SYNC_DATE=(MASTER)
47K


SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-7892
SCALE
SHT
NONE
PM_SLP_RMGT_L
59
NO_TEST=TRUE
TP_CPU_PECI_MCP
33 9
ZT0934
9 28
TP_MEM_B_A<15>
UNUSED EXPRESS CARD LANE
=MCP_HDMI_TXD_N<0..2>
DP_IG_DDC_CLK
DP_IG_DDC_DATA
84 9
NO STUFF
NO_TEST=TRUE
42
TP_MEM_A_A<15>
NO_TEST=TRUE
NC_USB_EXTCN
MAKE_BASE=TRUE
SM
MAKE_BASE=TRUE
SMC_MCP_SAFE_MODE
TP_MEM_A_A<15>
SH0914
NC_LVDS_IG_B_CLKP
MAKE_BASE=TRUE
90 17 9
18
MAKE_BASE=TRUE
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
18
=MCP_HDMI_TXD_P<0..2>
MAKE_BASE=TRUE
84 83 69 9
SH0917
18
=MCP_HDMI_TXC_N
90 18 9
MAKE_BASE=TRUE
MAKE_BASE=TRUE
81 18 9
84 18 9
9 18 84
R0903
MCP_SPKR
MAKE_BASE=TRUE
81 77 18 9
=MCP_HDMI_TXC_P
MAKE_BASE=TRUE
81 77 18 9
CPU_DPRSTP_L
FSB_BREQ0_L
FSB_CPURST_L
CPU_INTR
CPU_NMI
GND
GMUX_INT
MAKE_BASE=TRUE
MAKE_BASE=TRUE
9 84 86
MAKE_BASE=TRUE
90 81
R09501
ZT0990
28 9
LCD_BKLT_EN
MAKE_BASE=TRUE
90 81
NO STUFF
GMUX_INT
5%
1/16W
MF-LF
402
GMUX ALIASES
90 81
NO STUFF
SH0901
NO STUFF
OUT
21
SH0913
9 27 75
220
88 14 10
MAKE_BASE=TRUE
14 9
SM
88 14 13 10
RTL8211_CLK125
SM
NO STUFF
OUT
RTL8211_CLK125
9 27 75
PPCPUVTT_S0
88 14 10
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE
Exist in MRB but not Intel designs. Here for CYA.

If found to be necessary, will move to page14.csa
GND
9 20 91
91 20 9
Extra FSB Pull-ups
OUT
NC_USB_EXCARDN
MAKE_BASE=TRUE NO_TEST=TRUE
91 20 9
90 81
88 63 14 10
17
9 20 91
NC_USB_EXCARDN
MAKE_BASE=TRUE
SH0911
3R2P5
=PEG_R2D_C_N<0..15>
MAKE_BASE=TRUE
9 20 32 96
91 20 9
2 402
SM
ZT0960
17
9 20 32 96
USB_CARDREADER_N
NC_USB_EXCARDP
SM
GND
GND
SL-3.1X2.7-6CIR-NSP
=PEG_R2D_C_P<0..15>
USB_CARDREADER_P
NC_USB_EXCARDP
3R2P5
17 14 13 12 11 10 8 7 6
67 63 25 24 22 20 18
USB_CARDREADER_N
91 20 9
5%
1/16W
MF-LF
SH0912
17
9 20 91
22
ZT0950
TH
USB_CARDREADER_P
9 20 91
MAKE_BASE=TRUE
R0931
9 27 74
9 20 91
NC_USB_MINIP
NC_USB_MININ
MAKE_BASE=TRUE
96 32 20 9
GPU_FB_A_VREF_DIV
9 20 91
NC_USB_EXTDN
NO_TEST=TRUE
MAKE_BASE=TRUE
9 27 74
ZT0940
17
MAKE_BASE=TRUE
SM
MAKE_BASE=TRUE
1%
1/16W
MF-LF
402
PEG_R2D_C_P<0..15>
NC_USB_EXTDP
NC_USB_MINIP
MAKE_BASE=TRUE
NC_USB_MININNO_TEST=TRUE
84 18 9
R0901
90 71
=PEG_D2R_N<0..15>
GPU_FB_A_VREF_DIV
GND
PEG_D2R_N<0..15>
33 9
1%
1/16W
MF-LF
402
Frame Holes
90 71
NO_TEST=TRUE
MAKE_BASE=TRUE
96 32 20 9
=PEG_D2R_P<0..15>
MAKE_BASE=TRUE
SH0910
R0900
3R2P5
PEG_D2R_P<0..15>
SM
1
ZT0915
9 26 65 70
91 20 9
90 71
SH0904
75 74 73 72 47 8
91 20 9
MEM_VTT_EN
STDOFF-4.5OD.98H-1.1-3.48-TH
MEM_VTT_EN
NO_TEST=TRUE
NC_USB_EXTDN
14
GPU signals
SM
TOP MCP LEFT

TM Hole
PP1V8_S0GPU_ISNS
=MCP_BSEL<0..2>
MAKE_BASE=TRUE
ZT0986
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0987
91 20 9
CPU_BSEL<0..2>
NC_USB_EXTDP
MAKE_BASE=TRUE
63 88
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
SH0903
1
ZT0980
Right CPU
TM Hole
IMVP6_VID<0..6>
STDOFF-4.5OD.98H-1.1-3.48-TH
9 63
91 20 9
CPU_VID<0..6>
MAKE_BASE=TRUE
Top GPU Right

TM Hole
ZT0983
TP_IMVP6_CLKEN_L
MAKE_BASE=TRUE
SH0902
ZT0984
TP_IMVP6_CLKEN_L
A.0.0
OF
9
97
OMIT
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14
BI
88 14
BI
88 14
BI
88 14
BI
88 14
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14
BI
88 14
BI
88 14
BI
88 14
BI
88 14 7
BI
88 14
IN
88 14
OUT
88 14
IN
88 14
IN
88 14 9
IN
88 14 9
88 14
IN
IN
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
K3
H2
K2
J3
L1
REQ0*
REQ1*
REQ2*
REQ3*
REQ4*
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADSTB_L<1>
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
CPU_A20M_L
CPU_FERR_L
CPU_IGNNE_L
BR0*
D5
C6
B4
A3
M4
N5
T2
V3
B2
F6
D2
D22
D3
FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L
BI
14 88
F1
FSB_BREQ0_L
BI
9 14 88
CPU_IERR_L
CPU_INIT_L
IN
BI
14 88
BI
14 88
BI
14 88
BI
14 88
PPCPUVTT_S0
IERR*
INIT*
D20
B3
LOCK*
H4
FSB_LOCK_L
RESET*
RS0*
RS1*
RS2*
TRDY*
C1
F3
F4
G3
G2
FSB_CPURST_L
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L
HIT*
HITM*
G6
E4
FSB_HIT_L
FSB_HITM_L
BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*
TCK
TDI
TDO
TMS
TRST*
DBR*
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L
88
7 14 88
BI
6 7 8 9 10 11 12 13 14 17 18 20
22 24 25 63 67
R1002
PLACE TESTPOINT ON
FSB_IERR_L WITH A GND
0.1" AWAY
54.9
1%
1/16W
MF-LF
2 402
14 88
7 14 88
IN
9 13 14 88
IN
14 88
IN
14 88
IN
14 88
IN
14 88
OMIT
A17*
A18*
A19*
A20*
A21*
A22*
A23*
A24*
A25*
A26*
A27*
A28*
A29*
A30*
A31*
A32*
A33*
A34*
A35*
ADSTB1*
STPCLK*
LINT0
LINT1
SMI*
BI
7 14 88
BI
7 14 88
BI
13 88
BI
13 88
BI
13 88
BI
13 88
BI
13 88
PPCPUVTT_S0
6 7 8 9 10 11 12 13 14 17 18 20
22 24 25 63 67
88 14 7
BI
88 14 7
BI
R10031
88 14 7
BI
88 14 7
BI
1%
1/16W
MF-LF
402 2
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
54.9
BI
13 88
IN
6 10 13 88
88 14 7
BI
IN
6 10 13 88
88 14 7
BI
6 10 88
88 14 7
BI
IN
6 10 13 88
88 14 7
BI
IN
6 10 13 88
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
OUT
OUT
13 26
R1004
68
5%
1/16W
MF-LF
2 402
THERMAL
PROCHOT*
THERMDA
THERMDC
A6 A20M*
A5 FERR*
C4 IGNNE*
CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L
TP_CPU_RSVD0
TP_CPU_RSVD1
TP_CPU_RSVD2
TP_CPU_RSVD3
TP_CPU_RSVD4
TP_CPU_RSVD5
TP_CPU_RSVD6
TP_CPU_RSVD7
TP_CPU_RSVD8
DEFER*
DRDY*
DBSY*
H5
F21
E1
BI
THERMTRIP*
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
D21
A24
B25
CPU_PROCHOT_L
CPU_THERMD_P
CPU_THERMD_N
C7
PM_THRMTRIP_L
OUT
OUT
48 96
OUT
48 96
OUT
14 43 88
H CLK
BCLK0
BCLK1
A22
A21
FSB_CLK_CPU_P
FSB_CLK_CPU_N
14 43 63 88
PM_THRMTRIP#
SHOULD CONNECT TO ICH AND
GMCH WITHOUT T (NO STUB)
IN
14 88
88 14 7
BI
IN
14 88
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
88 14 7
BI
18 17 14 13 12 11 10 9 8 7 6
67 63 25 24 22 20
PPCPUVTT_S0
1
R1005
1K
1%
1/16W
MF-LF
402 2
R10061
R1020
XDP_TMS
88 13 10 6
XDP_TDI
88 10 6
54.9 2
1%
1/16W
MF-LF
402
XDP_TDO
2.0K
PPCPUVTT_S0
6 7 8 9 10 11 12 13 14 17 18 20
22 24 25 63 67
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402
R1021
1
54.9 2
NOSTUFF
1
C1000
0.1uF
10%
2 16V
X5R
402
R1024
PLACE C1000 CLOSE TO CPU_TEST4

PIN. MAKE SURE CPU_TEST4 IS
REFERENCED TO GND
54.9 2
PLACEMENT_NOTE=Place R1024 near ITP connector (if present) 1%

1/16W
MF-LF
402
BI
88 14 7
BI
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
D0*
D1*
D2*
D3*
D4*
D5*
D6*
D7*
D8*
D9*
D10*
D11*
D12*
D13*
D14*
D15*
DSTBN0*
DSTBP0*
DINV0*
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_DSTB_L_N<1>
FSB_DSTB_L_P<1>
FSB_DINV_L<1>
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
D16*
D17*
D18*
D19*
D20*
D21*
D22*
D23*
D24*
D25*
D26*
D27*
D28*
D29*
D30*
D31*
DSTBN1*
DSTBP1*
DINV1*
88 9
OUT
88 9
OUT
88 9
OUT
CPU_GTLREF
CPU_TEST1
CPU_TEST2
TP_CPU_TEST3
CPU_TEST4
TP_CPU_TEST5
TP_CPU_TEST6
TP_CPU_TEST7
CPU_BSEL<0>
CPU_BSEL<1>
CPU_BSEL<2>
AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21
R1023
88 13 10 6
XDP_TRST_L
649
FCBGA
2 OF 4
D32*
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*
DSTBN2*
DSTBP2*
DINV2*
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<2>
D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*
DSTBN3*
DSTBP3*
DINV3*
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<3>
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
BI
7 14 88
LAYOUT NOTE:
COMP0,2 CONNECT WITH ZO=27.4OHM,
MAKE TRACE LENGTH SHORTER THAN 0.5".
COMP1,3 CONNECT WITH ZO=55OHM,
MAKE TRACE LENGTH SHORTER THAN 0.5".
R1016
1
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL0
BSEL1
BSEL2
MISC
COMP0
COMP1
COMP2
COMP3
R26
U26
AA1
Y1
DPRSTP*
DPSLP*
DPWR*
PWRGOOD
SLP*
PSI*
E5
B5
D24
D6
D7
AE6
88
88
88
88
54.9 2
1%
1/16W
MF-LF
402
CPU_COMP<0>
CPU_COMP<1>
CPU_COMP<2>
CPU_COMP<3>
CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L
CPU_PSI_L
1%
1/16W
MF-LF
402
R1017
1
R1019
54.9 2
1
9 14 63 88
IN
14 88
IN
14 88
IN
13 14 88
IN
14 88
OUT
R1018
1
IN
27.4 2
27.4 2
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
63
R1030
1
54.9 2
1
XDP_TCK
PENRYN
NOSTUFF
R1022
88 13 10 6
U1000
0.5" MAX LENGTH FOR CPU_GTLREF

88 27
88 13 10 6
88 14 7
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_DSTB_L_N<0>
FSB_DSTB_L_P<0>
FSB_DINV_L<0>
DATA GRP 2
BI
FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L
DATA GRP 3
BI
88 14 7
H1
E2
G5
DATA GRP 0
88 14 7
FCBGA
1 OF 4
ADS*
BNR*
BPRI*
DATA GRP 1
BI
PENRYN
CONTROL
88 14 7
U1000
XDP/ITP SIGNALS
BI
A3*
A4*
A5*
A6*
A7*
A8*
A9*
A10*
A11*
A12*
A13*
A14*
A15*
A16*
ADSTB0*
ADDR GROUP0
88 14 7
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_ADSTB_L<0>
ADDR GROUP1
BI
ICH
BI
88 14 7
RESERVED
88 14 7
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
NOSTUFF
1
R1012
1%
1/16W
MF-LF
402
1K
5%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
NOSTUFF
1
R1007
1K
5%
1/16W
MF-LF
2 402
CPU FSB
SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
10
97
(CPU CORE POWER)
PPVCORE_S0_CPU
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
OMIT
U1000
PENRYN
FCBGA
3 OF 4
VCC
VCC
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
7 8 11 12 46 63
Standard Voltage:
Low Voltage:
Ultra Low Voltage:
44.0 A (Design Target)
41.0 A (HFM)
30.4 A (LFM)
25.5 A (SuperLFM)
21.0 A (HFM)
18.7 A (LFM)
TBD A (SuperLFM)
TBD
TBD
A (HFM)
A (LFM)
27.4 A (Auto-Halt/Stop-Grant HFM)

17.0 A (Auto-Halt/Stop-Grant SuperLFM)
TBD
TBD
A (Auto-Halt/Stop-Grant HFM)
A (Auto-Halt/Stop-Grant SuperLFM)
TBD
TBD
A (Auto-Halt/Stop-Grant HFM)
A (Auto-Halt/Stop-Grant LFM)
27.4 A (Sleep HFM)

16.8 A (Sleep SuperLFM)
TBD
TBD
A (Sleep HFM)
A (Sleep SuperLFM)
TBD
TBD
A (Sleep HFM)
A (Sleep LFM)
25.0 A (Deep Sleep HFM)

16.0 A (Deep Sleep SuperLFM)
TBD
TBD
A (Deep Sleep HFM)

A (Deep Sleep SuperLFM)
TBD
TBD
A (Deep Sleep HFM)

A (Deep Sleep LFM)
11.5 A (Deeper Sleep)
TBD
A (Deeper Sleep)
TBD
A (Deeper Sleep)
TBD
A (Enhanced Deeper Sleep)
TBD
A (Enhanced Deeper Sleep)
9.4 A (Enhanced Deeper Sleep)
(CPU IO POWER 1.05V)
PPCPUVTT_S0
VCCP
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
6 7 8 9 10 12 13 14 17 18 20 22
24 25 63 67
4500 mA (before VCC stable)

2500 mA (after VCC stable)
(CPU INTERNAL PLL POWER 1.5V)
PP1V8R1V5_S0_FET
B26
VCCA C26
VID0
VID1
VID2
VID3
VID4
VID5
VID6
AD6
AF5
AE5
AF4
AE3
AF3
AE2
7 8 12 16 24 28 29 39 68 69
70
130 mA
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
OUT
9 88
OUT
9 88
OUT
9 88
OUT
9 88
OUT
9 88
OUT
9 88
OUT
9 88
PPVCORE_S0_CPU
7 8 11 12 46 63
R1100
100
1%
1/16W
MF-LF
2 402
PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.
VCCSENSE AF7
CPU_VCCSENSE_P
VSSSENSE AE7
CPU_VCCSENSE_N
OUT
63 88
OUT
63 88
R1101
100
1%
1/16W
MF-LF
2 402
PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
B1
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
OMIT
U1000
PENRYN
FCBGA
4 OF 4
VSS
VSS
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
CPU Power & Ground
SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
Current numbers from Merom for Santa Rosa EMTS, doc #22221.
REV.
051-7892
A.0.0
OF
11
97
CPU VCORE HF AND BULK DECOUPLING

63 46 11 8 7
PPVCORE_S0_CPU
4x 330uF, 20x 22uF 0805
CRITICAL
C1250 1
330UF
CRITICAL
CRITICAL
C1251 1
CRITICAL
C1200
20%
6.3V
X5R-CERM
603
C1211
CRITICAL
C1202
20%
6.3V
X5R-CERM
603
C1212
22UF
20%
2 6.3V
X5R-CERM
603
20%
20%
2.0V 2 3
2.0V 2 3
POLY-TANT
POLY-TANT
D2T-SM2
D2T-SM2
CRITICAL
C1201
22UF
330UF
CRITICAL
C1203
20%
6.3V
X5R-CERM
603
C1213
22UF
CRITICAL
C1204
20%
6.3V
X5R-CERM
603
C1214
22UF
CRITICAL
C1205
20%
6.3V
X5R-CERM
603
C1215
22UF
CRITICAL
C1206
20%
6.3V
X5R-CERM
603
C1216
22UF
22UF
CRITICAL
C1207
20%
6.3V
X5R-CERM
603
22UF
CRITICAL
C1208
20%
6.3V
X5R-CERM
603
22UF
C1209
22UF
20%
6.3V
X5R-CERM
603
PLACEMENT_NOTE=Place in CPU center cavity.

CRITICAL
C1252 1
330UF
CRITICAL
CRITICAL
C1253 1
CRITICAL
C1210
22UF
330UF
20%
20%
2.0V
2.0V
POLY-TANT 2 3 POLY-TANT 2 3
D2T-SM2
D2T-SM2
CRITICAL
22UF
20%
6.3V
X5R-CERM
603
CRITICAL
22UF
20%
6.3V
X5R-CERM
603
20%
6.3V
X5R-CERM
603
CRITICAL
22UF
2
CRITICAL
22UF
20%
6.3V
X5R-CERM
603
20%
6.3V
X5R-CERM
603
CRITICAL
22UF
2
20%
6.3V
X5R-CERM
603
CRITICAL
1
22UF
2
20%
6.3V
X5R-CERM
603
C1217
CRITICAL
1
22UF
2
20%
6.3V
X5R-CERM
603
C1218
CRITICAL
1
22UF
2
20%
6.3V
X5R-CERM
603
C1219
22UF
20%
6.3V
X5R-CERM
603

VCCP (CPU I/O) DECOUPLING

20 18 17 14 13 11 10 9 8 7 6
67 63 25 24 22
PPCPUVTT_S0
1x 470uF, 6x 0.1uF 0402
CRITICAL
C1235 1
C1236
0.1UF
470UF
20%
2 10V
CERM
402
20%
2.5V 2 3
POLY
D2T
C1237
0.1UF
20%
2 10V
CERM
402
C1238
0.1UF
20%
2 10V
CERM
402
C1239
0.1UF
20%
2 10V
CERM
402
C1240
0.1UF
20%
2 10V
CERM
402
C1241
0.1UF
20%
2 10V
CERM
402
WF: Consider sharing bulk cap with NB Vtt?
VCCA (CPU AVdd) DECOUPLING
B
69 68 39 29 28 24 16 11 8 7
70
PP1V8R1V5_S0_FET
B
1x 10uF, 1x 0.01uF
C1280 1
10uF
20%
6.3V 2
X5R
603
C1281
0.01UF
10%
2 16V
CERM
402
PLACEMENT_NOTE=Place near CPU pin B26.
CPU Decoupling & VID
SYNC_MASTER=M87_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
12
97
Mini-XDP Connector
NOTE: This is not the standard XDP pinout.
Use with 920-0620 adapter board to support CPU, MCP debugging.
MCP79-specific pinout
84 82 81 80 77 70 69 68 63 60
29 28 25 24 22 21 19 18 8 7 6
59 55 51 49 48 47 45 43 39 37
96 85
6
67 63 25 24 22
20 18 17 14 12 11 10 9 8 7
PP3V3_S0
PPCPUVTT_S0
XDP
CRITICAL
XDP_CONN
R13151
54.9
J1300
1%
1/16W
MF-LF
402 2
88 10
BI
88 10
BI
88 10
BI
88 10
IN
88 10
IN
88 10
IN
LTH-030-01-G-D-NOPEGS
F-ST-SM
XDP_BPM_L<5>
XDP_BPM_L<4>
OBSFN_A0
OBSFN_A1
XDP_BPM_L<3>
XDP_BPM_L<2>
OBSDATA_A0
OBSDATA_A1
XDP_BPM_L<1>
XDP_BPM_L<0>
OBSDATA_A2
OBSDATA_A3
TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1
XDP
R1399
88 14 10
IN
CPU_PWRGD
1K
OBSFN_B0
OBSFN_B1
TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1
OBSDATA_B0
OBSDATA_B1
TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3
OBSDATA_B2
OBSDATA_B3
XDP_PWRGD
XDP_OBS20
5%
1/16W
MF-LF
402
19
76 21 6
IN
OUT
PM_LATRIGGER_L
JTAG_MCP_TCK
91 45 29 28 21
BI
91 45 29 28 21
BI
SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK
OUT
XDP_TCK
88 10 6
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
SDA
SCL
TCK1
TCK0
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
JTAG_MCP_TDO_CONN
JTAG_MCP_TRST_L
OBSDATA_C0
OBSDATA_C1
MCP_DEBUG<0>
MCP_DEBUG<1>
BI
19 91
BI
19 91
OBSDATA_C2
OBSDATA_C3
MCP_DEBUG<2>
MCP_DEBUG<3>
BI
19 91
OBSFN_D0
OBSFN_D1
JTAG_MCP_TDI
JTAG_MCP_TMS
OUT
6 21
OUT
6 21
OBSDATA_D0
OBSDATA_D1
MCP_DEBUG<4>
MCP_DEBUG<5>
BI
19 91
BI
19 91
OBSDATA_D2
OBSDATA_D3
MCP_DEBUG<6>
MCP_DEBUG<7>
BI
19 91
BI
19 91
FSB_CLK_ITP_P
ITPCLK/HOOK4
FSB_CLK_ITP_N
ITPCLK#/HOOK5
VCC_OBS_CD
88 XDP_CPURST_L
RESET#/HOOK6
XDP_DBRESET_L
DBR#/HOOK7
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
XDP_TDO_CONN
TDO
XDP_TRST_L
TRSTn
XDP_TDI
TDI
XDP_TMS
TMS
XDP_PRESENT#
XDP
IN
OUT
BI
6
6 21 76
19 91
IN
14 88
IN
14 88
OUT
10 26
XDP
R1303
1
IN
1K
5%
1/16W
MF-LF
402
FSB_CPURST_L
IN
9 10 14 88
PLACEMENT_NOTE=Place close to CPU to minimize stub.
OUT
6 10 88
OUT
6 10 88
OUT
6 10 88
XDP
C1300 1
0.1uF
C1301
0.1uF
10%
16V 2
X5R
402
OBSFN_C0
OBSFN_C1
10%
2 16V
X5R
402
998-1571
Direction of XDP module

Please avoid any obstructions
on even-numbered side of J1300
eXtended Debug Port(MiniXDP)
SYNC_MASTER=M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
13
97
OMIT
U1400
MCP79-TOPO-B
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10 7
BI
88 10
BI
88 10
BI
88 10
BI
88 10
18 17 14 13 12 11 10 9 8 7 6
67 63 25 24 22 20
PPCPUVTT_S0
R14101
R14151
1%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
54.9
62
R1416
BI
88 10 7
BI
88 10 7
BI
88 10
BI
88 10
BI
88 10
BI
88 10
BI
88 10
BI
88 10 7
BI
88 10
BI
88 10 9
BI
62
5%
1/16W
MF-LF
2 402
88
88 43 10
IN
88 10
IN
PM_THRMTRIP_L
CPU_FERR_L
88 10
BI
88 10
BI
88 10 7
BI
88 10 7
BI
88 10 7
NO STUFF
1
R1420
1K
5%
1/16W
MF-LF
402 2
9
IN
IN
IN
NO STUFF
1
R1421
1K
5%
1/16W
MF-LF
402 2
IN
88 10
OUT
OUT
88 63 43 10
OUT
NO STUFF
1
R1422
1K
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
FSB_DINV_L<0>
T40 CPU_DSTBP0#
U40 CPU_DSTBN0#
V41 CPU_DBI0#
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
FSB_DINV_L<1>
W39 CPU_DSTBP1#
W37 CPU_DSTBN1#
V35 CPU_DBI1#
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_DINV_L<2>
N37 CPU_DSTBP2#
L36 CPU_DSTBN2#
N35 CPU_DBI2#
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_DINV_L<3>
M39 CPU_DSTBP3#
M41 CPU_DSTBN3#
J41 CPU_DBI3#
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
AC34
AE38
AE34
AC37
AE37
AE35
AB35
AF35
AG35
AG39
AE33
AG37
AG38
AG34
AN38
AL39
AG33
AL33
AJ33
AN36
AJ35
AJ37
AJ36
AJ38
AL37
AL34
AN37
AJ34
AL38
AL35
AN34
AR39
AN35
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>
AE36 CPU_ADSTB0#
AK35 CPU_ADSTB1#
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
AC38
AA33
AC39
AC33
AC35
CPU_REQ0#
CPU_REQ1#
CPU_REQ2#
CPU_REQ3#
CPU_REQ4#
FSB_ADS_L
FSB_BNR_L
FSB_BREQ0_L
FSB_BREQ1_L
FSB_DBSY_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_TRDY_L
AD42
AD43
AE40
AL32
AD39
AD41
AB42
AD40
AC43
AE41
CPU_ADS#
CPU_BNR#
CPU_BR0#
CPU_BR1#
CPU_DBSY#
CPU_DRDY#
CPU_HIT#
CPU_HITM#
CPU_LOCK#
CPU_TRDY#
TP_CPU_PECI_MCP
CPU_PROCHOT_L
E41
AJ41
AG43
AH40
CPU_PECI
CPU_PROCHOT#
CPU_THERMTRIP#
CPU_FERR#
5%
1/16W
MF-LF
2 402
=MCP_BSEL<2>
=MCP_BSEL<1>
=MCP_BSEL<0>
CPU_A3#
CPU_A4#
CPU_A5#
CPU_A6#
CPU_A7#
CPU_A8#
CPU_A9#
CPU_A10#
CPU_A11#
CPU_A12#
CPU_A13#
CPU_A14#
CPU_A15#
CPU_A16#
CPU_A17#
CPU_A18#
CPU_A19#
CPU_A20#
CPU_A21#
CPU_A22#
CPU_A23#
CPU_A24#
CPU_A25#
CPU_A26#
CPU_A27#
CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_A32#
CPU_A33#
CPU_A34#
CPU_A35#
FSB
BGA
(1 OF 11)
88 10 7
F42 CPU_BSEL2
D42 CPU_BSEL1
F41 CPU_BSEL0
(MCP_BSEL<2>)
(MCP_BSEL<1>)
(MCP_BSEL<0>)
Y43
W42
Y40
W41
Y39
V42
Y41
Y42
P42
U41
R42
T39
T42
T41
R41
T43
W35
AA37
W33
W34
AA36
AA34
AA38
AA35
U38
U36
U35
U33
U34
W38
R33
U37
N34
N33
R34
R35
P35
R39
R37
R38
L37
L39
L38
N36
N38
J39
J38
J37
L42
M42
P41
N41
N40
M40
H40
K42
H41
L41
H43
H42
K41
J40
H39
M43
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
CPU_BPRI# AA41
CPU_DEFER# AA40
FSB_BPRI_L
FSB_DEFER_L
OUT
10 88
OUT
10 88
BCLK_OUT_CPU_P G42
BCLK_OUT_CPU_N G41
FSB_CLK_CPU_P
FSB_CLK_CPU_N
OUT
10 88
OUT
10 88
BCLK_OUT_ITP_P AL43
BCLK_OUT_ITP_N AL42
FSB_CLK_ITP_P
FSB_CLK_ITP_N
OUT
13 88
OUT
13 88
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
BCLK_OUT_NB_P AL41
BCLK_OUT_NB_N AK42
88
88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
BI
7 10 88
FSB_CLK_MCP_P
FSB_CLK_MCP_N
Loop-back clock for delay matching.
R14301
49.9
1%
1/16W
MF-LF
402 2
R1435
49.9
1%
1/16W
MF-LF
2 402
88 10
OUT
88 10
OUT
88 10
OUT
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
PP1V05_S0_MCP_PLL_FSB
24
270 mA (A01)
206 mA
20 mA
29 mA
15 mA
88
88
88
R14311
49.9
1%
1/16W
MF-LF
402 2
R1436
AC41 CPU_RS0#
AB41 CPU_RS1#
AC42 CPU_RS2#
88
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND
AG27
AH27
AG28
AH28
+V_DLL_DLCELL_AVDD
+V_PLL_MCLK
+V_PLL_FSB
+V_PLL_CPU
AM39 BCLK_VML_COMP_VDD
AM40 BCLK_VML_COMP_GND
AM43 CPU_COMP_VCC
AM42 CPU_COMP_GND
49.9
1%
1/16W
MF-LF
2 402
BCLK_IN_N AK41
BCLK_IN_P AJ40
CPU_A20M#
CPU_IGNNE#
CPU_INIT#
CPU_INTR
CPU_NMI
CPU_SMI#
AF41
AH39
AH42
AF42
AG41
AH41
CPU_PWRGD AH43
CPU_RESET# H38
CPU_SLP#
CPU_DPSLP#
CPU_DPWR#
CPU_STPCLK#
CPU_DPRSTP#
AM33
AN33
AM32
AG42
AN32
CPU_A20M_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L
CPU_PWRGD
FSB_CPURST_L
FSB_CPUSLP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_STPCLK_L
CPU_DPRSTP_L
OUT
10 88
OUT
10 88
OUT
10 88
OUT
9 10 88
OUT
9 10 88
OUT
10 88
PPCPUVTT_S0
NO STUFF
6 7 8 9 10 11 12 13 14 17 18 20
22 24 25 63 67
R1440
150
MCP CPU Interface
5%
1/16W
MF-LF
2 402
OUT
OUT
9 10 13 88
OUT
10 88
OUT
10 88
OUT
10 88
OUT
10 88
OUT
9 10 63 88
SYNC_MASTER=T18_MLB
10 13 88

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
REV.
051-7892
A.0.0
OF
14
97
OMIT
OMIT
U1400
U1400
MCP79-TOPO-B
MCP79-TOPO-B
BGA
(2 OF 11)
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
BI
89 28
OUT
89 28
OUT
89 28
OUT
89 28
OUT
89 28
OUT
89 28
OUT
89 28
OUT
89 28
OUT
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>
AL8
AL9
AP9
AN9
AL6
AL7
AN6
AN7
AR6
AR7
AV6
AW5
AN10
AR5
AU6
AV5
AU7
AU8
AW9
AP11
AW6
AY5
AU9
AV9
AU11
AV11
AV13
AW13
AR11
AT11
AR14
AU13
AR26
AU25
AT27
AU27
AP25
AR25
AP27
AR27
AP29
AR29
AP31
AR31
AV27
AN29
AV29
AN31
AU31
AR33
AV37
AW37
AT31
AV31
AT37
AU37
AW39
AV39
AR37
AR38
AV38
AW38
AR35
AP35
MDQ0_63
MDQ0_62
MDQ0_61
MDQ0_60
MDQ0_59
MDQ0_58
MDQ0_57
MDQ0_56
MDQ0_55
MDQ0_54
MDQ0_53
MDQ0_52
MDQ0_51
MDQ0_50
MDQ0_49
MDQ0_48
MDQ0_47
MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MDQ0_42
MDQ0_41
MDQ0_40
MDQ0_39
MDQ0_38
MDQ0_37
MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32
MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27
MDQ0_26
MDQ0_25
MDQ0_24
MDQ0_23
MDQ0_22
MDQ0_21
MDQ0_20
MDQ0_19
MDQ0_18
MDQ0_17
MDQ0_16
MDQ0_15
MDQ0_14
MDQ0_13
MDQ0_12
MDQ0_11
MDQ0_10
MDQ0_9
MDQ0_8
MDQ0_7
MDQ0_6
MDQ0_5
MDQ0_4
MDQ0_3
MDQ0_2
MDQ0_1
MDQ0_0
MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>
AN5
AU5
AR10
AN13
AN27
AW29
AV35
AR34
MDQM0_7
MDQM0_6
MDQM0_5
MDQM0_4
MDQM0_3
MDQM0_2
MDQM0_1
MDQM0_0
MDQS0_7_P
MDQS0_7_N
MDQS0_6_P
MDQS0_6_N
MDQS0_5_P
MDQS0_5_N
MDQS0_4_P
MDQS0_4_N
MDQS0_3_P
MDQS0_3_N
MDQS0_2_P
MDQS0_2_N
MDQS0_1_P
MDQS0_1_N
MDQS0_0_P
MDQS0_0_N
MEMORY PARTITION 0
89 28
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
MRAS0# AV17
MCAS0# AP17
MWE0# AR17
MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_BA<0>
MBA0_2 AP23
MBA0_1 AP19
MBA0_0 AW17
MA0_14
MA0_13
MA0_12
MA0_11
MA0_10
MA0_9
MA0_8
MA0_7
MA0_6
MA0_5
MA0_4
MA0_3
MA0_2
MA0_1
MA0_0
BGA
(3 OF 11)
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
AL10
AL11
AR8
AR9
AW7
AW8
AP13
AR13
AV25
AW25
AU30
AU29
AT35
AU35
AU39
AT39
MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<0>
AR23
AU15
AN23
AW21
AN19
AV21
AR22
AU21
AP21
AR21
AN21
AV19
AU19
AT19
AR19
BI
28 89
89 29
BI
BI
28 89
89 29
BI
BI
28 89
89 29
BI
BI
28 89
89 29
BI
BI
28 89
89 29
BI
BI
28 89
89 29
BI
BI
28 89
89 29
BI
BI
28 89
89 29
BI
BI
28 89
89 29
BI
BI
28 89
89 29
BI
BI
28 89
89 29
BI
BI
28 89
89 29
BI
BI
28 89
89 29
BI
BI
28 89
89 29
BI
BI
28 89
89 29
BI
BI
28 89
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
OUT
28 89
89 29
BI
OUT
28 89
89 29
BI
OUT
28 89
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
OUT
28 89
89 29
BI
OUT
28 89
89 29
BI
OUT
28 89
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
OUT
28 89
TP_MEM_A_CLK2P
NC_MEM_A_CLK2N
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
28 89
OUT
28 89
OUT
28 89
OUT
28 89
MEMORY
CONTROL
0A
MCLK0A_2_P AW33
MCLK0A_2_N AV33
BI
28 89
OUT
OUT
89 29
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
89 29
BI
MCLK0A_1_P BA24
MCLK0A_1_N AY24
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
OUT
28 89
89 29
BI
OUT
28 89
89 29
BI
MCLK0A_0_P BB20
MCLK0A_0_N BC20
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
89 29
28 89
BI
OUT
OUT
28 89
MCS0A_1# AT15
MCS0A_0# AR18
MEM_A_CS_L<1>
MEM_A_CS_L<0>
MODT0A_1 AP15
MODT0A_0 AV15
MEM_A_ODT<1>
MEM_A_ODT<0>
MCKE0A_1 AU23
MCKE0A_0 AT23
MEM_A_CKE<1>
MEM_A_CKE<0>
89 29
BI
89 29
BI
OUT
28 89
89 29
OUT
OUT
28 89
89 29
OUT
89 29
OUT
OUT
28 89
89 29
OUT
OUT
28 89
89 29
OUT
89 29
OUT
OUT
28 89
89 29
OUT
OUT
28 89
89 29
OUT
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>
AT4
AT3
AV2
AV3
AR4
AR3
AU2
AU3
AY4
AY3
BB3
BC3
AW4
AW3
BA3
BB2
BB5
BA5
BA8
BC8
BB4
BC4
BA7
AY8
BA9
BB10
BB12
AW12
BB8
BB9
AY12
BA12
BC32
AW32
BA35
AY36
BA32
BB32
BA34
AY35
BC36
AW36
BA39
AY40
BA36
BB36
BA38
AY39
BB40
AW40
AV42
AV41
BA40
BC40
AW42
AW41
AT40
AT41
AP41
AN40
AU40
AU41
AR41
AP42
MDQ1_63
MDQ1_62
MDQ1_61
MDQ1_60
MDQ1_59
MDQ1_58
MDQ1_57
MDQ1_56
MDQ1_55
MDQ1_54
MDQ1_53
MDQ1_52
MDQ1_51
MDQ1_50
MDQ1_49
MDQ1_48
MDQ1_47
MDQ1_46
MDQ1_45
MDQ1_44
MDQ1_43
MDQ1_42
MDQ1_41
MDQ1_40
MDQ1_39
MDQ1_38
MDQ1_37
MDQ1_36
MDQ1_35
MDQ1_34
MDQ1_33
MDQ1_32
MDQ1_31
MDQ1_30
MDQ1_29
MDQ1_28
MDQ1_27
MDQ1_26
MDQ1_25
MDQ1_24
MDQ1_23
MDQ1_22
MDQ1_21
MDQ1_20
MDQ1_19
MDQ1_18
MDQ1_17
MDQ1_16
MDQ1_15
MDQ1_14
MDQ1_13
MDQ1_12
MDQ1_11
MDQ1_10
MDQ1_9
MDQ1_8
MDQ1_7
MDQ1_6
MDQ1_5
MDQ1_4
MDQ1_3
MDQ1_2
MDQ1_1
MDQ1_0
MEM_B_DM<7>
MEM_B_DM<6>
MEM_B_DM<5>
MEM_B_DM<4>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>
AT5
BA2
AY7
BA11
BB34
BB38
AY43
AR42
MDQM1_7
MDQM1_6
MDQM1_5
MDQM1_4
MDQM1_3
MDQM1_2
MDQM1_1
MDQM1_0
MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P
MDQS1_3_N
MDQS1_2_P
MDQS1_2_N
MDQS1_1_P
MDQS1_1_N
MDQS1_0_P
MDQS1_0_N
MEMORY PARTITION 1
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
AT2
AT1
AY2
AY1
BB6
BA6
BA10
AY11
BB33
BA33
BB37
BA37
BA43
AY42
AT42
AT43
MRAS1# AW16
MCAS1# BA15
MWE1# BA16
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MBA1_2 BB29
MBA1_1 BB18
MBA1_0 BB17
MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>
BA29
BA14
AW28
BC28
BA17
BB28
AY28
BA28
AY27
BA27
BA26
BB26
BA25
BB25
BA18
MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>
MA1_14
MA1_13
MA1_12
MA1_11
MA1_10
MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0
BI
29 89
BI
29 89
BI
29 89
BI
29 89
BI
29 89
BI
29 89
BI
29 89
BI
29 89
BI
29 89
BI
29 89
BI
29 89
BI
29 89
BI
29 89
BI
29 89
BI
29 89
BI
29 89
OUT
29 89
OUT
29 89
OUT
29 89
OUT
29 89
OUT
29 89
OUT
29 89
OUT
29 89
OUT
29 89
OUT
29 89
OUT
29 89
OUT
29 89
OUT
29 89
OUT
29 89
OUT
29 89
OUT
29 89
OUT
29 89
OUT
29 89
OUT
29 89
OUT
29 89
OUT
29 89
OUT
29 89
MEMORY
CONTROL
1A
MCLK1A_2_P BA42
MCLK1A_2_N BB42
TP_MEM_B_CLK2P
TP_MEM_B_CLK2N
MCLK1A_1_P BB22
MCLK1A_1_N BA22
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
OUT
29 89
OUT
29 89
MCLK1A_0_P BA19
MCLK1A_0_N AY19
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
OUT
29 89
OUT
29 89
MCS1A_1# BB14
MCS1A_0# BB16
MEM_B_CS_L<1>
MEM_B_CS_L<0>
OUT
29 89
OUT
29 89
MODT1A_1 BB13
MODT1A_0 AY15
MEM_B_ODT<1>
MEM_B_ODT<0>
OUT
29 89
OUT
29 89
MCKE1A_1 AY31
MCKE1A_0 BB30
MEM_B_CKE<1>
MEM_B_CKE<0>
OUT
29 89
OUT
29 89
MCP Memory Interface

SYNC_MASTER=T18_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
15
97
OMIT
U1400
MCP79-TOPO-B
NC_MEM_A_CLK4P
TP_MEM_A_CLK4N
BB24 MCLK0B_1_P
BC24 MCLK0B_1_N
NC_MEM_A_CLK3P
NC_MEM_A_CLK3N
BA21 MCLK0B_0_P
BB21 MCLK0B_0_N
TP_MEM_A_CS_L<2>
NC_MEM_A_CS_L<3>
AU17 MCS0B_0#
AR15 MCS0B_1#
NC_MEM_A_ODT<2>
NC_MEM_A_ODT<3>
AN17 MODT0B_0
AN15 MODT0B_1
NC_MEM_A_CKE<2>
NC_MEM_A_CKE<3>
AV23 MCKE0B_0
AN25 MCKE0B_1
D
7
7
7
7
7
68 39 29 28 24 16 12 11 8 7
70 69
PP1V05_S0_MCP_PLL_CORE
24
87 mA (A01)
17 mA
12 mA
19 mA
39 mA
PP1V8R1V5_S0_FET
R16101
40.2
1%
1/16W
MF-LF
402 2
89
89
MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND
T27
U28
U27
T28
+V_PLL_XREF_XS
+V_PLL_DP
+V_PLL_CORE
+V_VPLL
MCLK1B_2_P BA41
MCLK1B_2_N BB41
TP_MEM_B_CLK5P
NC_MEM_B_CLK5N
MCLK1B_1_P AY23
MCLK1B_1_N BA23
NC_MEM_B_CLK4P
NC_MEM_B_CLK4N
MCLK1B_0_P BA20
MCLK1B_0_N AY20
NC_MEM_B_CLK3P
TP_MEM_B_CLK3N
MCS1B_0# BC16
MCS1B_1# BA13
TP_MEM_B_CS_L<2>
TP_MEM_B_CS_L<3>
MODT1B_0 AY16
MODT1B_1 BC13
NC_MEM_B_ODT<2>
TP_MEM_B_ODT<3>
MCKE1B_0 BA30
MCKE1B_1 BA31
NC_MEM_B_CKE<2>
TP_MEM_B_CKE<3>
MRESET0# AY32
AN41 MEM_COMP_VDD
AM41 MEM_COMP_GND
R16111
40.2
MEMORY CONTROL 1B
AU33 MCLK0B_2_P
AU34 MCLK0B_2_N
MEMORY CONTROL 0B
BGA
(4 OF 11)
TP_MEM_A_CLK5P
TP_MEM_A_CLK5N
AA22
AP12
G30
P10
T10
T6
V10
V34
W5
AA39
AB22
AB7
AD22
AE20
AF24
AG24
AH35
AK7
AM28
AT25
AP30
AR36
AU10
F28
BC21
AY9
BC9
D34
F24
G32
H31
K7
M38
M5
M6
M7
M9
N39
N8
P33
P34
P37
P4
P40
P7
R36
R40
R43
R5
T18
T20
AK11
T24
T26
1%
1/16W
MF-LF
402 2
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
+VDD_MEM1
+VDD_MEM2
+VDD_MEM3
+VDD_MEM4
+VDD_MEM5
+VDD_MEM6
+VDD_MEM7
+VDD_MEM8
+VDD_MEM9
+VDD_MEM10
+VDD_MEM11
+VDD_MEM12
+VDD_MEM13
+VDD_MEM14
+VDD_MEM15
+VDD_MEM16
+VDD_MEM17
+VDD_MEM18
+VDD_MEM19
+VDD_MEM20
+VDD_MEM21
+VDD_MEM22
+VDD_MEM23
+VDD_MEM24
+VDD_MEM25
+VDD_MEM26
+VDD_MEM27
+VDD_MEM28
+VDD_MEM29
+VDD_MEM30
+VDD_MEM31
+VDD_MEM32
+VDD_MEM33
+VDD_MEM34
+VDD_MEM35
+VDD_MEM36
+VDD_MEM37
+VDD_MEM38
+VDD_MEM39
+VDD_MEM40
+VDD_MEM41
+VDD_MEM42
+VDD_MEM43
+VDD_MEM44
+VDD_MEM45
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
AM17
AM19
AM21
AM23
AM25
AM27
AM29
AN16
BC29
AN20
AN24
AT17
AP16
AN22
AP20
AP24
AV16
AR16
AR20
AR24
AW15
AP22
AP18
AU16
AN18
AU24
AT21
AY29
AV24
AU20
AU22
AW27
BC17
AV20
AY17
AY18
AM15
AU18
AY25
AY26
AW19
AW24
BC25
AL30
AM31
7
7
MCP_MEM_RESET_L
OUT
TP or NC for DDR2.
PP1V8R1V5_S0_FET
4771 mA (A01, DDR3)
30
70
7 8 11 12 16 24 28 29 39 68 69
T33
T34
T35
T37
T38
T7
T9
U18
U20
U22
MCP Memory Misc

SYNC_MASTER=T18_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
16
97
OMIT
U1400
MCP79-TOPO-B
BGA
(5 OF 11)
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
31
IN
37
IN
37 9
IN
IN
IN
60
84
32
84 9 6
OUT
OUT
IN
PE0_RX0_P
PE0_RX0_N
PE0_RX1_P
PE0_RX1_N
PE0_RX2_P
PE0_RX2_N
PE0_RX3_P
PE0_RX3_N
PE0_RX4_P
PE0_RX4_N
PE0_RX5_P
PE0_RX5_N
PE0_RX6_P
PE0_RX6_N
PE0_RX7_P
PE0_RX7_N
PE0_RX8_P
PE0_RX8_N
PE0_RX9_P
PE0_RX9_N
PE0_RX10_P
PE0_RX10_N
PE0_RX11_P
PE0_RX11_N
PE0_RX12_P
PE0_RX12_N
PE0_RX13_P
PE0_RX13_N
PE0_RX14_P
PE0_RX14_N
PE0_RX15_P
PE0_RX15_N
Int PU
C9 PE0_PRSNT_16#
PEG_PRSNT_L
IN
31
F7
E7
D7
C7
E6
F6
E5
F5
E4
E3
C3
D3
G5
H5
J7
J6
J5
J4
L11
L10
L9
L8
L7
L6
N11
N10
N9
P9
N7
N6
N5
N4
=PEG_D2R_P<0>
=PEG_D2R_N<0>
=PEG_D2R_P<1>
=PEG_D2R_N<1>
=PEG_D2R_P<2>
=PEG_D2R_N<2>
=PEG_D2R_P<3>
=PEG_D2R_N<3>
=PEG_D2R_P<4>
=PEG_D2R_N<4>
=PEG_D2R_P<5>
=PEG_D2R_N<5>
=PEG_D2R_P<6>
=PEG_D2R_N<6>
=PEG_D2R_P<7>
=PEG_D2R_N<7>
=PEG_D2R_P<8>
=PEG_D2R_N<8>
=PEG_D2R_P<9>
=PEG_D2R_N<9>
=PEG_D2R_P<10>
=PEG_D2R_N<10>
=PEG_D2R_P<11>
=PEG_D2R_N<11>
=PEG_D2R_P<12>
=PEG_D2R_N<12>
=PEG_D2R_P<13>
=PEG_D2R_N<13>
=PEG_D2R_P<14>
=PEG_D2R_N<14>
=PEG_D2R_P<15>
=PEG_D2R_N<15>
PCI EXPRESS
Int PU
MINI_CLKREQ_L
PCIE_MINI_PRSNT_L
D5 PEB_CLKREQ#/GPIO_49
FW_CLKREQ_L
PCIE_FW_PRSNT_L
E8 PEC_CLKREQ#/GPIO_50
D9 PEB_PRSNT# Int PU
Int PU
C10 PEC_PRSNT# Int PU

Int PU
M15 PED_CLKREQ#/GPIO_51
TP_EXCARD_CLKREQ_L
B10 PED_PRSNT# Int PU
TP_PE4_CLKREQ_L
NC_PE4_PRSNT_L
L16 PEE_CLKREQ#/GPIO_16
L18 PEE_PRSNT#/GPIO_46
AUD_IP_PERIPHERAL_DET
GMUX_JTAG_TCK_L
M16 PEF_CLKREQ#/GPIO_17
M18 PEF_PRSNT#/GPIO_47
CARDREADER_RESET
JTAG_GMUX_TDO
M17 PEG_CLKREQ#/GPIO_18
M19 PEG_PRSNT#/GPIO_48
Int PU
F17 PE_WAKE# Int PU (S5)
Int PU
Int PU
Int PU
PE0_TX0_P
PE0_TX0_N
PE0_TX1_P
PE0_TX1_N
PE0_TX2_P
PE0_TX2_N
PE0_TX3_P
PE0_TX3_N
PE0_TX4_P
PE0_TX4_N
PE0_TX5_P
PE0_TX5_N
PE0_TX6_P
PE0_TX6_N
PE0_TX7_P
PE0_TX7_N
PE0_TX8_P
PE0_TX8_N
PE0_TX9_P
PE0_TX9_N
PE0_TX10_P
PE0_TX10_N
PE0_TX11_P
PE0_TX11_N
PE0_TX12_P
PE0_TX12_N
PE0_TX13_P
PE0_TX13_N
PE0_TX14_P
PE0_TX14_N
PE0_TX15_P
PE0_TX15_N
C5
D4
C4
B4
A4
A3
B3
B2
C1
D1
D2
E1
E2
F2
F3
F4
G3
H4
H3
H2
H1
J1
J2
J3
K2
K3
L4
L3
M4
M3
M2
M1
=PEG_R2D_C_P<0>
=PEG_R2D_C_N<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_N<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_N<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_N<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_N<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_N<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_N<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_N<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_N<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_N<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_N<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_N<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_N<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_N<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_N<14>
=PEG_R2D_C_P<15>
=PEG_R2D_C_N<15>
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PE0_REFCLK_P E11
PE0_REFCLK_N D11
PEG_CLK100M_P
PEG_CLK100M_N
OUT
71 90
OUT
71 90
PE1_REFCLK_P G11
PE1_REFCLK_N F11
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
OUT
31 90
OUT
31 90
PE2_REFCLK_P J11
PE2_REFCLK_N J10
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
OUT
36 90
OUT
36 90
PE3_REFCLK_P G13
PE3_REFCLK_N F13
OUT
9 90
OUT
9 90
PE4_REFCLK_P J13
PE4_REFCLK_N H13
PE5_REFCLK_P L14
PE5_REFCLK_N K14
PE6_REFCLK_P N14
PE6_REFCLK_N M14
TP_PCIE_CLK100M_PE6N
7
7
Int PU
7
7
Int PU
7
31 7
IN
PCIE_WAKE_L
PEX_RST0# K11
PCIE_RESET_L
OUT
26 37
90 31 7
IN
PE1_TX0_P D8
PE1_TX0_N C8
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
31 90
IN
K9 PE1_RX0_P
J9 PE1_RX0_N
OUT
90 31 7
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
OUT
31 90
90 36
IN
PE1_TX1_P B8
PE1_TX1_N A8
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
36 90
IN
H9 PE1_RX1_P
G9 PE1_RX1_N
OUT
90 36
PCIE_FW_D2R_P
PCIE_FW_D2R_N
OUT
36 90
90 9
IN
PE1_TX2_P A7
PE1_TX2_N B7
9 90
IN
F9 PE1_RX2_P
E9 PE1_RX2_N
OUT
90 9
OUT
9 90
TP_PCIE_PE4_D2RP
NC_PCIE_PE4_D2RN
H7 PE1_RX3_P
G7 PE1_RX3_N
PE1_TX3_P B6
PE1_TX3_N C6
TP_PCIE_PE4_R2D_CP
NC_PCIE_PE4_R2D_CN
PPCPUVTT_S0
18 17 14 13 12 11 10 9 8 7 6
67 63 25 24 22 20
T17
W19
U17
V19
W16
W17
W18
U16
57 mA (A01, DVDD0 & 1)
+DVDD0_PEX1
+DVDD0_PEX2
+DVDD0_PEX3
+DVDD0_PEX4
+DVDD0_PEX5
+DVDD0_PEX6
+DVDD0_PEX7
+DVDD0_PEX8
PPCPUVTT_S0
18 17 14 13 12 11 10 9 8 7 6
67 63 25 24 22 20
T19 +DVDD1_PEX1
U19 +DVDD1_PEX2
84 mA (A01)
90
+AVDD0_PEX1
+AVDD0_PEX2
+AVDD0_PEX3
+AVDD0_PEX4
+AVDD0_PEX5
+AVDD0_PEX6
+AVDD0_PEX7
+AVDD0_PEX8
+AVDD0_PEX9
+AVDD0_PEX10
+AVDD0_PEX11
+AVDD0_PEX12
+AVDD0_PEX13
Y12
AA12
AB12
M12
P12
R12
N12
T12
U12
AC12
AD12
V12
W12
T16 +V_PLL_PEX
PP1V05_S0_MCP_PLL_PEX
24
A11 PEX_CLK_COMP
MCP_PEX_CLK_COMP
8 17 24
206 mA (A01, AVDD0 & 1)
8 17 24
+AVDD1_PEX1 M13
+AVDD1_PEX2 N13
+AVDD1_PEX3 P13
MCP PCIe Interfaces
NO STUFF
SYNC_MASTER=T18_MLB
R1710
If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.

If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.
2.37K
1%
1/16W
MF-LF
402

PLACEMENT_NOTE=Place within 12.7mm of U1400

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
17
97
OMIT
U1400
MCP79-TOPO-B
BGA
(6 OF 11)
34 33 24 18 8 7
PP3V3_ENET_PHY
92 33
IN
92 33
IN
92 33
IN
92 33
IN
92 33
IN
92 33
IN
18 9
IN
18 9
IN
18 9
IN
R18101
ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
1%
1/16W
MF-LF
402 2
24
RGMII_RXD0
RGMII_RXD1
RGMII_RXD2
RGMII_RXD3
A23 RGMII_RXC/MII_RXCLK
C22 RGMII_RXCTL/MII_RXDV
MCP_MII_PD
MCP_MII_PD
MCP_MII_PD
F23 MII_RXER/GPIO_36
B26 MII_COL/GPIO_20/MSMB_DATA
B22 MII_CRS/GPIO_21/MSMB_CLK
PP1V2R1V05_ENET
92
RGMII_MDC D21
RGMII_MDIO C21
MCP_MII_COMP_VDD
MCP_MII_COMP_GND
C27 MII_COMP_VDD
B27 MII_COMP_GND
NC_MCP_RGB_DAC_RSET
NC_MCP_RGB_DAC_VREF
MII_RESET# J23
C39 RGB_DAC_RSET
B38 RGB_DAC_VREF
C
90 25
OUT
90 25
OUT
NC_MCP_TV_DAC_RSET
NC_MCP_TV_DAC_VREF
E36 TV_DAC_RSET
A35 TV_DAC_VREF
PP3V3_S5
R1820
47K
25
IN
25
OUT
NC_MCP_CLK27M_XTALIN
NC_MCP_CLK27M_XTALOUT
C38 XTALIN_TV
D38 XTALOUT_TV
TV
C
Y
Comp
5%
1/16W
MF-LF
402 2
44
BI
84 82 81 77
Interface Mode
LPCPLUS_GPIO
DP_CA_DET
MCP Signal
TMDS/HDMI
DisplayPort
=MCP_HDMI_TXC_P/N
=MCP_HDMI_TXD_P/N<0>
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA
=MCP_HDMI_HPD
DP_IG_AUX_CH_P/N
TMDS_IG_TXC_P/N
TMDS_IG_TXD_P/N<0>
TMDS_IG_TXD_P/N<1>
TMDS_IG_TXD_P/N<2>
TMDS_IG_DDC_CLK
TMDS_IG_DDC_DATA
TMDS_IG_HPD
TP_DP_IG_AUX_CHP/N
DP_IG_ML_P/N<3>
DP_IG_ML_P/N<2>
DP_IG_ML_P/N<1>
DP_IG_ML_P/N<0>
DP_IG_DDC_CLK
DP_IG_DDC_DATA
DP_IG_HPD
DP_IG_AUX_CH_P/N
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

NOTE: 20K pull-down required on DP_HPD_DET.
NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.
NOTE: HDMI port requires level-shifting. IFP interface can
be used to provide HDMI or dual-channel TMDS without
level-shifters.
LVDS:
Power +VDD_IFPx at 1.8V
Dual-channel TMDS: Power +VDD_IFPx at 3.3V
IN
OUT
84 9
OUT
84 9
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
90 81
OUT
90 81
OUT
84 9
IN
81 9
IN
87 84 70 69 55 25 8 7
25
20 17 14 13 12 11 10 9 8 7 6
67 63 25 24 22
90 25
OUT
90 25
OUT
/
/
/
/
G39 LCD_BKL_CTL/GPIO_57
E37 LCD_BKL_ON/GPIO_59
F40 LCD_PANEL_PWR/GPIO_58
=MCP_HDMI_TXC_P
=MCP_HDMI_TXC_N
D35 HDMI_TXC_P/ML0_LANE3_P
E35 HDMI_TXC_N/ML0_LANE3_N
=MCP_HDMI_TXD_P<0>
=MCP_HDMI_TXD_N<0>
=MCP_HDMI_TXD_P<1>
=MCP_HDMI_TXD_N<1>
=MCP_HDMI_TXD_P<2>
=MCP_HDMI_TXD_N<2>
G35
F35
F33
G33
J33
H33
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
D43 DP_AUX_CH0_P
C43 DP_AUX_CH0_N
(See below)
PP1V8_S0
190 mA (A01, 1.8V)
PP3V3_S0_MCP_VPLL
16 mA (A01)
PPCPUVTT_S0
95 mA (A01)
MCP_HDMI_RSET
MCP_HDMI_VPROBE
HDMI_TXD0_P/ML0_LANE2_P
HDMI_TXD0_N/ML0_LANE2_N
C31 HPLUG_DET2/GPIO_22
F31 HPLUG_DET3
M27 +VDD_IFPA
M26 +VDD_IFPB
8 mA
8 mA
OUT
33 92
OUT
33 92
ENET_CLK125M_TXCLK
ENET_TX_CTRL
OUT
33 92
OUT
33 92
ENET_MDC
ENET_MDIO
OUT
33 92
BI
RGMII
MII
NOTE: All Apple products set strap to

MII, RGMII products will enable
feature via software. This
avoids a leakage issue since
MCP79 requires a S5 pull-up.
33 92
M28 +V_PLL_IFPAB
M29 +V_PLL_HDMI
T25 +VDD_HDMI
J31 HDMI_RSET
J30 HDMI_VPROBE
MCP_CLK25M_BUF0_R
OUT
34 92
ENET_RESET_L
OUT
33 92
RGB_DAC_RED B39
RGB_DAC_GREEN A39
RGB_DAC_BLUE B40
NC_MCP_RGB_RED
NC_MCP_RGB_GREEN
NC_MCP_RGB_BLUE
RGB_DAC_HSYNC A40
RGB_DAC_VSYNC A41
NC_MCP_RGB_HSYNC
NC_MCP_RGB_VSYNC
Component
Pr
TV_DAC_RED
Y
TV_DAC_GREEN
Pb TV_DAC_BLUE
R18601
100K
5%
1/16W
MF-LF
402 2
60 63 68 69 70 77 80 81 82 84
6 7 8 13 19 21 22 24 25 28 29
37 39 43 45 47 48 49 51 55 59
85 96
R1861
100K
5%
1/16W
MF-LF
2 402
NC_CRT_IG_R_C_PR
NC_CRT_IG_G_Y_Y
NC_CRT_IG_B_COMP_PB
A36
B36
C36
Okay to float all RGB_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.
25
25
25
TV DAC Disable:
OUT
25 90
OUT
25 90
OUT
25 90
OUT
25 90
OUT
25 90
IFPA_TXC_P B35
IFPA_TXC_N C35
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
OUT
84 90
OUT
84 90
LVDS_IG_A_DATA_P<0> OUT
LVDS_IG_A_DATA_N<0> OUT
NC_LVDS_IG_A_DATAP<3>OUT
NC_LVDS_IG_A_DATAN<3>OUT
B32
A32
D32
C32
D33
C33
B34
C34
RGB DAC Disable:

25
NC_CRT_IG_HSYNC
NC_CRT_IG_VSYNC
IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N
PP3V3_S0
25
TV_DAC_HSYNC/GPIO_44 D36
TV_DAC_VSYNC/GPIO_45 C37
E16 GPIO_6/FERR*/IGPU_GPIO_6
B15 GPIO_7/NFERR*/IGPU_GPIO_7
NC_LVDS_IG_BKL_PWM(See below)
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR
GMUX_INT
DP_IG_HPD
33 92
MCP_DDC_CLK0
MCP_DDC_DATA0
DDC_CLK0 B31
DDC_DATA0 A31
RGB ONLY
25
Interface ENET_TXD<0>
33 92
OUT
PP3V3_S0_MCP_DAC 25
103 mA
206 mA (A01)
103 mA
+V_RGB_DAC J32
+V_TV_DAC K32
DACS
25
24
T23 +V_DUAL_MACPLL
FLAT PANEL
1%
1/16W
MF-LF
402 2
IN
OUT
NC_ENET_PWRDWN_L
RGMII_PWRDWN/GPIO_37 G23
49.9
ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>
B24
C24
C25
D25
RGMII_TXC/MII_TXCLK D24
RGMII_TXCTL/MII_TXEN C26
R18111
38 37 34 30 26 24 22 20 8 7
96 87 82 70 69 68 64 54 44
Network Interface Select

MCP_MII_VREF
BUF_25MHZ E23
92
7 8 24 33 34 37
131 mA (A01)
MII_VREF E28
J22 RGMII_INTR/GPIO_35
PP1V05_ENET_MCP_PLL_MAC
5 mA (A01)
7 8 18 24 33 34
83 mA (A01)
+V_DUAL_RMGT1 U23
+V_DUAL_RMGT2 V23
RGMII_TXD0
RGMII_TXD1
RGMII_TXD2
RGMII_TXD3
ENET_CLK125M_RXCLK
ENET_RX_CTRL
NC_ENET_INTR_L
49.9
C23
B23
E24
A24
LAN
PP3V3_ENET_PHY
+3.3V_DUAL_RMGT1 J24
+3.3V_DUAL_RMGT2 K24
Okay to float all TV_DAC signals.

Okay to float XTALIN_TV and XTALOUT_TV.
DDC_CLK0/DDC_DATA0 pull-ups still required.
84 90
84 90
84 90
84 90
84 90
84 90
9 90
9 90
WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

NC_LVDS_IG_B_CLKP
NC_LVDS_IG_B_CLKN
IFPB_TXC_P L31
IFPB_TXC_N K31
IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N
OUT
9 90
OUT
9 90
LVDS_IG_B_DATA_P<0> OUT
LVDS_IG_B_DATA_N<0> OUT
NC_LVDS_IG_B_DATAP<3>OUT
NC_LVDS_IG_B_DATAN<3>OUT
J29
H29
L29
K29
L30
K30
N30
M30
DDC_CLK2/GPIO_23 C30
DDC_DATA2/GPIO_24 B30
DDC_CLK3 D31
DDC_DATA3 E31
IFPAB_RSET E32
IFPAB_VPROBE G31
84 90
84 90
84 90
84 90
84 90
84 90
9 90
9 90
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
OUT
DP_IG_DDC_CLK
DP_IG_DDC_DATA
OUT
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
OUT
25 90
OUT
25 90
BI
BI
81
81
9 77 81
9 77 81
R1850
10K
GPIOs 57-59 (if LCD panel is used):
5%
1/16W
MF-LF
2 402
In MCP79 these pins have undocumented internal

pull-ups (~10K to 3.3V S0). To ensure pins are low
by default, pull-downs (1K or stronger) must be used.
MCP Ethernet & Graphics

SYNC_MASTER=T18_MLB

=DVI_HPD_GMUX_INT:
Alias to DVI_HPD for systems using IFP for DVI.
Alias to GMUX_INT for systems with GMUX.
Alias to HPLUG_DET2 for other systems.
Pull-down (20k) required in all cases.

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
18
97
OMIT
U1400
84 82 81 80 77 70 69 68 63 60
29 28 25 24 22 21 18 13 8 7 6
59 55 51 49 48 47 45 43 39 37
96 85
MCP79-TOPO-B
BGA
(7 OF 11)
37 19
OUT
60
OUT
19
IN
91 13
BI
91 13
BI
91 13
BI
91 13
BI
91 13
BI
91 13
BI
91 13
BI
91 13
BI
AC3
AE10
AC4
AE11
AB3
AC6
AB2
AC7
AC8
AA2
AC9
AC10
AC11
AA1
AA5
Y5
W3
W6
W4
W7
V3
W8
V2
W9
U3
W11
U2
U5
U1
U6
T5
U7
NC_PCI_INTW_L
NC_PCI_INTX_L
TP_PCI_INTY_L
NC_PCI_INTZ_L
P2
N3
N2
N1
NC_PCI_TRDY_L
Y3 PCI_TRDY#
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
44 42
IN
37 9
IN
PM_CLKRUN_L
7
44 42
BI
PCI_REQ0#
PCI_REQ1#/FANRPM2
PCI_REQ2#/GPIO_40/RS232_DSR#
PCI_REQ3#/GPIO_38/RS232_CTS#
PCI_REQ4#/GPIO_52/RS232_SIN#
MCP_DEBUG<0>
MCP_DEBUG<1>
MCP_DEBUG<2>
MCP_DEBUG<3>
MCP_DEBUG<4>
MCP_DEBUG<5>
MCP_DEBUG<6>
MCP_DEBUG<7>
NC_PCI_AD<8>
NC_PCI_AD<9>
NC_PCI_AD<10>
NC_PCI_AD<11>
NC_PCI_AD<12>
NC_PCI_AD<13>
NC_PCI_AD<14>
NC_PCI_AD<15>
NC_PCI_AD<16>
NC_PCI_AD<17>
NC_PCI_AD<18>
NC_PCI_AD<19>
NC_PCI_AD<20>
NC_PCI_AD<21>
NC_PCI_AD<22>
NC_PCI_AD<23>
NC_PCI_AD<24>
NC_PCI_AD<25>
NC_PCI_AD<26>
NC_PCI_AD<27>
NC_PCI_AD<28>
NC_PCI_AD<29>
NC_PCI_AD<30>
NC_PCI_AD<31>
T2
V9
T3
U9
T4
FW_PLUG_DET_L
NC_LPC_DRQ0_L
LPC_SERIRQ
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
NC_PCI_GNT0_L
NC_PCI_GNT1_L
JTAG_GMUX_TMS
JTAG_GMUX_TDI
MCP_RS232_SOUT_L
PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#
AA3
AA6
AA11
W10
NC_PCI_C_BE_L<0>
NC_PCI_C_BE_L<1>
NC_PCI_C_BE_L<2>
NC_PCI_C_BE_L<3>
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_PAR
PCI_PERR#/GPIO_43/RS232_DCD#
PCI_SERR#
PCI_STOP#
AA9
Y4
AA10
Y1
AB9
AA7
Y2
NC_PCI_DEVSEL_L
NC_PCI_FRAME_L
NC_PCI_IRDY_L
TP_PCI_PAR
NC_PCI_PERR_L
NC_PCI_SERR_L
NC_PCI_STOP_L
7
91 19
7
91 19
OUT
6 9 84
OUT
6 9 84
OUT
19
OUT
13
OUT
26
37 19
19
MCP_RS232_SOUT_L
R1989
8.2K
PCI_REQ0_L
PCI_REQ1_L
FW_PWR_EN
MCP_RS232_SIN_L
R1990
R1991
R1992
R1994
8.2K
8.2K
8.2K
8.2K
1
1
1
1
2
2
2
2
5%
1/16W MF-LF 402
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
7
7
7
7
7
7
7
7
7
7
PM_LATRIGGER_L
PCI_PME#/GPIO_30 T1
Int PU (S5)
MEM_VTT_EN_R
NC_PCI_RESET1_L
PCI_RESET0# R10
PCI_RESET1# R11
PCI_CLK0 R6
PCI_CLK1 R7
PCI_CLK2 R8
NC_PCI_CLK0
NC_PCI_CLK1
PCI_CLK33M_MCP_R
91
7
7
R1910
22
5%
1/16W
MF-LF
2 402
PCI_CLKIN R9
PCI_INTW#
PCI_INTX#
PCI_INTY#
PCI_INTZ#
PCI_CLK33M_MCP
91
LPC_FRAME_R_L
LPC_PWRDWN_L
LPC_FRAME# AD4
LPC_PWRDWN#/GPIO_54/EXT_NMI# AE12
AD11 PCI_CLKRUN#/GPIO_42
AE2 LPC_DRQ1#/GPIO_19 Int
AE1 LPC_DRQ0#
Int PU
AE6 LPC_SERIRQ Int PU
19
R3
U10
R4
U11
P3
PCI_GNT0#
PCI_GNT1#/FANCTL2
PCI_GNT2#/GPIO_41/RS232_DTR#
PCI_GNT3#/GPIO_39/RS232_RTS#
PCI_GNT4#/GPIO_53/RS232_SOUT#
PCI
91 19
PCI_REQ0_L
PCI_REQ1_L
FW_PWR_EN
AUD_IPHS_SWITCH_EN
MCP_RS232_SIN_L
PU
LPC
91 19
PP3V3_S0
LPC_RESET0# AE5
LPC_RESET_L
AD3
AD2
AD1
AD5
LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
PLACEMENT_NOTE=Place close to pin R8
R1960
R1950
R1951
R1952
R1953
22
LPC_FRAME_L
2
5%
22
22
22
22
1
1
1
1
2
2
2
2
5%
5%
5%
5%
1/16W MF-LF 402
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
42 44 84 91
OUT
42 44
OUT
26 84 91
BI
42 44 84 91
BI
42 44 84 91
BI
42 44 84 91
BI
LPC_CLK33M_SMC_R
LPC_CLK0 AE9
OUT
OUT
42 44 84 91
26 91
U24
U26
U39
U4
U8
V16
V17
V18
V20
V22
V24
V26
V27
V28
V33
V37
V4
V40
V7
W20
W22
W24
W36
W40
W43
Y16
Y17
Y18
Y19
Y20
Y22
Y24
Y25
GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
GND93
GND94
GND95
GND96
GND97
GND
GND98
GND99
GND100
GND101
GND102
GND103
GND104
GND105
GND106
GND107
GND108
GND109
GND110
GND111
GND112
GND113
GND114
GND115
GND116
GND117
GND118
GND119
GND120
GND121
GND122
GND123
GND124
GND125
GND126
GND127
GND128
GND129
GND130
R1961
Y26
Y27
AB18
H34
AB20
AB21
AB23
AB24
AB25
AB26
AB27
AB28
AB34
AB37
AB4
AB40
AC22
AC36
AC40
AB33
AC5
AD16
AD17
AD18
AD19
AD20
AD24
AD25
AD26
AD27
AD28
AD33
AD34
10K
5%
1/16W
MF-LF
2 402
Strap for Boot ROM Selection (See HDA_SDOUT)
MCP PCI & LPC

SYNC_MASTER=T18_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
19
97
OMIT
U1400
MCP79-TOPO-B
BGA
(8 OF 11)
90 39
OUT
90 39
OUT
90 39
IN
90 39
IN
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
AJ7 SATA_A0_TX_P
AJ6 SATA_A0_TX_N
USB0_P C29
USB0_N D29
SATA_HDD_D2R_N
SATA_HDD_D2R_P
AJ5 SATA_A0_RX_N
AJ4 SATA_A0_RX_P
USB1_P C28
USB1_N D28
USB2_P A28
USB2_N B28
OUT
90 39
OUT
90 39
90 39
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_D2R_N
SATA_ODD_D2R_P
IN
IN
NC_SATA_C_R2D_CP
NC_SATA_C_R2D_CN
7
7
TP_SATA_C_D2RN
NC_SATA_C_D2RP
7
7
AJ11 SATA_A1_TX_P
AJ10 SATA_A1_TX_N
USB3_P F29
USB3_N G29
AJ9 SATA_A1_RX_N
AK9 SATA_A1_RX_P
USB4_P K27
USB4_N L27
USB5_P J26
USB5_N J27
AK2 SATA_B0_TX_P
AJ3 SATA_B0_TX_N
AJ2 SATA_B0_RX_N
AJ1 SATA_B0_RX_P
TP_SATA_D_R2D_CP
TP_SATA_D_R2D_CN
AM4 SATA_B1_TX_P
AL3 SATA_B1_TX_N
NC_SATA_D_D2RN
NC_SATA_D_D2RP
AL4 SATA_B1_RX_N
AK3 SATA_B1_RX_P
USB6_P F27
USB6_N G27
SATA
USB
90 39
USB7_P D27
USB7_N E27
USB8_P K25
USB8_N L25
USB9_P H25
USB9_N J25
USB10_P F25
USB10_N G25
TP_SATA_E_R2D_CP
TP_SATA_E_R2D_CN
TP_SATA_E_D2RN
TP_SATA_E_D2RP
AN1 SATA_C0_TX_P
AM1 SATA_C0_TX_N
USB11_P K23
USB11_N L23
AP3 SATA_C1_TX_P
AP2 SATA_C1_TX_N
TP_SATA_F_D2RN
TP_SATA_F_D2RP
AN3 SATA_C1_RX_N
AN2 SATA_C1_RX_P
USB_OC0#/GPIO_25
USB_OC1#/GPIO_26
USB_OC2#/GPIO_27/MGPIO
USB_OC3#/GPIO_28/MGPIO
18 17 14 13 12 11 10 9 8 7 6
67 63 25 24 22
PP1V05_S0_MCP_PLL_SATA
84 mA (A01)
PPCPUVTT_S0
43 mA (A01, DVDD0 & 1)
Minimum 1.025V for Gen2 support
AE16 +V_PLL_SATA
AF19
AG16
AG17
AG19
+DVDD0_SATA1
+DVDD0_SATA2
+DVDD0_SATA3
+DVDD0_SATA4
AH17 +DVDD1_SATA1
AH19 +DVDD1_SATA2
24 8
127 mA (A01, AVDD0 & 1)
Minimum 1.025V for Gen2 support
AJ12
AN11
AK12
AK13
AL12
AM11
AM12
AN12
AL13
+AVDD0_SATA1
+AVDD0_SATA2
+AVDD0_SATA3
+AVDD0_SATA4
+AVDD0_SATA5
+AVDD0_SATA6
+AVDD0_SATA7
+AVDD0_SATA8
+AVDD0_SATA9
AN14
AL14
AM13
AM14
+AVDD1_SATA1
+AVDD1_SATA2
+AVDD1_SATA3
+AVDD1_SATA4
GND
MCP_SATA_TERMP
90
40 91
BI
9 91
BI
9 91
BI
9 91
BI
9 91
BI
7 31 91
BI
7 31 91
BI
41 91
BI
41 91
BI
50 91
BI
50 91
BI
7 31 91
BI
7 31 91
BI
40 91
BI
40 91
BI
9 91
BI
9 91
BI
9 91
BI
9 91
BI
9 32 96
BI
9 32 96
+V_PLL_USB L28
PP3V3_S5
R2051
8.2K
5%
1/16W
MF-LF
2 402
7 8 18 22 24 26 30 34 37 38 44
54 64 68 69 70 82 87 96
R2053
8.2K
5%
1/16W
MF-LF
2 402
R20501
8.2K
5%
1/16W
MF-LF
402 2
R20521
8.2K
5%
1/16W
MF-LF
402 2
USB_EXTA_OC_L
USB_EXTB_OC_L
USB_EXTC_OC_L
EXCARD_OC_L
PP3V3_S0_MCP_PLL_USB
19 mA (A01)
91
40
40
43
24
MCP_USB_RBIAS_GND
R20601
E12 SATA_LED#
GND
40 91
BI
L21
K21
J21
H21
USB_RBIAS_GND A27
24
NC_USB_10P
NC_USB_10N
SD Card Reader
USB_CARDREADER_P
USB_CARDREADER_N
BI
AM2 SATA_C0_RX_N
AM3 SATA_C0_RX_P
TP_SATA_F_R2D_CP
TP_SATA_F_R2D_CN
TP_MCP_SATALED_L
External A
USB_EXTA_P
USB_EXTA_N
AirPort (PCIe Mini-Card)
NC_USB_MINIP
NC_USB_MININ
External D
NC_USB_EXTDP
NC_USB_EXTDN
Camera
USB_CAMERA_P
USB_CAMERA_N
IR
USB_IR_P
USB_IR_N
Geyser Trackpad/Keyboard
USB_TPAD_P
USB_TPAD_N
Bluetooth
USB_BT_P
USB_BT_N
External B
USB_EXTB_P
USB_EXTB_N
ExpressCard
NC_USB_EXCARDP
NC_USB_EXCARDN
External C
NC_USB_EXTCP
NC_USB_EXTCN
AE3 SATA_TERMP
GND131
GND132
GND133
GND134
GND135
GND136
GND137
GND138
GND139
GND140
GND141
GND142
GND143
GND144
GND145
GND146
GND147
GND148
GND149
GND150
GND151
GND152
GND153
GND154
GND155
GND156
GND157
GND158
GND159
GND160
AD35
AD37
AD38
AE22
AE24
AE39
AE4
AD6
AF16
AF17
AF18
AF20
AF22
AF26
AF27
AF28
AF33
AF34
AF37
AF40
AG18
AG20
AG22
AG26
AG36
AG40
AH18
AH20
AH22
AH24
806
1%
1/16W
MF-LF
402 2
R2010
2.49K
1%
1/16W
MF-LF
2 402
If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.
If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.
MCP SATA & USB

SYNC_MASTER=T18_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
20
97
OMIT
U1400
81 82 84 85 96
45 47 48 49 51 55 59 60 63 68
6 7 8 13 18 19 21 22 24 25 28
29 37 39 43
PP3V3_S0
MCP79-TOPO-B
70 77 80
7 mA 69(A01)
BGA
(9 OF 11)
+V_DUAL_HDA1 J16
+V_DUAL_HDA2 K16
91 55
HDA_SDIN0
IN
G15 HDA_SDATA_IN0
Int PD
NC_MLB_RAM_SIZE
R2160
8.2K
5%
1/16W
MF-LF
2 402
HDA
HDA_SDATA_OUT F15
HDA_BITCLK E15
HDA_BIT_CLK_R
91 21
Int PD
77 70 69 68 63 60 59 55 51
25 24 22 21 19 18 13 8 7 6
49 48 47 45 43 39 37 29 28
96 85 84 82 81 80
TP_MLB_RAM_VENDOR
(MXM_OK for MXM systems)
PP3V3_S0
J15 HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA
HDA_RESET* K15
HDA_SYNC_R
91 21
PP3V42_G3H
44
43 42 37 34
1%
1/16W
MF-LF
402 2
OUT
IN
R2121
49.9K
1%
1/16W
MF-LF
2 402
42
IN
42
IN
MCP_HDA_PULLDN_COMP
A15 HDA_PULLDN_COMP
PP1V05_S0_MCP_PLL_NV
37 mA (A01)
20 mA
17 mA
SPIROM_USE_MLB
SMC_ADAPTER_EN
NC_SB_A20GATE
TP_MCP_KBDRSTIN_L
SMC_WAKE_SCI_L
SMC_RUNTIME_SCI_L
K13
L13
C19
C18
SM_INTRUDER_L
B20 INTRUDER*
A20GATE
Int PU
KBRDRSTIN* Int PU
SIO_PME*
Int PU (S5)
EXT_SMI/GPIO_32* Int PU
IN
PM_DPRSLPVR
M22 CPU_DPRSLPVR
42
IN
26
IN
PM_PWRBTN_L
PM_SYSRST_DEBOUNCE_L
C16 PWRBTN*
D16 RSTBTN*
RTC_RST_L
C20 RTC_RST*
M25 LID*
M24 LLB*
26
IN
IN
MCP_CPU_VLD
C17 CPU_VLD
JTAG_MCP_TDI
JTAG_MCP_TDO
JTAG_MCP_TMS
JTAG_MCP_TRST_L
JTAG_MCP_TCK
E19
F19
J19
J18
G19
MCP_CLK25M_XTALIN
MCP_CLK25M_XTALOUT
A16 XTALIN
B16 XTALOUT
RTC_CLK32K_XTALIN
RTC_CLK32K_XTALOUT
A19 XTALIN_RTC
B19 XTALOUT_RTC
IN
OUT
IN
76 13 6
IN
76 13 6
IN
26
IN
26
OUT
26
IN
26
OUT
(S5)
R21501
10K
5%
1/16W
MF-LF
402 2
D20 PWRGD_SB
E20 PS_PWRGD
SMB_CLK0
SMB_DATA0
SMB_CLK1/MSMB_CLK
SMB_DATA1/MSMB_DATA
SMB_ALERT*/GPIO_64
(MGPIO2)
(MGPIO3)
FANRPM0/GPIO_60
FANCTL0/GPIO_61
FANRPM1/GPIO_63
FANCTL1/GPIO_62
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
AP_PWR_EN
B12
A12
D12
C12
MEM_EVENT_L
ODD_PWR_EN_L
SMC_IG_THROTTLE_L
ARB_DETECT
C2172
JTAG_TDI Int
JTAG_TDO
JTAG_TMS Int
JTAG_TRST*
JTAG_TCK
PU
SPI_CS0/GPIO_10
SPI_CLK/GPIO_11
SPI_DI/GPIO_8
SPI_DO/GPIO_9
PU
100K
5%
1/16W
MF-LF
2 402
10K
5%
1/16W
MF-LF
2 402
21 91
R2141
10K
5%
1/16W
MF-LF
2 402
10PF
5%
50V
2 CERM
402
7 40 42 43 69 70
OUT
48 96
OUT
48 96
OUT
21 66
OUT
21 66
OUT
21 66
IN
OUT
PCI
SPI0
SPI1
R1961 and R2160 selects SPI0 ROM by

default, LPC+ debug card pulls
LPC_FRAME# high for SPI1 ROM override.
NOTE: MCP79 does not support FWH, only
LPC ROMs. So Apple designs will
not use LPC for BootROM override.
PP3V3_S0
BOOT_MODE_SAFE
51 55 59 60 63 68 69 70 77
6 7 8 13 18 19 21 22 24 25
28 29 37 39 43 45 47 48 49
80 81 82 84 85 96
NOTE: MCP79 rev A01 does not support

SPI1 option. Rev B01 will.
IN
OUT
R2142
10K
5%
1/16W
MF-LF
2 402
R2180
BUF_SIO_CLK Frequency
10K
5%
1/16W
MF-LF
2 402
Frequency
9
Connects to SMC for

automatic recovery.
14.31818 MHz
SPI Frequency Select

Frequency SPI_DO SPI_CLK
21 28 29 42
39
31 MHz
42 MHz
25 MHz
1 MHz
21 42 43
26
OUT
44 91
OUT
44 91
IN
44 91
OUT
44 91
OUT
26 91
NOTE: Straps not provided on this page.
PP3V3_S3
7 8 27 31 32 45 50 52 70
R2154
100K
5%
1/16W
MF-LF
1 402
MCP_GPIO_4
AUD_I2C_INT_L
MEM_EVENT_L
SMC_IG_THROTTLE_L
21 42 43
ARB_DETECT
21
AP_PWR_EN
21
21 31 34
21 60
MCP HDA & MISC
21 28 29 42
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
1
R2147
R2155
5%
1/16W
MF-LF
2 402
5%
50V
2 CERM
402
45 60 85 91
21 31 34
USER mode: Normal

SAFE mode: For ROMSIP
recovery
59 60 63 68 69 70 77 80 81 82
6 7 8 13 18 19 21 22 24 25 28
29 37 39 43 45 47 48 49 51 55
84 85 96
10PF
5%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
C2173
10K
13 28 29 45 91
45 60 85 91
1K
10K
21 91
13 28 29 45 91
R2190
R2143
21 91
R2181
R2156
21 66
SYNC_MASTER=T18_MLB
21 66

R2157
22K
22K
22K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
21 66

SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-7892
SCALE
SHT
NONE
HDA_SYNC
24 MHz
21 91
21
5%
1/16W
MF-LF
2 402
R2140
9 34
OUT
BI
10K
7 34 37 42 69 82 84
OUT
R2163
LPC_FRAME#
MCP_TEST_MODE_EN
100K
C2171
55 91
21 60
BI
OUT
OUT
OUT
PM_CLK32K_SUSCLK_R
TP_MCP_BUF_SIO_CLK
TEST_MODE_EN K22
PKG_TEST L22
5%
50V
CERM 2
402
HDA_SYNC
5%
1/16W
MF-LF
402
OUT
OUT
SPI_CS0_R_L
SPI_CLK_R
SPI_MISO
SPI_MOSI_R
C14
D13
C15
B14
SUS_CLK/GPIO_34 B18
BUF_SIO_CLK AE7
10PF
5%
50V
CERM 2
402
55 91
HDA_SDOUT
LPC
MCP_CPUVDD_EN
R2151
For EMI Reduction on HDA interface
10PF
OUT
OUT
L19
K19
G21
F21
M23
HDA Output Caps
C2170
HDA_RST_L
MCP_SPKR
CPUVDD_EN D17
PP3V3_S0
I/F
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

IN
55 91
BOOT_MODE_USER
Int PU (S5)
Int PU
26
HDA_RST_R_L
HDA_SYNC_R
OUT
21
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
MCP_VID0/GPIO_13 L20
MCP_VID1/GPIO_14 M20
MCP_VID2/GPIO_15 M21
Int PU (S5)
Int PU (S5)
PM_RSMRST_L
MCP_PS_PWRGD
HDA_SDOUT_R
HDA_BIT_CLK_R
BIOS Boot Select
MCP_THMDIODE_P
MCP_THMDIODE_N
THERM_DIODE_P B11
THERM_DIODE_N C11
SPKR C13
IN
13 6
PM_SLP_S3_L
PM_SLP_RMGT_L
PM_SLP_S4_L
L26 GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L
42
13 6
SLP_S3* G17
SLP_RMGT* J17
SLP_S5* H17
L24 GPIO_1/PWRDN_OK/SPI_CS1
88 63
IN
MCP_GPIO_4
AUD_I2C_INT_L
AE18 +V_PLL_NV_H
AE17 +V_PLL_SP_SPREF
TP_MCP_LID_L
PM_BATLOW_L
42
HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK K17
HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA L17
MISC
24
49.9K
22
55 91
5%
1/16W
MF-LF
402
91
22
R2173
HDA_SYNC L15
OUT
R2172
1
1%
1/16W
MF-LF
2 402
HDA_SDOUT
HDA_BIT_CLK
Int PD
49.9
5%
1/16W
MF-LF
402
HDA_RST_R_L
91 21
R2110
R21201
22
5%
1/16W
MF-LF
402
46 45 44 43 42 40 26 22 8 7
69 64 62 61 50
22
R2171
J14 HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK
R2170
HDA_SDOUT_R
91 21
A.0.0
OF
21
97
OMIT
OMIT
U1400
U1400
MCP79-TOPO-B
GND253
GND254
GND255
GND256
GND257
GND258
GND259
GND260
GND261
GND262
GND263
GND264
GND265
GND266
GND267
GND268
GND269
GND270
GND271
GND272
GND273
GND274
GND275
GND276
GND277
GND278
GND279
GND280
GND281
GND282
GND283
GND284
GND285
GND286
GND287
GND288
GND289
GND290
GND291
GND292
GND293
GND294
GND295
GND296
GND297
GND298
GND299
GND300
GND301
GND302
GND303
GND304
GND305
GND306
GND307
GND308
GND309
GND310
GND311
GND312
GND313
GND314
GND315
GND316
GND317
GND318
GND319
GND320
GND321
GND322
GND323
GND324
GND325
GND326
GND327
GND328
GND329
GND330
GND331
GND332
GND333
GND334
GND335
GND336
GND337
GND338
GND339
GND340
GND341
GND342
GND343
PPVCORE_S0_MCP_REG
23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)
BGA
(10 OF 11)
66 46 24 8 7
AV40
BA1
BA4
AW31
AY6
L35
BC33
BC37
BC41
AY14
BC5
C2
D10
D14
D15
D18
D19
D22
D23
D26
D30
D37
D6
E13
E17
E21
E25
E29
E33
F12
F16
F32
F8
G10
G12
G14
G16
BC12
G22
G24
AW20
G34
G4
G43
G6
G8
H11
H15
AW35
H23
AN8
G40
J12
J8
K10
K12
K18
K26
K37
K4
K40
K8
AU1
L40
L43
L5
M10
M34
M35
M37
Y28
Y33
Y34
Y35
Y37
Y38
AB17
AB16
AN26
AD7
M11
AA4
AB19
AY13
P11
Y6
T11
V11
Y11
AH16
T22
46 45 44 43 42 40 26 21 8 7
69 64 62 61 50
PP3V42_G3H
10 uA (G3)
80 uA (S0)
AA25
AC23
U25
AH12
AG10
AG5
Y21
Y23
AA16
AA26
AA27
AA28
AC16
AC17
AC18
AC19
AC20
AC21
AA17
AC24
AC25
AC26
AC27
AC28
AD21
AD23
W27
V25
AA18
AE19
AE21
AE23
AE25
AE26
AE27
AE28
AF10
AF11
AA19
AF2
AF21
AF23
AF25
AF3
AF4
AF7
AH23
AF9
AA20
AG11
AG12
AG21
AG23
AG25
AG3
AG4
AA21
AG6
AG7
AG8
AG9
AH1
AH10
AH11
W26
AH2
AA23
W28
AH25
AH21
AH3
AH4
AH5
AH6
AH7
AH9
AA24
W21
W23
W25
AF12
+VDD_CORE1
+VDD_CORE2
+VDD_CORE3
+VDD_CORE4
+VDD_CORE5
+VDD_CORE6
+VDD_CORE7
+VDD_CORE8
+VDD_CORE9
+VDD_CORE10
+VDD_CORE11
+VDD_CORE12
+VDD_CORE13
+VDD_CORE14
+VDD_CORE15
+VDD_CORE16
+VDD_CORE17
+VDD_CORE18
+VDD_CORE19
+VDD_CORE20
+VDD_CORE21
+VDD_CORE22
+VDD_CORE23
+VDD_CORE24
+VDD_CORE25
+VDD_CORE26
+VDD_CORE27
+VDD_CORE28
+VDD_CORE29
+VDD_CORE30
+VDD_CORE31
+VDD_CORE32
+VDD_CORE33
+VDD_CORE34
+VDD_CORE35
+VDD_CORE36
+VDD_CORE37
+VDD_CORE38
+VDD_CORE39
+VDD_CORE40
+VDD_CORE41
+VDD_CORE42
+VDD_CORE43
+VDD_CORE44
+VDD_CORE45
+VDD_CORE46
+VDD_CORE47
+VDD_CORE48
+VDD_CORE49
+VDD_CORE50
+VDD_CORE51
+VDD_CORE52
+VDD_CORE53
+VDD_CORE54
+VDD_CORE55
+VDD_CORE56
+VDD_CORE57
+VDD_CORE58
+VDD_CORE59
+VDD_CORE60
+VDD_CORE61
+VDD_CORE62
+VDD_CORE63
+VDD_CORE64
+VDD_CORE65
+VDD_CORE66
+VDD_CORE67
+VDD_CORE68
+VDD_CORE69
+VDD_CORE70
+VDD_CORE71
+VDD_CORE72
+VDD_CORE73
+VDD_CORE74
+VDD_CORE75
+VDD_CORE76
+VDD_CORE77
+VDD_CORE78
+VDD_CORE79
+VDD_CORE80
+VDD_CORE81
A20 +VBAT
POWER
GND
GND161
GND162
GND163
GND164
GND165
GND166
GND167
GND168
GND169
GND170
GND171
GND172
GND173
GND174
GND175
GND176
GND177
GND178
GND179
GND180
GND181
GND182
GND183
GND184
GND185
GND186
GND187
GND188
GND189
GND190
GND191
GND192
GND193
GND194
GND195
GND196
GND197
GND198
GND199
GND200
GND201
GND202
GND203
GND204
GND205
GND206
GND207
GND208
GND209
GND210
GND211
GND212
GND213
GND214
GND215
GND216
GND217
GND218
GND219
GND220
GND221
GND222
GND223
GND224
GND225
GND226
GND227
GND228
GND229
GND230
GND231
GND232
GND233
GND234
GND235
GND236
GND237
GND238
GND239
GND240
GND241
GND242
GND243
GND244
GND245
GND246
GND247
GND248
GND249
GND250
GND251
GND252
MCP79-TOPO-B
BGA
(11 OF 11)
AH26
AH33
AH34
AH37
AH38
AJ39
AJ8
AK10
AK33
AK34
AK37
AK4
AK40
AL36
AL40
AL5
AM10
AM16
AM18
AM20
AM22
AM24
AM26
AM30
AM34
AM35
AM37
AM38
AM5
AM6
AM7
AM9
AP26
AN28
AN30
AN39
AN4
Y7
AP10
AU26
AP14
AU14
AP28
AP32
AP34
AP36
AP37
AP4
AP40
AP7
AW23
AR28
AR32
AR40
AT10
AR12
AT13
AT29
AT33
AT6
AT7
AT9
AY21
AY22
L12
AU12
AU28
AP33
AU32
AR30
AU36
AU38
AU4
G28
F20
AV28
AV32
AV36
AV4
AV7
AW11
G20
AR43
AW43
AY10
AV12
AY30
AY33
AY34
AY37
AY38
AY41
+VTT_CPU1
+VTT_CPU2
+VTT_CPU3
+VTT_CPU4
+VTT_CPU5
+VTT_CPU6
+VTT_CPU7
+VTT_CPU8
+VTT_CPU9
+VTT_CPU10
+VTT_CPU11
+VTT_CPU12
+VTT_CPU13
+VTT_CPU14
+VTT_CPU15
+VTT_CPU16
+VTT_CPU17
+VTT_CPU18
+VTT_CPU19
+VTT_CPU20
+VTT_CPU21
+VTT_CPU22
+VTT_CPU23
+VTT_CPU24
+VTT_CPU25
+VTT_CPU26
+VTT_CPU27
+VTT_CPU28
+VTT_CPU29
+VTT_CPU30
+VTT_CPU31
+VTT_CPU32
+VTT_CPU33
+VTT_CPU34
+VTT_CPU35
+VTT_CPU36
+VTT_CPU37
+VTT_CPU38
+VTT_CPU39
+VTT_CPU40
+VTT_CPU41
+VTT_CPU42
+VTT_CPU43
+VTT_CPU44
+VTT_CPU45
+VTT_CPU46
+VTT_CPU47
+VTT_CPU48
+VTT_CPU49
+VTT_CPU50
+VTT_CPU51
+VTT_CPU52
R32
AC32
E40
J36
N32
T32
U32
V32
W32
P31
AF32
AE32
AH32
AJ32
AK31
AK32
AD32
AL31
AB32
B41
B42
C40
C41
C42
D39
D40
D41
E38
E39
F37
F38
F39
G36
G37
G38
H35
H37
J34
J35
K33
K34
K35
L32
L33
L34
M31
M32
M33
N31
P32
Y32
AA32
+VTT_CPUCLK AG32
PPCPUVTT_S0
1139 mA
43 mA
PP3V3_S0
+3.3V_1
+3.3V_2
+3.3V_3
+3.3V_4
+3.3V_5
+3.3V_6
+3.3V_7
+3.3V_8
AD10
AE8
AB10
AD9
Y10
AB11
AA8
Y9
+3.3V_DUAL1
+3.3V_DUAL2
+3.3V_DUAL3
+3.3V_DUAL4
G18
H19
J20
K20
+3.3V_DUAL_USB1
+3.3V_DUAL_USB2
+3.3V_DUAL_USB3
+3.3V_DUAL_USB4
G26
H27
J28
K28
6 7 8 9 10 11 12 13 14 17 18 20
24 25 63 67
1182 mA (A01)
82 84 85 96
47 48 49 51 55 59 60 63 68 69
6 7 8 13 18 19 21 24 25 28 29
37 39 43 45
77 80 81
450 mA 70(A01)
PP3V3_S5
16 mA
70 82 87 96
7 8 18 20 24 26 30 34 37 38 44
54 64 68 69
266 mA (A01)
250 mA
PP1V2R1V05_S5
+VDD_AUXC1 T21
+VDD_AUXC2 U21
+VDD_AUXC3 V21
7 8 24 34 68
105 mA (A01)
MCP Power & Ground

SYNC_MASTER=T18_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
22
97
MCP79 A01 Silicon Support
SYNC_MASTER=T18_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
23
97
8
MCP Core Power
66 46 22 8 7
NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
PPVCORE_S0_MCP_REG
23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)
(No IG vs. EG data)
C2500 1
C2501 1
C2502 1
C2503 1
20%
4V
X5R 2
402
20%
4V
X5R 2
402
20%
4V
X5R 2
402
20%
4V
X5R 2
402
4.7UF
4.7UF
4.7UF
4.7UF
C2504
C2505
1UF
C2506
1UF
10%
2 10V
X5R
402-1
10%
2 10V
X5R
402-1
MCP PCIE (DVDD) Power
17 14 13 12 11 10 9 8 7 6
67 63 25 24 22 20 18
1UF
C2507
1UF
10%
2 10V
X5R
402-1
C2508
0.1UF
10%
2 10V
X5R
402-1
C2509
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C2510
0.1UF
20%
2 10V
CERM
402
C2511
0.1UF
20%
2 10V
CERM
402
C2512
0.1UF
20%
2 10V
CERM
402
C2513
0.1UF
20%
2 10V
CERM
402
MCP SATA (DVDD) Power
PPCPUVTT_S0
57 mA (A01)
L2570
PPCPUVTT_S0
18 17 14 13 12 11 10 9 8 7 6
67 63 25 24 22 20
18 17 14 13 12 11 10 9 8 7 6
67 63 25 24 22 20
43 mA (A01)
PPCPUVTT_S0
333 mA (A01)
30-OHM-5A
1
2
0603
C2515
4.7UF
C2516
1UF
20%
4V
X5R 2
402
C2517
1UF
10%
2 10V
X5R
402-1
C2518
0.1uF
10%
2 10V
X5R
402-1
C2519
4.7UF
C2521
0.1uF
20%
4V
X5R 2
402
20%
2 10V
CERM
402
MCP 1.05V AUX Power

68 34 22 8 7
C2520
0.1uF
20%
2 10V
CERM
402
20%
2 6.3V
CERM
402-LF
131 mA (A01)
C2525
0.1uF
MCP FSB (VTT) Power

17 14 13 12 11 10 9 8 7 6
67 63 25 24 22 20 18
C2526
C2528 1
0.1uF
20%
2 10V
CERM
402
4.7uF
C2529
20%
2 6.3V
CERM
402-LF
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 7x 2.2uF 0402 (15.4 uF)
PPCPUVTT_S0
562 mA (A01)
30-OHM-1.7A
1
2
0402
C2530
2.2UF
C2531
2.2UF
20%
2 6.3V
CERM
402-LF
C2532
2.2UF
20%
2 6.3V
CERM
402-LF
20%
2 6.3V
CERM
402-LF
C2533
2.2UF
C2534
2.2UF
20%
2 6.3V
CERM
402-LF
20%
2 6.3V
CERM
402-LF
C2535
2.2UF
20%
2 6.3V
CERM
402-LF
C2536
C2580 1
2.2UF
20%
4V
X5R 2
402
C2540 1
4.7UF
C2541
0.1UF
20%
4V
X5R 2
402
PP3V3_S0
C2542
0.1UF
20%
2 10V
CERM
402
C2543
0.1UF
20%
2 10V
CERM
402
NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

Apple: 4x 2.2uF 0402 (8.8 uF)
C2544
0.1UF
20%
2 10V
CERM
402
450 mA (A01)
C2545
0.1UF
20%
2 10V
CERM
402
C2546
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C2547
0.1UF
C2548
30-OHM-1.7A
PP3V3_S0
19 mA (A01)
C2550
2.2UF
2.2UF
20%
2 6.3V
CERM
402-LF
MCP 3.3V AUX/USB Power

96 87 82
30 26 22 20 18 8 7
70 69 68 64 54 44 38 37 34
PP3V3_S5
C2551
20%
2 6.3V
CERM
402-LF
C2552
2.2UF
20%
2 6.3V
CERM
402-LF
C2553
MCP 3.3V Ethernet Power
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
PP3V3_S0_MCP_PLL_USB
VOLTAGE=3.3V
20
20%
2 6.3V
CERM
402-LF
C2573
34 33 24 18 8 7
PP3V3_ENET_PHY
19 mA (A01)
2
0402
C2584 1
C2555
4.7UF
20%
4V
X5R 2
402
8 20
127 mA (A01)
C2576
2.2UF
20%
6.3V
2 CERM
402-LF
14
270 mA (A01)
C2581
0.1UF
20%
10V
402
C2560
PP1V05_S0_MCP_PLL_PEX
VOLTAGE=1.05V
1
17
84 mA (A01)
C2583
0.1UF
20%
2 10V
CERM
402
PP1V05_S0_MCP_PLL_SATA
VOLTAGE=1.05V
1
20
84 mA (A01)
C2585
0.1UF
20%
2 10V
CERM
402
L2586
30-OHM-1.7A
1
83 mA (A01)
C2564
C2586 1
2.2UF
4.7UF
20%
4V
X5R 2
402
20%
2 6.3V
CERM
402-LF
PP1V05_S0_MCP_PLL_CORE
VOLTAGE=1.05V
1
16
87 mA (A01)
C2587
0.1UF
20%
2 10V
CERM
402
L2588
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
30-OHM-1.7A
1
PP1V05_S0_MCP_PLL_NV
VOLTAGE=1.05V
2
0402
C2562
C2588 1
2.2UF
4.7UF
MCP79 Ethernet VRef
20%
2 6.3V
CERM
402-LF
34 33 24 18 8 7
20%
4V
X5R 2
402
C2589
0.1UF
20%
2 10V
CERM
402
C2590
0.1UF
20%
2 10V
CERM
402
PP3V3_ENET_PHY
MCP Standard Decoupling
1.47K
1%
1/16W
MF-LF
402 2
L2595
30-OHM-1.7A
1
PP1V05_ENET_MCP_PLL_MAC
VOLTAGE=1.05V
2
0402
C2595
4.7UF
20%
4V
X5R 2
402
SYNC_MASTER=T18_MLB
MCP_MII_VREF
OUT
18

5 mA (A01)
R25901
1.47K
1%
1/16W
MF-LF
402 2
0.1UF
20%
2 10V
CERM
402
18
C2596
21
37 mA (A01)
R25911
5 mA (A01)
20%
2 6.3V
CERM
402-LF
7 mA (A01)
PP1V2R1V05_ENET
C2574
2.2UF
20%
2 6.3V
CERM
402-LF
L2584
0402
20%
2 6.3V
CERM
402-LF
37 34 33 24 18 8 7
2.2UF
2 CERM
30-OHM-1.7A
1
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
2.2UF
PP3V3_S0
20%
4V
X5R 2
402
20%
2 6.3V
CERM
402-LF
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)
1
MCP 3.3V/1.5V HDA Power
4.7UF
2.2UF
20%
2 6.3V
CERM
402-LF
266 mA (A01)
96
68 63 60 59 55 51 49 48 47
21 19 18 13 8 7 6
45 43 39 37 29 28 25 24 22
85 84 82 81 80 77 70 69
C2582 1
20%
2 10V
CERM
402
2.2UF
C2549
0.1UF
20%
2 10V
CERM
402
L2555
82 81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84
0.1UF
20%
2 10V
CERM
402
0402
1
2.2UF
L2582
1
0402
MCP 3.3V Power
C2572
PP1V05_S0_MCP_PLL_FSB
30-OHM-1.7A
PP1V8R1V5_S0_FET
4771 mA (A01, DDR3)
96
68 63 60 59 55 51 49 48 47
21 19 18 13 8 7 6
45 43 39 37 29 28 25 24 22
85 84 82 81 80 77 70 69
VOLTAGE=1.05V
4.7UF
20%
2 6.3V
CERM
402-LF
MCP Memory Power

29 28 16 12 11 8 7
70 69 68 39
20%
2 6.3V
CERM
402-LF
L2580
68 8 7
1182 mA (A01)
C2575
2.2UF
20%
2 10V
CERM
402
2.2UF
1
0.1uF
20%
4V
X5R 2
402
20%
2 10V
CERM
402
C2571
VOLTAGE=1.05V
2
0603
C2591
0.1UF
20%
10V
2 CERM
402

SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-7892
SCALE
SHT
NONE
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)
L2575
30-OHM-5A
PP1V2R1V05_ENET
37 34 33 24 18 8 7
105 mA (A01)
C2570
2.2UF
20%
2 10V
CERM
402
MCP 1.05V RMGT Power
PP1V2R1V05_S5
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)
Apple: 5x 2.2uF 0402 (11 uF)
PP1V05_S0_MCP_PEX_AVDD 8 17
206 mA (A01)
VOLTAGE=1.05V
A.0.0
OF
24
97
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
87 84 70 69 55 18 8 7
NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)
PP1V8_S0
PP3V3_S0_MCP_DAC
1
C2610
2.2UF
18 17 14 13 12 11 10 9 8 7 6
67 63 24 22 20
206 mA (A01)
R2651
20%
2 6.3V
CERM
402-LF
18
VOLTAGE=3.3V
190 mA (A01, 1.8V)
5%
1/16W
MF-LF
2 402
PPCPUVTT_S0
95 mA (A01)
C2615 1
4.7UF
90 18
90 18
MCP_HDMI_RSET
MCP_HDMI_VPROBE
NO STUFF
C2620 1
0.1UF
20%
10V
CERM 2
402
C2616
2.2UF
20%
4V
X5R 2
402
20%
6.3V
2 CERM
402-LF
90 18
90 18
R2620
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
NO STUFF
C2630 1
1K
1%
1/16W
MF-LF
2 402
0.1UF
20%
10V
CERM 2
402
25 18
NC_MCP_RGB_RED
25 18
NC_MCP_RGB_GREEN
25 18
NC_MCP_RGB_BLUE
25 18
NC_MCP_RGB_HSYNC
25 18
NC_MCP_RGB_VSYNC
NO STUFF
1
R2630
1K
1%
1/16W
MF-LF
2 402
NC_MCP_RGB_RED
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_R_C_PR
90 25 18
NC_CRT_IG_B_COMP_PB
90 25 18
NC_CRT_IG_HSYNC
90 25 18
NC_CRT_IG_VSYNC
L2640
84 82 81 80 77 70 69 68 63 60
29 28 24 22 21 19 18 13 8 7 6
59 55 51 49 48 47 45 43 39 37
96 85
PP3V3_S0
16 mA (A01)
30-OHM-1.7A
1
PP3V3_S0_MCP_VPLL
VOLTAGE=3.3V
2
0402
C2640 1
4.7UF
NC_MCP_RGB_DAC_VREF
18 25 90
NO_TEST=TRUE
18 25 90
NO_TEST=TRUE
NC_MCP_RGB_DAC_RSET
18 25
NO_TEST=TRUE
NC_MCP_RGB_DAC_VREF
MAKE_BASE=TRUE
18 25 90
NO_TEST=TRUE
NC_CRT_IG_VSYNC
MAKE_BASE=TRUE
18 25 90
NO_TEST=TRUE
NC_CRT_IG_HSYNC
MAKE_BASE=TRUE
NC_MCP_RGB_DAC_RSET
18 25 90
NO_TEST=TRUE
NC_CRT_IG_B_COMP_PB
MAKE_BASE=TRUE
25 18
18 25
NO_TEST=TRUE
NC_CRT_IG_G_Y_Y
MAKE_BASE=TRUE
25 18
NO_TEST=TRUE
NC_CRT_IG_R_C_PR
MAKE_BASE=TRUE
MAKE_BASE=TRUE
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: ???
18 25
NC_MCP_RGB_VSYNC
MAKE_BASE=TRUE
NC_CRT_IG_G_Y_Y
18 25
NO_TEST=TRUE
NC_MCP_RGB_HSYNC
MAKE_BASE=TRUE
90 25 18
18 25
NO_TEST=TRUE
NC_MCP_RGB_BLUE
MAKE_BASE=TRUE
90 25 18
18 25
NO_TEST=TRUE
NC_MCP_RGB_GREEN
18 25
NO_TEST=TRUE
18
16 mA (A01)
90 25 18
NC_MCP_TV_DAC_RSET
90 25 18
NC_MCP_TV_DAC_VREF
NC_MCP_TV_DAC_RSET
MAKE_BASE=TRUE
C2641
18 25 90
NO_TEST=TRUE
NC_MCP_TV_DAC_VREF
MAKE_BASE=TRUE
18 25 90
NO_TEST=TRUE
0.1uF
20%
6.3V 2
CERM
603
20%
2 10V
CERM
402
25 18
25 18
MAKE_BASE=TRUE
MAKE_BASE=TRUE
18 25
NO_TEST=TRUE
18 25
NO_TEST=TRUE
MCP Graphics Support
SYNC_MASTER=AMASON_M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
Current numbers from email Xiaowei Lin provided 11/12/2007 3:22pm (no official document number).
REV.
051-7892
A.0.0
OF
25
97
RTC Power Sources

Platform Reset Connections
LPC Reset (Unbuffered)
R2881
91 84 19
45 44 43 42 40 26 22 21 8 7
69 64 62 61 50 46
PP3V42_G3H
PP3V42_G3H
IN
LPC_RESET_L
33
5%
1/16W
MF-LF
402
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
4.7UF
4.7UF
20%
6.3V 2
X5R
402
33
OUT
44
SMC_LRESET_L
OUT
42
OUT
17 26 37
5%
1/16W
MF-LF
402
C28031 C28021
DEBUG_RESET_L
R2883
C28011
0.1UF
10%
16V 2
X5R
402
20%
6.3V 2
X5R
402
PCIE Reset (Unbuffered)
37 26 17
IN
PCIE_RESET_L
PCIE_RESET_L
MAKE_BASE=TRUE
R2890
C2810
RTC Crystal
21
IN
RTC_CLK32K_XTALOUT
RTC_CLK32K_XTALOUT_R
5%
1/16W
MF-LF
402
R2811
10M
Y2810
21
OUT
12pF
MCP 25MHz Crystal

IN
MCP_CLK25M_XTALOUT_R
5%
1/16W
MF-LF
402
R28161
1M
CRITICAL
21
OUT
25.0000M
SM-3.2X2.5MM
NC
NC
IN
MEM_VTT_EN_R
MINI_RESET_L
31
OUT
32
OUT
33
MEM_VTT_EN
OUT
9 65 70
LPC_CLK33M_SMC
OUT
42 91
LPC_CLK33M_LPCPLUS
OUT
44 91
5%
1/16W
MF-LF
402
12pF
R2825
2
IN
LPC_CLK33M_SMC_R
33
5%
1/16W
MF-LF
402
R2826
1
MCP S0 PWRGD & CPU_VLD

33
33
5%
1/16W
MF-LF
402
R2827
PP3V3_S5
LPC_CLK33M_GMUX
OUT
84
OUT
42 91
5%
1/16W
MF-LF
402
MCPSEQ_SMC
1
CARDREADER_PLT_RST_L
5%
50V
CERM
402
86
R2870
91 19
38 37 34 30 24 22 20 18 8 7
96 87 82 70 69 68 64 54 44
OUT
5%
1/16W
MF-LF
402
C2816
1
MCP_CLK25M_XTALIN
27
5%
1/16W
MF-LF
402
19
Y2815
5%
1/16W
MF-LF
402 2
OUT
R2894
NO STUFF
2 4
PCA9557D_RESET_L
BKLT_PLT_RST_L
R2895
5%
50V
CERM
402
R2815
1
12pF
5%
1/16W
MF-LF
402
C2815
MCP_CLK25M_XTALOUT
26 84
5%
1/16W
MF-LF
402
R2893
C2811
RTC_CLK32K_XTALIN
OUT
R2891
5%
50V
CERM
402
21
GMUX_PCIE_RESET_L
32.768K
7X1.5X1.4-SM
26 84
MAKE_BASE=TRUE
CRITICAL
5%
1/16W
MF-LF
402 2
GMUX_PCIE_RESET_L
NO STUFF
5%
1/16W
MF-LF
402
5%
50V
CERM
402
R2810
0
12pF
C2850
0.1UF
20%
10V
2 CERM
402
R2829
91 21
5
69 42
63
IN
ALL_SYS_PWRGD
IN
VR_PWRGOOD_DELAY
S0_AND_IMVP_PGOOD
MCP_PS_PWRGD
OUT
21
MCP_CPU_VLD
OUT
21
PM_CLK32K_SUSCLK
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
B
3
22
1
R2853
SOT665
PM_CLK32K_SUSCLK_R
MCPSEQ_SMC
TC7SZ08AFEAPE
U2850Y
IN
MCPSEQ_SMC
MCPSEQ_MIX
R2852
1
MCPSEQ_MIX
R2851
0
5%
1/16W
MF-LF
402
21
IN
Reset Button
MCPSEQ_SMC
R2850
MCP_CPUVDD_EN
1
5%
1/16W
MF-LF
402
42
IN
PM_SYSRST_L
XDP
5%
1/16W
MF-LF
402
13 10
IN
XDP_DBRESET_L
R2896
R2899
5%
1/16W
MF-LF
402
MCPSEQ_SMC represents MCP79 MLB power sequencing connections,

but results in MCP79 ROMSIP sequence happening after CPU powers up.
OMIT
R28971
0
33
5%
1/16W
MF-LF
402
PM_SYSRST_DEBOUNCE_L
NO STUFF
1
SB Misc
OUT
21
SYNC_MASTER=DDR
C2899
1UF
10%
2 10V
X5R
402
5%
1/16W
MF-LF
402 2
MCPSEQ_MIX is cross between MLB and internal power sequencing, which

results in earlier ROMSIP and MCP FSB I/O interface initialization.
10K pull-up to 3.3V S0 inside MCP

SILK_PART=FP SYS RESET
SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for
VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before
CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).

SIZE
DRAWING NUMBER
NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
26
97
Page Notes
MEM A VREF DQ
Power aliases required by this page:
MEM A VREF CA
MEM B VREF DQ
MEM B VREF CA
CPU FSB VREF
FRAME BUFFER VREF
- =PP3V3_S3_VREFMRGN
DAC channel
- =PP3V3_S5_VREFMRGN
Min DAC code
0x00
0x00
0x00
0x00
0x00
Max DAC code
0x87
0x87
0x87
0x87
0x55
0x00
- =PPVTT_S3_DDR_BUF
Signal aliases required by this page:
Max sink I
-3.75 mA
-3.75 mA
-3.75 mA
-3.75 mA
- =I2C_VREFDACS_SCL
Max source I
5 mA
5 mA
5 mA
5 mA
- =I2C_VREFDACS_SDA
Nominal Vref
0.75 V
0.75 V
0.75 V
0.75 V
- =I2C_PCA9557D_SCL
Min Vref
0.375 V
0.375 V
0.375 V
0.375 V
- =I2C_PCA9557D_SDA
Max Vref
1.250 V
1.250 V
1.250 V
1.250 V
Vref Stepping
6.5 mV
6.5 mV
6.5 mV
6.5 mV
0xFF
-0.91 mA
-59.04 mA
0.52 mA
51.15 mA
0.70 V
1.248 V
0.091 V
1.042 V
1.044 V
1.426 V
SO-DIMM A and SO-DIMM B Vref settings should be margined separately

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.
PPVTTDDR_S3
65 8
11.2 mV
1.5 mV
BOM options provided by this page:
10mA max load
(per DAC LSB)

VREFMRGN
R2903
NO_VREFMRGN
A2
C2903
V+
0.1UF
70 52 50 45 32 31 21 8 7
U2902
A3
27
B4
VREFMRGN
1
R2901
C2901
0.1UF
20%
2 6.3V
CERM
402-LF
100K
20%
2 10V
CERM
402
C2
B1
V+
VREFMRGN
U2900
C3
SMBUS_SMC_MGMT_SCL
6 SCL
BI
SMBUS_SMC_MGMT_SDA
7 SDA
9 A0
ADDR=0x98(WR)/0x99(RD)
10 A1
VOUTB 2
VREFMRGN_CA_SODIMM
VOUTC 4
VREFMRGN_CPUFSB
VOUTD 5
VREFMRGN_FRAMEBUF
VREFMRGN_DQ_SODIMMB_BUF
27
5%
1/16W
MF-LF
402
A2
C2904
B1
V+
20%
2 10V
CERM
402
A3
VREFMRGN_CA_SODIMMA_BUF
27
V+
VREFMRGN_CA_SODIMMB_BUF
100K
B1
V+
0.1UF
A3
U2904
VREFMRGN_FRAMEBUF_EN
100K
94 45 42 39 27
94 45 42 39 27
IN
BI
16
U2901
1 SCL
2 SDA
VREFMRGN_CPUFSB_EN 27
VREFMRGN_CA_SODIMMA_EN 27
VREFMRGN_DQ_SODIMMA_EN 27
VREFMRGN_CA_SODIMMB_EN 27
VREFMRGN_DQ_SODIMMB_EN 27
VREFMRGN_FRAMEBUF_EN 27
GND
8
29
2
Place close to J3200.126
VREFMRGN
49.9 2
GPU_FB_A_VREF_DIV
OUT
9 74
Place close to U8400, U8450
VREFMRGN
49.9 2
1%
1/16W
MF-LF
402
GPU_FB_B_VREF_DIV
OUT
9 75
Place close to U8500, U8550
VREFMRGN
U2904
R2914
MAX4253
UCSP
VREFMRGN_CPUFSB_BUF
27
VREFMRGN_CPUFSB_EN
R2913
NC
100
1%
1/16W
MF-LF
402
VREFMRGN
CPU_GTLREF
OUT
10 88
Place close to U1000.AD26
100K
VREFMRGN
5%
1/16W
MF-LF
402
NC
RESET* 15
PAD
17
THRM
6
7
9
10
11
12
13
14
5%
1/16W
MF-LF
402
C4
V-
B4
P0
P1
P2
P3
P4
P5
P6
P7
3 A0
4 A1
5 A2
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
C3
PCA9557
QFN
ADDR=0x30(WR)/0x31(RD)
V+
VCC
20%
2 10V
CERM
402
B1
VREFMRGNC1
VREFMRGN
C2
PP0V75_S3_MEM_VREFCA_B
R2917
1
R2915
VREFMRGN
1%
1/16W
MF-LF
402
VREFMRGN_FRAMEBUF_BUF
27
100
28
R2916
1
A4
V-
200
1%
1/16W
MF-LF
402
UCSP
VREFMRGN
MAX4253
B4
VREFMRGN
VREFMRGN
5%
1/16W
MF-LF
402
VREFMRGNA1
20%
2 10V
CERM
402
100
VREFMRGN
1%
1/16W
MF-LF
402
A2
C2905
VREFMRGN_CA_SODIMMB_EN
R2908
VREFMRGN
PP0V75_S3_MEM_VREFCA_A
R2912
27
VREFMRGN
1%
1/16W
MF-LF
402
C4
V-
R2911
VREFMRGN
MAX4253
B4
5%
1/16W
MF-LF
402
U2903
UCSP
VREFMRGNC1
C3
200
29
C2
0.1UF
1%
1/16W
MF-LF
402
VREFMRGN_CA_SODIMMA_EN
100K
B1
100
R2910
R2907
C2902
A4
B4
PP0V75_S3_MEM_VREFDQ_B
VREFMRGN
1%
1/16W
MF-LF
402
MAX4253
V-
VREFMRGN
R2909
VREFMRGN
U2903
UCSP
VREFMRGNA1
0.1UF
1%
1/16W
MF-LF
402
VREFMRGN_DQ_SODIMMB_EN
100K
VREFMRGN
200
VREFMRGN
R2906
R2902
GND
3
C4
B4
VREFMRGN_DQ_SODIMM
MSOP VOUTA 1
MAX4253
V-
100
R2905
VREFMRGN
94 45 42 39 27
IN
DAC5574
94 45 42 39 27
5%
1/16W
MF-LF
402
U2902
UCSP
VREFMRGNC1
8
VDD
28
1%
1/16W
MF-LF
402
2.2UF
C2900
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN
1
VREFMRGN_DQ_SODIMMA_BUF
A4
V-
PP0V75_S3_MEM_VREFDQ_A
R2904
MAX4253
UCSP
VREFMRGNA1
20%
2 10V
CERM
402
PP3V3_S3
B1
1%
1/16W
MF-LF
402
VREFMRGN
1
200
VREFMRGN
PCA9557D_RESET_L
IN
26
FSB/DDR3/FRAMEBUF Vref Margining
SYNC_MASTER=DDR

Required zero ohm resistors when no VREF margining circuit stuffed
PART NUMBER
116S0004
QTY
DESCRIPTION
1 RES,MTL FILM,0,5%,0402,SM,LF
REFERENCE DES
CRITICAL
R2903
CRITICAL
BOM OPTION

NO_VREFMRGN
116S0004
R2905
CRITICAL
NO_VREFMRGN
116S0004
R2909
CRITICAL
NO_VREFMRGN
116S0004
R2911
CRITICAL
NO_VREFMRGN
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
27
97
DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)
Page Notes
PP1V8R1V5_S0_FET
69 68 39 29 24 16 12 11 8 7
70

- =PP1V5_S0_MEM_A
70 65 30 29 8 7
- =PP1V5_S3_MEM_A
PP1V8R1V5_S3
20%
2 10V
CERM
402
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
C3100
10UF
- =I2C_SODIMMA_SCL
20%
2 6.3V
X5R
603
- =I2C_SODIMMA_SDA
C3111
0.1UF
20%
2 10V
CERM
402
C3112
0.1UF
C3113
0.1UF
20%
2 10V
CERM
402
C3114
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C3115
0.1UF
20%
2 10V
CERM
402
C3116
0.1UF
C3117
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C3118
0.1UF
20%
2 10V
CERM
402
C3119
0.1UF
20%
2 10V
CERM
402
C3120
0.1UF
20%
2 10V
CERM
402
C3121
0.1UF
20%
2 10V
CERM
402
C3122
0.1UF
20%
2 10V
CERM
402
C3123
0.1UF
20%
2 10V
CERM
402
C3101
10UF
20%
2 6.3V
X5R
603
27
PP0V75_S3_MEM_VREFDQ_A
(NONE)
C3130
2.2UF
20%
2 6.3V
CERM
402-LF
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
IN
89 15
BI
89 15
BI
89 15
BI
89 15
BI
89 15
BI
89 15
BI
MEM_A_CKE<0>
MEM_A_BA<2>
MEM_A_A<12>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_A<1>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_A<10>
MEM_A_BA<0>
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_A<13>
MEM_A_CS_L<1>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
MEM_A_DQ<34>
MEM_A_DQ<35>
89 15
BI
89 15
BI
MEM_A_DQ<44>
MEM_A_DQ<41>
89 15
IN
MEM_A_DM<5>
89 15
BI
89 15
BI
89 15
BI
89 15
BI
89 15
BI
89 15
BI
89 15
BI
89 15
BI
89 15
BI
89 15
BI
89 15
IN
89 15
BI
89 15
BI
MEM_A_DQ<45>
MEM_A_DQ<42>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DM<7>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_SA<0>
85 84 82 81 80
51 49 48 47 45
19 18 13 8 7 6
43 39 37 29 25 24 22 21
77 70 69 68 63 60 59 55
96
PP3V3_S0
MEM_A_SA<1>
C3140
2.2UF
20%
2 6.3V
CERM
402-LF
R3140
10K
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
CKE0
CKE1
VDD
VDD
NC
A15
BA2
A14
F-RT-THB
VDD
VDD
A12/BC*
A11
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK1
CK0
CK0*
CK1*
VDD
VDD
A10/AP
BA1
RAS*
BA0
VDD
VDD
WE*
S0*
CAS*
ODT0
VDD
VDD
ODT1
A13
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VSS
VSS
DM4
DQS4*
DQS4
VSS
DQ38
VSS
DQ39
DQ34
DQ35
VSS
VSS
DQ44
DQ45
DQ40
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VSS
VSS
DQS6*
DM6
VSS
DQS6
DQ54
VSS
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
VSS
DQS7*
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
SA0
EVENT*
VDDSPD
SDA
SCL
SA1
VTT
VTT
J3100
(SYMBOL 2 OF 2)
89 15
89 15
IN
DDR3-SODIMM-DUAL-M97-3
89 15
KEY
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
MEM_A_CKE<1>
IN
15 89
89 15
BI
89 15
BI
TP_MEM_A_A<15>
MEM_A_A<14>
IN
IN
15 89
89 15
IN
MEM_A_A<11>
MEM_A_A<7>
IN
15 89
89 15
BI
IN
15 89
89 15
BI
MEM_A_A<6>
MEM_A_A<4>
IN
15 89
89 15
BI
IN
15 89
89 15
BI
MEM_A_A<2>
MEM_A_A<0>
IN
15 89
89 15
BI
IN
15 89
89 15
BI
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
IN
15 89
89 15
BI
IN
15 89
89 15
BI
MEM_A_BA<1>
MEM_A_RAS_L
IN
15 89
89 15
BI
IN
15 89
89 15
BI
MEM_A_CS_L<0>
MEM_A_ODT<0>
IN
15 89
89 15
BI
IN
15 89
89 15
BI
IN
15 89
89 15
BI
89 15
BI
MEM_A_ODT<1>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DM<4>
BI
15 89
BI
15 89
IN
BI
15 89
BI
15 89
MEM_A_DQ<47>
MEM_A_DQ<40>
BI
15 89
BI
15 89
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
BI
15 89
BI
15 89
MEM_A_DQ<46>
MEM_A_DQ<43>
BI
15 89
BI
15 89
MEM_A_DQ<48>
MEM_A_DQ<53>
BI
15 89
BI
15 89
MEM_A_DM<6>
IN
BI
89 15
BI
89 15
15 89
MEM_A_DQ<38>
MEM_A_DQ<39>
89 15
IN
89 15
BI
89 15
BI
C3131
0.1UF
20%
2 10V
CERM
402
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DM<0>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<9>
MEM_A_DQ<13>
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MEM_A_DQ<11>
MEM_A_DQ<14>
MEM_A_DQ<16>
MEM_A_DQ<18>
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
MEM_A_DQ<23>
MEM_A_DQ<19>
MEM_A_DQ<24>
MEM_A_DQ<30>
MEM_A_DM<3>
MEM_A_DQ<27>
MEM_A_DQ<25>
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
VREFDQ
VSS
VSS
DQ4
DQ5
DQ0
CRITICAL
VSS
DQ1
VSS
DQS0*
DQS0
DM0
F-RT-THB
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ12
DQ8
DQ13
DQ9
VSS
VSS
DQS1*
DM1
RESET*
DQS1
VSS
VSS
DQ14
DQ10
DQ15
DQ11
VSS
VSS
DQ20
DQ16
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
DQ22
VSS
DQ18
DQ23
VSS
DQ19
DQ28
VSS
DQ24
DQ29
VSS
DQ25
DQS3*
VSS
DQS3
DM3
VSS
VSS
DQ30
DQ26
DQ31
DQ27
VSS
VSS
J3100
(SYMBOL 1 OF 2)
DDR3-SODIMM-DUAL-M97-3
C3110
0.1UF
- =PP0V75_S0_MEM_VTT_A
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
MEM_A_DQ<4>
MEM_A_DQ<5>
BI
15 89
BI
15 89
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
BI
15 89
BI
15 89
MEM_A_DQ<6>
MEM_A_DQ<7>
BI
15 89
BI
15 89
MEM_A_DQ<8>
MEM_A_DQ<12>
BI
15 89
MEM_A_DM<1>
MEM_RESET_L
IN
15 89
IN
29 30
MEM_A_DQ<15>
MEM_A_DQ<10>
BI
15 89
BI
15 89
MEM_A_DQ<21>
MEM_A_DQ<20>
BI
15 89
BI
15 89
MEM_A_DM<2>
BI
IN
15 89
15 89
MEM_A_DQ<17>
MEM_A_DQ<22>
BI
15 89
BI
15 89
MEM_A_DQ<29>
MEM_A_DQ<28>
BI
15 89
BI
15 89
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>
BI
15 89
BI
15 89
MEM_A_DQ<26>
MEM_A_DQ<31>
BI
15 89
BI
15 89
KEY
516-0196
15 89
MEM_A_DQ<50>
MEM_A_DQ<49>
BI
15 89
BI
15 89
MEM_A_DQ<57>
MEM_A_DQ<56>
BI
15 89
BI
15 89
PP0V75_S3_MEM_VREFCA_A
C3135
2.2UF
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
BI
15 89
BI
15 89
MEM_A_DQ<62>
MEM_A_DQ<63>
BI
15 89
BI
15 89
MEM_EVENT_L
OUT 21
SMBUS_MCP_0_DATA
BI
SMBUS_MCP_0_CLK
IN
20%
2 6.3V
CERM
402-LF
27
C3136
0.1UF
20%
2 10V
CERM
402
29 42
"Factory" (top) slot
13 21 29 45 91
13 21 29 45 91
7 8 29 65 70
DDR3 SO-DIMM Connector A
R3141
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
SYNC_MASTER=DDR
516-0196
SPD ADDR=0xA0(WR)/0xA1(RD)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
28
97
DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)
Page Notes
PP1V8R1V5_S0_FET
69 68 39 28 24 16 12 11 8 7
70

- =PP1V5_S0_MEM_B
70 65 30 28 8 7
- =PP1V5_S3_MEM_B
PP1V8R1V5_S3
C3200
10UF
- =I2C_SODIMMB_SCL
20%
2 6.3V
X5R
603
- =I2C_SODIMMB_SDA
C3211
0.1UF
20%
2 10V
CERM
402
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
20%
2 10V
CERM
402
C3212
0.1UF
C3213
0.1UF
20%
2 10V
CERM
402
C3214
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C3215
0.1UF
20%
2 10V
CERM
402
C3216
0.1UF
C3217
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C3218
0.1UF
20%
2 10V
CERM
402
C3219
0.1UF
20%
2 10V
CERM
402
C3220
0.1UF
20%
2 10V
CERM
402
C3221
0.1UF
20%
2 10V
CERM
402
C3222
0.1UF
20%
2 10V
CERM
402
C3223
0.1UF
20%
2 10V
CERM
402
C3201
10UF
20%
2 6.3V
X5R
603
27
PP0V75_S3_MEM_VREFDQ_B
(NONE)
C3230
2.2UF
20%
2 6.3V
CERM
402-LF
R3240
IN
MEM_B_BA<2>
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
IN
89 15
MEM_B_CKE<0>
MEM_B_A<12>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<1>
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_A<10>
MEM_B_BA<0>
MEM_B_WE_L
MEM_B_CAS_L
MEM_B_A<13>
MEM_B_CS_L<1>
IN
89 15
BI
89 15
BI
89 15
BI
89 15
BI
89 15
BI
89 15
BI
MEM_B_DQ<32>
MEM_B_DQ<37>
MEM_B_DQS_N<4>
MEM_B_DQS_P<4>
MEM_B_DQ<34>
MEM_B_DQ<35>
89 15
BI
89 15
BI
MEM_B_DQ<41>
MEM_B_DQ<40>
89 15
IN
MEM_B_DM<5>
89 15
BI
89 15
BI
89 15
BI
89 15
BI
89 15
BI
89 15
BI
89 15
BI
89 15
BI
89 15
BI
89 15
BI
89 15
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<55>
MEM_B_DQ<49>
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DM<7>
IN
10K
5%
1/16W
MF-LF
2 402
89 15
BI
89 15
BI
MEM_B_DQ<63>
MEM_B_DQ<59>
MEM_B_SA<0>
96 85
60 59 55 51 49 48
21 19 18 13 8 7 6
47 45 43 39 37 28 25 24 22
84 82 81 80 77 70 69 68 63
PP3V3_S0
MEM_B_SA<1>
R3241
C3240
10K
2.2UF
5%
1/16W
MF-LF
2 402
20%
2 6.3V
CERM
402-LF
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
CKE0
CKE1
VDD
VDD
NC
A15
A14
BA2
VDD F-RT-BGA3 VDD
A11
A12/BC*
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK1
CK0
CK0*
CK1*
VDD
VDD
A10/AP
BA1
RAS*
BA0
VDD
VDD
S0*
WE*
CAS*
ODT0
VDD
VDD
ODT1
A13
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ36
DQ32
DQ37
DQ33
VSS
VSS
DQS4*
DM4
DQS4
VSS
VSS
DQ38
DQ34
DQ39
DQ35
VSS
DQ44
VSS
DQ40
DQ45
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ47
DQ43
VSS
VSS
DQ52
DQ48
DQ53
DQ49
VSS
VSS
DQS6*
DM6
DQS6
VSS
VSS
DQ54
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
DQS7*
VSS
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
EVENT*
SA0
VDDSPD
SDA
SA1
SCL
VTT
VTT
J3200
(2 OF 2)
89 15
IN
DDR3-SODIMM
89 15
KEY
MTG PINS
MTG PIN
MTG PIN
MTG PIN
MTG PIN
MTG PIN
MTG PIN
MTG PIN
MTG PIN
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
MEM_B_CKE<1>
TP_MEM_B_A<15>
MEM_B_A<14>
IN
15 89
IN
IN
15 89
89 15
BI
MEM_B_DQ<0>
MEM_B_DQ<1>
89 15
IN
MEM_B_DM<0>
15 89
89 15
BI
IN
15 89
89 15
BI
MEM_B_A<6>
MEM_B_A<4>
IN
15 89
89 15
BI
IN
15 89
89 15
BI
MEM_B_A<2>
MEM_B_A<0>
IN
15 89
89 15
BI
IN
15 89
89 15
BI
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
IN
15 89
89 15
BI
IN
15 89
89 15
BI
MEM_B_BA<1>
MEM_B_RAS_L
IN
15 89
89 15
BI
IN
15 89
89 15
BI
MEM_B_CS_L<0>
MEM_B_ODT<0>
IN
15 89
89 15
BI
IN
15 89
89 15
BI
IN
15 89
89 15
BI
89 15
BI
MEM_B_DM<4>
BI
15 89
BI
15 89
IN
MEM_B_DQ<38>
MEM_B_DQ<39>
BI
15 89
BI
15 89
MEM_B_DQ<44>
MEM_B_DQ<45>
BI
15 89
BI
15 89
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
BI
15 89
BI
15 89
MEM_B_DQ<47>
MEM_B_DQ<46>
BI
15 89
BI
15 89
MEM_B_DQ<48>
MEM_B_DQ<54>
BI
15 89
BI
15 89
MEM_B_DM<6>
IN
89 15
BI
89 15
BI
89 15
15 89
0.1UF
20%
2 10V
CERM
402
BI
IN
MEM_B_DQ<33>
MEM_B_DQ<36>
C3231
89 15
MEM_B_A<11>
MEM_B_A<7>
MEM_B_ODT<1>
IN
89 15
BI
89 15
BI
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<28>
MEM_B_DQ<24>
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
MEM_B_DQ<15>
MEM_B_DQ<10>
MEM_B_DQ<21>
MEM_B_DQ<17>
MEM_B_DM<2>
MEM_B_DQ<18>
MEM_B_DQ<22>
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
VREFDQ
VSS
VSS
DQ4
DQ5
DQ0
CRITICAL
DQ1
VSS
VSS
DQS0*
DM0
DQS0
F-RT-BGA3
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ8
DQ12
DQ9
DQ13
VSS
VSS
DQS1*
DM1
DQS1
RESET*
VSS
VSS
DQ14
DQ10
DQ11
DQ15
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
DQ22
VSS
DQ18
DQ23
VSS
DQ19
VSS
DQ28
DQ29
DQ24
VSS
DQ25
DQS3*
VSS
DM3
DQS3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VSS
VSS
J3200
(1 OF 2)
DDR3-SODIMM
C3210
0.1UF
- =PP0V75_S0_MEM_VTT_B
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
MEM_B_DQ<4>
MEM_B_DQ<5>
BI
15 89
BI
15 89
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
BI
15 89
BI
15 89
MEM_B_DQ<6>
MEM_B_DQ<7>
BI
15 89
BI
15 89
MEM_B_DQ<29>
MEM_B_DQ<25>
BI
15 89
MEM_B_DM<3>
MEM_RESET_L
IN
15 89
IN
28 30
MEM_B_DQ<26>
MEM_B_DQ<27>
BI
15 89
BI
15 89
MEM_B_DQ<13>
MEM_B_DQ<12>
BI
15 89
BI
15 89
MEM_B_DM<1>
BI
IN
15 89
15 89
MEM_B_DQ<14>
MEM_B_DQ<11>
BI
15 89
BI
15 89
MEM_B_DQ<20>
MEM_B_DQ<16>
BI
15 89
BI
15 89
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>
BI
15 89
BI
15 89
MEM_B_DQ<19>
MEM_B_DQ<23>
BI
15 89
BI
15 89
KEY
516s0704
15 89
MEM_B_DQ<53>
MEM_B_DQ<50>
BI
15 89
BI
15 89
MEM_B_DQ<60>
MEM_B_DQ<61>
BI
15 89
BI
15 89
PP0V75_S3_MEM_VREFCA_B
C3235
2.2UF
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
BI
15 89
BI
15 89
MEM_B_DQ<58>
MEM_B_DQ<62>
BI
15 89
BI
15 89
MEM_EVENT_L
OUT 21
SMBUS_MCP_0_DATA
BI
SMBUS_MCP_0_CLK
IN
20%
2 6.3V
CERM
402-LF
27
C3236
0.1UF
20%
2 10V
CERM
402
28 42
13 21 28 45 91
"Expansion" (bottom) slot

13 21 28 45 91
7 8 28 65 70
DDR3 SO-DIMM Connector B
206
208
210
212
SYNC_MASTER=DDR

516s0704
SPD ADDR=0xA2(WR)/0xA3(RD)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
29
97
DDR3 RESET Support

Required becaues MCP79 does not meet DDR3 spec power-up reset timing requirement.
R3309
MCP_MEM_RESET_L
MEM_RESET_L
OUT
28 29
5%
1/16W
MF-LF
402
CRITICAL
Q3305
R33101
1K
B
E
R33011
20K
5%
1/16W
MF-LF
402 2
0.1UF
R3305
1
C3300
5%
1/16W
MF-LF
402 2
MEM_RESET_RC_L
10K
R3300
7 8 18 20 22 24 26 34 37 38 44
54 64 68 69 70 82 87 96
SOT-363
Q1
PP3V3_S5
DMB53D0UDW
5%
1/16W
MF-LF
402 2
PP1V8R1V5_S3
70 65 29 28 8 7
IN
Q2
16
100K
5%
1/16W
MF-LF
402 2
3.3V S5 is used because MEM_RESET

must be high before 1.5V starts to
rise to avoid glitch on MEM_RESET_L.
MEM_RESET
20%
10V
2 CERM
402
DDR3 Support
SYNC_MASTER=T18_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
30
97
17
OUT
PCIE_MINI_PRSNT_L
5V S3 WLAN FET
3
Q3401
SSM6N15FEAPE
SOT563
G 5
AP_PWR_EN
IN
21 34
Q3401
C3421
0.1uF
SSM6N15FEAPE
PP5V_WLAN_R
C3420
20%
10V
2 X5R
805
G 2
XW3451
SM
PLACEMENT_NOTEs:
Place close to Q3450.
(C3420 & C3421)
AIRPORT
CRITICAL
J3401
C3430
20347-325E-12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
10%
16V
X5R
402
0.1uF
1
F-RT-SM
31
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
96
90 7
96
90 7
OUT
7 17 90
OUT
7 17 90
2
10%
16V
X5R
402
96 7
96 7
7
7
IN
17 90
PCIE_MINI_R2D_C_N
IN
17 90
PP3V3_S3
7 8 21 27 31 32 45 50 52 70
U3402
Y
U3401
DLP11S
SYM_VER-1
PCIE_CLK100M_MINI_P
IN
17 90
PCIE_CLK100M_MINI_N
IN
17 90
WLAN_SMIT_BUF
SOT-553
4
53 96
OUT
NC
C3453 R3454
62K
1UF
1
1
BI
IN
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
Q3455
3
7 42 45 51 94
7 42 45 51 94
CONN_USB2_BT_P
CONN_USB2_BT_N
275 mA peak
206 mA nominal max
SSM3K15FV
SOD-VESM-HF
5%
1/16W
MF-LF
402 2
10%
2 6.3V
CERM
402
IN
G 1
26
ALS
CAMERA
PP3V3_S3_BT_F
VOLTAGE=3.3V
PLACEMENT_NOTE=Place close to J3401.
L3405
PP3V3_S3
7 8 21 27 31 32 45 50 52 70
FERR-120-OHM-1.5A
C3462
0402-LF
0.1uF
20%
10V
CERM 2
402
FERR-120-OHM-1.5A
PP5V_S3
7 8 9 31 39 40 41 43 51 53 55
64 65 70 79
0402-LF
1
DLP0NS
SYM_VER-1
0.1uF
L3406
VOLTAGE=5V
L3402
90-OHM
20%
10V
2 CERM
402
34
7 17
CRITICAL
C3422
IN
WLAN_SMIT_DISCHRG
5%
1/16W
MF-LF
402
MINI_RESET_L
PP5V_S3_BTCAMERA_F
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
PM_WLAN_EN_L
5%
1/16W
MF-LF
402
PLACE_NEAR=J3401.8,2mm
MINI_CLKREQ_Q_L
PCIE_WAKE_L
MINI_RESET_CONN_L
PP5V_WLAN
100K 2
R3455
WLAN_SMIT_RC
53 96
OUT
NC
NC
26
27
28
29
30
5%
1/16W
MF-LF
402 2
MIN_LINE_WIDTH=1 mm
VOLTAGE=5V
OUT
5%
1/16W
MF-LF
2 402
R3450
R34531
74LVC1G17DRL
L3401
90-OHM-100MA
10K
P5VWLAN_SS
R3451
33K
TC7SZ08AFEAPE 5
SOT665
ISNS_AIRPORT_P
ISNS_AIRPORT_N
PCIE_MINI_R2D_C_P
7 8 9 31 39 40 41 43 51 53 55
64 65 70 79
1
1
10%
16V
X5R
402
0.1UF
XW3452
SM
CRITICAL
PCIE_MINI_R2D_P
PCIE_MINI_R2D_N
C3451
0.033UF
10%
16V 2
X5R
402
C3450
C3431
0.1uF
PP5V_S3
MIN_LINE_WIDTH=1 mm
VOLTAGE=5V
2
1
23V1K-SM
10UF
20%
10V
CERM 2
402
SOT563
0.8 A (EDP)
PP5V_WLAN_F
MIN_LINE_WIDTH=1 mm
VOLTAGE=5V
4 G
Loading
TPCP8102
6 7
53
0402-LF
14 mOhm @4.5V
MINI_CLKREQ_L
P-Channel
Rds(on)
Q3450
XW3450
SM
L3404
OUT
TPCP8102
Type
CRITICAL
1000 mA peak
FERR-120-OHM-1.5A
750 mA nominal max
2
1
Part
17
C3452
0.1uF
USB_CAMERA_P
BI
7 20 91
USB_CAMERA_N
BI
7 20 91
20%
10V
2 CERM
402
CRITICAL
32
BLUETOOTH
L3403
90-OHM
DLP0NS
518S0610
SYM_VER-1
USB_BT_P
BI
7 20 91
USB_BT_N
BI
7 20 91
Right Clutch Connector

SYNC_MASTER=MUXGFX

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
31
97
R3511
70 52 50 45 31 27 21 8 7
PP3V3_S3
VOLTAGE=3.3V
PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN
32
5%
1/16W
MF-LF
402
PP3V3_S3_CARDREADER_DVDD
1
C3500
10UF
0.1UF
20%
6.3V
2 X5R
603
C3501
C3502
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
VOLTAGE=3.3V
C3503
0.1UF
20%
10V
2 CERM
402
L3500
0.22UH
PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN
PP3V3_S3_CARDREADER_AVDD
1
C3514
10UF
C3504
0.1UF
20%
2 6.3V
X5R
603
VOLTAGE=3.3V
0805-1
MAX CURRENT = 250MA
C3508
PLACEMENT_NOTE=KEEP THIS NET AS SHORT AS POSSIBLE
0.1UF
20%
2 10V
CERM
402
PP3V3_SW_SD_PWR
20%
2 10V
CERM
402
VOLTAGE=3.3V
1
1
C3507
2.2UF
C3505
0.1UF
20%
6.3V
2 CERM1
603
20%
10V
2 CERM
402
R3505
39K
5%
1/16W
MF-LF
2 402
PP1V8_S3_CARDREADER
1
VOLTAGE=1.8V
C3506
0.1UF
20%
2 10V
CERM
402
OMIT
96 20 9
96 20 9
BI
32
32
CARDREADER_GPIO1
CARDREADER_GPIO2
NC
LQFP
48 GPIO1
47 GPIO2
46 GPIO3
19
SK
NC
20 CS
NC
21 DO
NC
22 DI /IPD
NC
R3503
1M
IPD/
IPD/
10 RREF
CARDREADER_RREF
5%
1/16W
MF-LF
402
17 TESTMOD
CARDREADER_TEST_MOD
CARDREADER_RESET_L 18 EXTRSTZ* /IPU
Y3500
12.000M-100PPM
2
IPD/
5%
50V
CERM
402
5%
50V
CERM
402
C3513
0.1UF
93 7
93 7
93 7
93 7
93 7
93 7
SD_CLK_R
5 G
CARDREADER_RESET
7
8
9
1
10
11
12
13
14
16
4
17
18
R3504
NC
NC
42
NC
44
NC
45
NC
31
19
20
5%
1/16W
MF-LF
402
VSS
VSS
CLK
CMD
DAT0
DAT1
DAT2
CD/DAT3
DAT4
DAT5
DAT6
DAT7
CARD_DETECT_SW
CARD_DETECT_GND
WRITE_PROTECT_SW
VDD
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
NO STUFF
1
C3515
10PF
5%
50V
2 CERM
402-1
NC
NC
GND
20%
10V
2 CERM
402
PDMOD: POWER DOWN MODES

NC = DISABLE (DEFAULT)
10K LOW = POWER SAVING MODE ENABLE
10K HIGH = REMOTE WAKE UP ENABLE
D 3
R3512
TABLE_5_HEAD
10K
SOT563
IN
CARDREADER_PDMOD
24
IPU/ MS_INS
MS_BS 33
15
SSM6N15FEAPE
17
SD_WP
93 7
32
Q3500
93 7
34
5%
1/16W
MF-LF
2 402
40
43
37
29
28
30
32
38
SD_CMD 41
2
IPU/ PDMOD
23
IPU/ SD_CDZ
27
1%
1/16W
MF-LF
2 402
NO STUFF
R3502
715
12
R3506
33PF
16
C3512
33PF
93 7
D0
D1
D2
D3
D4
D5
D6
D7
SD_WP 3
8X4.5X1.4-SM
C3511
IPU/ XD_CDZ
XD_CE
IPD/ XD_WEZ
IPD/ XD_RBZ
IPD/ XD_WPZ
/IPD
CRITICAL
SD_CLK
SD_CMD
SD_D<0>
SD_D<1>
SD_D<2>
SD_D<3>
SD_D<4>
SD_D<5>
SD_D<6>
SD_D<7>
SD_CD_L
93 7
CLK 39
13 X1
14 X2
CARDREADER_XTAL1
CARDREADER_XTAL2
NO STUFF
36
25
GL137A
F-RT-TH
PMOSO
VDD5V
15
26
35
DVDD
U3500
7 DM
8 DP
USB_CARDREADER_N
USB_CARDREADER_P
BI
6
AVDD 11
VDD18O
J3500
SD-CARD-K19
PART#
5%
1/16W
MF-LF
2 402
S 4
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
J3500
CRITICAL
BOM OPTION
TABLE_5_ITEM
516-0225
CONN,SD CARD READER,OPTN B
(PDMOD)
CARDREADER_PLT_RST
Q3500
D 6
10K
SOT563
26
IN
32
R3507
32
5%
1/16W
MF-LF
2 402
S 1
2 G
CARDREADER_PLT_RST_L
NO STUFF
R3513
SSM6N15FEAPE
NO STUFF
R3508
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
CARDREADER_GPIO1
SECUREDIGITAL CARD READER

SYNC_MASTER=VEMURI
CARDREADER_GPIO2 32
1NO
STUFF
R3509

R3510
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
32
97
PP1V2R1V05_ENET
C3710 1 C3711 1
0.1UF
34 24 18 8 7
10%
16V
X5R 2
402
PP3V3_ENET_PHY
0.1UF
7 8 18 24 34 37
(221mA typ - 1000base-T)

( 7mA typ - Energy Detect)
WF: Marvell numbers, update for Realtek
CRITICAL
10%
16V
X5R 2
402
L3715
FERR-120-OHM-1.5A
0402-LF
(43mA typ - 1000base-T)

(19mA typ - Energy Detect)
WF: Marvell numbers, update for Realtek
C3700
0.1UF
CRITICAL
L3705
FERR-120-OHM-1.5A
10%
2 16V
X5R
402
C3701
0.1UF
10%
2 16V
X5R
402
C3702
0.1UF
10%
2 16V
X5R
402
PP1V05_ENET_PHYAVDD
C3714 1
0402-LF
C3715 1 C3716 1
0.1UF
0.1UF
10%
16V 2
X5R
402
VOLTAGE=1.05V
0.1UF
10%
16V 2
X5R
402
10%
16V 2
X5R
402
PP3V3_ENET_PHYAVDD
VOLTAGE=3.3V
C3705
0.1UF
10%
16V
2 X5R
402
C3706
0.1UF
10%
16V
2 X5R
402
TP_PP3V3_ENET_PHY_VDDREG
If internal switcher is used, must place 1x 22uF &

1x 0.1uF caps within 5mm of U3700 pins 44 & 45.
GND
IN
IN
ENET_CLK125M_TXCLK
22
ENET_CLK125M_TXCLK_R
92 18
IN
ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>
92 18
IN
ENET_TX_CTRL
92 18
IN
92 18
IN
92 18
ENSWREG
10
40
AVDD12
28
36
44
45
15
21
37
U3700
ENET_RESET_L
IN
92 18
IN
92 18
BI
ENET_MDC
ENET_MDIO
ENET_RESET_L is not asserted when WOL is active.

Hence, RC (R3725 and C3725) are made NOSTUFF.
NO STUFF
RTL8211_PHYRST_L
5%
1/16W
MF-LF
402
R37521
R3751
4.7K
NC_RTL8211_REGOUT
4.7K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402 2
If internal switcher is used, must place inductor within 5mm

of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.
If internal switcher is not used, VDDREG and REGOUT can float.
REGOUT
48
RXC
19
RXD[0]
RXD[1]/TXDLY
RXD[2]/AN0
RXD[3]/AN1
14
16
17
18
RXCTL
13
RTL8211CLGR
22
TXC
23
24
25
26
TXD[0]
TXD[1]
TXD[2]
TXD[3]
27
TXCTL
30
31
MDC
MDIO
RGMII/MII
29
PHYRSTB*
0.1UF
RTL8211_RSET
20%
2 10V
CERM
402
RTL8211_CLK125
46
32
RSET
CLOCK
2.49K
IN
RTL8211_CLK25M_CKXTAL1
TP_RTL8211_CKXTAL2
42
43
92
92
ENET_RXD_R<0>
ENET_RXD_R<1>
ENET_RXD_R<2>
ENET_RXD_R<3>
R3791
R3792
R3793
R3794
22
22
22
22
1
1
1
1
2
2
2
2
ENET_RXCTL_R
R3795
22
ENET_MDI_P<0>
ENET_MDI_N<0>
BI
35 92
BI
35 92
MDI+[1]
MDI-[1]
4
5
ENET_MDI_P<1>
ENET_MDI_N<1>
BI
35 92
BI
35 92
MDI+[2]
MDI-[2]
8
9
ENET_MDI_P<2>
ENET_MDI_N<2>
BI
35 92
BI
35 92
MDI+[3]
MDI-[3]
11
12
ENET_MDI_P<3>
ENET_MDI_N<3>
BI
35 92
BI
35 92
LED0/PHYAD0
LED1/PHYAD1
LED2/RXDLY
34
35
38
RTL8211_PHYAD0
RTL8211_PHYAD1
RTL8211_RXDLY
CKXTAL1
CKXTAL2
LED
ENET_CLK125M_RXCLK
2
5%
1/16W MF-LF 402
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
5%
1/16W MF-LF 402
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
ENET_RX_CTRL
OUT
18 92
OUT
18 92
OUT
18 92
OUT
18 92
OUT
18 92
OUT
18 92
GND
C3790 1
7
20
33
47
92 34
92
22
CLK125
R37301
1%
1/16W
MF-LF
402 2
REFERENCE
92
R3790
ENET_CLK125M_RXCLK_R
1
2
RESET MEDIA DEPENDENT
C3725
92
MDI+[0]
MDI-[0]
MANAGEMENT
R3724
IN
5%
1/16W
MF-LF
402 2
TQFP
5%
1/16W
402
MF-LF
PLACE R3796 CLOSE TO U1400, PIN D24
92 18
4.7K
OMIT
39
R3796
92 18
DVDD12
5%
1/16W
MF-LF
2 402
FB12
4.7K
VDDREG
5%
1/16W
MF-LF
402 2
Alias to =PP3V3_ENET_PHY for internal switcher.

Alias to GND for external 1.05V supply.
R3725
AVDD33
10K
DVDD33
NO STUFF
R37201
6
41
NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.
R37501
10PF
5%
50V
CERM 2
402
R37551 R37561
4.7K
5%
1/16W
MF-LF
402 2
4.7K
5%
1/16W
MF-LF
402 2
R3757
4.7K
5%
1/16W
MF-LF
2 402
Reserved for EMI

per RealTek request.
Ethernet PHY (RTL8211CL)
SYNC_MASTER=SUMA_M98_MLB

Configuration Settings:
SIZE
PHYAD
AN[1:0]
RXDLY
TXDLY
=
=
=
=
01
11
0
0
DRAWING NUMBER
(PHY Address 00001)

(Full auto-negotiation)
(RXCLK transitions with data)
(No TXCLK Delay)
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
33
97
3.3V ENET FET

CRITICAL
@ 2.5V Vgs:
Rds(on) = 90mOhm max
I(max) = 1.7A (85C)
Q3810
NTR4101P
SOT-23-HF
37 34 30 26 24 22 20 18 8 7
96 87 82 70 69 68 64 54 44 38
PP3V3_S5
PP3V3_ENET_PHY
S
5%
1/16W
MF-LF
402 2
R3810
P3V3ENET_EN_L
10%
16V
2 X5R
402
C3810
0.01UF
100K 2
P3V3ENET_SS
5%
1/16W
MF-LF
402
D 3
0.033UF
10K
Q3801
C3811
R38001
7 8 18 24 33
D 3
10%
16V
CERM
402
SSM6N15FEAPE
SOT563
5 G
34 21 9
IN
S 4
PM_SLP_RMGT_L
MOBILE:
Recommend aliasing PM_SLP_RMGT_L and
=P3V3ENET_EN. Nets separated on
ARB for alternate power options.
WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
PM_WLAN_EN_L
OUT
31
Q3805
D 6
SSM6N15FEAPE
SOT563
2 G
31 21
IN
68 24 22 8 7
1.8V Vgs
C3840 1
Q3805
D 3
6 D
Q3801
37 34 30 26 24 22 20 18 8 7
96 87 82 70 69 68 64 54 44 38
SOT563
IN
1 S
100K 2
Q3841
IN
P1V05ENET_EN_L
PM_SLP_S3_L
10K
SOT23
2 G
PP1V2R1V05_ENET
S 1
7 8 18 24 33 37
C3841
0.01UF
10%
2 16V
CERM
402
1%
1/16W
MF-LF
402
D 3
Q3841
D 6
SOT563
R3841
84 82 69 42 37 21 7
SI2312BDS
SSM6N15FEAPE
1%
1/16W
MF-LF
402 2
SMC_ADAPTER_EN
Q3840
1
69.8K
G 2
CRITICAL
P1V05ENET_SS
5%
1/16W
MF-LF
402
R38421
S 4
20%
10V
CERM 2
402
R3840
PP3V3_S5
SSM6N15FEAPE
SOT563
5 G
0.1UF
AC_OR_S0_L
SSM6N15FEAPE
43 42 37 21
PP1V2R1V05_S5
S 1
AP_PWR_EN
1.05V ENET FET
Pull-up is with power FET.
P1V05ENET_EN_L_RC
SSM6N15FEAPE
SOT563
5 G
34 21 9
IN
S 4
PM_SLP_RMGT_L
Non-ARB:
Recommend aliasing PM_SLP_RMGT_L and
=P1V05ENET_EN. Nets separated on
ARB for alternate power options.
RTL8211 25MHz Clock
Ethernet & AirPort Support
NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.
Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.
SYNC_MASTER=SUMA_M98_MLB
R3895
92 18
IN
MCP_CLK25M_BUF0_R
22
OUT

33 92
5%
1/16W
MF-LF
402

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
34
97
Page Notes
(NONE)
(NONE)
(NONE)
Place one of 0.1uf cap close to each centertap pin of transformer
ENETCONN_CTAP
1
1 C39021 C39041 C3906

C3900
0.1UF 0.1UF 0.1UF 0.1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
10%
2 16V
X5R
402
10%
2 16V
X5R
402
CRITICAL
92 33
92 33
BI
ENET_MDI_P<0>
BI
ENET_MDI_N<0>
T3900
SM
96
12
ENETCONN_P<0>
96
11
ENETCONN_N<0>
10
ENET_CTAP0
ENET_CTAP1
8 96
ENETCONN_N<1>
7 96
ENETCONN_P<1>
CRITICAL
J3900
RJ45-M97-3
TX
4
92 33
BI
ENET_MDI_N<1>
92 33
BI
ENET_MDI_P<1>
TLA-6T213HF
F-RT-TH
9
10
1
2
3
4
5
6
7
8
RX
CRITICAL
92 33
BI
ENET_MDI_N<2>
92 33
BI
ENET_MDI_P<2>
T3901
SM
96
12
ENETCONN_N<2>
96
11
ENETCONN_P<2>
10
ENET_CTAP2
11
12
514-0636
TX
4
92 33
92 33
TLA-6T213HF
ENET_CTAP3
BI
ENET_MDI_N<3>
8 96
ENETCONN_N<3>
BI
ENET_MDI_P<3>
7 96
ENETCONN_P<3>
RX
Transformers should be
1R39011
mirrored on opposite
R3900
75
75
sides of the board
5%
5%
B
CRITICAL
C3910
10PF
5%
2 50V
CERM
402-1
CRITICAL
C3920
10PF
5%
2 50V
CERM
402-1
CRITICAL
C3911
10PF
5%
2 50V
CERM
402-1
CRITICAL
C3930
10PF
5%
2 50V
CERM
402-1
CRITICAL
C3921
10PF
5%
2 50V
CERM
402-1
CRITICAL
C3940
10PF
5%
1/16W
MF-LF
4022
1/16W
MF-LF
4022
1R3903
R3902
75
75
5%
1/16W
MF-LF
2402
5%
1/16W
MF-LF
2402
ENET_BOB_SMITH_CAP1
402-1
2 50V
CERM
402-1
C3908
1000PF
2 50V
CERM
CRITICAL
1 C3931
10PF
5%
CRITICAL
2
10%
2KV
CERM
1206
CRITICAL
C3941
10PF
5%
2 50V
CERM
402-1
PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.
Ethernet Connector

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
35
97
PP3V3_FW_FWPHY
7 mA I/O
C4120 1
C4121 1 C4122 1
1UF
1UF
10%
6.3V 2
CERM
402
C4123 1 C4124 1
1UF
10%
6.3V 2
CERM
402
8 36 37 38
138 mA
1UF
10%
6.3V 2
CERM
402
1UF
10%
6.3V 2
CERM
402
10%
6.3V 2
CERM
402
L4130
120-OHM-0.3A-EMI
1
2
PP3V3_FW_FWPHY_VDDA
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
BOM OPTION
114 mA FireWire PHY

TABLE_5_ITEM
114S0557
RES,0.475 ohm,1%,1/16W,0402
R4100
C4130 1 C4131 1
1UF
OMIT
1
0.2
VOLTAGE=1.0V
1%
1/16W
MF-LF
402
135 mA
10%
6.3V 2
CERM
402
L4135
120-OHM-0.3A-EMI
1
2
PP1V0_FW_FWPHY_AVDD
PP1V0_FW_R
25 mA PCIe SerDes
VOLTAGE=1.0V
0402-LF
C4110
1UF
10%
2 6.3V
CERM
402
C4100
1UF
10%
2 6.3V
CERM
402
C4101
1UF
10%
2 6.3V
CERM
402
120-OHM-0.3A-EMI
1
2
PP3V3_FW_FWPHY_VP25
17 mA PCIe SerDes
C4111
1UF
C4135 1
C4136 1
10%
6.3V 2
CERM
402
10%
6.3V 2
CERM
402
1UF
10%
2 6.3V
CERM
402
110 mA Digital Core

1
0402-LF
1UF
10%
6.3V 2
CERM
402
L4110
R4100
PP1V0_FW
C4132 1
1UF
10%
6.3V 2
CERM
402
37 8
VOLTAGE=3.3V
CRITICAL
VOLTAGE=3.3V
0402-LF
1UF
0 mA VReg PWR
1
C4102
1UF
10%
2 6.3V
CERM
402
C4103
1UF
10%
2 6.3V
CERM
402
C4104
1UF
C4105
1UF
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
C4106
C4141 1
1UF
0.1UF
10%
2 6.3V
CERM
402
20%
10V
CERM 2
402
C4140
1UF
10%
2 6.3V
CERM
402
VDD10
PPVP_FW_CPS
R41601
200K
1%
1/16W
MF-LF
402 2
C4150
R4150
22PF
2
1
NC
22PF
Y4150
24.576MHZ
412
1%
1/16W
MF-LF
402
SM-3.2X2.5MM
R41611
2.94K
1%
1/16W
MF-LF
402 2
C4151 NC
2 4
5%
50V
CERM
402
FW_CLK24P576M_XO
CRITICAL
R4170
191
1%
1/16W
MF-LF
2 402
5%
50V
CERM
402
R41621
470K
5%
1/16W
MF-LF
402 2
IN
38
IN
38
IN
93 38
BI
93 38
BI
93 38
BI
93 38
BI
38
BI
38
BI
93 38
BI
93 38
BI
93 38
BI
93 38
BI
38
BI
38
BI
38
BI
38 37
BI
38
BI
FWPHY_DS0
FWPHY_DS1
FWPHY_DS2
B8
A8
B5
A5
B3
A3
B9
A9
B6
A6
B4
A4
NC_FW0_TPBIAS
FW_P1_TPBIAS
NC_FW2_TPBIAS
TPA0N
TPA0P
TPA1N
TPA1P
TPA2N
TPA2P
TPB0N
TPB0P
TPB1N
TPB1P
TPB2N
TPB2P
L6
L9
L5
L10
K12
90
90
90
90
0.1UF
PCIE_FW_R2D_N
PCIE_FW_R2D_P
PCIE_FW_D2R_C_N
PCIE_FW_D2R_C_P
C4175
1
0.1UF
C4176
1
BGA
REFCLKN N9
REFCLKP N10
PCI EXPRESS PHY
TP_FW643_TCK
TP_FW643_TDI
TP_FW643_TDO
TP_FW643_TMS
NT-2 (IPU) TRST* N1
FW643_TRST_L
NT-4 (IPU) TCK

NT-3 (IPU) TDI
(IPU) TDO
NT-1 (IPU) TMS
0.1UF
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
M4
N2
M1
M3
NT-10 (IPD)
FIXME!!! - TYPO IN SYMBOL REGCTL
POWER MANAGEMENT
NT-12 (IPD)
NT-13
IN
17 90
IN
17 90
PCIE_FW_R2D_C_N
IN
17 90
PCIE_FW_R2D_C_P
IN
17 90
10%
2 16V
X5R 402
10%
2 16V
X5R 402
PCIE_FW_D2R_N
OUT
17 90
PCIE_FW_D2R_P
OUT
17 90
PLACEMENT_NOTE=Place C4175 close to U4000

PP3V3_FW_FWPHY
WAKE*
REGCLT
VAUX_DETECT
VAUX_DISABLE
(OD) CLKREQN
C2
D13
E1
D2
L2
8 36 37 38
FW643_LDO
R41651
FW643_WAKE_L
FW643_REGCTL
FW643_VAUX_DETECT
TP_FW643_VAUX_ENABLE
FW_CLKREQ_PHY_L
OUT
9 37
OUT
37
5%
1/16W
MF-LF
402 2
R4166
10K
5%
1/16W
MF-LF
2 402
R4164
10K
K1
L8
F13
G13
NAND_TREE
REXT
XO
XI NT-9
TP_FW643_SE
TP_FW643_SM
TP_FW643_MODE_A
TP_FW643_CE
TP_FW643_FW620_L
TP_FW643_JASI_EN
TP_FW643_AVREG
TP_FW643_VBUF
FW643_PU_RST_L
M13
N13
J2
L13
D12
D1
A10
H13
K13
SE (IPD)
SM (IPD)
MODE_A (IPD) NT-18
CE (IPD)
FW620* (IPU)
JASI_EN (IPD) NT-11
AVREG
VBUF
FW_RESET* (IPU) NT-8
NT-16 (IPD) SCIFCLK

NT-14 (IPD) SCIFDAIN
NT-17 SCIFDOUT
NT-15 (IPD)
SCIFMC
SCIF
NT-OUT
NOTE: NT-xx notes show
NAND tree order.
SERIAL EEPROM
CONTROLLER
NT-7 SCL
NT-6 SDA
G2
G1
H1
F2
TP_FW643_SCIFCLK
TP_FW643_SCIFDAIN
TP_FW643_SCIFDOUT
TP_FW643_SCIFMC
N12
M11
FW643_SCL
TP_FW643_SDA
N4
FW_RESET_L
5%
1/16W
MF-LF
2 402
MISCELLANEOUS
CHIP RESET
NT-5 PERST*
IN
37
R4163
10K
J12 OCR_CTL_V10
J13 OCR_CTL_V12 (Reserved)
VSS
10%
2 6.3V
CERM-X5R
402
N8
N7
N5
N6
10%
2 16V
X5R 402
10%
2 16V
X5R 402
10K
TP_FW643_NAND_TREE
FW643_REXT
FW_CLK24P576M_XO_R
FW_CLK24P576M_XI
0.33UF
FW643
1394 PHY
B11 R0
B10 TPCPS
NC
PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N
PCIE_TXD0P
TEST CONTROLLER
FW643_R0
FW643_TPCPS
C4162
0.1UF
C4171
1
VREG_PWR
U4100
B7 TPBIAS0
C3 TPBIAS1
A2 TPBIAS2
TP_FW643_OCR10_CTL
1
VP25
OMIT
CRITICAL
B13 ATBUSB
A13 ATBUSH
A11 ATBUSN
F12 DS0 (IPD) NT-19
E12 DS1 (IPD) NT-20
E13 DS2 (IPD) NT-21
NC_FW0_TPAN
NC_FW0_TPAP
FW_PORT1_TPA_N
FW_PORT1_TPA_P
NC_FW2_TPAN
NC_FW2_TPAP
NC_FW0_TPBN
NC_FW0_TPBP
FW_PORT1_TPB_N
FW_PORT1_TPB_P
NC_FW2_TPBN
NC_FW2_TPBP
VP
5%
1/16W
MF-LF
2 402
VREG_VSS
B2
D4
D7
D9
D10
E4
E5
E9
F4
F6
F7
F8
F10
G4
G6
G7
G8
G10
H4
H6
H7
H8
H10
J4
J5
J9
J10
K4
K5
K7
K8
K9
L7
K6
K10
38
38
VDDH
VDD33
L12
NC
NC
NC
A12
D5
D6
D8
C1
C12
F1
G12
J1
L3
L11
M2
A1
B1
B12
C13
E2
E10
H2
H12
K2
L1
M12
N3
N11

C4170
1
FireWire LLC/PHY (FW643)
SYNC_MASTER=SENSOR

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
4.12.0
OF
36
97
Page Notes
3.3V FW FET
@ 2.5V Vgs:
- =PPBUS_S5_FWPWRSW (system supply for bus power)

- =PP3V3_FW_LATEVG_ACTIVE
81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84 82
CRITICAL
PP3V3_S0
81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84 82
Q4291
Rds(on) = 90mOhm max

I(max) = 1.7A (85C)
- =PPVP_FW_SUMNODE (power passthru summation node)
NTR4101P
R4281
PP3V3_FW_FWPHY
(NONE)
3
37 36 8
10K
R4291
1
PP3V3_FW_FWPHY
Q4290
D 3
SOT563
FW_PLUG_DET_L
R4276
5 G
100K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
37 19
IN
SOT-563
1UF
PCIE_FW_PRSNT_L
OUT
9 17
MAKE_BASE=TRUE
Q4264
D 3
P1V0_RESET_GATE
SOT563
FW_CLKREQ_L
1.05V FW FET
SOT-563
37 34 33 24 18 8 7
5 G
PP1V2R1V05_ENET
R4283
OUT
17
CRITICAL
C4296 1
Q4264
0.1UF
10%
16V
2 X5R
402
20%
10V
CERM 2
402
R4297
38 37 36 8
220K 2
1
PP3V3_FW_FWPHY
Q4276
SI2312BDS
PP3V3_S5
2 G
96 87 82 70 69 68
26 24 22 20 18 8 7
64 54 44 38 37 34 30
D 6
FW_RESET_L
37 19
PP1V05_FW PGOOD/FW_RESET_L
SOT563
PP1V0_FW
10K
2 G
5%
1/16W
MF-LF
402 2
37 36
C4295
IN
FW_CLKREQ_PHY_L
37
36
FW_CLKREQ_PHY_L
MAKE_BASE=TRUE
FireWire Port Power Switch
0.068UF
100K 2
5%
1/16W
MF-LF
402
D 3
8 36 37
NOSTUFF
1
R4296
P1V05_FW_EN_L
Q4293
S 1
36
SSM6N15FEAPE
OUT
S 1
FW_PWR_EN
R42951
17 26
SOT23
Q4293
SOT-563
FW643_WAKE_L
IN
SOT-563
2 G
DMB53D0UV
36 9
PCIE_RESET_L
DMB53D0UV
2 G
Q4299
P1V05FW_SS
SOT563
CRITICAL
Q4295
5%
1/16W
MF-LF
402
D 6
SSM6N15FEAPE
10K
5%
1/16W
MF-LF
402
S 4
C4276
DMB53D0UV
10%
6.3V 2
CERM
402
10%
16V
CERM
402
CRITICAL
Q4299
C4281 1
CRITICAL
0.1UF
S 4
DMB53D0UV
NOSTUFF
2 402
P1V0_FW_RC
0.01UF
P3V3FW_SS
FW_PWR_EN
Q4276
FW_WAKE
5%
1/16W
MF-LF
C4291
SSM6N15FEAPE
3
CRITICAL
10K
1%
1/16W
MF-LF
402
9 19 37
5%
1/16W
MF-LF
402
SSM6N15FEAPE
10K
10%
2 16V
X5R
402
100K 2
PP1V0_FW
0.033UF
P3V3FW_EN_L
38 37 36 8
C4290
5%
1/16W
MF-LF
402 2
100K
R4280
8 36 37 38
R4290
R42771
PP3V3_S0
SOT-23-HF
P1V05_FW_EN_L_RC
10%
2 10V
CERM
402
SSM6N15FEAPE
SOT563
5 G
37 19
S 4
FW_PWR_EN
CRITICAL
CRITICAL
Q4260
NDS9407
79 67 66 65 64 62 61 46 8 7
86 83
PPBUS_G3H
1
R4260
CRITICAL
SOT-563
Late-VG Event Detection
PPVP_FW
PP3V3_S0
37 34 33 24 18 8 7
59 60 63 68 69 70 77 80 81 82
6 7 8 13 18 19 21 22 24 25 28
29 37 39 43 45 47 48 49 51 55
84 85 96
R4274
PP1V2R1V05_ENET
100K
R4275
Q4261
D 6
SSM6N15FEAPE
D 3
Q4261
SSM6N15FEAPE
SOT563
IN
84 82 69 42 34 21 7
IN
PP3V3_S5
PP2V4_FW_LATEVG
FW_PLUG_DET_L
56K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
SOT563
S 1
5 G
OUT
9 19 37
CRITICAL
Q4275
DMB53D0UV
SOT-563
S 4
SMC_ADAPTER_EN
FW_PLUG_DET
FW_DET_MIRROR
FW_PWR_EN_L
2 G
42 34 21
43
R4271
330K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
R4270
1K
10%
10V
X5R 2
402-1
CRITICAL
Q4270
BC847CDXV6TXG
SOT563
PM_SLP_S3_L
CRITICAL
Q4270
BC847CDXV6TXG
SOT563
1
C4270
0.1UF
10%
16V
2 X5R
402
Enables port power when machine
FW_P1_TPBIAS_R
is running or on AC.
R42111
10K
5%
1/16W
MF-LF
402 2
R4212
10K
2
4
R4272
SM-HF
1K
6
D
U4210
1
P2V4_FWLATEVG_RC
CRITICAL
5%
1/16W
MF-LF
2 402
Q4275
R4273
12K
5%
1/16W
MF-LF
2 402
DMB53D0UV
LMC7211
V+
FW_DET_EMIT
1
20%
2 10V
CERM
402
1%
1/16W
MF-LF
2 402
C4210
0.1UF
FWLATEGV_3V_REF
SOT-563
LATEVG_EVENT
37 19
IN
FW_PWR_EN
FireWire Port Power
2 G
SYNC_MASTER=YUN_K19_MLB
C4211
100pF
5%
50V
CERM 2
402
V-
R4213
80.6K

1%
1/16W
MF-LF
2 402
R4210
1
200K 2
1%
1/16W
MF-LF
402

FWLATEVG Hysteresis:
3.08V when port power is on

2.91V when late Vg event and port power is off
38 36
IN
FW_P1_TPBIAS
SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-7892
SCALE
SHT
NONE
8 38
FWPWR_EN_L
1UF
96 87 82
54 44 38 37
22 20 18 8 7
34 30 26 24
70 69 68 64
CRS08-1.5A-30V
3
2
5%
1/16W
MF-LF
2 402
LATEVG_FAULT_EVENT
1%
1/16W
MF-LF
402
C4263 1
10%
25V 2
X5R
402
330K
PPBUS_FW_FWPWRSW_D
VOLTAGE=12.6V
R4261
Q1
100
Q2
4
1
NOSTUFF
LATEVG_FAULT_EVENT_PNP
R4263
LATEVG_RETRY_RC
5%
1/16W
MF-LF
402
NOSTUFF
10K
MINISMDC110H24
FWPWR_EN_L_DIV
R4265
2
PPBUS_FW_FWPWRSW_F
VOLTAGE=12.6V
0.1UF
5%
1/16W
MF-LF
2 402
DMB54D0UV
C4260 1
470K
Q4262
D4260
SM
1.1A-24V
8
7
6
5
3
2
1
CRITICAL
F4260
SOI-HF
A.0.0
OF
37
97
8
Page Notes

38 37 36 8
PP3V3_FW_FWPHY
- =PPVP_FW_PORT1
- =PP3V3_FW_LATEVG
R43821 R43801
10K
10K
1%
1/16W
MF-LF
402 2
- =GND_CHASSIS_FW_PORT1
- =GND_CHASSIS_FW_EMI_R
1%
1/16W
MF-LF
402 2
38 36
FireWire PHY Config Straps

(NONE)
NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.
Configures PHY for:

38 36
- 1-port Portable Power Class (0)
FWPHY_DS1
FWPHY_DS1
38 36
38 36
93 38 36
38 36
93 38 36
93 38 36
Termination
38 36
SOT-363
(SYM-VER2)
C4360
0.33UF
NC_FW0_TPBN
NC_FW0_TPBP
NC_FW2_TPBN
NC_FW2_TPBP
NC_FW0_TPBN
NC_FW0_TPBP
NC_FW2_TPBN
NC_FW2_TPBP
PPVP_FW_CPS MAKE_BASE=TRUE
VOLTAGE=12.6V
38 36
5%
1/16W
MF-LF
402 2
PPVP_FW_CPS
1%
1/16W
MF-LF
2 402
38 37
56.2
1%
1/16W
MF-LF
402 2
0.01uF
CPS_EN_L
FW_PORT1_TPB_P
FW_PORT1_TPB_P
36 38 93
FW_PORT1_TPB_N
MAKE_BASE=TRUE
PP3V3_FW_FWPHY
38 37 36 8
56.2
1%
1/16W
MF-LF
2 402
C4314
PPVP_FW_PORT1_F
VOLTAGE=33V
0.01UF
10%
2 50V
X7R
402
SOT-363
5
PORT 1
3
4
BILINGUAL
36 38 93
SOT-363
2
CRITICAL
J4310
1394B-M97
F-RT-TH
BSS8402DW
93 38 36
SOT-363
FW_PORT1_TPB_N
1
9
2
8
NC 7
6
3
5
4
(FW_PORT1_BREF)
(SYM-VER1)
93 38 36
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
R4362
10%
50V 2
X7R
402
Q4300
MAKE_BASE=TRUE
FW_PORT1_TPB_N
0.01uF
6
MAKE_BASE=TRUE
Note: Trace PPVP_FW_PORT1 must handle up to 5A
BAV99DW-X-G
36 38 93
36 38 93
2
SM
10%
50V 2
X7R
402
DP4310
C4310
93 38 36
BAV99DW-X-G
MAKE_BASE=TRUE
FW_PORT1_TPA_N
FERR-250-OHM
PPVP_FW
CRITICAL
CRITICAL
5%
1/16W
MF-LF
402 2
FW_PORT1_TPA_N
36 38
CRITICAL
PP2V4_FW_LATEVG
330K
93 38 36
36 38
DP4310
R43611
FW_PORT1_TPA_P
36 38 93
36 38 93
L4310
R43121
FW_PORT1_TPA_P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
38 37 8
C4311 1
56.2
36 38
36 38
CPS_EN_L_DIV
R4360
36 38 93
36 38
"Snapback" & "Late VG" Protection
470K
36 38
R43111
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
36 38
36 38 93
Cable Power
PPVP_FW
38 37 8
10%
2 6.3V
CERM-X5R
402
NC_FW0_TPBIAS MAKE_BASE=TRUE
NC_FW2_TPBIAS MAKE_BASE=TRUE
NC_FW0_TPAN MAKE_BASE=TRUE
NC_FW0_TPAP MAKE_BASE=TRUE
NC_FW2_TPAN MAKE_BASE=TRUE
NC_FW2_TPAP MAKE_BASE=TRUE
Q4300
TI PHYs require 1uF even though

FW spec calls out 0.33uF
NC_FW0_TPBIAS
NC_FW2_TPBIAS
NC_FW0_TPAN
NC_FW0_TPAP
NC_FW2_TPAN
NC_FW2_TPAP
BSS8402DW
38 36
Place close to FireWire PHY
36 38
10K
38 36
93 38 36
36 38
1%
1/16W
MF-LF
402 2
1394b implementation based on Apple

FireWire Design Guide (FWDG 0.6, 5/14/03)
93 38 36
36 38
R43811
- Port "1" Bilingual (1394B)
93 38 36
FWPHY_DS2
MAKE_BASE=TRUE
NOTE: FireWire TPA/TPB pairs are NOT

constrained on this page. It is
assumed that FireWire PHY page will
provide the appropriate constraints
to apply to entire TPA/TPB XNets.
FW_P1_TPBIAS
FWPHY_DS0
FWPHY_DS2
MAKE_BASE=TRUE

(NONE)
37 36
FWPHY_DS0
MAKE_BASE=TRUE
38 36
FW_PORT1_TPB_P
R43631
56.2
1%
1/16W
MF-LF
402 2
(GND_FW_PORT1_VG)
93 38 36
FW_PORT1_TPA_N
93 38 36
FW_PORT1_TPA_P
FW_PORT1_AREF
FW_PORT1_TPB_C
DP4311
SOT-363
2
10
11
12
13
220pF
5%
2 25V
CERM
402
1%
1/16W
MF-LF
402 2
0.01uF
10%
50V 2
X7R
402
0.1uF
DP4311
6
C4312 1
C4319 1
CRITICAL
10%
50V 2
X7R
603-1
BAV99DW-X-G
SOT-363
5
C4313 1
0.01uF
10%
50V 2
X7R
402
TPB<R>
OUTPUT
VP
NCSC/NC
VG
TPA- TPAVG
TPA<R>
TPA+
INPUT
TPA(R)
TPA+
CHASSIS
GND
R4319
1M
TPB(R)
TPB-
TPB+ TPB+
VP
CRITICAL
BAV99DW-X-G
1
1 C4364 R4364
4.99K
TPB-
5%
1/16W
MF-LF
2 402
AREF needs to be isolated from all

local grounds per 1394b spec
514S0605
When a bilingual device is connected to a

beta-only device, there is no DC path
between them (to avoid ground offset issue)
PLACEMENT_NOTE=Place C4319 close to connector pin 5.
BREF should be hard-connected to logic

ground for speed signaling and connection
Late-VG Protection Power

A
37 34 30 26 24 22 20 18 8 7
96 87 82 70 69 68 64 54 44
PP3V3_S5
R4390
1
332
PP2V4_FW_LATEVG
1%
1/16W
MF-LF
402
FireWire Ports
SYNC_MASTER=SENSOR

D4390
MMBZ5227BLT1H
PP2V4_FWLATEVG needs to be biased

to at least 2.1V for FW signal integrity
and should be biased to 2.4V for margin
R4390 should be 390 Ohms max for a 3.3V rail
37 38
VOLTAGE=2.4V
ESD and late-VG rail
CRITICAL
for snap-back diodes
(Common to all ports)
SOT23

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
38
97
ODD Power Control

CRITICAL
Q4590
TPCP8102
81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84 82
R4595
R45971
10%
2 10V
CERM
402
100K 2
C4596
0.01UF
1
ODD_PWR_SS
5%
1/16W
MF-LF
402
100K
Q4596
0.068UF
5%
1/16W
MF-LF
402 2
ODD_PWR_EN_LS5V_L
5%
1/16W
MF-LF
402 2
C4595
100K
PP3V3_S0
6 7
R45961
NOTE: 3.3V must be S0 if 5V is S3 or S5 to

ensure the drive is unpowered in S3/S5.
VOLTAGE=5V
PP5V_SW_ODD_R
23V1K-SM
PP5V_S0
70 67 66 63 51 49 44 39 8 7
85 83
D 6
XW4504
SM
10%
16V
CERM
402
SSM6N15FEAPE
2 G
D 3
SOT563
5 G
OUT
53 96
ISNS_ODD_N
OUT
53 96
XW4503
SM
XW4505
1
SM
S 1
SSM6N15FEAPE
21
ISNS_ODD_P
ODD_PWR_EN
Q4596
SOT563
S 4
ODD_PWR_EN_L
IN
53 7
PP5V_SW_ODD
VOLTAGE=5V
SATA ODD Port

FL4520
PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79

PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520
90-OHM-100MA
DLP11S
CRITICAL
SYM_VER-1
J4500
96
96
CRITICAL 54722-0164
F-ST-SM
81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84 82
PP3V3_S0
90 7
90 7
R45901
33K
5%
1/16W
MF-LF
402 2
10
11
12
13
14
15
16
OUT
IN
20 90
C4520
SATA_ODD_R2D_C_N
IN
20 90
1
SATA_ODD_R2D_UF_N
0.01UF
2
10% 16V CERM 402
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_C_N
SATA_ODD_D2R_C_P
FL4525
PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500

PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526
C4526 1
0.01UF
516S0616
42 7
SATA_ODD_R2D_C_P
2
10% 16V CERM 402
PLACEMENT_NOTE=Place FL4520 close to J4500
C4521
1
SATA_ODD_R2D_UF_P
0.01UF
C4525 1
SMC_ODD_DETECT
0.01UF
90-OHM-100MA
DLP11S
SYM_VER-1
2
96 7 SATA_ODD_D2R_UF_N
10% 16V CERM 402
2
96 7 SATA_ODD_D2R_UF_P
10% 16V CERM 402
CRITICAL
3
SATA_ODD_D2R_N
2
SATA_ODD_D2R_P
OUT
20 90
OUT
20 90
Indicates disc presence
B
1
68 29 28 24 16 12 11 8 7
70 69
PP1V8R1V5_S0_FET
20%
2 10V
CERM
402
PP1V5_S0_HDD_FLT
VOLTAGE=1.5V
0402
C4501
C4503
VOLTAGE=5V
7
1UF
10%
2 6.3V
CERM
402
C4502
0.1UF
L4502
FERR-220-OHM
0.1UF
20%
2 10V
CERM
402
CRITICAL
L4500
XW4500
SM
FERR-70-OHM-4A
1
PP5V_S0_HDD_FLT
0603
PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501
PP5V_S0_HDD_R
CRITICAL
FL4501
90-OHM-100MA
VOLTAGE=5V
PLACEMENT_NOTE=Place C4510 close to MCP79

PLACEMENT_NOTE=Place C4511 next to C4510
DLP11S
SYM_VER-1
90 7
90 7
SATA HDD Port

SATA_HDD_R2D_P
SATA_HDD_R2D_N
96
C4510 1
SATA_HDD_R2D_UF_P
0.01UF
2
96
C4511 1
SATA_HDD_R2D_UF_N
0.01UF
94 45 42 27
IN
SMBUS_SMC_MGMT_SCL
94 45 42 27
BI
SMBUS_SMC_MGMT_SDA
10
PP5V_S3_IR_R
1/16W
402
5%
MF-LF
22
19
20
17
18
15
16
0.01UF
13
14
11
12
C4516 1
10
R4532
PP5V_S3
64 55 53 51 43 41 40 31 9 8 7
79 70 65
21
C4532
10%
16V
X7R-CERM
402
90 7
SATA_HDD_D2R_C_N
SATA_HDD_D2R_C_P
OUT
F-ST-SM
516S0687
R4531
2
4.7
IN
20 90
2
SATA_HDD_R2D_C_N
10% 16V CERM 402
IN
20 90
XW4501
SM
XW4502
SM
C4531
ISNS_HDD_P
OUT
53 96
ISNS_HDD_N
OUT
53 96
FL4502
90-OHM-100MA
CRITICAL
2
96 SATA_HDD_D2R_UF_N
10% 16V CERM 402
SATA_HDD_D2R_N
2
1
2
SATA_HDD_D2R_P
96 SATA_HDD_D2R_UF_P
10% 16V CERM 402
0.01UF
PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501
PLACEMENT_NOTE=Place C4515 next to C4516
PLACEMENT_NOTE=Place C4516 close to J4501
SYS_LED_ANODE
OUT
SATA Connectors
20
90
SYNC_MASTER=PWRSQNC
OUT
20 90

43
402

5% 1/16W
MF-LF
0.001UF
J4501
10%
50V
CERM
402
SIZE
DRAWING NUMBER
D
APPLE INC.
REV.
051-7892
SCALE
SHT
NONE
7 8 39 44 49 51 63 66 67 70
83 85
DLP11S
SYM_VER-1
C4515 1
7 41
IR_RX_OUT
SYS_LED_ANODE_R
54722-0224
0.1UF
2
90 7
2
SATA_HDD_R2D_C_P
10% 16V CERM 402
PP5V_S0
A.0.0
OF
39
97
Port Power Switch
Left USB Port A
CRITICAL
CRITICAL
L4605
Q4690
64 55 53 51 43 41 39 31 9 8 7
79 70 65
70 69 43 42 21 7
PM_SLP_S4_L
20
R4690
20
8
3
5
4
USB_EXTA_OC_L
OUT
USB_EXTB_OC_L
OUT
5.1K
5%
1/16W
MF-LF
2 402
PP5V_S3_RTUSB_A_ILIM
VOLTAGE=5V
OC1*
OUT2 6
EN1
PP5V_S3_RTUSB_B_ILIM
20%
16V
CERM 2
402
J4600
10UF
20%
6.3V 2
X5R
603
0.47UF
10%
10V 2
X5R
402
CRITICAL
C4695 1
0.1UF
10UF
20%
2 10V
CERM
402
F-RT-TH-M97-4
5
6
L4600
90-OHM-100MA
DLP11S
SYM_VER-1
C4691
USB
CRITICAL
GND TPAD
CRITICAL
0.01uF
EN2
VOLTAGE=5V
0603
C4605 1
VOLTAGE=5V
OC2*
USB_PWR_EN
C4690 1
C4692
7
OUT1
MSOP
20%
6.3V 2
X5R
603
CRITICAL
C4696 C4617
10UF
100UF
20%
2 6.3V
POLY-TANT
CASE-B2-SM
20%
6.3V
X5R
603
USB2_EXTA_MUXED_N
C4616
100UF
96
20%
2 6.3V
POLY-TANT
CASE-B2-SM
96
USB2_EXTA_MUXED_P
96
USB2_LT1_N
96
USB2_LT1_P
1
2
3
4
2 5 3 4
6 VBUS
7
8
NC
IO
NC
IO
TPS2064DGN
2 IN
PP5V_S3
FERR-220-OHM-2.5A
1
2
PP5V_S3_RTUSB_A_F
1 GND
514-0606
D4600
RCLAMP0502N
SLP1210N6
CRITICAL
CRITICAL
We can add protection to 5V if we want, but leaving NC for now
L4615
FERR-220-OHM-2.5A
1
2
PP5V_S3_RTUSB_B_F
0603
C4615
Place L4600 and L4605 at connector pin
VOLTAGE=5V
0.01uF
20%
2 16V
CERM
402
CRITICAL
J4610
USB/SMC Debug Mux
USB
SMC_DEBUG_YES
69 64 62
42 26 22 21 8 7
61 50 46 45 44 43
PP3V42_G3H
F-RT-TH-M97-4
5
6
CRITICAL
L4610
90-OHM-100MA
SIGNAL_MODEL=USB_MUX
DLP11S
1
2
3
4
SYM_VER-1
R4650
0.1UF
44 43 42
IN
44 43 42
OUT
SMC_RX_L
SMC_TX_L
20%
10V
CERM 2
402
VCC
5 M+
4 M-
BI
USB_EXTB_N
91 20
BI
USB_EXTB_P
10K
C4650 1
91 20
Y+ 1
U4650
96
3
96
5%
1/16W
MF-LF
2 402
Y- 2
2 5 3 4
PI3USB102ZLE
91 20
BI
91 20
BI
7 D+
6 D-
USB_EXTA_P
USB_EXTA_N
6 VBUS
TQFN
CRITICAL
7
8
1 GND
SEL 10
OE*
USB_LT2_N
USB_LT2_P
NC
IO
NC
IO
SMC_DEBUG_YES
USB_DEBUGPRT_EN_L
IN
42
D4610
SEL=0 Choose SMC

SEL=1 Choose USB
GND
RCLAMP0502N
SLP1210N6
External USB Connectors
CRITICAL
SYNC_MASTER=M98_MLB
SMC_DEBUG_NO
1
5%
1/16W
MF-LF
402
R4651
Left USB Port B

SMC_DEBUG_NO
R4652
0

5%
1/16W
MF-LF
402
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
40
97
IR SUPPORT
D
PP5V_S3
64 55 53 51 43 40 39 31 9 8 7
79 70 65
C4801
0.1UF
14
10%
2 16V
X7R-CERM
402
VCC
U4800
CY7C63803-LQXC
91 20
BI
91 20
BI
QFN
12 P1.0/D+
P0.0
13 P1.1/DP0.1
15
IR_VREF_FILTER
P1.2/VREG
INT0/P0.2
16 P1.3/SSEL
INT1/P0.3
17 P1.4/SCLK
INT2/P0.4
1
18 P1.5/SMOSI
TIO0/P0.5
1UF
10%
19 P1.6/SMISO
TIO1/P0.6
2 10V
X5R
402-1
8
CRITICAL
OMIT
9
10
P/N 338S0633
20
21 NC
USB_IR_P
DIFFERENTIAL_PAIR=USB2_IR
USB_IR_N
DIFFERENTIAL_PAIR=USB2_IR
C4803
R4800
IR_RX_OUT_RC
100
IR_RX_OUT
IN
7 39
5%
1/16W
MF-LF
402
1
C4804
0.001UF
10%
2 50V
CERM
402
C
25
THRML
PAD
VSS
11
22
23
24
7
6
5
4
3
2
1
Front Flex Support
SYNC_MASTER=PWRSQNC

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
41
97
NOTE: Unused pins have "SMC_Pxx" names. Unused

pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
43 7
46 45 44 43 40 26 22 21 8 7
69 64 62 61 50
PP3V3_S5_AVREF_SMC
PP3V42_G3H
C4902 1
22UF
IN
21
OUT
PM_RSMRST_L
IMVP_VR_ON
PM_PWRBTN_L
43
OUT
NC_ESTARLDO_EN
21
OUT
63
OUT
43
46 43
NC
NC
NC
NC
TP_SMC_P24
NC
SMC_BMON_MUX_SEL
NC
91 84 44 19
BI
91 84 44 19
BI
91 84 44 19
BI
91 84 44 19
BI
91 84 44 19
IN
26
IN
91 26
44 19
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
SMC_LRESET_L
LPC_CLK33M_SMC
LPC_SERIRQ
IN
BI
NC
52
BI
OUT
77
OUT
51
OUT
44 43 42 40
OUT
44 43 42 40
94 78 53 48 45
IN
BI
(DEBUG_SW_1)
(DEBUG_SW_2)
TP_SMC_P41
SMBUS_SMC_MGMT_SDA(OC)
SMS_PWRDN
SMC_GFX_THROTTLE_L
SMC_SYS_KBDLED
NC
NC
SMC_TX_L
SMC_RX_L
SMBUS_SMC_0_S0_SCL(OC)
SMC_PA0
SMC_PA1
PM_SYSRST_L
USB_DEBUGPRT_EN_L
MEM_EVENT_L
SMC_PA5
43
SYS_ONEWIRE
PM_BATLOW_L
P20
P21
P22
P23
P24
P25
P26
P27
D4
A5
B4
A1
C2
B2
C1
C3
P40
P41
P42
P43
P44
P45
P46
P47
G2
F3
E4
P50
P51
P52
OUT
40
OUT
29 28 21
BI
61
BI
21
OUT
21
OUT
IN
43
IN
43
IN
77
IN
43
49
OUT
49
OUT
43
OUT
43
OUT
49
IN
49
IN
43
IN
43
IN
52
IN
52
IN
52
IN
47 43
IN
47 43
IN
47 43
IN
46 43
IN
46 43
IN
OMIT
L13
K12
K11
J12
K13
J10
J11
H12
P70
P71
P72
P73
P74
P75
P76
P77
N10
M11
L10
N11
N12
M13
N13
L12
SMC_CPU_ISENSE
SMC_CPU_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_CPU_FSB_ISENSE
P80
P81
P82
P83
P84
P85
P86
A7
B6
C7
D5
A6
B5
C6
SMC_WAKE_SCI_L
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_TX_L
SMC_RX_L
(OC) SMBUS_SMC_MGMT_SCL
P90
P91
P92
P93
P94
P95
P96
P97
J4
G3
H2
G1
H4
G4
F4
F1
SMC_ONOFF_L
SMC_BC_ACOK
SMC_BS_ALRT_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S4_L
PM_CLK32K_SUSCLK
(OC) SMBUS_SMC_0_S0_SDA
NC
NC
NC
NC
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
B8
C9
B9
A10
C10
B10
C11
A11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
SMC_IG_THROTTLE_L
21
(See below)
SMC_EXCARD_CP
SMC_EXCARD_OC_L
SMC_GFX_OVERTEMP_L
NC
SMC_FAN_0_CTL
SMC_FAN_1_CTL
NC_SMC_FAN_2_CTL
NC_SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
NC_SMC_FAN_2_TACH
NC_SMC_FAN_3_TACH
G11
G13
F12
H13
G10
G12
H11
J13
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
SMC_GPU_1V8_ISENSE
SMC_MCP_CORE_ISENSE
SMC_MCP_DDR_ISENSE
SMC_MCP_VSENSE
SMC_CPU_HI_ISENSE
M10
N9
K10
L8
M9
N8
K9
L7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
H8S2117
LGA-HF
(2 OF 3)
OMIT
PE0
PE1
PE2
PE3
PE4
PF0
K1
J3
K2
J1
K4
K5
PF1
PF2
PF3
PF4
PF5
PF6
PF7
N5
M6
L5
M5
N4
L4
M4
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
M8
N7
K8
K7
K6
N6
M7
L6
PH0
PH1
PH2
PH3
PH4
PH5
E2
F2
J2
A4
B3
C4
0.1UF
20%
2 10V
CERM
402
C4906
0.1UF
20%
2 10V
CERM
402
PLACEMENT_NOTE=Place C4907 close to U4900 pin F1
SMC_PM_G2_EN
P60
P61
P62
P63
P64
P65
P66
P67
OUT
7 64 69
SMC_VCL
R4999
1
SMC_ADAPTER_EN
OUT
SMC_PROCHOT_3_3_L
SMC_BIL_BUTTON_L
43
IN
7 43 61
IN
46
IN
46
IN
47
IN
46
IN
46
IN
46
IN
46
IN
43 47
OUT
5%
1/16W
MF-LF
402
21 34 37 43
IN
4.7
PP3V3_S5_SMC_AVCC
VOLTAGE=3.3V
C4920 1
C4907 1
0.47UF
0.1UF
20%
10V
CERM 2
402
VCC
AVCC
VCL AVREF
U4900
H8S2117
PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15

PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15
10%
6.3V
CERM-X5R 2
402
R49091
NC
E5
MD1
MD2
D1
H1
NMI
E3
ETRST
H3
AVSS
L9
10K
NC
5%
1/16W
MF-LF
402 2
LGA-HF
(3 OF 3)
OMIT
44 43
IN
43
43
SMC_RESET_L
D3
RES*
SMC_XTAL
SMC_EXTAL
A3
A2
XTAL
EXTAL
R4901
10K
5%
1/16W
MF-LF
2 402
SMC_MD1
IN
44
SMC_NMI
IN
44
IN
44
SMC_KBC_MDE
21
NC
U4900
NC
39 7
LGA-HF
(1 OF 3)
N3
N1
M3
M2
N2
L1
K3
L2
43
26
H8S2117
P30
P31
P32
P33
P34
P35
P36
P37
43
D13
E11
D12
F11
E13
E12
F13
E10
A9
D9
C8
B7
A8
D8
D7
D6
43
94 45 39 27
P10
P11
P12
P13
P14
P15
P16
P17
C4905
E1
IN
69
B12
A13
A12
B13
D11
C13
C12
D10
0.1UF
20%
2 10V
CERM
402
L11
69 26
U4900
NC_EXCARD_PWR_EN
TP_SMC_RSTGATE_L
ALL_SYS_PWRGD
RSMRST_PWRGD
C4904
B1
M1
H10
OUT
0.1UF
20%
2 10V
CERM
402
M12
OUT
43
C4903
SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
OUT
19 44
IN
19 44
OUT
40 42 43 44
IN
40 42 43 44
BI
R4902
10K
5%
1/16W
MF-LF
2 402
27 39 45 94
IN
43 50
IN
43 61 62
IN
43
IN
7 21 34 37 69 82 84
IN
7 21 40 42 43 69 70
IN
7 21 40 42 43 69 70
IN
26 91
BI
SMC_TRST_L
NO STUFF
1
VSS
D2
L3
F10
B11
C5
43
20%
6.3V 2
CERM
805
D
1
XW4900
SM
2
NOTE: P94 and P95 are shorted, P95 could be spare.
R4998
10K
5%
1/16W
MF-LF
2 402
R4903
0
5%
1/16W
MF-LF
2 402
GND_SMC_AVSS
43 46 47
45 48 53 78 94
IN
43
IN
43 44
IN
43 44
OUT
43 44
IN
43 44
NC
SMC_SYS_LED
SMC_LID
NC
NC
OUT
IN
SMC_MCP_SAFE_MODE
43
43 50 61
OUT
IN
43
NC
NC
NC
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
SMS_INT_L
SMBUS_SMC_BSA_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_B_S0_SCL
SMC_PROCHOT
SMC_THRMTRIP
SMC_PH2
NC_ALS_GAIN
BI
7 45 61 62 94
BI
7 45 61 62 94
BI
7 31 45 51 94
BI
7 31 45 51 94
BI
45 48 94
BI
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
45 48 94
OUT
43
OUT
43
OUT
43
43
NC
NC
SMC
SYNC_MASTER=T18_MLB

SMC_PB3:
SMC_IG_THROTTLE_L for MG systems.

Otherwise, TP/NC okay (was ISENSE_CAL_EN)

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
42
97
43 42
NC_SMC_FAN_2_CTL
43 42
NC_SMC_FAN_2_TACH
43 42
NC_SMC_FAN_3_CTL
43 42
NC_SMC_FAN_3_TACH
NC_SMC_FAN_2_CTL
NC_SMC_FAN_2_TACH
45 44 43 42 40 26 22 21 8 7
69 64 62 61 50 46
PP3V42_G3H
NC_SMC_FAN_3_CTL
NC_SMC_FAN_3_TACH
MAKE_BASE=TRUE
C5000 1
U5000
NC
OUT
IN
CD
NC
0.01UF
5%
1/10W
MF-LF
2 603
43 42
SMC_RESET_L
OUT
1
2
10%
16V
CERM 2
402
NC_ESTARLDO_EN
42 43
NO_TEST=TRUE
SMC_BC_ACOK
SMC_BC_ACOK
SMC_MCP_VSENSE
MAKE_BASE=TRUE
D 3
46 43 42
SMC_MCP_VSENSE
50 43 42
46 43 42
47 43 42
SOT-563
SMC_CPU_HI_ISENSE
SMC_CPU_HI_ISENSE
88 63 14 10
42 43 46
SMC_MCP_CORE_ISENSE
SMC_MCP_CORE_ISENSE
BI
CPU_PROCHOT_L
U5001
47 43 42
SMC_MCP_DDR_ISENSE
47 43 42
SMC_CPU_FSB_ISENSE
47 43 42
SMC_GPU_1V8_ISENSE
6 D
SMC_MCP_DDR_ISENSE
SMC_CPU_FSB_ISENSE
43 42
SMC_GPU_1V8_ISENSE
43 42
1 S
G 2
SMC_PROCHOT
TP_SMC_P24
TP_SMC_P24
42 43
88 14 10
MAKE_BASE=TRUE
46 43 42
SMC_BMON_MUX_SEL
SMC_BMON_MUX_SEL
OUT
TP_SMC_P41
PM_THRMTRIP_L
3 D
TP_SMC_P41
42 43
43 42 21
43 42
NC_ALS_GAIN
SOT563
NC_ALS_GAIN
42 43
MAKE_BASE=TRUE
SMC_IG_THROTTLE_L
SMC_IG_THROTTLE_L
TP_SMC_RSTGATE_L
MAKE_BASE=TRUE
4 S
21 42 43
MAKE_BASE=TRUE
TP_SMC_RSTGATE_L
Q5059
SSM6N15FEAPE
MAKE_BASE=TRUE
43 42
42
IN
42 43 46
MAKE_BASE=TRUE
43 42
S
1
42 43
NO_TEST=TRUE
MAKE_BASE=TRUE
SOT-563
SOT563
42 43 47
NC_EXCARD_PWR_EN
NC_EXCARD_PWR_EN
DMB53D0UV
4
Q5059
MAKE_BASE=TRUE
Q5060
42 43 47
MAKE_BASE=TRUE
02
3.3K 2 CPU_PROCHOT_L_R
SSM6N15FEAPE
42 43 47
MAKE_BASE=TRUE
SN74LVC1G02
2 G
5%
1/16W
MF-LF
402
42 43 47
MAKE_BASE=TRUE
S 4
SOT553-5
4
SMC_TPAD_RST
SMC_ONOFF_L
D
DMB53D0UV
R5062
TO CPU
42 43 46
MAKE_BASE=TRUE
SMC_TPAD_RST_L
42
Q5060
42 43 61 62
MAKE_BASE=TRUE
SSM6N15FEAPE
5 G
OUT
CPU_PROCHOT_BUF
6
62 61 43 42
PP3V42_G3H
TO SMC
SMC_PROCHOT_3_3_L
NC_ESTARLDO_EN
MAKE_BASE=TRUE
42 44
SOT563
50
5%
1/16W
MF-LF
2 402
Q5032
45 44 43 42 40 26 22 21 8 7
69 64 62 61 50 46
10K
5%
1/16W
MF-LF
2 402
GND
3
CRITICAL
C5001 1
SILK_PART=SMC_RST
5
4
R5060
100K
5%
1/16W
MF-LF
2 402
SOT23-5-HF
R5061
1K
NCP303LSN
SMC_MANUAL_RST_L
OMIT
R5001
R5000
20%
10V
CERM 2
402
42 43
NO_TEST=TRUE
0.1uF
82 81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84
42 43
NO_TEST=TRUE
MAKE_BASE=TRUE
SMC FSB to 3.3V Level Shifting

PP3V3_S0
42 43
NO_TEST=TRUE
MAKE_BASE=TRUE
42 43
NO_TEST=TRUE
MAKE_BASE=TRUE
SMC Reset "Button" / Brownout Detect
G 5
SMC_THRMTRIP
42 43
IN
42
R5095
42
SMC_EXCARD_OC_L
OUT
EXCARD_OC_L
45 44 43 42 40 26 22 21 8 7
69 64 62 61 50 46
IN
PP3V42_G3H
20
5%
1/16W
MF-LF
402
42
42
SMC_PA0
SMC_PA1
R5091
R5092
100K
100K
1
1
2
2
SMC_ONOFF_L
SMC_LID
SMC_PH2
SMC_TX_L
SMC_RX_L
R5070
R5071
R5072
R5073
R5074
10K
100K
10K
10K
100K
1
1
1
1
1
2
2
2
2
2
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_BIL_BUTTON_L
SMC_BC_ACOK
SMS_INT_L
R5077
R5078
R5079
R5080
R5081
R5087
R5093
10K
10K
10K
10K
10K
470K
10K
1
1
1
1
1
1
1
2
2
2
2
2
2
2
5%
5%
1/16W MF-LF 402

1/16W MF-LF 402
5%
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
402
5%
5%
5%
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
402
402
402
SMC AVREF Supply

43 42
CRITICAL
SMS_INT_L
SMS_INT_L
MAKE_BASE=TRUE
42 43
50 43 42
VR5020
45 44 43 42 40 26 22 21 8 7
69 64 62 61 50 46
61 50 42
REF3333
PP3V42_G3H
PP3V3_S5_AVREF_SMC
SOT23-3
IN
OUT
VOLTAGE=3.3V
C5020 C5025
C5026
15pF
10%
16V
2 CERM
402
42
R5010
20%
6.3V 2
X5R
603
VOLTAGE=0V
TABLE_ALT_HEAD
BOM OPTION
SMC_XTAL
GND_SMC_AVSS
REF DES
COMMENTS:
ALL
Intersil ISL60002-33
SMC_XTAL_R
Debug Power "Button"
5%
50V
CERM
402
44 42
44 42
44 42
5%
1/16W
MF-LF
402
42 46 47
SMC_ONOFF_L
OMIT
61 42 7
62 61 43 42
C5011
5X3.2-SM
15pF
2
42
44 42
42 43 50
R5015
Y5010 1
20.00MHZ
OUT
CRITICAL
TABLE_ALT_ITEM
353S1381 353S1912
44 42 40
C5010
10uF
10%
2 6.3V
CERM-X5R
402
ALTERNATE FOR
PART NUMBER
SMC Crystal Circuit
0.01UF
0.47UF
PART NUMBER
42
44 42 40
GND
7 42
SMC_EXTAL
SILK_PART=PWR_BTN
43 42
5%
1/10W
MF-LF
2 603
Place R5015,R5001 on bottom side
5%
50V
CERM
402
System (Sleep) LED Circuit
42
SMC_BS_ALRT_L
SMC_ADAPTER_EN
SMC_CASE_OPEN
R5076
R5085
R5086
42
SMC_EXCARD_CP
PM_SLP_S4_L
PM_SLP_S4_L
42
42 37 34 21
64 55 53 51 41 40 39 31 9 8 7
79 70 65
PP5V_S3
R50311
100K
10K
10K
1
1
1
2
2
2
R5088
10K
R5090
100K
R5030
523
20
1%
1/16W
MF-LF
402 2
70 69 43 42 40 21 7
1%
1/16W
MF-LF
2 402
70 69 43 42 40 21 7
SYS_LED_ILIM
82 81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84
SYS_LED_L_VDIV
42
R5089
SMC_PA5
10K
5%
5%
5%
1/16W MF-LF 402

1/16W MF-LF 402
1/16W MF-LF 402
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
PP3V3_S0
2
5%
1/16W MF-LF 402
R50321
1.47K
1%
1/16W
MF-LF
402 2
Q5030
SMC Support
DMB54D0UV
SOT-563
SYNC_MASTER=DDR
SYS_LED_L
Q2
Q1
S

42
IN
SMC_SYS_LED
SYS_LED_ANODE
SIZE
OUT
39
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
43
97
LPC+SPI Connector
CRITICAL
LPCPLUS
J5100
55909-0374
45 44 43 42 40 26 22 21 8 7
69 64 62 61 50 46
83 70 67 66 63 51 49 39 8 7
85
91 84 42 19
BI
44
IN
44
OUT
IN
42 19
OUT
43 42
OUT
26
IN
43 42
45 44 43 42 40 26 22 21 8 7
69 64 62 61 50 46
PP3V42_G3H
1
91 44 21
IN
OUT
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
33
34
LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO
IN
26 91
BI
19 42 84 91
BI
19 42 84 91
OUT
21 44
IN
44
IN
44
BI
19 42
IN
19 42
OUT
42 43
OUT
42 43
OUT
42 43
OUT
42
OUT
40 42 43
OUT
18
516S0573
C5114
20%
2 10V
CERM
402
LPCPLUS
5%
1/16W
MF-LF
402 2
SPI_CLK_R
42
0.1UF
10K
IN
IN
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
DEBUG_RESET_L
SMC_TDO
SMC_TRST_L
SMC_MD1
SMC_TX_L
M-ST-SM
31
32
LPCPLUS
PP3V3_S5
R51901
91 44 21
OUT
42
IN
Alternate SPI ROM Support
LPC_AD<0>
LPC_AD<1>
BI
91 84 42 19
91 84 42 19
37 34 30 26 24 22 20 18 8 7
96 87 82 70 69 68 64 54 44 38
PP3V42_G3H
PP5V_S0
VCC
1 Y+
2 Y-
SPI_MOSI_R
U5110
M+ 5
M- 4
SPI_ALT_CLK
SPI_ALT_MOSI
OUT
44
OUT
44
SPI_CLK_MUX
SPI_MOSI_MUX
OUT
44 54
OUT
44 54
PI3USB102ZLE
TQFN
R51911
10K
CRITICAL
5%
1/16W
MF-LF
402 2
10 SEL
D+ 7
D- 6
OE* 8
3
GND
SEL HIGH OUTPUTS TO D (ON BOARD ROM)

SEL LOW OUTPUTS TO M (FRANKCARD ROM)
PP3V42_G3H
69 64 62 61
40 26 22 21 8 7
50 46 45 44 43 42
LPCPLUS
1
C5124
0.1UF
20%
2 10V
CERM
402
LPCPLUS
VCC
R51401
100K
91 44 21
5%
1/16W
MF-LF
402 2
91 21
OUT
IN
1 Y+
2 Y-
SPI_MISO
SPI_CS0_R_L
U5120
SPI_ALT_MISO
M+ 5
M- 4
IN
44
Pull-up on debug card

SPI_ALT_CS_L OUT 44
PI3USB102ZLE
TQFN
D+ 7
D- 6
SPI_MISO_MUX
IN
44 54
CRITICAL
44 21
SPIROM_USE_MLB
BI
44
21
SPIROM_USE_MLB
10 SEL
MAKE_BASE=TRUE
SPI_MLB_CS_L
OE* 8
OUT
54
GND
R5144
PP3V3_S5
20K
LPCPLUS_NOT
R5146
1
7 8 18 20 22 24 26 30 34 37 38
44 54 64 68 69 70 82 87 96
5%
1/16W
MF-LF
402 2
2
5%
PLACEMENT_NOTE=PLACE NEXT TO U1400
1/16W
MF-LF
402
SPI MUX BYPASS

LPCPLUS_NOT
R5156
54 44
OUT
SPI_CLK_MUX
5%
1/16W
MF-LF
402
54 44
OUT
SPI_MOSI_MUX
R5158
IN
SPI_MISO_MUX
IN
21 44 91
SPI_MOSI_R
IN
21 44 91
OUT
21 44 91
R5157
LPCPLUS_NOT
54 44
SPI_CLK_R
LPCPLUS_NOT
0
5%
1/16W
MF-LF
402
SPI_MISO
LPC+SPI Debug Connector
5%
1/16W
MF-LF
402
SYNC_MASTER=CHANGZHANG

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
44
97
7
MCP79 SMBus "0" Connections
SMC "0" SMBus Connections
SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state
81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84 82
PP3V3_S0
R52001
MCP79
1.6K
5%
1/16W
MF-LF
402 2
U2300
(MASTER)
29 28 21 13
91 45
29 28 21 13
91 45
81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84 82
PP3V3_S0
70 52 50 45 32 31 27 21 8 7
R5201
1.6K
5%
1/16W
MF-LF
2 402
SMBUS_MCP_0_CLK
SO-DIMM "A"
SMC
J3100
U4900
(Write: 0xA0 Read: 0xA1)
(MASTER)
SMBUS_MCP_0_CLK
MAKE_BASE=TRUE
SMBUS_MCP_0_DATA
SMBUS_MCP_0_DATA
MAKE_BASE=TRUE
13 21 28 29
45 91
53 48 45 42
94 78
13 21 28 29
45 91
53 48 45 42
94 78
R52501
1.6K
SMBUS_SMC_0_S0_SCL
94
78
53
48 45
42
5%
1/16W
MF-LF
402 2
R5251
GPU Temp (Ext)
SMC
EMC1413: U5550
U4900
(Write: 0x98 Read: 0x99)
(MASTER)
1.6K
5%
1/16W
MF-LF
2 402
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUE
94 78 53
48 45
42
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
SO-DIMM "B"
SMBUS_MCP_0_DATA
42 45 48
53 78 94
45 42 31 7
94 51
42 45 48
53 78 94
45 42 31 7
94 51
R52701
R5271
2.2K
SMBUS_SMC_A_S3_SCL
TRACKPAD
2.2K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
J5800
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SCL
94
7 31
42 45 51
SMBUS_SMC_A_S3_SDA
94
7 31
42 45 51
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
GT216: U8000
J3401
(Write: 0x9E Read: 0x9F)
SMBUS_SMC_0_S0_SCL
13 21 28 29
45 91
SMBUS_SMC_A_S3_SCL
42 45 48
53 78 94
SMBUS_SMC_0_S0_SDA
13 21 28 29
45 91
ALS
GPU Temp (Int)
J3200
(Write: 0xA2 Read: 0xA3)
SMBUS_MCP_0_CLK
PP3V3_S3
7 31 42 45
51 94
SMBUS_SMC_A_S3_SDA
42 45 48
53 78 94
7 31 42 45
51 94
Sensor ADCs
U5930
SMBUS_SMC_0_S0_SCL
78 94
42 45
48 53
SMBUS_SMC_0_S0_SDA
78 94
42 45
48 53
SMC "Battery A" SMBus Connections

46 44 43 42 40 26 22 21 8 7
69 64 62 61 50
PP3V42_G3H
2.61K
1%
1/16W
MF-LF
402 2
U4900
(MASTER)
MCP79 SMBus "1" Connections

81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84 82
61 45 42 7
94 62
PP3V3_S0
61 45 42 7
94 62
MCP79
U2300
(MASTER?)
85 60 45 21
91
85 60 45 21
91
R5230
2.0K
5%
1/16W
MF-LF
402 2
SMBUS_MCP_1_CLK
R5231
2.0K
5%
1/16W
MF-LF
2 402
SMBUS_SMC_BSA_SCL
R5281
Battery
2.61K
1%
1/16W
MF-LF
2 402
R52601
SMC
(See Table)
(MASTER)
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
7 42 45
61 62 94
R5261
94 48 45 42
SMBUS_SMC_B_S0_SCL
94
48 45
42
94 48 45 42
SMBUS_SMC_B_S0_SDA
94
48 45
42
CPU Temp
3.3K
5%
1/16W
MF-LF
402 2
U4900
SMBUS_SMC_BSA_SCL
3.3K
J6955
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SDA
PP3V3_S0
5%
1/16W
MF-LF
2 402
EMC1413: U5570
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SCL
42 45
48 94
MAKE_BASE=TRUE
7 42 45
61 62 94
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_B_S0_SDA
42 45
48 94
MAKE_BASE=TRUE
Mikey
Battery Charger
U6860
(WRITE: 0X72 READ: 0X73)
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
MAKE_BASE=TRUE
MCP TEMP
ISL6258A - U7000
EMC1413: U5500
Battery
MAKE_BASE=TRUE
SMBUS_MCP_1_DATA
81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84 82
R52801
SMC
SMC "B" SMBus Connections

(WRITE: 0XD8 READ: 0XD9)
21 45 60
85 91
Battery Manager - (Write: 0x16 Read: 0x17)
SMBUS_SMC_BSA_SCL
Battery LED Driver - (Write: 0x36 Read: 0x37)
21 45 60
85 91
SMBUS_SMC_BSA_SDA
Battery Temp - (Write: 0x90 Read: 0x91)
7 42 45 61
62 94
SMBUS_SMC_B_S0_SCL
7 42 45 61
62 94
SMBUS_SMC_B_S0_SDA
42 45
48 94
42 45
48 94
LED BACKLIGHT
U9701
SMC "Management" SMBus Connections
(WRITE: 0x58 READ: 0x59)
The bus formerly known as "Battery B"
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
21 45 60 85
91
70 52 50 45 32 31 27 21 8 7
PP3V3_S3
21 45 60 85
91
R52901
SMC
1.6K
5%
1/16W
MF-LF
402 2
U4900
(MASTER)
45 42 39 27
94
45 42 39 27
94
SMBUS_SMC_MGMT_SCL
94
45
42 39
27
R5291
Vref DACs
1.6K
5%
1/16W
MF-LF
2 402
U2900
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SCL
94
27 39
42 45
SMBUS_SMC_MGMT_SDA
94
27 39
42 45
MAKE_BASE=TRUE
94 45
42 39
27
SMBUS_SMC_MGMT_SDA
SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
Margin Control
U2901
SMBUS_SMC_MGMT_SCL
94
27 39
42 45
SMBUS_SMC_MGMT_SDA
94
27 39
42 45
K19 SMBUS CONNECTIONS
HDD Margin Control
J4501
SYNC_MASTER=DDR
(Write: 0xXX Read: 0xXX)
SMBUS_SMC_MGMT_SCL
94
27 39
42 45
SMBUS_SMC_MGMT_SDA
94
27 39
42 45

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
45
97
7
CPU Voltage Sense / Filter
63 12 11 8 7
XW5309
SM
PPVCORE_S0_CPU
4.53K2
Q5315
SMC_CPU_VSENSE
1%
1/16W
MF-LF
402
Place short near U1000 center
OUT
FDG6332CG
42
C5309
SC70-6
67 66 65 64 62 61 46 37 8 7
86 83 79
0.22UF
P-CHN
PPBUS_G3H
4
20%
2 6.3V
X5R
402
R5315
100K
42 43 46 47
PPBUS_G3H_VSENSE
VOLTAGE=18.5V
GND_SMC_AVSS
R53851
27.4K
5%
1/16W
MF-LF
402 2
Place RC close to SMC
GPU Voltage Sense / Filter
1%
1/16W
MF-LF
402 2
XW5359
SM
PPVCORE_GPU
R5359
4.53K2
GPUVSENSE_IN
SMC_GPU_VSENSE
1%
1/16W
MF-LF
402
Place short near U8000 center
OUT
42
SMC_PBUS_VSENSE
R53161
R53861
5%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
100K
C5359
0.22UF
20%
2 6.3V
X5R
402
5.49K
OUT
42
C5385
0.22UF
20%
2 6.3V
X5R
402
GND_SMC_AVSS
PBUSVSENS_EN_L
GND_SMC_AVSS
Rthevanin = 4573 ohms
PBUSVSENS_EN_DIV
79 72 8
PBUS Voltage Sense & Filter
R5309
CPUVSENSE_IN
42 43 46 47

42 43 46 47
6
PM_SLP_S3_L_R
70 69
PPVCORE_S0_MCP_REG XW5399
SM
66 24 22 8 7
SMC_MCP_VSENSE
1%
1/16W
MF-LF
402
Q5315
FDG6332CG
SC70-6
4.53K2
MCPVSENSE_IN
2 G
Enables PBUS VSense divider when high.
R5399
PLACEMENT_NOTE=Place near U1400 center
N-CHN
MCP Voltage Sense / Filter
OUT
42 43
C5399
0.22UF
20%
6.3V
2 X5R
402
GND_SMC_AVSS
42 43 46 47
C
BMON Current Sense - Entire circuit must be near SMC (U4900)
45 44 43 42 40 26 22 21 8 7
69 64 62 61 50 46
PP3V42_G3H
BMON_ENG
BMON_ENG
1
C5318
1 B1
BMON_INA_OUT
0.1uF
BMON_ENG
OUT
96 62
IN
CHGR_CSO_R_P
5 IN-
CHGR_CSO_R_N
0.1uF
2 GND
4 IN+
SMC_BMON_MUX_SEL
OUT
62
DCIN Current Sense Filter
R5391
4
B0
BMON_AMUX_OUT
BMON_ENG
VER 1
1%
1/16W
MF-LF
402
R5371
100K
R5330
GND
SMC_BATT_ISENSEOUT
1
R5380
C5390
0.22UF
62
IN
4.53K2
SMC_DCIN_ISENSE
CHGR_AMON
1%
1/16W
MF-LF
402
GND_SMC_AVSS 42
5%
1/16W
MF-LF
402
Monitors battery discharge
42
20%
2 6.3V
X5R
402
5%
1/16W
MF-LF
2 402
4.53K2
1
BMON_PROD
42 43
VCC 5
CHGR_BMON
IN
REF 1
LOAD SIDE:
IN
INA213
SC70
SEL 6
V+
U5303
96 62
SC70
C5369
20%
10V
2 CERM
402
NC7SB3157P6XG
20%
2 10V
CERM
402
REGULATOR SIDE:
U5313
BMON_ENG
OUT
42
C5380
0.22UF
20%
2 6.3V
X5R
402
43 46 47
GND_SMC_AVSS
current from battery to PBUS
B
42 43 46 47
INA213 has gain of 50V/V
CPU VCore High Side Current Sensor

42 40 26 22 21 8 7
69 64 62 61 50 46 45 44 43
PP3V42_G3H
1
C5388
CPU VCore Load Side Current Sense / Filter
0.1UF
20%
2 10V
CERM
402
63 8
OUT
PPBUS_CPU_IMVP_ISNS
R5331
V+
63
U5388
CRITICAL
R5388
1 3
96
ISNS_CPU_N
0.001
1%
0.5W
MF
1206 2 4
96
ISNS_CPU_P
5 IN-
INA210
SC70
4 IN+
CPUVCORE_HISIDE_IOUT
4.53K2
1%
1/16W
MF-LF
402
REF 1
PPBUS_G3H
OUT
42 43
C5335
0.22UF
GND_SMC_AVSS
SMC_CPU_ISENSE
1
R5332
17.4K
1%
1/16W
MF-LF
402 2
20%
2 6.3V
X5R
402
IN
SMC_CPU_HI_ISENSE
GND
86 83
62 61 46 37 8 7
79 67 66 65 64
1%
1/16W
MF-LF
402
R5335
OUT 6
IN
IMVP6_IMON16.19K2
OUT
42
C5330
0.22UF
Current & Voltage Sensing
20%
2 6.3V
X5R
402
GND_SMC_AVSS
SYNC_MASTER=SENSOR
42 43 46 47

42 43 46 47

Consider INA211 (GAIN 500 version) since I=4.93 Amps across R5388
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
46
97
MCP VCore Current Sense
GPU VCore Current Sense
MCP VCore Current Sense Filter

R5470
66
4.53K2
MCPCORES0_IMON
IN
SMC_MCP_CORE_ISENSE
1%
1/16W
MF-LF
402
NC
OUT
42 43
R5493
C5470
79
0.22UF
IN
96
GPUISENS_P
1%
1/16W
MF-LF
402
20%
2 6.3V
X5R
402
GND_SMC_AVSS
10K
OPA2330
R5475
8 DFN
V+
R5491
42 43 46 47
GPU VCore Current Sense Filter
U5410
GFXIMVP6_IMON12.87K2
4.53K2
GPUVCORE_IOUT
1%
1/16W
MF-LF
402
THRM
9
96
0.22UF
NC
NC
42
OUT
C5475
20%
2 6.3V
X5R
402
GPUISENS_N
1%
1/16W
MF-LF
402
SMC_GPU_ISENSE
V-
GND_SMC_AVSS
R5498
42 43 46 47
4.02K2
1%
1/16W
MF-LF
402
1.4X GAIN FOR SENSING CURRENT UP TO 25 AMPS
C5498
MCP MEM VDD Current Sense
470PF
1
82 81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84
PP3V3_S0
C5440
0.1UF
70
IN
70
IN
20%
2 10V
CERM
402
P1V5_S0_KELVIN
R5441
C5441
0.1UF
5%
1/16W
MF-LF
2 402
4.53K2
1%
1/16W
MF-LF
402
THRM
42 43
OUT
C5490
0.22UF
20%
2 6.3V
X5R
402
10%
16V
X5R
402
P1V5_S0_SENSE_E
SMC_MCP_DDR_ISENSE
V-
dual package opamp U5410
R5440
8 DFN
V+
GPU VCore Current Sense and GPU 1.8V Current Sense share
OPA2330
3
MCP MEM VDD Current Sense Filter
CRITICAL
U5440
P1V5_S0_SENSE
1
10%
50V
CERM
402
Q5441
GND_SMC_AVSS
2SA2154MFV-YAE
R5442
SOD
1
P1V5_S0_SENSE_B 1 0 2
5%
1/16W
MF-LF
402
42 43 46 47
GPU 1.8V Current Sense
P1V5_S0_SENSE_AMP
P1V5_S0_SENSE_C
82 81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84
R5443
PP3V3_S0
1
118
20%
2 10V
CERM
402
83 8
IN
R5413
R5415
1 3
96
P1V8GPU_P
3.65K2
1
0.002
PP1V8_S0GPU_ISNS
96
P1V8GPU_N
3.65K2
V+
1%
1/16W
MF-LF
402
4
9
P1V8GPUISNS_R_N
10%
50V
CERM 2
402
R5412
1M
1%
1/16W
MF-LF
2 402
1M
1%
1/16W
MF-LF
402
96
CPUVTTISNS_R_P
C5411
470PF
2
96 67
CPUVTT_ISNS_N
3.65K2
V+
SIGNAL_MODEL=EMPTY
C5472
470PF
10%
50V
CERM 2
402
R5437
1M
1%
1/16W
MF-LF
2 402
OUT
42 43
C5435
0.22UF
GND_SMC_AVSS
SIGNAL_MODEL=EMPTY
1M
SMC_CPU_FSB_ISENSE
20%
2 6.3V
X5R
402
NC
R5432
1
4.53K2
1%
1/16W
MF-LF
402
CPUVTTISNS_R_N
NC
SIGNAL_MODEL=EMPTY
CPU1V05_S0_IOUT
THRM
96
V-
1%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
R5495
8 DFN
R5436
Current Sensing

SIGNAL_MODEL=EMPTY
C5432
470PF
1
42 43 46 47
1%
1/16W
MF-LF
402
10%
50V
CERM
402
SIZE
DRAWING NUMBER
Gain: 274x
APPLE INC.
REV.
051-7892
SCALE
SHT
NONE
42 43 46 47
U5440
OPA2330
1%
1/16W
MF-LF
402
0.22UF
1.05V CPU Current Sense Filter
NC
3.65K2
42 43
Gain: 274x
R5431
1
OUT
C5465
SIGNAL_MODEL=EMPTY
10%
50V
CERM
402
CPUVTT_ISNS_P
GND_SMC_AVSS
R5411
96 67
SMC_GPU_1V8_ISENSE
20%
2 6.3V
X5R
402
SIGNAL_MODEL=EMPTY
470PF
CPU FSB 1.05V Current Sense
4.53K2
1
P1V8_S0GPU_IOUT
V-
1%
1/16W
MF-LF
402
C5412 1
dual package opamp U5440
THRM
96
R5465
8 DFN
SIGNAL_MODEL=EMPTY
MCP MEM VDD Current Sense and CPU FSB 1.05V Current Sense share
P1V8GPUISNS_R_P
R5414
96
OUT
GPU 1.8V Current Sense Filter

OPA2330
1%
1/16W
MF-LF
402
1%
1/4W
MF
1206 2 4
75 74 73 72 9 8
CRITICAL
U5410
PP1V8_S0GPU_ISNS_R
CRITICAL
C5410
0.1UF
1%
1/16W
MF-LF
2 402
A.0.0
OF
47
97
CPU Proximity/CPU Die/Right Fin Stack

R5570
82 81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84
PP3V3_S0
96 10
47
BI
PP3V3_S0_CPUTHMSNS_R
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
DFN
C5580 1
2 DP1
3 DN1
10%
50V
CERM 2
402
BI
96
CPU_THERMD_N
R5572
10K
5%
1/16W
MF-LF
2 402
CPUTHMSNS_THM_L
CPUTHMSNS_ALERT_L
ALERT*
4 DP2/DN3
SMDATA
SMBUS_SMC_B_S0_SDA
BI
42 45 48 94
5 DN2/DP3
GND
6
SMCLK
10
SMBUS_SMC_B_S0_SCL
BI
42 45 48 94
THRM_PAD
11
Placement note:
CPUTHMSNS_D2_P
Place U5570 under CPU

and close to left fin stack
SIGNAL_MODEL=EMPTY
Q5501
THERM*/ADDR
CRITICAL
10K
1%
1/16W
MF-LF
402 2
EMC1413
0.0022UF
96 10
C5570
0.1uF R55711
20%
10V
2 CERM
402
U5570
CPU_THERMD_P
SIGNAL_MODEL=EMPTY
Detect CPU Die Temperature
C5590 1
0.0022uF
10%
50V
CERM 2
402
BC846BMXXH
Detect Right Fin Stack Temperature
1
1
VDD
SOT732-3
2
96
CPUTHMSNS_D2_N
Placement note:
Place Q5501 on bottom side
close to right fin stack
MCP Proximity/MCP Die/Battery Charger Proximity

C
R5500
82 81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84
PP3V3_S0
47
PP3V3_S0_REMTHMSNS_R
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
96 21
C5500
0.1uF
20%
R55011
2 10V
CERM
MCP_THMDIODE_P
BI
402
1
VDD
SIGNAL_MODEL=EMPTY
C5511 1
Detect MCP Die Temperature
U5500
0.0022uF
10%
50V
CERM 2
402
96 21
96
MCPTHMSNS_D_P
Detect Battery Charger Temperature
SIGNAL_MODEL=EMPTY
Q5502
C5521
15.0K
1%
1/16W
MF-LF
402 2
R5502
10K
5%
1/16W
MF-LF
2 402
EMC1413
DFN
2 DP1
REMTHMSNS_THM_L
ALERT*
REMTHMSNS_ALERT_L
4 DP2/DN3
SMDATA
SMBUS_SMC_B_S0_SDA
BI
42 45 48 94
5 DN2/DP3
GND
6
SMCLK
10
SMBUS_SMC_B_S0_SCL
BI
42 45 48 94
3 DN1
MCP_THMDIODE_N
BI
Note: EMC1413 can perform Beta

Compensation for External Diode 1 only
THERM*/ADDR
CRITICAL
THRM_PAD
11
0.0022uF
BC846BMXXH
10%
50V
CERM 2
402
SOT732-3
2
96
Placement note:
Placement note:
Place U5500 near MCP
MCPTHMSNS_D_N
Placement note:
Place Q5502 near battery

charger circuit
Keep 2 caps as close

to IC pins as possible
GPU Proximity/GPU Die/Left Heat Pipe

R5550
82 81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84
PP3V3_S0
47
96 77 76
PP3V3_S0_GPUTHMSNS_R
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
GPU_TDIODE_P
BI
1
VDD
SIGNAL_MODEL=EMPTY
C5551 1
Detect GPU Die Temperature
U5550
0.0022uF
10%
50V
CERM 2
402
96 77 76
96
GPUTHMSNS_D_P
Detect Left Heat Pipe Temperature
GPU_TDIODE_N
BI
Q5503
SIGNAL_MODEL=EMPTY
C5552 1
0.0022uF
BC846BMXXH
10%
50V
CERM 2
402
SOT732-3
2
Placement note:
96
C5550
0.1uF
R55511
20%
10V
2 CERM
402
10K
1%
1/16W
MF-LF
402 2
R5552
10K
5%
1/16W
MF-LF
2 402
EMC1413
DFN
2 DP1
THERM*/ADDR
GPUTHMSNS_THM_L
3 DN1
ALERT*
GPUTHMSNS_ALERT_L
4 DP2/DN3
SMDATA
SMBUS_SMC_0_S0_SDA
BI
42 45 53 78 94
5 DN2/DP3
GND
6
SMCLK
10
SMBUS_SMC_0_S0_SCL
BI
42 45 53 78 94
CRITICAL
Thermal Sensors
THRM_PAD
11

Placement note:
GPUTHMSNS_D_N
Place on top side under left heat pipe near CPU
Place U5550 near GPU

Placement note:
Keep 2 caps as close

to IC pins as possible
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
48
97
Left Fan
70 67 66 63 51 49 44 39 8 7
85 83
77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84 82 81 80
PP5V_S0
PP3V3_S0
CRITICAL
1
R5650
47K
5%
1/16W
MF-LF
402 2
R5655
42
OUT
SMC_FAN_0_TACH
47K
FAN_LT_TACH
5%
1/16W
MF-LF
402
R56511
5%
1/16W
MF-LF
402 2
42
IN
SMC_FAN_0_CTL
70 67 66 63 51 49 44 39 8 7
85 83
77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84 82 81 80
PP5V_S0
PP3V3_S0
R5660
78171-0004
M-RT-SM
5
47K
2N7002DW-X-G
D
SOT-363
3
7 FAN_LT_PWM
5%
1/16W
MF-LF
402 2
R5665
1
2
3
4
42
OUT
SMC_FAN_1_TACH
47K
FAN_RT_TACH
5%
1/16W
MF-LF
402
R56611
5%
1/16W
MF-LF
402 2
518S0369
42
IN
SMC_FAN_1_CTL
J5660
78171-0004
M-RT-SM
5
1
2
3
4
6
100K
Q5660
4 S
CRITICAL
J5650
100K
Right Fan
2
G
Q5660
2N7002DW-X-G
SOT-363
1 S
D 6
518S0369
FAN_RT_PWM
Fan Connectors
SYNC_MASTER=M87_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
49
97
KEYBOARD CONNECTOR
PSOC USB CONTROLLER
IC
PIN NAME
TMP102
V+
CURRENT
R_SNS
V_SNS
POWER
10UA
2.55 KOHM
0.0255 V
0.255E-6 W
0.204 V
16.32E-6 W
80UA
3V3 LDO
USB INTERFACES TO MLB

SPI HOST TO Z2
TRACKPAD PICK BUTTONS

KEYBOARD SCANNER
VDD
60MA MAX
10 OHM
VOUT
60MA MAX
0.2 OHM
0.012 V
1.5 OHM
0.012 V
96E-6 W
0.021 V
294E-6 W
PSOC
VDD
18V BOOSTER
VIN
8MA (TYP)
0.6 V
14MA (MAX)
51 7
50
51 7
50
51 7
51 7
51 7
51 7
51 7
51 7
51 7
51 7
51 7
51 7
51 7
P2_3
P2_1
P4_7
P4_5
P4_3
P4_1
P3_7
P3_5
P3_3
P3_1
P5_7
P5_5
P5_3
P5_1
P2_5
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
4.7 OHM
0.0188 V
75.2E-6 W
CRITICAL
U5701
CY8C24794
MLF
(SYM-VER2)
APN 337S2983
OMIT
APN 518S0430
TEST POINTS ARE FOR ON BOARD PROGRAMMING
WS_KBD17 7 50
WS_KBD16N 50
WS_KBD15_C 50
WS_KBD14 7 50
WS_KBD13 7 50
WS_KBD12 7 50
WS_KBD11 7 50
WS_KBD10 7 50
WS_KBD9 7 50
WS_KBD8 7 50
WS_KBD7 7 50
WS_KBD1 7 50
WS_KBD2 7 50
WS_KBD3 7 50
FH19C-4S-0.5SH25
NC
70 52 50 45 32 31 27 21 8 7
PP3V3_S3
50
ISSP_SCLK_P1_1
50
ISSP_SDATA_P1_0
50
470
1%
1/16W
MF-LF
402
ISSP CLOCK
R5715
ISSP DATA
50
NC
WS_KBD15_C
WS_KBD16N
10K
1%
1/16W
MF-LF
402
43 42
OUT
SMC_ONOFF_L
1
57
C5710
0.1UF
20%
2 10V
CERM
402
WS_KBD4 7
WS_KBD5 7
WS_KBD6 7
NC_PSOC_SDA
F-RT-SM1
5
1
2
3
4
WS_KBD1
50 7 WS_KBD2
50 7 WS_KBD3
50 7 WS_KBD4
50 7 WS_KBD5
50 7 WS_KBD6
50 7 WS_KBD7
50 7 WS_KBD8
50 7 WS_KBD9
50 7 WS_KBD10
50 7 WS_KBD11
50 7 WS_KBD12
50 7 WS_KBD13
50 7 WS_KBD14
7 WS_KBD15_CAP
7 WS_KBD16_NUM
50 7 WS_KBD17
50 7 WS_KBD18
50 7 WS_KBD19
50 7 WS_KBD20
50 7 WS_KBD21
50 7 WS_KBD22
R5710
50 7 WS_KBD23
1K
1
2
7 WS_KBD_ONOFF_L
5%
8 7 PP3V42_G3H
1/16W44 436942644062266122502146 45
MF-LF
50 7 WS_LEFT_SHIFT_KBD
402
50 7 WS_LEFT_OPTION_KBD
50 7 WS_CONTROL_KBD
50
46 45 44 43 42 40 26 22 21 8 7
69 64 62 61 50
PP3V3_S3
7 51
50 7
WS_LEFT_SHIFT_KBD
20%
CRITICAL
10V
5 TC7SZ08AFEAPE
CERM
SOT665
402
4
NC_P7_7
ISSP_SCLK_P1_1
31
F-RT-SM
U5725Y
SMC_MANUAL_RESET LOGIC
45 44 43 42 40 26 22 21 8 7
69 64 62 61 50 46
WS_LEFT_SHIFT_KEY 50
PP3V42_G3H
1
C5758
0.1UF
10%
16V
2 X7R-CERM
402
50
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0.1UF
50
52 50 45 32 31 27 21 8 7
70
32
FF14-30A-R11B-B-3H
C5725
PP3V42_G3H
50
ISSP_SDATA_P1_0
Z2_CLKIN
NC
PLACEMENT_NOTE=NEAR J5713
ISOLATION CIRCUIT
ISSP SDATA/I2C SDA
NC_PSOC_P1_3
PP3V3_S3
50
R5714
J5702
P2_2
P2_0
P4_6
P4_4
P4_2
P4_0
P3_6
P3_4
P3_2
P3_0
P5_6
P5_4
P5_2
P5_0
THRML
PAD
42
41
40
39
38
37
36
35
34
33
32
31
30
29
TP_PSOC_SCL
NC
IN
TPAD_DEBUG
15 P1_7
16 P1_5
17 P1_3
18 P1_1
19 VSS
20 D+
21 D22 VDD
23 P7_7
24 P7_0
25 P1_0
26 P1_2
27 P1_4
28 P1_6
50
WS_CONTROL_KEY
Z2_KEY_ACT_L
TP_BOOT_CFG1
TP_P4_5
Z2_DEBUG3
Z2_RESET
PSOC_MISO
PSOC_F_CS_L
PSOC_MOSI
PSOC_SCLK
Z2_MISO
Z2_CS_L
Z2_MOSI
Z2_SCLK
4MA (MAX)
PSOC PROGRAMMING CONNECTOR
56
55
54
53
52
51
50
49
48
47
46
45
44
43
50
PICKB_L
BUTTON_DISABLE
Z2_HOST_INTN
WS_LEFT_SHIFT_KEY
WS_LEFT_OPTION_KEY
36E-3 W
0.72E-3 W
50 7
50
WS_KBD23 7 50
WS_KBD22 7 50
WS_KBD21 7 50
WS_KBD20 7 50
WS_KBD19 7 50
WS_KBD18 7 50
PP3V3_S3_PSOC
J5713
APN 518S0637
ISSP SCLK/I2C SCL

45 44 43 42 40 26 22 21 8 7
69 64 62 61 50 46
PP3V42_G3H
APN 311S0406
CRITICAL
DIFFERENTIAL_PAIR=USB2_TPAD
USB_TPAD_P
91 20
R5701
24
TO MLB CONNECTOR
NET_SPACING_TYPE=USB
NET_PHYSICAL_TYPE=USB_90D
50
50 7
WS_LEFT_OPTION_KBD
U5726Y
WS_LEFT_OPTION_KEY 50
50 7
50 7
50 7
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
1
3
6
CRITICAL
SN74LVC1G10
SC70
4
B
Y
U5703
43
SMC_TPAD_RST_L
R5702
USB_TPAD_N
91 20
PP3V3_S3
USB_TPAD_R_P
PP3V3_S3_PSOC
5%
1/16W
MF-LF
402
70 52 50 45 32 31 27 21 8 7
5 TC7SZ08AFEAPE
SOT665
4
24
5%
1/16W
MF-LF
402
USB_TPAD_R_N
1
NET_SPACING_TYPE=USB
NET_PHYSICAL_TYPE=USB_90D
R5769
PP3V42_G3H
33K
5%
1/16W
MF-LF
2 402
46 45 44 43 42 40 26 22 21 8 7
69 64 62 61 50
CRITICAL
70 52 50 45 32 31 27 21 8 7
50 7
PP3V3_S3
WS_CONTROL_KBD
5 TC7SZ08AFEAPE
SOT665
4
U5727Y
R5770
33K
5%
1/16W
MF-LF
2 402
R5771
33K
5%
1/16W
MF-LF
2 402
WS_CONTROL_KEY 50
3
U5701 CHIP DECOUPLING
PLACE C5701, C5702 & C5703
PLACE C5704, C5705 & C5706
CLOSE TO U5701
CLOSE TO U5701
VDD PIN 22
VDD PIN 49
TPAD BUTTONS DISABLE

R5704
50
PP3V3_S3_PSOC
1
C5701
4.7UF
20%
2 6.3V
X5R
603
C5702
100PF
5%
2 50V
CERM
402
C5703
0.1UF
10%
2 16V
X7R-CERM
402
1.5
1
C5704
100PF
5%
2 50V
CERM
402
C5705
0.1UF
10%
2 16V
X7R-CERM
402
PP3V3_S3
50
BUTTON_DISABLE
7 8 21 27 31 32 45 50 52 70
5%
1/16W
MF-LF
402
PLACE THESE COMPONENTS CLOSE TO J5800

THIS ASSUMES THERES A PP3V42_G3H PULL UP ON MLB
C5706
4.7UF
Q5701
20%
2 6.3V
X5R
603
SSM3K15FV
WELLSPRING 1
D 3
SOD-VESM-HF
1 G
SMC_LID
61 43 42
IN
S 2
THE TPAD BUTTONS WILL BE DISABLE

WHEN THE LID IS CLOSED
LID OPEN => SMC_LID_LC ~ 3.42V
LID CLOSE => SMC_LID_LC < 0.50V

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
50
97
BOOSTER +18.5VDC FOR SENSORS
BOOSTER DESIGN CONSIDERATION:

- POWER CONSUMPTION
- DROOP LINE REGULATION
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM
- STARTUP TIME LESS THAN 2MS
- R5812,R5813,C5818 MODIFIED
D
APN 152S0504
PP5V_S3
D
IPD FLEX CONNECTOR
CRITICAL
55 53 51 43 41 40 39 31 9 8 7
79 70 65 64
INPUT_SW
D5802
SOD-323
BOOST_SW
R5806
PP18V5_S3_SW 1
MIN_NECK_WIDTH=0.20MMB0520WSXG
VLF3010AT-SM-HF
0.50MM
0.20MM
SWITCH_NODE=TRUE
APN 371S0313
5%
1/16W
MF-LF
402
R5805
L5801
3.3UH-870MA
PP5V_S3_BOOSTER
C5818
39PF
PP18V5_S3
7 51
APN 516S0689
CRITICAL
R5812
J5800
1M
55560-0228
1%
1/16W
MF-LF
2 402
5%
2 50V
CERM
402
APN 353S1401
5%
1/16W
MF-LF
402
M-ST-SM
Z2_CS_L
50 7 Z2_DEBUG3
50 7 Z2_MOSI
50 7 Z2_MISO
50 7 Z2_SCLK
51 7 Z2_BOOST_EN
50 7 Z2_HOST_INTN
50 7
VIN
U5805
1 L
1
FB
BOOST_FB
Z2_BOOST_EN
1UF
10%
2 25V
X5R
603-1
TPS61045
3
QFN
DO
CTRL
7 51
CRITICAL
0.1UF
10%
2 16V
X7R-CERM
402
PAD
C5817
2.2UF
R5813
71.5K
6 GND
C5816
1
8
SW
7 PGND
THRML
C5819
1%
1/16W
MF-LF
2 402
R5811
100K
50 7
51 7
Z2_CLKIN
PP3V3_S3_LDO
1%
1/16W
MF-LF
2 402
10%
2 16V
X5R
603
0.50MM
0.20MM
2
4
6
8
10
12
14
16
18
20
22
1
3
5
7
9
11
13
15
17
19
21
Z2_KEY_ACT_L 7 50
Z2_RESET 7 50
PSOC_F_CS_L 7 50
PICKB_L 7 50
PSOC_MISO 7 50
PSOC_MOSI 7 50
PSOC_SCLK 7 50
SMBUS_SMC_A_S3_SDA 7 31 42 45
94
SMBUS_SMC_A_S3_SCL 7 31 42 45
94
PP18V5_S3 7 51
0.50MM
0.20MM
3V3 LDO FOR IPD
R5873
PP5V_S3
10
55 53 51 43 41 40 39 31 9 8 7
79 70 65 64
PP5V_S3_VR
1%
1/16W
MF-LF
402
51 7
PP3V3_S3_LDO
VR5802
2.2UF
MM3243DRRE
10%
2 16V
X5R
603
MLF
1 CE
VOUT
1%
1/6W
MF
402-HF
VDD
C5853
0.2
R5836
APN 353S1364
CRITICAL
PP3V3_S3_LDO_R
C5838
0.1UF
C5854
4.7UF
10%
2 16V
X7R-CERM
402
20%
2 6.3V
X5R
603
GND
Keyboard LED Driver

82 81 80 77 70 69 68 63 60
28 25 24 22 21 19 18 13 8 7 6
59 55 49 48 47 45 43 39 37 29
96 85 84
PP3V3_S0
83 70 67 66 63 49 44 39 8 7
85
PP5V_S0
CRITICAL
L5850
10UH-0.58A-0.35OHM
1
2
KBDLED_SW
R5853
To detect Keyboard backlight, SMC will
470K
LOW = keyboard backlight present

HIGH= keyboard backlight not present
42
1098AS-SM
1UF
VIN
10%
10V 2
X5R
402-1
51 7
LED 5
KBDLED_ANODE
CRITICAL
R58541
R5853 ALWAYS PRESENT
4.7K
5%
1/16W
MF-LF
402 2
NO STUFF
U5850
R58521
LT3491
5%
1/16W
MF-LF
402 2
CAP 4
THRML
PAD
7
GND
R5855
WELLSPRING 2
APN 518S0612
SYNC_MASTER=PWRSQNC
10
1%
1/16W
MF-LF
2 402
DFN
10K
F-RT-SM
1
2
3
4
BOM OPTION: KBDLED_YES
SW 3
6 CTRL
J5815 pin 1 is grounded

on keyboard backlight flex
FF18-4A-R11AD-B-3H
SWITCH_NODE=TRUE
C5850 1
SMC_SYS_KBDLED
J5815
5%
1/16W
MF-LF
402 2
tristate SMC_SYS_KBDLED:
CRITICAL
KBD BACKLIGHT CONNECTOR

KBDLED_CAP
C5855
1UF
10%
2 35V
X5R
603
SIZE
DRAWING NUMBER
51 7
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
51
97
Analog SMS
R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC
70 50 45 32 31 27 21 8 7
PP3V3_S3
Desired orientation when
14
R59211
52 42
IN
SMS_PWRDN
52 42
SMS_PWRDN
MAKE_BASE=TRUE
C5926
placed on board top-side:
10UF
10%
2 16V
X5R
402
U5920
5%
1/16W
MF-LF
402 2
0.1UF
VDD
10K
C5922
AP344ALH
+Y
LGA
1 FS
5 PD
SMS_SELFTEST2 ST
SMS_X_AXIS
OUT
42
VOUTY 10
SMS_Y_AXIS
OUT
42
VOUTZ 8
SMS_Z_AXIS
OUT
42
VOUTX 12
CRITICAL
20%
2 4V
X5R
603
Front of system
+X
+Z (up)
15 RES
4 RES
NC
1
R5922
10K
NC
NC
NC
3 NC
6 NC
9 NC
NC 11 NC
NC 13 NC
NC 16 NC
C5923
0.01UF
GND
10%
2 16V
CERM
402
5%
1/16W
MF-LF
2 402
C5924
0.01UF
10%
2 16V
CERM
402
C5925
Circle indicates pin 1 location when placed

in correct orientation
0.01UF
10%
2 16V
CERM
402
Sudden Motion Sensor (SMS)
SYNC_MASTER=SENSOR

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
52
97
XW6020
SM
PP5V_WLAN_F_XW
39 7
PP5V_SW_ODD
DEBUG_ADC
1
PP5V_SW_ODD_XW
DEBUG_ADC
1M
1%
1/16W
MF-LF
2 402
R6020
1M
1%
1/16W
MF-LF
2 402
R6012
PP5V_WLAN_F_DIV
DEBUG_ADC
1
R6011
681K
226K 2
ADC_CH0
1%
1/16W
MF-LF
402
DEBUG_ADC
1
R6021
C6012
681K
2.2UF
1%
1/16W
MF-LF
2 402
ADC_CH1
1%
1/16W
MF-LF
402
DEBUG_ADC
1
C6022
53
2.2UF
53
10%
2 6.3V
X5R
402
53
53
53
53
53
55 53 51 43 41 40 39 31 9 8 7
79 70 65 64
22
23
24
1
2
3
4
5
I2C ADDRESS: 0X10 / 0X11

ADC RANGE: 0V TO 4.096V
LSB: 0.001V
R6001
AD0 14
AD1 15
QFN
DEBUG_ADC
SDA 17
SCL 16
REFCOMP 8
1
R6030
ISNS_AIRPORT_P
243
96
ISNS_AIRPORT_R_P
U6030
OPA2330
V+
ISNS_AIRPORT_N
243
ISNS_AIRPORT_IOUT
226K 2
ADC_CH2
1%
1/16W
MF-LF
402
GAIN: 1239X
ISNS_AIRPORT_R_N
96 39
IN
ISNS_ODD_P
53
C6032 1
470PF
96 39
IN
ISNS_ODD_N
10%
50V
CERM 2
402
R6032
ISNS_ODD_R_P
OPA2330
499
1%
1/16W
MF-LF
2 402
3.65K2
1
ISNS_1V5_S3_P
DEBUG_ADC
1
C6005
DEBUG_ADC
1
10UF
C6006
2.2UF
20%
2 6.3V
CERM
402-LF
20%
2 6.3V
X5R
603
3.65K2
C6040
R6054
ISNS_ODD_IOUT
226K 2
ADC_CH4
1%
1/16W
MF-LF
402
GAIN: 561X
53
DEBUG_ADC
1
C6054
2.2UF
R6053
280K
1%
1/16W
MF-LF
2 402
10%
50V
CERM 2
402
280K 2
1% DEBUG_ADC
1/16W
MF-LF
402
C6053
470PF
10%
50V
CERM
402
10%
50V
CERM
402
DEBUG_ADC
R6060
96
ISNS_1V5_S3_R_P
PLACEMENT_NOTE=PLACE RC NEAR U6000

DEBUG_ADC
U6030
OPA2330
V+
GAIN: 273X
ISNS_1V5_S3_R_N
226K 2
ADC_CH3
1%
1/16W
MF-LF
402
VTHRM
96
ISNS_1V5_S3_IOUT
96 39
IN
ISNS_HDD_P
53
DEBUG_ADC
1
DEBUG_ADC
C6042 1
470PF
96 39
IN
ISNS_HDD_N
10%
50V
CERM 2
402
R6042
1%
1/16W
MF-LF
2 402
1M
1%
1/16W
MF-LF
402
ISNS_HDD_IOUT
226K 2
ADC_CH5
1%
1/16W
MF-LF
402
GAIN: 845X
53
DEBUG_ADC
1
C6064
2.2UF
10%
2 6.3V
X5R
402
DEBUG_ADC
1
DEBUG_ADC
C6043
DEBUG_ADC
R6062
R6063
348K
1%
1/16W
MF-LF
2 402
10%
50V
CERM 2
402
348K 2
1% DEBUG_ADC
1/16W
MF-LF
402
C6063
470PF
470PF
C6050
PPVOUT_S0_LCDBKLT
85 80 7
20%
2 10V
CERM
402
XW6080
SM
1
DEBUG_ADC
U6050
R6080
1M
1%
1/16W
MF-LF
2 402
R6074
INA210
ISNS_LCDBKLT_IOUT
OUT 6
DEBUG_ADC
REF 1
PPVOUT_S0_LCDBKLT_XW
1

DEBUG_ADC
V+
10%
50V
CERM
402
PLACEMENT_NOTE=PLACE NEAR D9701
0.1UF
4 IN+
4
9
ISNS_HDD_R_N
96
VTHRM
470PF
DEBUG_ADC
SC70
V+
C6062 1
PP5V_S3
ISNS_LCDBKLT_P
R6064
8 DFN
DEBUG_ADC
10%
50V
CERM
402
5 IN-
412

DEBUG_ADC
U6040
OPA2330
R6043
1M
ISNS_LCDBKLT_N
ISNS_HDD_R_P
1%
1/16W
MF-LF
402
DEBUG_ADC
DEBUG_ADC
1
96
R6061
C6044
2.2UF
DEBUG_ADC
10%
2 6.3V
X5R
402
1%
1/16W
MF-LF
402
412
1%
1/16W
MF-LF
402
R6044
8 DFN
R6041
IN
42 45 48 78 94
DEBUG_ADC
R6052
C6052 1
C6033
DEBUG_ADC
96 85
IN
10%
2 6.3V
X5R
402
1% DEBUG_ADC
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
ISNS_1V5_S3_N
ISNS_ODD_R_N
DEBUG_ADC
R6040
IN
VTHRM
96
470PF
DEBUG_ADC
V+
301K 2
1
96 85
C6004
8 DFN
R6033
301K
U6040
470PF
55 53 51 43 41 40 39 31 9 8 7
79 70 65 64
SMBUS_SMC_0_S0_SCL
5%
1/16W
MF-LF
402

DEBUG_ADC
DEBUG_ADC
1%
1/16W
MF-LF
402
DEBUG_ADC
DEBUG_ADC
1
96
R6051
C6034
2.2UF
DEBUG_ADC
DEBUG_ADC
1
499
1%
1/16W
MF-LF
402
10%
2 6.3V
X5R
402
DEBUG_ADC
IN
PLACEMENT_NOTE=PLACE CLOSE TO U4900
0.1UF
R6050
THRM
96
1%
1/16W
MF-LF
402
96 65
20%
2 10V
CERM
402
DEBUG_ADC
V-
R6031
42 45 48
78 94
DEBUG_ADC
R6034
8 DFN
DEBUG_ADC
IN
R6002
1
20%
2 10V
CERM
402

DEBUG_ADC
DEBUG_ADC
1%
1/16W
MF-LF
402
96 65
BI
DEBUG_ADC
0.1UF
C6030
20%
2 10V
CERM
402
DEBUG_ADC
IN
SMBUS_SMC_0_S0_SDA
ADC_REFCOMP
DEBUG_ADC
DEBUG_ADC
THRM
PAD
ADC_VREF
0.1UF
96 31
5%
1/16W
MF-LF
402
ADC_SDA
ADC_SCL
VREF 7
GND
DEBUG_ADC
IN
10UF
20%
2 6.3V
X5R
603
PP5V_S3
1
96 31
C6003
DEBUG_ADC
LTC2309
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
6 COM
DIVIDER: ~ 2/5
DIVIDER: ~ 2/5
DVDD
U6000
ADC_CH0
ADC_CH1
ADC_CH2
ADC_CH3
ADC_CH4
ADC_CH5
ADC_CH6
ADC_CH7
20%
2 10V
CERM
402
20%
2 6.3V
X5R
603
53
53
DEBUG_ADC
C6002
0.1UF
AVDD
226K 2
1%
1/16W
MF-LF
2 402
10%
2 6.3V
X5R
402
10UF
R6022
1
DEBUG_ADC
C6001

DEBUG_ADC
PP5V_SW_ODD_DIV
DEBUG_ADC
53
20%
2 10V
CERM
402

DEBUG_ADC
DEBUG_ADC
C6000
0.1UF
DEBUG_ADC
R6010
PP5V_S3
55 53 51 43 41 40 39 31 9 8 7
79 70 65 64
12
13
PP5V_WLAN_F
21
XW6010
SM
31
PP5V_S3
55 53 51 43 41 40 39 31 9 8 7
79 70 65 64
PLACEMENT_NOTE=PLACE NEAR Q4590
PLACEMENT_NOTE=PLACE NEAR Q3450
25
9
10
11
18
19
20
GAIN: 200X
226K 2
ADC_CH6
1%
1/16W
MF-LF
402
PPVOUT_S0_LCDBKLT_DIV
DEBUG_ADC
53
DEBUG_ADC
1
R6081
C6074
47.0K
2.2UF
R6082
1
226K 2
1%
1/16W
MF-LF
402
ADC_CH7
53
DEBUG SENSORS AND ADC
DEBUG_ADC
1
C6082
SYNC_MASTER=DDR
2.2UF
1%
1/16W
MF-LF
2 402
10%
2 6.3V
X5R
402
GND

DEBUG_ADC
10%
2 6.3V
X5R
402

DIVIDER: ~ 1/22

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
53
97
37 34 30 26 24 22 20 18 8 7
96 87 82 70 69 68 64 44 38
PP3V3_S5
NO STUFF
10K
R6150
44
IN
SPI_CLK_MUX

44
IN
SPI_MLB_CS_L
5%
1/16W
MF-LF
402 2
3.3K
5%
1/16W
MF-LF
402 2
R6101
3.3K
5%
1/16W
MF-LF
2 402
91
C6100 1
R61901 R61001
SPI_CLK
5%
1/16W
MF-LF
402
SPI_WP_L
SPI_HOLD_L
20%
10V
CERM 2
402
CRITICAL
VCC
0.1UF
U6100
32MBIT
SOP
6 SCLK
SI/SIO0 5
MX25L3205DM2I-12G
1 CE*
3 WP*/ACC
7 HOLD*
SPI_MISO_R
NO STUFF
91
R6191
10K
GND
R6105
OMIT
SO/SIO1 2
R6152
SPI_MOSI
91
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SPI_MOSI_MUX
IN
44
SPI_MISO_MUX
OUT
44
5%
1/16W
MF-LF
2 402
MCP79 SPI Frequency Select

Frequency
SPI_MOSI
SPI_CLK
31 MHz
42 MHz
25 MHz
1 MHz
25MHz is selected with R5190 and R5191

Any of the 4 frequencies can be selected
with R6190, R6191, R5190 and R5191
SPI ROM
SYNC_MASTER=CHANG_M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
54
97
AUDIO CODEC
APPLE P/N 353S2355
CRITICAL
L6201
FERR-220-OHM
87 84 70 69 25 18 8 7
PP1V8_S0
IN
PP5V_S3
2
0402
PP1V8_S0_AUDIO_DIG
VOLTAGE=1.8V
CRITICAL
C6210
4.7UF
20%
4V
X5R
402
C6211
10%
2 16V
X5R
402
C6216
R6210
R6218
1%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
C6220
10UF
20%
6.3V
X5R
603-1
2.67K
10K
10UF
20%
6.3V
X5R
603-1
VBIAS_DAC
CS4206_FP
CS4206_FN
AUD_GPIO_1
58
NC TP_AUD_GPIO_2
OUT AUD_GPIO_3
60
IN
AUD_SENSE_A
CS4206_FLYP
CS4206_FLYC
CRITICAL
K19I
1
CRITICAL
R6219
C6222
10K
5%
1/16W
MF-LF
2 402
20%
6.3V
CERM
402-LF
2.2UF
2
20%
6.3V
CERM
402-LF
2
12
14
15
GPIO0/DMIC_SDA1
GPIO1/DMIC_SDA2
/SPDIF_OUT2
GPIO2
GPIO3
LINEOUT_L1+
LINEOUT_L1LINEOUT_R1+
LINEOUT_R1-
35
34
36
37
13
SENSE_A
LINEOUT_L2+
LINEOUT_L2LINEOUT_R2+
LINEOUT_R2-
31
30
32
33
MICBIAS
16
VL_HD
VL_IF
HDA_BIT_CLK
IN
HDA_SYNC
BITCLK
91 21
OUT
HDA_SDIN0
R6211
91 21
IN
91 21
IN
59
IN
HDA_SDOUT
HDA_RST_L
AUD_SPDIF_IN
39
10
AUD_SDI_R
QFN
VCOM
28
LINEIN_L+
LINEIN_CLINEIN_R+
21
22
23
MICIN_L+
MICIN_LMICIN_R+
MICIN_R-
18
17
19
20
VREF+_ADC
27
59
AUD_SPDIF_OUT
OUT
SDI
SDO
11
39
RESET*
47
48
AUD_SPDIF_OUT_CHIP
R6212
SPDIF_IN
SPDIF_OUT
DMIC_SCL
5%
1/16W
MF-LF
402
AUD_HP_PORT_L
AUD_HP_PORT_R
AUD_HP_PORT_REF
55 57 59
55 56 60
OUT
57
OUT
57
IN
59
NC_AUD_LO1_P_L NC 7
NC_AUD_LO1_N_L NC 7
AUD_LO1_P_R OUT 58
AUD_LO1_N_R OUT 58
AUD_LO2_P_L
AUD_LO2_N_L
AUD_LO2_P_R
AUD_LO2_N_R
AUD_CODEC_MICBIAS
OUT
58
OUT
58
OUT
58
OUT
58
OUT
60
IN
56
CS4206_VCOM
AUD_LI_P_L
AUD_LI_REF
AUD_LI_P_R
AUD_MIC_INP_L
AUD_MIC_INN_L
AUD_MIC_INP_R
AUD_MIC_INN_R
CS4206_VREF_ADC
IN
56
IN
56
IN
60
IN
60
IN
60
IN
60
NC
TP_AUD_DMIC_CLK
NC
DGND THRM_PAD AGND
CRITICAL
CRITICAL
C6224 1
1UF
C6225
10UF
20%
16V
TANT 2
0603-SM
60 56 55
10UF
SYNC
8
5
5%
1/16W
MF-LF
402
7 55
CS4206ACNZC
26
IN
91 21
VOLTAGE=4.5V
GND_AUDIO_HP_AMP
GND_AUDIO_CODEC
C6213
20%
2 6.3V
X5R
603
10%
16V 2
X5R
402
FLYP
FLYC
FLYN
0.1UF
39
49
91 21
10%
16V 2
X5R
402
CRITICAL
U6201
CS4206_FLYN
C6217
38
40
29
45
43
42
C6223
2.2UF
10%
1CRITICAL10V
X5R
402-1
10UF
20%
2 16V
TANT-POLY
2012-LLP
CRITICAL
C6215 1 C6214 1
0.1UF
VD VA_REF VA_HP VA
VBIAS_DAC
HPOUT_L
VHP_FILT+
HPOUT_R
VHP_FILTHPREF
44
41
NC TP_AUD_GPIO_0
10%
16V 2
X5R
402
25
CRITICAL
C6221
1
46
CRITICAL
K19
0.1UF
24
IN
70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7
55 51 49 48 47 45 43 39 37
96 85 84 82 81 80 77
C6218 1
20%
16V
TANT-POLY 2
2012-LLP
9
55 7
1UF
10UF
GND_AUDIO_HP_AMP
PP4V5_AUDIO_ANALOG
6 PP3V3_S0
29
59 57 55
59 60 63 68 69 70 77 80 81 82
6 7 8 13 18 19 21 22 24 25 28
29 37 39 43 45 47 48 49 51 55
84 85 96
PP4V5_AUDIO_ANALOG IN
CRITICAL
CRITICAL
C6219
PP3V3_S0
0.1UF
7 8 9 31 39 40 41 43 51 53 55
64 65 70 79
20%
2 16V
POLY-TANT
CASE-B2-SM
R6213
100K
5%
1/16W
MF-LF
2 402
VOLTAGE=0V
GND_AUDIO_CODEC
B
4.5V POWER SUPPLY FOR CODEC
APPLE P/N 353S2234
CRITICAL
L6200
55 53 51 43 41 40 39 31 9 8 7
79 70 65 64
IN
80 77 70 69 68 63 60 59 55
28 25 24 22 21 19 18 13 8 7 6
51 49 48 47 45 43 39 37 29
96 85 84 82 81
IN
PP5V_S3
CRITICAL
U6200
FERR-220-OHM MIN_NECK_WIDTH=0.10MM
VOLTAGE=5V
1
2
4V5_REG_IN
VOLTAGE=4.5V
NOTES ON CODEC I/O
MAX8840-4.5V
1 IN
UDFN
PP4V5_AUDIO_ANALOG
OUT 6
OUT
DIFF FSINPUT= 2.45VRMS

SE FSINPUT= 1.22VRMS
DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS
7 55
0402
R6200
4V5_REG_EN
2.21K2
1%
1/16W
MF-LF
402
BP 4 4V5_NR
3 SHDN*
GND
C6200
CRITICAL
1UF
10%
10V
2 X5R
402-1
NC 5
PP3V3_S0
10%
2 10V
X5R
402-1
C6203
1UF
10%
2 10V
X5R
402-1
10%
16V
X7R-CERM
402
1UF
XW6200
SM
0.1UF
1
C6201
CRITICAL
C6202
GND_AUDIO_CODEC
55 56 60
VOLTAGE=0V
AUDIO: CODEC/REGULATOR
NOSTUFF
R6201
XW6201
SM
1
5%
1/16W
MF-LF
402

VOLTAGE=0V
GND_AUDIO_HP_AMP 55
57 59

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
55
97
D
LINE INPUT VOLTAGE DIVIDER
CODEC RIN = 20K OHMS
NET RIN = 20K OHMS
FC = 8 HZ
VIN = 2VRMS, CODEC VIN = 1.21 VRMS
CRITICAL
C6301
R6301
59
AUD_LI_L
IN
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
6.04K2
1%
1/16W
MF-LF
402
3.3UF
1
AUD_LI_L_DIV
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
AUD_LI_P_L
55
OUT
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
10%
10V
CERM-X5R
805-1
CRITICAL
NOSTUFF
1
R6302
15PF
16.5K
1%
1/16W
MF-LF
2 402
C6303
5%
2 50V
CERM
402
CRITICAL
C6302
3.3UF
1
10%
10V
CERM-X5R
805-1
59
IN
AUD_LI_REF
AUD_LI_GND
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
OUT
55
R6300
10
CRITICAL
1%
1/16W
MF-LF
2 402
C6312
3.3UF
1
60 55
IN
10%
10V
CERM-X5R
805-1
GND_AUDIO_CODEC
CRITICAL
NOSTUFF
R6312
16.5K
1%
1/16W
MF-LF
2 402
C6313
15PF
5%
2 50V
CERM
402
CRITICAL
C6311
R6311
59
IN
AUD_LI_R
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
3.3UF
6.04K2
AUD_LI_R_DIV
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
1%
1/16W
MF-LF
402
10%
10V
CERM-X5R
805-1
AUD_LI_P_R
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
OUT
55
AUDIO: LINE INPUT FILTER

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
56
97
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

R6501
55
IN
AUD_HP_PORT_L
C6500 1
0.1UF
NC
AUD_HP_L OUT
59
5%
1/10W
MF-LF
603
CRITICAL
NO STUFF
CRITICAL
10%
16V
X7R-CERM 2
402
C6501 1
0.0022UF
AUD_HP_ZOBEL_L
10%
50V
CERM 2
402
R6500
R6502
2.21K
1%
1/16W
MF-LF
2 402
39
5%
1/16W
MF-LF
402 2
59 55
IN
GND_AUDIO_HP_AMP
R65101
39
5%
1/16W
MF-LF
402 2
NC
NO STUFF
CRITICAL
C6511 1
AUD_HP_ZOBEL_R
0.0022UF
10%
50V
CERM 2
402
CRITICAL
C6510
0.1UF
10%
16V
X7R-CERM 2
402
55
IN
AUD_HP_PORT_R
R6512
2.21K
1%
1/16W
MF-LF
2 402
R6511
1
AUD_HP_R
OUT
59
5%
1/10W
MF-LF
603
AUDIO: HEADPHONE FILTER
SYNC_MASTER=AUDIO

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
57
97
3X MONO SPEAKER AMPLIFIERS (SSM2315)

APN: 353S2500
GAIN = 6DB
1ST ORDER FC (L&R) = 120 HZ +/- 30%
1ST ORDER FC (SUB) = 58HZ +/- 30%
PLACE C6610 CLOSE TO VDD PIN

58 9
PP5V_S3_AUDIO_AMP
CRITICAL
CRITICAL
C6612 1
55
55
IN
IN
IN
B2
B1
PVDD
SSM2315L_P
SSM2315L_N
WLCSP OUT+ C3
OUT_ A3
C1 INA1 IN+
SPKRAMP_L_OUT_P
SPKRAMP_L_OUT_N
58 96
96 58
SPKRAMP_L_OUT_P
58 96
SPKRCONN_L_OUT_P
OUT
7 59 96
OUT
7 59 96
5%
1/16W
MF-LF
402
C2 SD*
GND
SPKRAMP_L_OUT_N
R66011
R6611
0
SPKRCONN_L_OUT_N
5%
1/16W
MF-LF
402
100K
AUD_SPKRAMP_SHUTDOWN_L
R6610
CRITICAL
96 58
0402
58
VDD
U6610
SSM2315
A2
B3
55
SPEAKER CHECKPOINTS
10%
2 16V
X5R
402
20%
6.3V
TANT-POLY 2
CASE-A4
CRITICAL
L6610
C6610
FERR-1000-OHM CRITICAL
0.033UF
1
2 AUD_SPKRAMP_INP_L
1
2
AUD_LO2_P_L
0402
NO_TEST=TRUE CRITICAL 10%
L6611
C6611 16V
X5R
0.033UF 402
1
2
2
AUD_SPKRAMP_INN_L 1
AUD_LO2_N_L
L6601 0402CRITICAL NO_TEST=TRUE
10%
FERR-1000-OHM
16V
X5R
1
2
402
AUD_GPIO_3
C6613
0.1UF
47UF
5%
1/16W
MF-LF
402 2
C

58 9
PP5V_S3_AUDIO_AMP
96 58
SPKRAMP_R_OUT_P
R6620
2
CRITICAL
C6622 1
47UF
CRITICAL
55
AUD_LO2_P_R
IN
L6621
AUD_LO2_N_R
IN
58
B1
C1 INA1 IN+
WLCSP OUT+ C3
OUT_ A3
SPKRCONN_R_OUT_P
OUT
7 59 96
96 58
SPKRAMP_R_OUT_N
R6621
2
SPKRAMP_R_OUT_P
SPKRAMP_R_OUT_N
OUT
7 59 96
OUT
7 59 96
OUT
7 59 96
SPKRCONN_R_OUT_N
5%
1/16W
MF-LF
402
58 96
58 96
C2 SD* CRITICAL
GND
16V
X5R
402
0.1UF
SSM2315
SSM2315R_P
SSM2315R_N
A2
B3
55
C6623
10%
2 16V
X5R
402
U6620
16V
X5R
402
C6621
0.033UF
1
2
2
AUD_SPKRAMP_INN_R 1
0402
NO_TEST=TRUE
10%
PVDD
VDD
L6620
C6620
0.033UF
1
2
1
2
AUD_SPKRAMP_INP_R
0402
NO_TEST=TRUE CRITICAL
10%
B2
5%
1/16W
MF-LF
402
CRITICAL
20%
6.3V
TANT-POLY 2
CASE-A4
B
96 58
SPKRAMP_S_OUT_P
R6630
2
SPKRCONN_S_OUT_P
5%
1/16W
MF-LF
402
96 58

58 9
1
B1
20%
6.3V 2
TANT
CASE-AL1
VDD
L6630
IN
AUD_LO1_N_R
IN
C6630
0.068UF
1
2
1
2
AUD_SPKRAMP_INP_SUB
0402
NO_TEST=TRUE
10%
CRITICAL
10V
L6631
C6631
CERM
402
0.068UF
1
2 AUD_SPKRAMP_INN_SUB 1
2
0402
NO_TEST=TRUE
10%
10V
CERM
402
58
SPKRCONN_S_OUT_N
PVDD
C6633
0.1UF
10%
2 16V
X5R
402
U6630
SSM2315
SSM2315S_P
SSM2315S_N
C1 INA1 IN+
WLCSP OUT+ C3
OUT_ A3
SPKRAMP_S_OUT_P
SPKRAMP_S_OUT_N
58 96
58 96
CRITICAL
C2 SD*
GND
A2
B3
55
AUD_LO1_P_R
B2
100UF
55
CRITICAL
C6632 1
CRITICAL
R6631
5%
1/16W
MF-LF
402
PP5V_S3_AUDIO_AMP
CRITICAL
SPKRAMP_S_OUT_N
AUDIO: SPEAKER AMP
SYNC_MASTER=AUDIO

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
58
97
AUDIO JACK 1 LO/HP JACK, SPDIF TX

AUD_SPDIF_OUT
MIC CONNECTOR
55
IN
L6703
1
CRITICAL
HS_MIC_HI
J6780
60
OUT
L6702
96 85 84
69 68 63 60
47 45 43 39
22 21 19 18 13 8 7 6
37 29 28 25 24
59 55 51 49 48
82 81 80 77 70
78171-0003
APN: 518S0520
0402
M-RT-SM
4
PP3V3_S0
HS_MIC_LO
0402
APN: 514-0671
CRITICAL
FERR-220-OHM
1
J6700
AUD_HP_PORT_REF
60 7
OUT
60 7
OUT
60 7
OUT
BI_MIC_LO
BI_MIC_SHIELD
BI_MIC_HI
1
2
3
55
BI
0402
CRITICAL
SPDIF-TXRX-K24
L6701
F-RT-TH
FERR-220-OHM-2.5A
1
AUD_CONNJ1_SLEEVE2
AUD_CONNJ1_SLEEVEDET
AUD_CONNJ1_TIPDET
AUD_CONNJ1_TIP
AUD_CONNJ1_RING
AUD_CONNJ1_SLEEVE
6
5
MIC
DETECT
SWITCH
LEFT
RIGHT
GND
2
1
3
4
2
0603
GND_AUDIO_HP_AMP
OUT
AUD_HP_R
BI
55 57
CRITICAL
L6704
FERR-220-OHM
1
57
0402
CRITICAL
AUDIO
L6706
7
8
A - VIN
B - VCC
C - GND
FERR-220-OHM
1
AUD_HP_L
BI
57
0402
R6700
OPERATING VOLTAGE 3.3
60
OUT
L6707
POF
10K
1
10
11
12
SHELL
SHIELD
PINS
CRITICAL
1
13
C6700
0.1UF
10%
2 16V
X5R
402
C6701
CRITICAL
2.2UF
DZ6703
20%
2 6.3V
CERM
402-LF
DZ6704
CRITICAL
6.8V-100PF
402
402
2
DZ6706
6.8V-100PF
402
402
OUT
60
C
SPEAKER CONNECTOR
CRITICAL
J6781
DZ6701
6.8V-100PF
60
0402
CRITICAL
CRITICAL
1
2
AUD_J1_TIPDET_R
6.8V-100PF
402
OUT
L6705
DZ6700
6.8V-100PF
AUD_J1_SLEEVEDET_R
5%
1/16W
MF-LF
402
APN: 518S0519
C6705
100PF
5%
2 50V
CERM
402
78171-0002
VOLTAGE=0V
9 59
96 58 7
IN
96 58 7
IN
M-RT-SM
3
SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
1
2
XW6701
SM
1
CRITICAL
XW6702
SM
GND PATCH
J6782
78171-0004
M-RT-SM
5
APN: 518S0521
R6701
84 82 81 80 77
49 48 47 45 43
19 18 13 8 7 6
39 37 29 28 25 24 22 21
70 69 68 63 60 59 55 51
96 85
59 9
4.7
5%
1/16W
MF-LF
402
R6749
AUD_J2_OPT_OUT
APN: 514-0635
PP3V3_S0
AUD_SPDIF_IN
5%
1/16W
MF-LF
402
J6750
SWITCH
LEFT
RIGHT
GROUND
33PF
5%
50V
NOSTUFF CERM
CRITICAL 402
NOSTUFF
CRITICAL
C6781 1
AUD_CONNJ2_RING
33PF
AUD_LI_R
BI
56
AUD_LI_L
BI
56
NOSTUFF
CRITICAL
1
C6784
33PF
5%
2 50V
CERM
402
C6782
33PF
5%
50V
CERM 2
402
FERR-1000-OHM
5%
50V
2 CERM
402
0402
CRITICAL
L6756
FERR-1000-OHM
6
7
8
AUD_CONNJ2_TIP
2
0402
CRITICAL
L6758
FERR-220-OHM
POF
SHIELD
PINS
IN
C6783
L6754
OPERATING VOLTAGE 3.3
SHELL
IN
96 58 7
1
2
3
4
NOSTUFF
CRITICAL
CRITICAL
AUD_CONNJ2_TIPDET
AUDIO
A - VDD
B - GND
C - VOUT
96 58 7
SPKRCONN_S_OUT_P
SPKRCONN_S_OUT_N
SPKRCONN_R_OUT_P
SPKRCONN_R_OUT_N
55
0402
5
2
1
3
4
IN
F-RT-TH5
DETECT FOR PLUG TYPE
IN
96 58 7
L6751
AUD_CONNJ2_SLEEVE
AUDIO-RCVR-M97
OUT
96 58 7
9
10
11
12
AUD_CONNJ2_SLEEVEDET
AUD_LI_GND
56
0402
CRITICAL
1
C6750
CRITICAL
1UF
DZ6754
10%
2 10V
X5R
402-1
2
CRITICAL
DZ6758
6.8V-100PF
6.8V-100PF
6.8V-100PF
CRITICAL402
DZ6756
L6752
FERR-1000-OHM
402
CRITICAL
OUT
60
AUDIO: JACKS
SYNC_MASTER=AUDIO
C6756
402
5%
50V
2 CERM
402
AUD_J2_TIPDET_R
DZ6751
6.8V-100PF
2
0402
402
100PF

9 59

AUDIO JACK 2 LINE IN JACK, SPDIF RX
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
59
97
CODEC OUTPUT SIGNAL PATHS

CONVERTER
0X02 (2)
0X04 (4)
0X03 (03)
0X08 (8)
PIN COMPLEX
0X09 (9,A)
0X0B (11)
0X0A (10)
0X10 (16)
MUTE CONTROL
N/A
GPIO_3
GPIO_3
N/A
PORT B LEFT(HEADSET MIC)

CRITICAL HP=80HZ, LP=8.82KHZ
MIKEY
L6880
FERR-1000-OHMVOLTAGE=3.3V
1
2 PP3V3_S0_HS_RX
DRC MIKEY
0402
DET ASSIGNMENT
0X09 (A)
N/A
N/A
0X0C (B)
82 81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84
PP3V3_S0
CODEC INPUT SIGNAL PATHS

FUNCTION
LINE IN
SPDIF IN
BUILT-IN MIC
HEADSET MIC
CONVERTER
0X05 (5)
0X07 (7)
0X06 (6)
0X06 (6)
PIN COMPLEX
0X0C (12,C)
0X0F (15)
0X0D (13,B,RIGHT)
0X0D (13,V22,B,LEFT)
VREF
N/A
N/A
MIC_BIAS (80%)
MIKEY
6.3V 20% 2
603 X5R
AVDD
DRC
91 85 45 21
IN
SMBUS_MCP_1_CLK
91 85 45 21
BI
SMBUS_MCP_1_DATA
PORT B DETECT(SPDIF DELEGATE)
SCL
MICBIAS
HS_MIC_BIAS
SDA
DETECT
HS_SW_DET
OUT
AUD_I2C_INT_L
INT*
IN
AUD_IPHS_SWITCH_EN
ENABLE
GND
MIKEY
60 55
OUT
60
PP3V3_S0_AUDIO_F
5%
1/16W
MF-LF
2 402
AUD_PORTA_DET_L NC
SOT563
47K
D 3
SSM6N15FEAPE
Q6801
AUD_PORTB_DET_L NC
55
OUT
MIKEY
CRITICAL
SOT563
C6886
5 G
1
AUD_MIC_INP_L
0.1UF
S 4
5 G
C6801
S 4
2 G
S 1
55
OUT
AUD_MIC_INN_L
0.1UF
10V
2 20%
CERM 402
60 56 55
GND_AUDIO_CODEC
60 56 55
R6803
60
PP3V3_S0_AUDIO_F
R6804
220K
IN
AUD_J1_SLEEVEDET_R
5%
1/16W
MF-LF
2 402
Q6800
D 6
60 59
C6802
2 G
S 1
55
IN
AUD_CODEC_MICBIAS
100
1%
1/16W
MF-LF
402
60 56 55
10%
25V
X5R
402
55
EXTRACT_BUFF
OUT
EXTRACT_BUFF
C6851
0.1UF
55
OUT
AUD_MIC_INN_R
MF-LF
PP3V3_S0_AUDIO_F 1 220K 2 AUD_J1_TIPDET_INV 402
EXTRACT_BUFF
15K
5%
1/16W
MF-LF
402
60 56 55
GND_AUDIO_CODEC
2
10%
25V
X5R
402
Q6803
CRITICAL
HS_MIC_LO
C6852
MF
402-1
2.2UF
L6850
FERR-1000-OHM
BI_MIC_HI_F
BI_MIC_HI
IN
7 59
IN
7 59
IN
7 59
0402
25V
X5R
402
R6852
100K
2.4K 2
5%
1/16W
MF-LF
2 402
CRITICAL
1
C6853
0.001UF
50V
10%
402 CERM 2
BI_MIC_LO_F
CRITICAL
C6854
27PF
50V
2 5%
CERM 402
L6851
FERR-1000-OHM
1
BI_MIC_LO
0402
1%
1/16W
MF
402-1
XW6851
SM
D 3
SSM6N15FEAPE
SOT563
BI_MIC_SHIELD
TIPDET_FILT
1
59
27PF
CRITICAL
R6851
R6853
1
EXTRACT_BUFF
D 6
R6860
AUD_J1_TIPDET_R1
CRITICAL 10%
5%
1/16W
R6864
60 59
IN
C6885
50V
2 5%
CERM 402
20%
2 6.3V
TANT
402
AUD_MIC_INP_R
100K 2
1
Q6803
59
MIC_BIAS_FILT 1 2.4K 2
1%
CRITICAL
1/16W
GND_AUDIO_CODEC
R6865
SSM6N15FEAPE
SOT563
EXTRACT_BUFF
IN
1 MIKEY
XW6880
SM
0.1UF
5%
1/16W
MF-LF
402
HS_MIC_HI
10%
2 X7R
402
C6850
5%
1/16W
MF-LF
2 402
MIKEY
CRITICAL
60
2.2K
PORT B RIGHT(BUILT-IN MIC)
R6850
10%
2 16V
CERM
402
GND_AUDIO_CODEC
R6882
AUD_J1_SLEEVEDET_R
SOT563
0.01UF
60 56 55
R6881
R6884
MF-LF
2 402
GND_AUDIO_CODEC
SSM6N15FEAPE
AUD_J1_SLEEVEDET_INV
5%
1/16W
MF-LF
402
60 59
220K 2
HS_MIC_HI_RC 1 2.2K 2
5%
MIKEY
1/16W
1
R6883 1 MIKEYMF-LF
402
100K
C6884
5%
0.0082UF
1/16W
25V
2
10%
25V
X5R
402
55 56 60
MIKEY
1%
1/16W
MF-LF
402 2
C6883
D 6
AUD_J1_DET_RC
5%
1/16W
MF-LF
402
GND_AUDIO_CODEC
MIKEY
10%
402 CERM 2
MIKEY
CRITICAL
SSM6N15FEAPE
SOT563
MIKEY 1
0.01UF
16V
0.1UF
Q6801
2.2UF
1K
1%
1/16W
MF-LF
2 402
C6882
20%
2 6.3V
TANT
402
20.0K
1%
1/16W
MF-LF
2 402
D 3
Q6800
SSM6N15FEAPE
R6802
AUD_J1_TIPDET_R
39.2K
APN:376S0613
AUD_OUTJACK_INSERT_L
220K
R6805
HS_RX_BP
C6881
5%
1/16W
MF-LF
402 2
R6806
10
MIKEY
CRITICAL
1
THM
100K
R6801
IN
BYPASS
4
9
R68801
AUD_SENSE_A
60 59
MIKEY
U6880
CD3275
PULLUPS ON MCP PAGE
19
C6880
10UF
21
PORT A DETECT (HEADPHONES)
APN:353S2256
CRITICAL
MIKEY 1
DET ASSIGNMENT
0X0C (12,C)
N/A
N/A
MIKEY
VOLUME
0X02 (2)
0X04 (4)
0X03 (3)
N/A
11
FUNCTION
HP/LINE OUT
SATELLITES
SUB
SPDIF OUT
HP=80HZ
2 G
5 G
S 1
C6860
S 4
0.1UF
10V
2 20%
CERM 402
60 56 55
60
EXTRACT_BUFF
GND_AUDIO_CODEC
PORT C DETECT (LINE-IN)
EXTRACTION NOTIFICATION
PP3V3_S0_AUDIO_F
APN:353S2401
VOLTAGE=3.3V
CRITICAL
60 55
AUD_SENSE_A
OUT
L6862
FERR-1000-OHM
80 77 70 69 68 63 60 59 55
28 25 24 22 21 19 18 13 8 7 6
51 49 48 47 45 43 39 37 29
96 85 84 82 81
IN
PP3V3_S0
60
R6811
AUD_J1_TIPDET_R
C6861
U6860
RST*
MR*
SC-70-1
GND
0.1UF
5%
1/16W
MF-LF
2 402
R6861
100
1
AUD_PERPH_DET_R
AUD_IP_PERIPHERAL_DET
17
OUT
Q6802
SSM3K15FV
AUDIO: JACK TRANSLATORS
D 3
SOD-VESM-HF
5%
1/16W
MF-LF
402
R6812
59
10V 20% 2
402 CERM
60 56 55
AUD_INJACK_INSERT_L
NC
270K
TPS3801E18DCK
VDD
10K
1%
1/16W
MF-LF
402 2
EXTRACT_DEBOUNCE
2
0402
60 59
R68131
PP3V3_S0_AUDIO_F
IN
AUD_J2_TIPDET_R
47K
5%
1/16W
MF-LF
402
GND_AUDIO_CODEC
SYNC_MASTER=AUDIO
APN:376S0612
AUD_J2_DET_RC
1
1 G
C6811
S 2

0.1UF
10V
2 20%
CERM 402
PLACE L6800/C6800 CLOSE TO U6800

60 56 55

GND_AUDIO_CODEC

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
60
97
MagSafe DC Power Jack

CRITICAL
CRITICAL
F6905
J6900
7
M-RT-SM
GND
GND
SIG
MIN_LINE_WIDTH=1mm
VOLTAGE=18.5V
1
2
3
4
5
C6905
1206-2
PP3V42_G3H
0.01UF
20% PLACEMENT_NOTE=Place
2 50V
CERM
603
2.0K
VCC
5%
1/16W
MF-LF
2 402
C6908
SC70-5
SYS_ONEWIRE
4 INT
EXT 5
CRITICAL
GND
NC
NO STUFF
402
SMC_BC_ACOK
U6901
IN
42 43 62
CRITICAL
RCLAMP2402B
20% PLACEMENT_NOTE=PLACE NEAR U6900 and U6901

2 10V
CERM
TC7SZ08AFEAPE
SOT665
A
MAX9940
D6900
U6900
SC-75
0.1UF
R6929
BI
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
SMC_BC_ACOK_VCC
near L6900
42
8 61 62
PWR
PP18V5_DCIN_FUSE
PWR
PPDCIN_G3H
6AMP-24V
78048-0573
NC
BIL CONNECTOR
PP3V42_G3H
45 44 43 42 40 26 22 21 8 7
69 64 62 61 50 46
C6951
1-Wire OverVoltage Protection

7
516S0523
CRITICAL
0.1UF
10%
25V
X5R
402
ADAPTER_SENSE
J6955
CPB6312-0101F
F-ST-SM
14
The chassis ground will otherwise float and can

send transients onto ADAPTER_SENSE when AC is
connected.
R6961
50 43 42
SMC_LID
OUT
100
NC
402
SMC_LID_R
SMBUS_SMC_BSA_SDA
BI
SMBUS_SMC_BSA_SCL
BI
7
1/16W
94 62
45 42 7
61
94
45 42 7
62 61
5%
MF-LF
C6955
C6953
10%
50V
CERM
402
C6952
47PF
0.001UF
5%
50V
CERM
402
5%
50V
CERM
402
10
12
11
16
15
NC
TO SMC
SMC_BIL_BUTTON_L
C6954
47PF
2
13
OUT
7 42 43
0.001UF
10%
50V
CERM
402
3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator
R6905
1
47
D6905
HN2D01JEAPE
5%
1/8W
MF-LF
805
SOT665
PPDCIN_S5_P3V42G3H
VOLTAGE=18.5V
79 67 66 65 64 62 46 37 8 7
86 83
PPVIN_G3H_P3V42G3H
NC
C6990
NC
VIN
10UF
10%
25V 2
X5R
805
518-0358
P3V42G3H_BOOST
VOLTAGE=18.5V
1
PPBUS_G3H
PPDCIN_G3H
62 61 8
BOOST
DFN
SW 4
NC
BIAS 2
L6995
33UH
7 62
DIDT=TRUE
THRM
PAD
C6995 1
22pF
5%
50V
CERM 2
402
7 42 45 61 62 94
RCLAMP2402B
SC-75
D6950
R6950 1
5%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
<Rb>
1
20%
2 6.3V
X5R-CERM
603
C6999
200K
1%
1/16W
MF-LF
2 402
10
11
348K
22UF
0.1UF
10%
25V
X5R
402
(Switcher limit)
R6995
R6996
C6950
10K
<Ra>
1
P3V42G3H_FB
7
42 45 61 62 94
CRITICAL
1
6
7
SMBUS_SMC_BSA_SCL
SYS_DETECT_L
SMBUS_SMC_BSA_SDA
250mA max output
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
Vout = 3.425
CDPH4D19FHF-SM
GND
PPVBAT_G3H_CONN
1
2
4
5
PP3V42_G3H
2
FB 1
M-RT-TH
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
CRITICAL
1
P3V42G3H_SW
SWITCH_NODE=TRUE
7 NC
BAT-K19
P1
P2
P3
P4
P5
P6
P7
P8
P9
20%
6.3V 2
X5R
402
LT3470A
CRITICAL
BATTERY CONNECTOR
J6950
0.22UF
U6990
8 SHDN*
CRITICAL
C6994 1
12
GND
Vout = 1.25V * (1 + Ra / Rb)
13
DC-In & Battery Connectors

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
61
97
FROM ADAPTER
61 8
Inrush Limiter
PPDCIN_G3H
Reverse-Current Protection
PPDCIN_S5_CHGR_R
R7060
R70651
C7060 1
100K
CRITICAL
Q7060
R7061
Q7065
HAT1128R01
SOI
HAT1128R01
SOI
5%
1/16W
MF-LF
2 402
PP3V42_G3H
7 8
7 8 21 22 26 40 42 43 44 45 46
50 61 62 64 69
CHGR_SGATE_DIV
R70701
C7070
5%
1/16W
MF-LF
402 2
U7070
SOT23-5
4
CHGR_SGATE
VOLTAGE=18.5V
R7074
5%
1/16W
MF-LF
2 402
CHGR_AMON
VCC
1M
1%
1/16W
MF-LF
402 2
10%
2 16V
X5R
402
TL331
PPDCIN_S5_INRUSH
57.6K
0.1uF
R70661
62K
330K
6 7
5%
1/16W
MF-LF
402 2
CRITICAL
CHGR_AGATE_DIV
1
1 2
10%
25V
X5R 2
402
0.1UF
5%
SOD-723-HF
1/16W
MF-LF
1
2 402
470K
1SS418
D7005
VOLTAGE=18.5V
46 62
R7075 clamps CHGR_AMON when charger is

not powered to counter TL331 bias current.
GND
3 D
SGATE_P0V1_VREF
Q7074
SSM6N15FEAPE
SOT563
R7071
6 D
Q7074
SSM6N15FEAPE
1.82K
1%
1/16W
MF-LF
402 2
SOT563
G 5
4 S
AMON_CLAMP
G 2
1 S
PP5V1_CHGR_VDD 62
D7040
1
(CHGR_DCIN)
R7021
10
1
1
R7001
R7022
96
94
56.2K
94
1%
1/16W
MF-LF
2 402
CHGR_VCOMP_R
C7015 1
ICOMP
VCOMP
VNEG
CSOP
CSON
C7050
0.1uF
10%
2 16V
X5R
402
0.001UF
OMIT
C7031
22UF
20%
2 25V
POLY-TANT
CASE-D2-SM
94
94
CHGR_BGATE
CHGR_DCIN
BOOT 25
UGATE 24
PHASE 23
CHGR_BOOT
CHGR_UGATE
CHGR_PHASE
CHGR_LGATE
TP_CHGR_TRKL
CHGR_AMON
CHGR_BMON
SMC_BC_ACOK
CRITICAL
4
1
RJK0305DPB
10%
2 25V
X5R
603-1
LFPAK-HF
0.1UF
3
1 2 3
DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
OUT
46
OUT
42 43 61
C7033
1UF
10%
2 25V
X5R
603-1
C7034
0.001UF
10%
2 50V
X7R
402
L7030
4.7UH-10.2A
2
FDA1254F-SM
46 62
1UF
CRITICAL
10%
2 25V
X5R
402
OUT
C7032
Q7030
C7035
PPVBAT_G3H_CHGR_REG
VOLTAGE=12.6V
CRITICAL
C7040 1
22UF
CRITICAL
Q7035
RJK0305DPB
DIDT=TRUE
20%
25V 2
POLY-TANT
CASE-D2-SM
CRITICAL
LFPAK-HF
R7050
2
4
1
3
PPVBAT_G3H_CHGR_R
VOLTAGE=12.6V
0.01uF
XW7000
SM
1
1%
1/16W
MF-LF
402 2
1UF
10%
25V
X5R 2
603-1
R7051
CHGR_VNEG_R
10
5%
1/16W
MF-LF
402
C7016
470PF
(CHGR_CSO_P)
(CHGR_CSO_N)
10%
50V
2 CERM
402
10%
16V
CERM 2
402
C7055 1
Max Current = 8.5A

(L7030 limit)
f = 400 kHz
96 46
0.001UF
CRITICAL
Q7055
SO-8
C7057 1
3.01K
C7041
10%
2 50V
X7R
402
SI7137DP
0.5%
1W
MF
0612-1
1 2 3
R70161
0.01
152S0542
10%
50V
CERM 2
402
20%
2 25V
POLY-TANT
CASE-D2-SM
0.1UF
CRITICAL
1
C7030
22UF
10%
2 25V
X5R
402
CHGR_AGATE
CHGR_CSI_P
CHGR_CSI_N
BGATE 16
DCIN 2
LGATE 21
(OD) TRKL* 13
20V/V AMON 9
32V/V BMON 15
(OD) ACOK 14
10%
25V 2
X5R
402
CRITICAL
1
C7021
CHGR_CSO_R_P
B
D
R7015
5
7
8
18
17
29
CHGR_ICOMP
CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P
CHGR_CSO_N
0.1UF
VOLTAGE=18.5V
PPVBAT_G3H_CONN 7
5
9.31K
THRM_PAD
R70111
4 VREF
3 ACIN
PPDCIN_S5_FET_CHGR
NC
CHGR_ACIN
ISL6258A
U7000
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
22 PGND
BI
26
6 AGND
IN
94 61 45 42 7
20
19
94 61 45 42 7
C7022 1
10%
10V 2
X5R
402-1
VDD
VDDP
12 VHST CRITICAL AGATE 1
11 SCL
CSIP 28
QFN
10 SDA
CSIN 27
VREF = 3.2V, < 300uA
1%
1/16W
MF-LF
402 2
C7001 1
1UF
Input impedance of ~40K meets

sparkitecture requirements
1%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
VOLTAGE=5.1V
10%
10V 2
X5R
402-1
30.1K
PP5V1_CHGR_VDDP
1206-2
1UF
Divider sets ACIN

threshold at 13.07V
R7010
8AMP-24V
0.5%
1W
MF
4 2 0612-1
CHGR_CSI_R_N
CRITICAL
F7040
0.02
C7002 1
ACIN pin threshold

is 3.2V, +/- 50mV
PP5V1_CHGR_VDD
VOLTAGE=5.1V
30mA max load
R7020
62
4.7
10
3 1
CHGR_CSI_R_P
VOLTAGE=12.6V
61
PP3V42_G3H
1SS418
45 44 43 42 40 26 22 21 8 7
69 64 62 61 50 46
10%
2 10V
CERM
402
7 8 37 46 61 64 65 66 67 79 83
86
CRITICAL
96
C7020
PPBUS_G3H
SOD-723-HF
5%
1/16W
MF-LF
402
0.047UF
TO SYSTEM
NOSTUFF
(CHGR_AGATE)
C7056
0.1UF
10%
2 16V
X5R
402
R7052
1
10
96
46
CHGR_CSO_R_N
5%
1/16W
MF-LF
402
(PPVBAT_G3H_CHGR_R)
C7042
C7000 1
0.033UF
1UF
10%
10V 2
X5R
402-1
10%
16V
2 X5R
402
C7011
C7005 1
0.01UF
0.1UF
10%
16V
2 CERM
402
C7026
0.001UF
10%
25V
X5R 2
402
10%
50V
2 CERM
402
GND_CHGR_AGND
VOLTAGE=0V
PBus Supply & Battery Charger
SYNC_MASTER=M99_MLB

PART NUMBER
DESCRIPTION
REFERENCE DES
CRITICAL
353S1811
QTY
1
IC,ISL6258,BAT CHARGER,28P,4X4,QFN,L
U7000
CRITICAL
BOM OPTION
ISL6258
2S Battery Default
353S1832
IC,ISL6258A,BAT CHARGER,4X4MM,QFN28
U7000
CRITICAL
ISL6258A
3S Battery Default
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
62
97
8
46 8
PPBUS_CPU_IMVP_ISNS
10
0.001UF
VOLTAGE=12.6V
C7196
10%
50V 2
X7R
402
0.1UF
10%
16V 2
X5R
402
PP5V_S0
1
VOLTAGE=5V
1%
1/16W
MF-LF
402
C7126
10
88 43 14 10
PM_DPRSLPVR
IN
CPU_PROCHOT_L
OUT
C7130
LAYOUT NOTE:
(IMVP6_NTC)
1
CRITICAL
C7110 1
470K
88 9
IN
88 9
IN
88 9
IN
88 9
IN
88 9
IN
88 9
IN
88 9
IN
88 14 10 9
IN
10
IN
R7197
10K
5%
1/16W
MF-LF
2 402
CCM
1-Phase
1-Phase
DCM
1-Phase
DCM
1
2
CCM
PPVCORE_S0_CPU
CRITICAL
DIDT=TRUE
L7100
7 8 11 12 46
44A MAX CURRENT
0.36UH-26A-1.05MOHM
(IMVP6_PHASE1)
2
MPCG1040-SM
XW7103
SM
C7135
6 7
CRITICAL
Q7101
5
XW7104
SM
IMVP6_VSUM1
63
C7156 1
0.001UF
10%
50V 2
X7R
402
IMVP6_VO1
63
IRF6795
DIRECTFET-MX
R7104
DIDT=TRUE
46
43
42
41
40
39
38
37
IMVP6_VID<6>
IMVP6_VID<5>
IMVP6_VID<4>
IMVP6_VID<3>
IMVP6_VID<2>
IMVP6_VID<1>
IMVP6_VID<0>
88
10%
16V
CERM 2
402
10%
2 25V
X5R
603-1
20%
16V 2
POLY-TANT
CASE-D2E-SM
0.01uF
402
2-Phase
20%
2 6.3V
X5R-CERM
402
22
VIN
spot of reg circuit.
R7126
4.7UF
10%
16V 2
X5R
402
R7198
5%
1/16W
MF-LF
402
Place R7126 in hot
20
0.1uF
5%
1/16W
MF-LF
2 402
0
0
1%
1/16W
MF-LF
402
CRITICAL
C7154
1UF
68UF
10%
50V 2
X7R
402
20%
16V 2
POLY-TANT
CASE-D2E-SM
C7153 1
0.001UF
68UF
DIDT=TRUE
68
R7119
CRITICAL
C7152 1
C7155 1
R7199
88 21
Mode
VOLTAGE=3.3V
499
Operation
PP3V3_S0_IMVP6_3V3
1%
1/16W
MF-LF
402
PPCPUVTT_S0
PSI*
10%
10V 2
X5R
402-1
10%
2 25V
X5R
603-1
20%
16V 2
POLY-TANT
CASE-D2E-SM
OUT
CPU_DPRSTP_L
IMVP_DPRSLPVR
CPU_PSI_L
IMVP6_IMON
46
45
2
3
TP_IMVP6_CLKEN_L
IMVP_VR_ON_R
VR_PWRGOOD_DELAY
IMVP6_VR_TT_L
IMVP6_NTC
48
47
44
1
5
6
VDD
31
PVCC
VID6
BOOT1
VID5
U7100 BOOT2
VID4
QFN
ISL9504BCRZ
67 25 24
12 11 10 9 8 7 6
22 20 18 17 14 13
PP3V3_S0
DPRSTP*
1UF
R7121
70
39
6
22
51
85
C7109
1UF
68UF
IRF6710
S1
DPRSLPVR
PP5V_S0_IMVP6_VDD
CRITICAL
1
C7117 1
Q7100
R7112
10
These caps are for Q7102
CRITICAL
C7108 1
PPVIN_S5_IMVP6_VIN
1%
1/16W
MF-LF
402
84 82 81 80 77
49 48 47 45 43
21 19 18 13 8 7
37 29 28 25 24
69 68 60 59 55
96
These caps are for Q7100
R7120
51 49 44 39 8 7
85 83 70 67 66
VID3
VID2
VID1
VID0
DPRSTP*
DPRSLPVR
36
26
63
63
UGATE1 35
63
IMVP6_UGATE1
PHASE1 34
63
IMVP6_PHASE1
LGATE1 32
63
IMVP6_LGATE1
PGND1 33
C7127
IMVP6_BOOT1
IMVP6_BOOT2
0.22UF
C7115
R7100
0.22UF
20%
25V 2
X5R
603
20%
2 25V
X5R
603
63
IMVP6_ISEN1
27
UGATE2
63
IMVP6_UGATE2
PHASE2 28
63
IMVP6_PHASE2
LGATE2 30
63
IMVP6_LGATE2
10K
5%
1/16W
MF-LF
2 402
0.22UF
1
1%
1/16W
MF-LF
402
10%
10V
CERM
402
R7101
3.65K
1%
1/10W
MF-LF
2 603
(GND)
ISEN1 24
C7103
(IMVP6_ISEN1)
PSI*
IMON
(PGD_IN)
(ISL9504A)
IMVP6_NTC_R
9
R71271
4.02K
1%
1/16W
MF-LF
402 2
R7108
C7105 1
OUT
63
IN
26
OUT
147K
0.015UF
CLK_EN*
VR_ON
PGND2 29
63
VR_TT*
23
ISEN2
63
(GND_IMVP6_SGND)
63
C7106
0.001UF
R7113
63
1K
63
10%
2 50V
CERM
402
1%
1/16W
MF-LF
402 2
IMVP6_VDIFF_RC
63
63
63
IMVP6_VSUM
IMVP6_OCSET
IMVP6_VO
IMVP6_DROOP
12
11
10
9
IMVP6_FB2
IMVP6_FB
IMVP6_COMP
IMVP6_VW
63
IMVP6_DFB
C7114
470PF
0.068UF
R71141
DIRECTFET-MX
R7107
1
R7105
1
97.6K
0.001UF
1%
1/16W
MF-LF
402 2
10%
50V
CERM 2
402
10%
6.3V
CERM-X5R 2
402
1%
1/16W
MF-LF
2 402
0.22UF
1
10%
10V
CERM
402
1%
1/10W
MF-LF
2 603
10KOHM-5%
0.22UF
6.81K
C7104
3.65K
R7131
C7128 1
R7110
5%
1/16W
MF-LF
2 402
R7106
CRITICAL
1
10K
1%
1/16W
MF-LF
402
IMVP6_VO_R
C7107 1
10%
50V 2
X7R
402
IMVP6_VO2
63
1%
1/16W
MF-LF
402 2
(IMVP6_VW)
C7157 1
0.001UF
IRF6795
DIDT=TRUE
IMVP6_COMP_RC
IMVP6_VSUM2
63
2.61K
1%
1/16W
MF-LF
2 402
10%
50V
X7R-CERM 2
402
R7130
11K
10%
10V
2 CERM
402
XW7102
SM
R7115
C7134
CRITICAL
Q7103
3
6 7
(IMVP6_VO)
220PF
10%
2 50V
CERM
402
XW7101
SM
1
1%
1/16W
MF-LF
2 402
5%
2 50V
CERM
402
2
MPCG1040-SM
13.3K
49
C7113 1
(IMVP6_PHASE2)
R7116
180pF
1%
1/16W
MF-LF
2 402
L7101
0.36UH-26A-1.05MOHM
C7129
GND_IMVP6_SGND
(IMVP6_FB)
1K
VOLTAGE=0V
CRITICAL
DIDT=TRUE
R7118
TPAD
21
DIDT=TRUE
10%
50V
CERM 2
402
10%
16V
CERM 2
402
GND
1%
1/16W
MF-LF
2 402
C7116 1
0.001uF
4.42K2
0.01UF
1K
OUT
63
NO STUFF
C7131 1
VW
R7109
255
1%
1/16W
MF-LF
402 2
63
1%
1/16W
MF-LF
402
R7111
OUT
R7117
15
RTN
COMP
2
5
VSEN 14
FB
FB2
25 NC
1
Q7102
IRF6710
13 VDIFF
IMVP6_VDIFF
DFB 17
CRITICAL
IMVP6_ISEN2
S1
19
8
OCSET
VO 18
16
DROOP
VSUM
4 RBIAS
IMVP6_RBIAS
63
NTC
7 SOFT
IMVP6_SOFT
(GND)
PGOOD
(GND_IMVP6_SGND)
1%
1/16W
MF-LF
2 402
10%
16V 2
X7R
402
3V3
0603-LF
(IMVP6_ISEN2)
(IMVP6_VSUM)
(IMVP6_COMP)
Place R7131 Between L7100,L7101 and CPU
(IMVP6_VO)
R7122
88 63
88 63
R7160
42
63
IMVP_VR_ON
IMVP6_OCSET
5%
1/16W
MF-LF
402
IMVP_VR_ON_R
XW7100
SM
63
C7121 1
C7133 1
0.22UF
0.01uF
20%
6.3V 2
X5R
402
10%
16V
CERM 2
402
IMVP6_VSEN_P
IMVP6_VSEN_N
NO STUFF
C7132
0.01uF
5%
1/16W
MF-LF
402
CPU_VCCSENSE_P
IN
11 88
CPU_VCCSENSE_N
IN
11 88
R7123
0
5%
1/16W
MF-LF
402
10%
2 16V
CERM
402
IMVP6 CPU VCore Regulator
SYNC_MASTER=M87_MLB

63
63
63
63
63
63
63
63
63
63
IMVP6_VO
IMVP6_DROOP
IMVP6_DFB
IMVP6_SOFT
IMVP6_RBIAS
IMVP6_VDIFF
IMVP6_FB2
IMVP6_FB
IMVP6_COMP
IMVP6_VW
MIN_LINE_WIDTH=0.25
MIN_LINE_WIDTH=0.25
MIN_LINE_WIDTH=0.25
MIN_LINE_WIDTH=0.25
MIN_LINE_WIDTH=0.25
MIN_LINE_WIDTH=0.25
MIN_LINE_WIDTH=0.25
MIN_LINE_WIDTH=0.25
MIN_LINE_WIDTH=0.25
MIN_LINE_WIDTH=0.25
MM
MM
MM
MM
MM
MM
MM
MM
MM
MM
MIN_NECK_WIDTH=0.20
MIN_NECK_WIDTH=0.20
MIN_NECK_WIDTH=0.20
MIN_NECK_WIDTH=0.20
MIN_NECK_WIDTH=0.20
MIN_NECK_WIDTH=0.20
MIN_NECK_WIDTH=0.20
MIN_NECK_WIDTH=0.20
MIN_NECK_WIDTH=0.20
MIN_NECK_WIDTH=0.20
MM
MM
MM
MM
MM
MM
MM
MM
MM
MM

63
63
63
63
63
63
63
88 63
IMVP6_PHASE1
IMVP6_BOOT1
IMVP6_UGATE1
IMVP6_LGATE1
IMVP6_ISEN1
IMVP6_VSUM1
IMVP6_VO1
IMVP6_VSEN_P
63
63
63
63
63
63
63
I849
88 63
IMVP6_PHASE2
IMVP6_BOOT2
IMVP6_UGATE2
IMVP6_LGATE2
IMVP6_ISEN2
IMVP6_VSUM2
IMVP6_VO2
IMVP6_VSEN_N

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
I848
REV.
051-7892
A.0.0
OF
63
97
D
69 42 7
SMC_PM_G2_EN
R7273
100K
5%
1/16W
MF-LF
2 402
PPBUS_G3H
79 67 66 65 62 61 46 37 8 7
86 83
CRITICAL
CRITICAL
C7240 1
P5VP3V3_VREG5
C7241
1UF
22UF
10%
2 25V
X5R
603-1
20%
25V 2
POLY-TANT
CASE-D2-SM
5
1
CRITICAL
Q7220
f=365KHz
55 53 51 43 41 40 39 31 9 8 7
79 70 65
PP5V_S3
5%
1/16W
MF-LF
402
10%
25V 2
X5R
603-1
10%
2 50V
X7R
603-1
VIN
14 SKIPSEL
PWRFLAT-SM
Vout = 5.0V
4 TONSEL
L7220
(Q7220 limit)
C7252 1
5
3 2 1
2
4.7UH-13A-15MOHM
CRITICAL
PCMB104E4R7-SM
C7250 1
NO STUFF1
R7222
10UF
330UF
20%
10V 2
X5R
805
20%
6.3V 2
POLY-TANT
CASE-D3L-SM1
1
10
5%
1/16W
MF-LF
402 2
CRITICAL
0.001UF
10%
50V
2 CERM
402
XW7220
SM
5%
50V
CERM 2
402
20%
25V 2
POLY-TANT
CASE-D2-SM
U7201
QFN
VREG5 17
DRVH2 10
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
DIDT=TRUE
P3V3S5_LL
DIDT=TRUE
P3V3S5_DRVL
GATE_NODE=TRUE
VO2 7
1 ENTRIP1
CRITICAL
Q7260
FDMS9600S
DIDT=TRUE
mm
mm
mm
mm
mm
mm
mm
mm
L7260
ENTRIP2 6
1%
1/16W
MF-LF
2 402
Q2
C7208
220PF
5%
2 25V
CERM
402
PLACEMENT_NOTE=Place XW7220 next to L7220.
P5V_S5_REG_XW
5%
1/16W
MF-LF
402 2
PLACEMENT_NOTE=Place XW7200 next to U7200 pin 15.
C7292
150UF-.025-OHM
C7290
P3V3S5_RC
20%
2 6.3V
TANT
CASE-B2-SM
10UF
20%
6.3V 2
X5R
603
NO STUFF1
5 C7262
100PF
5%
50V
CERM 2
402
NO STUFF
CRITICAL
1
10
7 6
(L7260 limit)
2
IHLP2525CZ
R7262
P3V3S5_ENTRIP
EN0 13
5V3V3_REG_EN
GND THRM_PAD
86.6K
NO STUFF1
PGOOD 23
R7200
10
SW
5.5A max output
4.7UH-5.5A
S
3 2 1
Vout = 3.3V
Q1
P3V3S5_VFB
68 69 70
30 34 37
7 8 18 20
22 24 26
38 44 54
82 87 96
PP3V3_S5
(P3V3S5_V02)
VFB2 5
f=460KHz
9 4 3 2
CRITICAL
VCLK 18
PWRFLAT-SM
402
P3V3S5_DRVH
DIDT=TRUE
P5VS5_ENTRIP
10%
25V
2 X5R
603-1
MLP
SWITCH_NODE=TRUE
2 VFB1
10%
50V 2
X7R
603-1
10%
10V
CERM
402
DRVL2 12
P5VS5_VFB
1UF
P3V3S5_VBST
DIDT=TRUE
24 VO1
0.1UF
0.22UF
LL2 11
19 DRVL1
10%
50V
C7281CERM
C7264 1
20%
2 6.3V
X5R
603
C7201
VBST2 9
C7205
10UF
20%
6.3V 2
X5R
603
GATE_NODE=TRUE
P5VS5_DRVL
VREG3 8
20 LL1
GATE_NODE=TRUE
VREF
DIDT=TRUE
P5VS5_LL
SWITCH_NODE=TRUE
TPS51125
21 DRVH1
P5VS5_DRVH
GATE_NODE=TRUE
(P5VS5_VO1)
Q7225
STL15N3LLH5
P5VS5_RC
NO STUFF1
C7222
100PF
C7251
22 VBST1
P5VS5_VBST
CRITICAL
10.5A max output
10UF
1UF
15
STL11NH3LL
C7203 1
C7200 1
C7224
0.1UF
0.001UF
22UF
P3V3S5_VBST_R
P5VP3V3_VREF
R7224
0
2
P5VS5_VBST_R
5%
1/16W
MF-LF
402
P5VP3V3_VREG3
10%
50V
CERM 2
402
25
0.001UF
16
C7243
C7282 1
C7280 1
R7264
C7291
0.001UF
10%
2 50V
CERM
402
XW7260
SM
R7206
75K
1%
1/16W
MF-LF
2 402
PLACEMENT_NOTE=Place XW7260 next to L7260.
P3V3_S5_REG_XW
PATH=I621
PATH=I623
R7260
XW7200
SM
R7220
15K
GND_P5VP3V3_SGND
5%
1/16W
MF-LF
2 402
6.49K
1%
1/16W
MF-LF
2 402
VOLTAGE=0V
R7261
R7221
10K
One master PGOOD for both 5V and 3V3
10K
1%
1/16W
MF-LF
2 402
69 68 67 66
OUT
1%
1/16W
MF-LF
2 402
S0_PWR_PGOOD
Q7210
D 6
SSM6N15FEAPE
SOT563
45 44 43 42 40 26 22 21 8 7
69 62 61 50 46
PP3V42_G3H
2 G
S 1
Q7211
R7210
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
ALL
Cyntec alternate to MagLayers
SOT563
5%
1/16W
MF-LF
2 402
TABLE_ALT_HEAD
PART NUMBER
D 3
SSM6N15FEAPE
10K
5 G
P5VS3_EN_L
S 4
TABLE_ALT_ITEM
152S0778 152S0693
Q7210
D 3
SSM6N15FEAPE
SOT563
69
5 G
69
P3V3S5_EN_L
M99
1.
2.
3.
4.
S 4
P5VS3_EN
differences from last sync on 11/01/07 to M88 MLB:

L7260 changed from M88 MLB inductors to 152S0693.
Q7220 changed to 372S0512. Q7225 changed to 376S0511.
U7200 changed to 353S2087.
Added R7200, R7220,R7221, R7260,R7261, C7201.
5V / 3.3V Power Supply
SYNC_MASTER=PWRSQNC

.
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
64
97
70 65 30 29 28 8 7
PP1V8R1V5_S3
C7355
86 83 79 67
46 37 8 7
66 64 62 61
PPBUS_G3H
10UF
20%
2 6.3V
X5R
603
55 53 51 43 41 40 39 31 9 8 7
79 70 64
CRITICAL
4.7
PP5V_S3_DDRREG_V5FILT
C7331 1
20%
25V
POLY-TANT 2
CASE-D2-SM
20%
25V
POLY-TANT 2
CASE-D2-SM
22UF
R7305
PP5V_S3
CRITICAL
C7330 1
22UF
C7332
1UF
10%
2 25V
X5R
603-1
C7333
0.001UF
10%
2 50V
X7R
402
VOLTAGE=5V
5%
1/16W
MF-LF
402
ISNS_1V5_S3_P
OUT
53 96
ISNS_1V5_S3_N
OUT
53 96
CRITICAL
V5IN
V5FILT
70 29 28 8 7
VBST 22
U7300
TPS51116
PPVTTDDR_S3
10mA max load
Vout
XW7360
SM
1
CRITICAL
C7360
22UF
20%
6.3V
X5R-CERM 2
603
LL 20
= VTTREF
C7361
22UF
DDRREG_VBST
DRVL 19
(DDRREG_VBST)
DDRREG_DRVH
GATE_NODE=TRUE
DDRREG_LL
SWITCH_NODE=TRUE
DDRREG_DRVL
GATE_NODE=TRUE
DIDT=TRUE
2 VTTSNS
CS 16
VDDQSET 9
VTTGND
THRM_PAD GND
CRITICAL
2 3
VOLTAGE=1.5V
L7330
1.0UH-13A-5.6MOHM
2
5
CRITICAL
(DDRREG_LL)
Q7335
(DDRREG_DRVL)
SI7108DN
PWRPK-1212-8-HF
S
DDRREG_CS
DDRREG_FB
PLACEMENT_NOTE=Place next to Q7335
(DDRREG_CSGND)
PP1V8R1V5_S3
7 8 28 29 30 65 70
Vout = 1.5V
15A max output
(Q7335 limit)
f = 400 kHz
270UF
20%
2 2V
TANT
CASE-B4-SM
CRITICAL
C7345
C7341 1
20%
2V 2
TANT
CASE-B4-SM
20%
2 6.3V
X5R
603
10UF
C7346
0.001UF
XW7345
SM
10%
50V
2 X7R
402
NO STUFF
C7320 1
100PF
5%
50V
CERM 2
402
(DDRREG_VDDQSNS)
(DDRREG_FB)
XW7300
SM
10%
16V 2
X5R
402
XW7330
SM
PLACEMENT_NOTE=Place next to C7345
XW7335
SM
C7350 1
XW7332
SM
PGND CS_GND
DDRREG_CSGND
0.033UF
XW7331
SM
C7340
270UF
CRITICAL
1
PPDDR_S3_REG_R
1
2
PCMB065T-SM
10%
50V
X7R
603-1
1 2
7 NC0
12 NC1
20%
2 6.3V
X5R-CERM
603
PWRPK-1212-8-HF
C7325
DIDT=TRUE
NC
NC
SI7110DN
DIDT=TRUE
SYM (2 OF 2)
24 VTT
DDRREG_VTTSNS
CRITICAL
QFN
5 VTTREF
Vout = VDDQSNS/2
MIN_LINE_WIDTH=2 mm
DRVH 21
18
27 8
Q7330
0.1UF
IN
OUT
10K
1%
1/16W
MF-LF
402 2
MODE 4
10 S3
VTT Enable
11 S5
VDDQ/VTTREF Enable
13 PGOOD VDDQ PGOOD
25
69
69
MEM_VTT_EN
DDRREG_EN
TP_DDRREG_PGOOD
IN
R73101
VDDQSNS 8
CRITICAL
70 26 9
(DDRREG_DRVH)
VLDOIN
6 COMP
DDRREG_VDDQSNS
23
1UF
10%
10V 2
X5R
402-1
17
C7305
20%
6.3V 2
CERM
603
14
4.7UF
1
15
C7300
Vout = 0.75V * (1 + Ra / Rb)
R7320
15.0K
1%
1/16W
MF-LF
2 402
<Ra>
R7321
15.0K
1%
1/16W
MF-LF
2 402
<Rb>
GND_DDRREG_SGND
VOLTAGE=0V
1.5V DDR3 Supply

SYNC_MASTER=DDR

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
65
97
79 67 65 64 62 61 46 37 8 7
86 83
5V_S0_MCPREG_VIN
2.2
VOLTAGE=5V
1UF
R7561
1K
5%
1/16W
MF-LF
2 402
R7590
21
21
IN
IN
MCP_VID<0>
5%
1/16W
MF-LF
402
MCP_VID<1>
R7591
IN
MCP_VID<2>
VDD
MCPCORES0_RBIAS
1 RBIAS
MCPCORES0_SOFT
2 SOFT
MCPCORES0_IMON_R
68
64
67
69
5%
1/16W
MF-LF
402
S0_PWR_PGOOD
MCP_VID0_R
MCP_VID1_R
MCP_VID2_R
MCPCORES0_OS0
MCPCORES0_OS1
MCPCORES0_EN
IN
MCPCORES0_FDE
R7580 R7581
20.0K
1%
1/16W
MF-LF
2 402
20.0K
69
1%
1/16W
MF-LF
2 402
MCPCORES0_VSEN
MCPCORES0_RTN
MCPCORES0_VW
PGOOD
VID0
VID1
VID2
OFFSET0
OFFSET1
VR_ON
AF_EN
FDE
VSEN
RTN
Q7560
FDMC8676
POWER33-SM
GATE_NODE=TRUE
DIDT=TRUE
VIN 14
UGATE 18
R7565
MCPCORES0_UGATE 1
C7564
0.22UF
1
2
MCPCORES0_BOOT_R
5%
1/10W
BOOT 17 MCPCORES0_BOOT
0.2 MM MF-LF
0.25 MM 603
19
PHASE
MCPCORES0_PHASE
0.25 MM
0.2 MM
CRITICAL
1 2 3
HAHF651R0AP-SM
R7589
(Q7560 Limit)
PPVCORE_S0_MCP_REG 7
1
3
10UF
20%
4V
X5R 2
603
NO STUFF
1
C7589
0.001UF
C7567
10UF
10%
50V 2
X7R
402
4 VW
f = 300 kHz
CRITICAL
1
MICROFET3X3
20%
2 4V
X5R
603
VO 12
MCPCORES0_COMP
5 COMP
MCPCORES0_FB
6 FB
MCPCORES0_VDIFF
PGND
1
R7563
C7576 1
100
XW7562
SM
66 46 24 22 8 7
1
2
PPVCORE_S0_MCP_REG
OMIT
PLACE XW NEAR THE MCP,

CONNECT SENSE LINES TO CLOSEST
MCPCORE AND GND BALL
OF MCP
XW7563
SM
1
R7566
20
1
MCPCORES0_RSEN_P
1%
1/16W
MF-LF
402
OMIT
1%
1/16W
MF-LF
402
0.1UF
10%
16V
X7R-CERM 2
402
MCPCORES0_OCSET
MCPCORES0_ISP
MCPCORES0_ISN
ICOMP 10
MCPCORES0_ICOMP
R7572
R7573
10K C7573 1
1%
1/16W
MF-LF
2 402
47PF
5%
50V
CERM 2
402
R7500
1%
1/16W
MF-LF
2 402
100
MCPCORES0_ISP_R
1%
1/16W
MF-LF
402
XW7561
SM
1
(MCPCORES0_ISN)
2
1
R7575
GND_MCPCORES0_AGND
47.0K
VOLTAGE=0V
1%
1/16W
MF-LF
2 402
R7571
100
C7575
47PF
5%
2 50V
CERM
402
(MCPCORES0_ICOMP)
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402
150K
C7570
10%
50V
2 X7R
402
(MCPCORES0_RTN)
11.3K2
THRM_PAD
0.001UF
R7568
20
1
MCPCORES0_RSEN_N
1%
1/16W
MF-LF
2 402
(MCPCORES0_VSEN)
VSS
C7569
10%
2 50V
X7R
402
(MCPCORES0_VO)
R7569
33
PPVCORE_S0_MCP_REG
20
66 46 24 22 8 7
MCPCORES0_VO
ISP 13
ISN 11
7 VDIFF
20%
2 2V
TANT
CASE-B4-SM
0.001UF
OCSET 3
15
1%
1/16W
MF-LF
2 402
C7568
270UF
20%
2 2V
TANT
CASE-B4-SM
20.0K
270UF
R7582 1R7583
1%
1/16W
MF-LF
2 402
CRITICAL
C7565
20.0K
8 22 24 46 66
C7566 1
MCPCORE_SNUBBER
FDMC8678S
G
S
GATE_NODE=TRUE
DIDT=TRUE
2
4
5%
1/10W
MF-LF
2 603
CRITICAL
Q7565
PPMCPCORE_S0_R
VOLTAGE=1V
MCPCORES0_LGATE
1%
1W
MF-1
0612
1.0UH-17A-5M-OHM
NO STUFF
MAX CURRENT: 15.5A
0.001
L7560
CERM-X7R
10V
603
5%
(MCPCORES0_PHASE)
SWITCHNODE
(MCPCORES0_LGATE)4
R7525
CRITICAL
SWITCH_NODE=TRUE
DIDT=TRUE
LGATE 21
10%
2 25V
X5R
603-1
20%
16V 2
POLY-TANT
CASE-D2E-SM
CRITICAL
D
G
(MCPCORES0_UGATE)
QFN
C7561
1UF
68UF
10%
2 16V
X5R
402
U7500
28 IMON
31
25
26
27
23
24
29
30
32
8
9
OUT
1NOSTUFF 1NOSTUFF
10%
50V
X7R 2
402
C7560 1
0.001UF
20%
16V 2
POLY-TANT
CASE-D2E-SM
C7562
PVCC
5%
1/16W
MF-LF
402
R7592
21
C7563 1
68UF
1UF
10%
16V 2
X5R
402
22
5%
1/16W
MF-LF
402
ISL6263D
MCPCORES0_IMON
C7550 1
16
47
CRITICAL
C7540 1
7 8 39 44 49 51
63 67 70 83 85
5%
1/10W
MF-LF
603
R7593
1
CRITICAL
PP5V_S0
PPBUS_G3H
R7560
B
(MCPCORES0_VW)
C7579 1
C7580
0.001UF
10%
50V 2
X7R
402
68PF
1
R7576
6.98K
5%
50V
CERM
402-1
C7581
R7577
1
560PF
133K 2 MCPCORES0_COMP_C
1
2
1%
1/16W
MF-LF
2 402
(MCPCORES0_COMP)
1%
1/16W
MF-LF
402
10%
50V
CERM
402
R7578
1
100
1%
1/16W
MF-LF
402
(MCPCORES0_FB)
C7582
VID<2:0>
560PF
1
2
MCPCORES0_VDIF_C
R7579
2.21K2
1
1%
1/16W
MF-LF
402
10%
50V
CERM
402
(MCPCORES0_VDIFF)
VOLTAGE
000
1.05V
001
1.00V
010
0.95V
011
0.90V
100
101
MCP CORE REGULATOR

SYNC_MASTER=M98_MLB
0.85V
0.80V
110
0.75V
111
0.70V

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
66
97
79 66 65 64 62 61 46 37 8 7
86 83
PPBUS_G3H
CRITICAL
C7690 1
C7695
1UF
22UF
10%
2 25V
X5R
603-1
20%
25V
POLY-TANT 2
CASE-D2-SM
CRITICAL
Q7660
FDMS9600S
83 70 66 63 51 49 44 39 8 7
85
9 4 3 2
MLP
PP5V_S0
1
1%
1/16W
MF-LF
402
VOLTAGE=5V
2.2UF
V5FILT
10%
16V 2
X5R
603
69
69 68 66 64
CPUVTTS0_EN
IN
S0_PWR_PGOOD
OUT
(=PPCPUVTT_S0_REG)
R7679
1
10%
2 10V
X5R
402-1
U7600
TPS51117RGY_QFN14
SYM (2 OF 2)
QFN
1 EN_PSV
CPUVTTS0_TON
TON 2
6 PGOOD
VBST 14
3 VOUT
DRVH 13
5 VFB
THRM_PAD
PGND
10%
50V 2
X7R
603-1
1
3
PPCPUVTT_S0
2
4
C7665
96 47
2
7 6 5
XW7665
SM
96 47
8A max output
10UF
Q2
6 7 8 9 10 11 12 13 14 17 18 20
22 24 25 63
Vout = 1.052V
20%
6.3V
2 X5R
603
(Q7660 limit?)
f = 360 kHz
CPUVTT_ISNS_P
CRITICAL
C7660 1
CPUVTT_ISNS_N
330UF
20%
2.0V 2
POLY-TANT
B2-SM
1
PLACEMENT_NOTE=Place XW7665 next to L7660
CPUVTTS0_VSNS
NO STUFF
1
R7670
8.06K
R7685
1%
1/16W
MF-LF
2 402
8.87K
XW7600
SM
1
VOLTAGE=1.05V
DIDT=TRUE
1%
1/16W
MF-LF
2 402
PPCPUFSB_ISNS
2
PCMB065T-SM
0.1UF
CPUVTTS0_LL
SWITCH_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6MM
CPUVTTS0_DRVL MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6MM
DRVL 9
GND
10
SW
CPUVTTS0_DRVH
LL 12
11 TRIP
15
CPUVTTS0_TRIP
C7680 1
CPUVTTS0_VBST
GATE_NODE=TRUE
CPUVTTS0_VFB
1%
1/16W
MF-LF
402 2
1UF
V5DRV
CRITICAL
Q1
226K
C7600
1%
1W
MF
0612
2.2UH-8.0A
C7601 1
0.002
L7660
PP5V_S0_CPUVTTS0_V5FILT
10
200
R7660
CRITICAL
R7601
C7670 1
100PF
5%
50V
CERM 2
402
<Ra>
(GND)
1
R7671
20.0K
1%
1/16W
MF-LF
2 402
<Rb>
GND_CPUVTTS0_SGND
VOLTAGE=0V
Vout = 0.75V * (1 + Ra / Rb)
(CPUVTTS0_VFB)
(=PPCPUVTT_S0_REG)
CPU VTT / 1V05 S0 Power Supply
SYNC_MASTER=M99_MLB

M99 differences from last sync on 12/03/07 to T18 MLB:

1. Tied THERMAL_PAD to PGND. GND and THERMAL_PAD disconnected.

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
67
97
1.05V S0 PLL LDO

84 82 81 80 77 70 69 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85
R7743
PP3V3_S0
100
PP3V3_S0_MCP_PLL_VLDO_BIAS
5%
1/16W
MF-LF
402
C7740 1
1UF
VOUT = 0.8V * (1 + RA / RB)

4
10%
6.3V 2
CERM
402
CRITICAL
BIAS
PP1V8R1V5_S0_FET
1
2
69 39 29 28 24 16 12 11 8 7
70
IN0
IN1
OUT0
OUT1
9
10
<Ra>
TPS74701
5
10%
6.3V 2
CERM
402
P1V05S0_LDO_SS
NOSTUFF
C7743
0.0022UF
10%
50V
CERM 2
402
SON
EN
FB
R7744
1.37K
U7740
7
SS
PG
1%
1/16W
MF-LF
2 402
P1V05S0_LDO_FB
GND THRML_PAD
C7742
Vout = 1.05V
MAX CURRENT = 0.5A
4.7UF
20%
4V
402
2 X5R
<Rb>
1
R7745
4.42K
11
1UF
C7741 1
7 8 24
1%
1/16W
MF-LF
2 402
R7746
P1V05S0_PGOOD
S0_PWR_PGOOD
64 66 67 69
5%
1/16W
MF-LF
402
MCP 1.05V S5 (AUXC) SUPPLY

CRITICAL
1
37 34 30 26 24 22 20 18 8 7
96 87 82 70 69 64 54 44 38
C7750
22UF
PP3V3_S5
2
20%
6.3V
CERM
805
1
VIN
CRITICAL
L7770
U7750
2.2UH-3.25A
ISL8009B
IHLP1616BZ-SM
DFN
69
IN
PM_G2_P1V05S5_EN
2 EN
CRITICAL
LX 8
1V05S5_SW1
DIDT=TRUE
69
3 POR
P1V05_S5_PGOOD
VFB 6
4 SKIP
GND
7
1V05S5_FB
C7776 1
5%
50V
CERM 2
402
255K
1%
1/16W
MF-LF
402
<Rb>
1
R7781
7 8 22 24 34
Vout = 1.053V
R7780
47PF
RSI 5
THRM_PAD
9
PP1V2R1V05_S5
<Ra>
1
CRITICAL
MAX CURRENT = 0.8A
C7771
FREQ = 1.6MHZ
22UF
20%
6.3V
CERM
805
806K
2
1%
1/16W
MF-LF
402
VOUT = 0.8V * (1 + RA / RB)

Misc Power Supplies
SYNC_MASTER=M99_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
68
97
State
SMC_PM_G2_ENABLE
PM_SLP_S4_L
PM_SLP_S3_L
Run (S0)
Sleep (S3)
Soft-Off (S5)
Battery Off (G3Hot)
3.3V 1,05V S5 ENABLE
100K 1
2
PP3V42_G3H
P3V3S5_EN_L
5%
1/16W
MF-LF
402
Q7800
10%
10V
2 CERM
402
D 3
SOD-VESM-HF
R7810
100K
R7811
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=near U7201
S5 rail PWRGD
69 64
PP3V42_G3H
PP3V3_S5
7
1 G
100K
37 34 30 26 24 22 20 18 8
96 87 82 70 69 68 64 54 44 38
S 2
5%
1/16W
MF-LF
402 2
C7840
5.1K 1
69 65
0.1uF
R7801
2
69 68
PM_G2_P1V05S5_EN
PM_G2_P1V05S5_EN
68
OUT
MAKE_BASE=TRUE
R7840
69
C7801
5 SENSE
10%
6.3V
2 CERM-X5R
402
C7810
0.47UF
5%
1/16W
MF-LF
2 402
VDD
0.47UF
100K
10%
2 6.3V
CERM-X5R
402
P5VS3_EN
OUT
64 69
DDRREG_EN
OUT
65 69
C7812
0.47UF
10%
2 6.3V
CERM-X5R
402
U7840RESET*
DDRREG_EN
MAKE_BASE=TRUE
NO STUFF
20%
10V
CERM 2
402
5%
1/16W
MF-LF
402
P5VS3_EN
MAKE_BASE=TRUE
45 44 43 42 40 26 22 21 8 7
69 64 62 61 50 46
R78581
7 21 40 42 43 69 70
R7812
5.1K
5%
1/16W
MF-LF
402 2
SMC_PM_G2_EN
PM_SLP_S4_L
OUT
MAKE_BASE=TRUE
RSMRST_PWRGD 42
TPS3808G33DBVRG4
CT
C7841
SOT23-6
4 CT
P1V05_S5_PGOOD 68
MR* 3
GND
1
TPS3808 MR* HAS INTERNAL PULLUP
IN
C7802
(PM_S4_STATE_L)
PM_SLP_S4_L
IN
0.068UF
SSM3K15FV
64 42 7
70 69 43 42 40 21 7
64
OUT
NO STUFF
1
3.3V,5V S3 ENABLE
R7802
61 50 46 45
26 22 21 8 7
44 43 42 40
69 64 62
0.001UF
20%
50V
CERM 2
402
Other S0 RAILS
PM_ALL_GFX_PGOOD
S0 ENABLE
IG
high
EG
PM_ALL_GPU_PGOOD
PP3V3_S0
PM_SLP_S3_L_R
(PM_SLP_S3_L)
81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84 82
46 69 70
MAKE_BASE=TRUE
R7878
IN
5%
1/16W
MF-LF
402
22K
5%
1/16W
MF-LF
402
33K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
46 69 70
5%
1/16W
MF-LF
402 2
69 68 67 66 64
PLACEMENT_NOTE=nearU7700
100K
5%
1/16W
MF-LF
402 2
70 69
P3V3S0_EN
P3V3S0_EN
OUT
69 70
P1V2R1V8S0_EN
OUT
69 87
MCPDDR_EN
OUT
69 70
MAKE_BASE=TRUE
87 69
P1V2R1V8S0_EN
MAKE_BASE=TRUE
70 69
MCPDDR_EN
MAKE_BASE=TRUE
69 67
CPUVTTS0_EN
CPUVTTS0_EN
OUT
67 69
MCPCORES0_EN
OUT
66 69
MAKE_BASE=TRUE
69 66
MCPCORES0_EN
MAKE_BASE=TRUE
Unused PGOOD signal
TP_DDRREG_PGOOD
MAKE_BASE=TRUE
0.47UF
0.47UF
EG_PWRSEQ_HW
EG_PWRSEQ_HW
10K
5%
1/16W
100K 2
5%
1/16W
MF-LF
402
Q7850
D 3
SSM6N15FEAPE
R7852
81 79 77 76 70 69 8 6
P1V1_GPU_EN
P1V1_GPU_EN
OUT
69 83 84
79
5%
1/16W
MF-LF
402 2
0
1
PM_ALL_GPU_PGOOD
ALL_GFX_PGOOD_R1
C7884
5% 2
MF-LF
1/16W
402
OUT
26 42
place XW0402 if needed to save trace space for pin 7,8
5% 2 MAKE_BASE=TRUE
1/16W
MF-LF
402
PP3V3_S0
P1V8_S0GPU_EN
OUT
69 70 83 84
81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84 82
C7870 1
0.1uF
APN: 353S2310
G96 GPU requires rails to come
EG_PWRSEQ_HW
NO STUFF
C7850
NO STUFF
D 3
Q7861
C7869 1
SSM6N15FEAPE
20%
16V
CERM
402
0.022UF
SOT563
GPU_S0_EN_L
20%
10V
CERM 2
402
20%
16V
CERM 2
402
5 G
GPU_S0_EN_L
5 TC7SZ08AFEAPE
SOT665
4
ALL_SYS_PWRGD
U7880Y
5%
1/16W
MF-LF
402
up in the following order:

1) 1.1V
VDD
2) GPU_3.3V
U7870
3) GPUVcore
S 4
ISL88042IRTEZ
4) GDDR3 1.8V
TDFN
BOMOPTION: EG
68 39 29 28 24 16 12 11 8 7
70
69
PP1V8R1V5_S0_FET
MAKE_BASE=TRUE
S 1
3 V2MON
5 V3MON
6 V4MON
GND
4
2 G
NO STUFF
69
100K
S0_PWR_PGOOD
MAKE_BASE=TRUE
0.47UF
SOT563
R7853
69
68
67
66
64
S0_PWR_PGOOD
10%
2 6.3V
CERM-X5R
402
GPUVCORE_PGOOD
0.022UF
S 4
EG_PWRSEQ_HW
Q7850 D 6
EXTGPU_PWR_EN
SSM6N15FEAPE
1
IN
84 83 69 9
EG_PWRSEQ_HW
R7869
P1V8_S0GPU_EN_RC 0 P1V8_S0GPU_EN
R7868
100K
1
MAKE_BASE=TRUE
1
PP3V3_S0GPU
84 83 69
SOT563
5 G
IN
69 68 67 66 64
EG_PWRSEQ_HW
5%
1/16W
MF-LF
402
EG_PWRSEQ_HW
0.1UF
20%
2 10V
CERM
402
5%
1/16W
MF-LF 2
402
EG_PWRSEQ_HW
INS0_PWR_PGOOD
C7889
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT
R7850 MF-LF
402
PP3V3_S5
69 68 67 66 64
Graphic MEM ENABLE
P1V1_GPU_EN_RC
R78941
0
1.1V GPU ENABLE
70 69 68 64 54 44
26 24 22 20 18 8 7
38 37 34 30
96 87 82
84
C7883
10%
6.3V
2 CERM-X5R
402
R7851
PP3V3_S0
S0_PWR_PGOOD
PLACEMENT_NOTE=nearQ7971
82 81 80 77 70 69
55 51 49 48
37 29 28 25
18 13 8 7 6
24 22 21 19
47 45 43 39
68 63 60 59
96 85 84
IN
NO STUFF
0.47UF
10%
10%
10%
6.3V
6.3V
2 6.3V
CERM-X5R 2 CERM-X5R 2 CERM-X5R
402
402
402
65 69
IN
69 68 67 66 64
7 8 18 20 22 24 26 30 34 37 38
44 54 64 68 69 70 82 87 96
2
7
TP_DDRREG_PGOOD
69 65
C7880 C7881 C7882

1
0.47UF
69 68 67 66 64
S0_PWR_PGOOD
R7891
NO STUFF
1
PP3V3_S5
S0_PWR_PGOOD
R78791
PM_SLP_S3_L_R
OUT
R78921
10K
5%
1/16W
MF-LF
402
46 69 70
R7884
10K
5%
1/16W
MF-LF
402
PM_SLP_S3_L_R
OUT
1
87 84 70 55 25 18 8 7
MR*
RST*
NC
S0_PWR_PGOOD
64 66 67 68 69
THRM_PAD
9
84 82 42 37 34 21 7
PM_SLP_S3_L1 100
R78802 R78812 R7882 2 R7883
PP1V8_S0
GPUVCORE ENABLE
1
5%
1/16W
MF-LF
402
1 5%
1/16W
402
MF-LF
MAKE_BASE=TRUE
Q7861
D 6
2 G
EXT GPU PWRGD Pullup
69 79 84
Power Control
PP3V3_S0
5%
1/16W
MF-LF
402 2
EG_PWRSEQ_HW
R7888
0
P1V1GPU_PGOOD
P3V3GPU_ENOUT
1
83

100K
5%
1/16W
MF-LF
402 2
5%
MF-LF
1/16W
402
R78901
100K
SYNC_MASTER=PWRSQNC
PP3V3_S0
R7889
10%
16V
CERM 2
402
S 1
82 81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84
EG_PWRSEQ_HW1
0.01UF
SOT563
GPU_S0_EN_L
OUT
C7861 1
SSM6N15FEAPE
69
GPUVCORE_EN
82 81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84
EG_PWRSEQ_HW
V2MON THRESHOLD IS 2.866V


70 84
84 83 69 9
PM_ALL_GPU_PGOOD
PM_ALL_GPU_PGOOD
OUT
MAKE_BASE=TRUE
70 69 8 6
81 79 77 76
EG_PWRSEQ_HW
EG_PWRSEQ_HW
R7863
R7864
100K
PP3V3_S0GPU
GPUVCORE_EN_RC 0 79 84
69 GPUVCORE_EN
9 69 83 84
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
69
97
3.3V S0 FET
CRITICAL
CRITICAL
Q7910
Q7930
FDC638P_G
FDC606P_G
Q7912
10K
SOT563
43 42 40 21 7
69
IN
PM_SLP_S4_L
0.033UF
10%
16V 2
X5R
402
5%
1/16W
MF-LF
402 2
SSM6N15FEAPE
2 G
C7911 1
R79121
D 6
P3V3S3_EN_L
S 1
47K
FDC638P
CHANNEL
P-TYPE
C7910
0.01UF
1
P3V3S3_SS
RDS(ON)
Q7912
0.033UF
100K
10%
16V 2
X5R
402
5%
1/16W
MF-LF
402 2
SOT563
P3V3S0_EN_L
0.087 A (EDP)
69
IN
5 G
P3V3S0_EN
S 4
47K
0.01UF
1
P3V3S0_SS
MOSFET
FDC606P
CHANNEL
P-TYPE
RDS(ON)
26 mOhm @4.5V
2
LOADING
5%
1/16W
MF-LF
402
10%
16V
CERM
402
59 60 63 68 69 77 80 81 82 84
6 7 8 13 18 19 21 22 24 25 28
29 37 39 43 45 47 48 49 51 55
85 96
3.3V S0 FET
C7930
R7930
48 mOhm @4.5V
2
LOADING
5%
1/16W
MF-LF
402
C7931 1
R79321
D 3
SSM6N15FEAPE
R7910
1
3.3V S3 FET
MOSFET
PP3V3_S0
SOT-6
PP3V3_S5
6
5
2
1
37 34 30 26 24 22 20 18 8 7
96 87 82 70 69 68 64 54 44 38
PP3V3_S5
7 8 21 27 31 32 45 50 52
PP3V3_S3
SM
3.3V S3 FET
96
37 34 30 26 24 22 20 18 8 7
87 82 70 69 68 64 54 44 38
1 2 5 6
2.9 A (EDP)
10%
16V
CERM
402
3.3V GPU FET
CRITICAL
Q7970
FDC606P_G
87 84 69 55 25 18 8 7
0.1UF
20%
10V
CERM 2
402
100K 2
R79421
CRITICAL
Q7940
SI2312BDS
D 6
Q7941
84 69
IN
PP1V8_GPUIFPX
Q7950
PP5V_S0
8
7 8 39 44 49 51 63 66 67 83 85
10%
16V
5%
1/16W
X5R
MF-LF
402
402
2
C7950
R7950
P5V0S0_EN_L
S 4
47K
1
6 7
0.033UF
47K
P1V8GPU_EN_L_RC
5.0V S0 FET
C7951
R7952
10%
2 16V
CERM
402
PP5V_S3
MOSFET
FDC606P
CHANNEL
P-TYPE
D 3
0.01UF
55 53 51 43 41 40 39 31 9 8 7
79 70 65 64
10K
1%
1/16W
MF-LF
402
C7941
S 1
2 G
RDS(ON)
0.01UF
P5V0S0_SS
26 MOHM @4.5V
LOADING
1.7 A (EDP)
5%
10%
1/16W
Q7955
SSM3K15FV
P1V8_S0GPU_EN
MF-LF
16V
402
CERM
402
D 3
SOD-VESM-HF
1.5V S0 FET
1.5V S0 FET
69 46
65 30 29 28 8 7
IN
CRITICAL
Q7901
D
ROME
MOSFET
Rome SenseFET
CHANNEL
N-TYPE
6.3 mOhm @4.5V
20%
10V
CERM 2
402
R7901
1
R7903
MCPDDR_SS
LOADING
5.4 A (EDP)
KELVIN
1 2 3
Q7971
OUT
47
OUT
47
D 6
65 29 28 8 7
PP1V8R1V5_S0_FET
SSM6N15FEAPE
R79751
10
R7971
MCPDDR_EN_L
47K
5%
1/16W
MF-LF
402
D 3
SSM6N15FEAPE
2 G
S 1
5%
1/16W
MF-LF
402 2
C7903
0.068UF
10%
2 10V
CERM
402
MCPDDR_EN_L_RC
PP5V_S3
Q7975
R79761
100K
69
IN
90mA max load @ 0.9V

81mW max power
VTTCLAMP_L
55 53 51 43 41 40 39 31 9 8 7
79 70 65 64
SOT563
5 G
7 8 11 12 16 24 28 29 39 68 69
SOT563
5%
1/16W
MF-LF
402 2
P1V5_S0_KELVIN
P1V5_S0_SENSE
5%
1/16W
MF-LF
402
100K
Q7971
NC
G
SENSE
0.1UF
10K
S 2
MCP79 DDR FETs
RDS(ON)
GND
C7902 1
MCP79 DDR pad leakage is high enough that nVidia recommends unpowering during sleep.
In order to support unpowering rail, hardware must guarantee MEM_CKE signals are low
before rail is turned off, and remains low until after rail turns back on or DIMMs
will exit self-refresh prematurely. MEM_VTT_EN output from MCP79 used to enable clamp
on VTT rail, which pulls all CKE signals low through VTT termination resistors.
DFN
PP5V_S3
PM_SLP_S3_L_R
PP1V8R1V5_S3
EG
TPCP8102
SOT563
41 40 39 31 9 8 7
79 70 65 64 55 53 51 43
1.1 A (EDP)
BOM_OPTION
CRITICAL
8 78
SSM6N15FEAPE
IN
26 mOhm @4.5V
LOADING
S 2
23V1K-SM
P1V8GPU_EN_L
84 83 69
C
1 G
SOT563
R7941
5 G
10%
16V
CERM
402
5.0V S0 FET
SSM6N15FEAPE
1%
1/16W
MF-LF
402 2
P-TYPE
P3V3GPU_EN
SOT23
69.8K
D 3
SOD-VESM-HF
FDC606P
CHANNEL
RDS(ON)
0.01UF
P3V3GPU_SS
5%
1/16W
MF-LF
402
Q7972
SSM3K15FV
1K
MOSFET
P1V8GPU_SS
5%
1/16W
MF-LF
402
6 8 69 76 77 79 81
3.3V GPU FET
C7970
R7970
P3V3GPU_EN_L
R7940
PP5V_S3
Q7941
10%
10V 2
X5R
402-1
1UF
PP1V8_S0
1.8V Vgs
43 41 40 39 31 9 8 7
79 70 65 64 55 53 51
C7971 1
5%
1/16W
MF-LF
402 2
51K
C7940 1
R79721
PP3V3_S0GPU
1.8V GPU FET
PP3V3_S5
4
37 34 30 26 24 22 20 18 8 7
96 87 82 70 69 68 64 54 44 38
1 2 5 6
SOT-6
SOT563
5%
1/16W
MF-LF
402 2
S 4
MCPDDR_EN
D 6
SSM6N15FEAPE
Power FETs
2 G
S 1
SYNC_MASTER=DDR
VTTCLAMP_EN
Q7975
D 3
SSM6N15FEAPE
5 G
65 26 9
IN
NO STUFF

C7976 1
0.001UF
SOT563
20%
50V
CERM 2
402

S 4
SIZE
MEM_VTT_EN
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
70
97
OMIT
Page Notes
U8000
NB9P-GS

- =PP1V2_GPU_PEX_PLLXVDD
- =PP1V2_GPU_PEX_IOVDDQ
- =PP1V2_GPU_PEX_IOVDD
90 9
90 9

(NONE)
90 9

(NONE)
90 9
D
83 78 76 73 71 8
83 78 76 73 71 8
83 78 76 73 71 8
PP1V1_S0GPU_REG
PP1V1_S0GPU_REG
PP1V1_S0GPU_REG
1UF
4.7UF
10%
2 6.3V
CERM
402
NC_GPU_DFM
C8001
C8000
U8000
NB9P-GS
H32
M7
P6
P7
R7
U7
V6
AB7
AD6
AF6
AG6
AJ5
D35
AK15
AL7
E7
E35
F7
A2
BGA
SYMBOL 2 OF 9
PEX_IOVDD1
PEX_IOVDD2
PEX_IOVDD3
PEX_IOVDD4
PEX_IOVDD5
1UF
10%
2 6.3V
CERM
402
AK16
AK17
AK21
AK24
AK27
PEX_PLLVDD
C8004
0.1UF
20%
2 10V
CERM
402
AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24
AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16
1UF
10%
2 6.3V
CERM
402
PEG_R2D_C_P<3>
C8026
0.1uF
IN
IN
IN
IN
IN
IN
IN
PEG_R2D_C_N<3>
PEG_R2D_C_P<4>
PEG_R2D_C_N<4>
PEG_R2D_C_P<5>
PEG_R2D_C_N<5>
PEG_R2D_C_P<6>
4.7UF
20%
2 6.3V
CERM
603
C8009
1UF
C8010
22UF
0.1UF
180mA
20%
2 10V
CERM
402
GPU_VDD_SENSE
79
GPU_GND_SENSE
79
0.1uF
0.1uF
PEG_R2D_C_P<7>
C8034
0.1uF
IN
IN
PEG_R2D_C_N<7>
C8035
0.1uF
IN
PEG_R2D_C_P<8>
C8036
0.1uF
90 9
IN
PEG_R2D_C_N<8>
C8037
0.1uF
90 9
IN
PEG_R2D_C_P<9>
1
1
C8016 C8015 1
4.7UF
20%
2 6.3V
CERM
603
0.1uF
PEG_R2D_C_N<9>
C8039
0.1uF
IN
IN
PEG_R2D_C_P<10>
C8040
0.1uF
90 9
IN
PEG_R2D_C_N<10>
C8041
0.1uF
90 9
IN
PEG_R2D_C_P<11>
C8042
0.1uF
90 9
90 9
C8038
90 9
90 9
IN
IN
IN
PEG_R2D_C_N<11>
PEG_R2D_C_P<12>
PEG_R2D_C_N<12>
IN
90 9
IN
PEG_R2D_C_P<13>
PEG_R2D_C_N<13>
C8043
C8044
C8045
C8046
C8047
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
4.7UF
20%
6.3V 2
CERM
603
AG14
AD19
0.1uF
90 9
0603
C8017
0.1UF
AD20
10NH-600MA
PP1V1_GPU_PEX_PLLVDD_F
GND_SENSE
C8032
0.1uF
0.1uF
90 9
VDD_SENSE
C8031
C8033
L8015
C8030
0.1uF
PEG_R2D_C_N<6>
90 9
VOLTAGE=1.2V
C8029
IN
C8011
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C8028
0.1uF
90 9
C8006
20%
2 6.3V
CERM-X5R
805
0.1UF
10%
2 6.3V
CERM
402
C8027
0.1UF
20%
2 10V
CERM
402
C8007
0.1uF
90 9
90 9
C8008
90 9
C8005
0.1uF
0.1uF
1500mA
1
PEX_IOVDDQ1
PEX_IOVDDQ2
PEX_IOVDDQ3
PEX_IOVDDQ4
PEX_IOVDDQ5
PEX_IOVDDQ6
PEX_IOVDDQ7
PEX_IOVDDQ8
PEX_IOVDDQ9
PEX_IOVDDQ10
PEX_IOVDDQ11
PEX_IOVDDQ12
PEX_IOVDDQ13
PEX_IOVDDQ14
PEX_IOVDDQ15
PEX_IOVDDQ16
PEX_IOVDDQ17
PEX_IOVDDQ18
PEX_IOVDDQ19
PEX_IOVDDQ20
PEX_IOVDDQ21
PEX_IOVDDQ22
PEX_IOVDDQ23
PEX_IOVDDQ24
PEX_IOVDDQ25
NC
C8003
C8025
NO_TEST=TRUE
0.1uF
PEG_R2D_C_N<2>
22UF
OMIT
IN
90 9
20%
2 6.3V
CERM-X5R
805
20%
2 6.3V
CERM
603
C8023
0.1uF
90 9
90 9
PEG_R2D_C_N<1>
C8022
C8024
90 9
C8002
IN
PEG_R2D_C_P<1>
C8021
0.1uF
PEG_R2D_C_P<2>
90 9
IN
PEG_R2D_C_N<0>
C8020
IN
90 9
250mA
IN
PEG_R2D_C_P<0>
90 9
90 9
PEX 1.1V Current = 2A
IN
90 9
IN
PEG_R2D_C_P<14>
C8048
0.1uF
0.1uF
0.1uF
90 9
IN
PEG_R2D_C_N<14>
C8049
90 9
IN
PEG_R2D_C_P<15>
C8050
90 9
IN
90 17
IN
90 17
IN
84 9
IN
PEG_R2D_C_N<15>
C8051
0.1uF
R8020
0
5%
1/16W
MF-LF
402
BGA
SYMBOL 1 OF 9
PEX_RX0
PEX_TX0
PEX_RX0*
PEX_TX0*
AL17
AM17
PEG_R2D_P<0>
PEG_R2D_N<0>
2
90
10% 16V X5R 40290
2
10% 16V X5R 402
PEG_R2D_P<1>
PEG_R2D_N<1>
2
90
10% 16V X5R 40290
2
10% 16V X5R 402
PEG_R2D_P<2>
PEG_R2D_N<2>
AR19
AR20
PEX_RX2
PEX_RX2*
PEX_TX2
PEX_TX2*
AL19
AK19
2
90
10% 16V X5R 40290
2
10% 16V X5R 402
PEG_R2D_P<3>
PEG_R2D_N<3>
AP20
AN20
PEX_RX3
PEX_RX3*
PEX_TX3
PEX_TX3*
AL20
AM20
2
90
10% 16V X5R 40290
2
10% 16V X5R 402
PEG_R2D_P<4>
PEG_R2D_N<4>
2
90
10% 16V X5R 40290
2
10% 16V X5R 402
PEG_R2D_P<5>
PEG_R2D_N<5>
2
90
10% 16V X5R 40290
2
10% 16V X5R 402
PEG_R2D_P<6>
PEG_R2D_N<6>
AP23
AN23
PEX_RX6
PEX_RX6*
PEX_TX6
PEX_TX6*
AL23
AM23
2
90
10% 16V X5R 40290
2
10% 16V X5R 402
PEG_R2D_P<7>
PEG_R2D_N<7>
AN25
AP25
PEX_RX7
PEX_RX7*
PEX_TX7
PEX_TX7*
AM24
AM25
2
90
10% 16V X5R 40290
2
10% 16V X5R 402
PEG_R2D_P<8>
PEG_R2D_N<8>
2
90
10% 16V X5R 40290
2
10% 16V X5R 402
PEG_R2D_P<9>
PEG_R2D_N<9>
AP26
AN26
PEX_RX9
PEX_RX9*
2
90
10% 16V X5R 40290
2
10% 16V X5R 402
PEG_R2D_P<10>
PEG_R2D_N<10>
AN28
AP28
2
90
10% 16V X5R 40290
2
10% 16V X5R 402
PEG_R2D_P<11>
PEG_R2D_N<11>
AR28
AR29
2
90
10% 16V X5R 40290
2
10% 16V X5R 402
PEG_R2D_P<12>
PEG_R2D_N<12>
2
90
10% 16V X5R 40290
2
10% 16V X5R 402
PEG_R2D_P<13>
PEG_R2D_N<13>
AN19
AP19
AN22
AP22
AR22
AR23
AR25
AR26
AP29
AN29
AN31
AP31
PEX_RX1
PEX_RX1*
PEX_RX4
PEX_RX4*
PEX_RX5
PEX_RX5*
PEX_RX8
PEX_RX8*
PEX_TX1
PEX_TX1*
PEX_TX4
PEX_TX4*
PEX_TX5
PEX_TX5*
PEX_TX8
PEX_TX8*
AM18
AM19
AM21
AM22
AL22
AK22
AL25
AK25
PEX_TX9
PEX_TX9*
AL26
AM26
PEX_RX10
PEX_RX10*
PEX_TX10
PEX_TX10*
AM27
AM28
PEX_RX11
PEX_RX11*
PEX_TX11
PEX_TX11*
AL28
AK28
PEX_RX12
PEX_RX12*
PEX_RX13
PEX_RX13*
PEX_TX12
PEX_TX12*
PEX_TX13
PEX_TX13*
AK29
AL29
AM29
AM30
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
2
90
10% 16V X5R 40290
2
10% 16V X5R 402
PEG_R2D_P<14>
PEG_R2D_N<14>
AR31
AR32
PEX_RX14
PEX_RX14*
PEX_TX14
PEX_TX14*
AM31
90
AM32
90
2
90
10% 16V X5R 40290
2
10% 16V X5R 402
PEG_R2D_P<15>
PEG_R2D_N<15>
AR34
AP34
PEX_RX15
PEX_RX15*
PEX_TX15
PEX_TX15*
AN32
AP32
AR16
AR17
PEX_REFCLK
PEX_REFCLK*
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT*
AJ17
PEX_TERMP
AG21
90
90
PEG_D2R_C_P<0>
PEG_D2R_C_N<0>
PEG_D2R_C_P<1>
PEG_D2R_C_N<1>
PEG_D2R_C_P<2>
PEG_D2R_C_N<2>
PEG_D2R_C_P<3>
PEG_D2R_C_N<3>
PEG_D2R_C_P<4>
PEG_D2R_C_N<4>
PEG_D2R_C_P<5>
PEG_D2R_C_N<5>
PEG_D2R_C_P<6>
PEG_D2R_C_N<6>
PEG_D2R_C_P<7>
PEG_D2R_C_N<7>
PEG_D2R_C_P<8>
PEG_D2R_C_N<8>
PEG_D2R_C_P<9>
PEG_D2R_C_N<9>
PEG_D2R_C_P<10>
PEG_D2R_C_N<10>
PEG_D2R_C_P<11>
PEG_D2R_C_N<11>
PEG_D2R_C_P<12>
PEG_D2R_C_N<12>
PEG_D2R_C_P<13>
PEG_D2R_C_N<13>
PEG_D2R_C_P<14>
PEG_D2R_C_N<14>
PEG_D2R_C_P<15>
PEG_D2R_C_N<15>
C8055
0.1uF
C8056
0.1uF
C8057
0.1uF
C8058
0.1uF
C8059
0.1uF
C8060
0.1uF
C8061
0.1uF
C8062
0.1uF
C8063
0.1uF
C8064
0.1uF
C8065
0.1uF
C8066
0.1uF
C8067
0.1uF
C8068
0.1uF
C8069
0.1uF
C8070
0.1uF
C8071
0.1uF
C8072
0.1uF
C8073
0.1uF
C8074
0.1uF
C8075
0.1uF
C8076
0.1uF
C8077
0.1uF
C8078
0.1uF
C8079
0.1uF
C8080
0.1uF
C8081
0.1uF
C8082
0.1uF
C8083
0.1uF
C8084
0.1uF
C8085
0.1uF
C8086
0.1uF
1
1
1
1
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<0>
OUT
9 90
PEG_D2R_N<0>
OUT
9 90
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<1>
OUT
9 90
PEG_D2R_N<1>
OUT
9 90
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<2>
OUT
9 90
PEG_D2R_N<2>
OUT
9 90
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<3>
OUT
9 90
PEG_D2R_N<3>
OUT
9 90
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<4>
OUT
9 90
PEG_D2R_N<4>
OUT
9 90
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<5>
OUT
9 90
PEG_D2R_N<5>
OUT
9 90
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<6>
OUT
9 90
PEG_D2R_N<6>
OUT
9 90
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<7>
OUT
9 90
PEG_D2R_N<7>
OUT
9 90
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<8>
OUT
9 90
PEG_D2R_N<8>
OUT
9 90
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<9>
OUT
9 90
PEG_D2R_N<9>
OUT
9 90
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<10>
OUT
9 90
PEG_D2R_N<10>
OUT
9 90
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<11>
OUT
9 90
PEG_D2R_N<11>
OUT
9 90
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<12>
OUT
9 90
PEG_D2R_N<12>
OUT
9 90
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<13>
OUT
9 90
PEG_D2R_N<13>
OUT
9 90
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<14>
OUT
9 90
PEG_D2R_N<14>
OUT
9 90
2
10% 16V X5R 402
2
10% 16V X5R 402
PEG_D2R_P<15>
OUT
9 90
PEG_D2R_N<15>
OUT
9 90
R8060
PEG_CLK100M_P
PEG_CLK100M_N
EG_RESET_L
AP17
AN17
2
90
10% 16V X5R 40290
2
10% 16V X5R 402
GPU_RESET_R_L
TP_PEX_CLKREQ_L
AM16
PEX_RST*
AR13
PEX_CLKREQ*
PEX_RFU1
PEX_RFU2
AJ18
AG19
NC
AG20
PEX_TSTCLK_P
PEX_TSTCLK_N
PEX_TERMP_PD
200
1%
1/16W
MF-LF
402
R8050
2.49K2
1%
1/16W
MF-LF
402
NC
NV G96 PCI-E
SYNC_MASTER=MUXGFX

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
71
97
8
Page Notes
OMIT

- =PPVCORE_GPU
- =PP1V8_GPU_FBVDDQ
U8000
U8000
NB9P-GS
BGA
NB9P-GS

(NONE)
79
8
46
PPVCORE_GPU
???A @ ???/???MHz Core/Mem Clk for VDD

(NONE)
75 74 73 47 9 8
C8100
C8101
4.7UF
4.7UF
20%
6.3V
X5R-CERM
402
20%
6.3V
X5R-CERM
402
C8103
C8102
4.7UF
C8104
20%
6.3V
X5R-CERM
402
C8105
C8106
0.47UF
0.47UF
0.47UF
0.47UF
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
C8110
C8108
C8109
C8111
0.47UF
0.47UF
0.47UF
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
C8115
C8113
C8114
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
C8118
C8119
C8120
10%
6.3V
CERM-X5R
402
C8112
0.47UF
C8116
0.1UF
C8107
0.47UF
0.47UF
2
10%
6.3V
CERM-X5R
402
C8117
0.1UF
C8121
20%
10V
CERM
402
C8122
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
PP1V8_S0GPU_ISNS
Nvidia PRD for GB-128 uses 4x4.7uF, 8x0.47uF, 16x0.1uF

???A @ ???MHz 1.8V GDDR3
C8150
C8151
4.7UF
4.7UF
20%
6.3V
CERM
603
20%
6.3V
CERM
603
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
M12
M14
M16
M18
M20
M22
M24
P11
P13
P15
P17
P19
P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17
BGA
SYMBOL 9 OF 9
VDD
B3
B6
B9
B12
B15
B21
B24
B27
B30
B33
C2
C34
E6
E9
E12
E15
E18
E24
E27
E30
F2
F5
F31
F34
J2
J5
J31
J34
L9
M2
M5
M11
M13
M15
M17
M19
M21
M23
M25
M31
M34
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
P12
P14
P16
P18
P20
P22
P24
R2
R5
R31
R34
T11
T13
T15
T17
T19
T21
T23
T25
U11
U12
U13
U14
U15
V19
V21
V23
V25
W11
W12
W13
W14
W15
W16
W17
W18
W19
AD24
W21
W22
W23
W24
W25
Y12
Y14
Y16
Y18
Y20
Y22
Y24
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
VDD
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD12
AD14
AD16
AD18
AD22
W20
OMIT
C8156
0.1UF
20%
10V
CERM
402
C8162
C8157
0.1UF
2
20%
10V
CERM
402
C8163
C8158
0.1UF
2
20%
10V
CERM
402
C8164
C8159
0.1UF
2
20%
10V
CERM
402
C8165
C8160
0.47UF
2
10%
6.3V
CERM-X5R
402
C8166
C8161
0.47UF
10%
6.3V
CERM-X5R
402
C8167
0.1UF
0.1UF
0.1UF
0.1UF
0.47UF
0.47UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
U8000
NB9P-GS
BGA
B18
J17
U27
1
SYMBOL 7 OF 9
J21
J22
AB27
J23
AB29
AC27
J24
J29
AD27
N27
AE27
AJ28
P27
R27
E21
C8168
C8169
C8170
C8171
0.47UF
0.47UF
0.47UF
0.47UF
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
G8
G9
J20
T27
FBVDDQ
FBVDDQ
U29
V27
U16
U17
G17
G18
V29
V34
G22
W27
U18
U19
H29
J14
Y27
AA27
U20
J15
AA29
U21
U22
J16
AA31
U23
U24
U25
V2
V5
V9
V12
V14
SYMBOL 8 OF 9
GND
GND
V18
V20
V22
V24
V31
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25
AA2
AA5
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA34
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC9
AD2
AD5
AD11
AD13
AD15
AD17
AD21
AD23
AD25
AD31
AD34
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AG2
AG5
AG31
AG34
AK2
AK5
AP33
AK31
AK34
AL6
AL9
AL12
AL15
AL18
AL21
AL24
AL27
AL30
AN2
AN34
AP3
AP6
AP9
AP12
AP15
AP18
AP21
AP24
AP27
AP30
NV G96 Core/FB Power

SYNC_MASTER=MUXGFX

SIZE
DRAWING NUMBER
V16
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
72
97
8
Page Notes

- =PP1V2_GPU_FBPLLAVDD
- =PP1V8_GPU_FBIO
(NONE)
OMIT
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
95 74
BI
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
BI
95 74
95 74
BI
BI
FB_A_DQ<0>
FB_A_DQ<1>
FB_A_DQ<2>
FB_A_DQ<3>
FB_A_DQ<4>
FB_A_DQ<5>
FB_A_DQ<6>
FB_A_DQ<7>
FB_A_DQ<8>
FB_A_DQ<9>
FB_A_DQ<10>
FB_A_DQ<11>
FB_A_DQ<12>
FB_A_DQ<13>
FB_A_DQ<14>
FB_A_DQ<15>
FB_A_DQ<16>
FB_A_DQ<17>
FB_A_DQ<18>
FB_A_DQ<19>
FB_A_DQ<20>
FB_A_DQ<21>
FB_A_DQ<22>
FB_A_DQ<23>
FB_A_DQ<24>
FB_A_DQ<25>
FB_A_DQ<26>
FB_A_DQ<27>
FB_A_DQ<28>
FB_A_DQ<29>
FB_A_DQ<30>
FB_A_DQ<31>
FB_A_DQ<32>
FB_A_DQ<33>
FB_A_DQ<34>
FB_A_DQ<35>
FB_A_DQ<36>
FB_A_DQ<37>
FB_A_DQ<38>
FB_A_DQ<39>
FB_A_DQ<40>
FB_A_DQ<41>
FB_A_DQ<42>
FB_A_DQ<43>
FB_A_DQ<44>
FB_A_DQ<45>
FB_A_DQ<46>
FB_A_DQ<47>
FB_A_DQ<48>
FB_A_DQ<49>
FB_A_DQ<50>
FB_A_DQ<51>
FB_A_DQ<52>
FB_A_DQ<53>
FB_A_DQ<54>
FB_A_DQ<55>
FB_A_DQ<56>
FB_A_DQ<57>
FB_A_DQ<58>
FB_A_DQ<59>
FB_A_DQ<60>
FB_A_DQ<61>
FB_A_DQ<62>
FB_A_DQ<63>
OMIT
U8000

(NONE)
U8000
NB9P-GS
NB9P-GS
BGA
R30
R32
P31
N30
L31
M32
M30
L30
P33
P34
N35
P35
N34
L33
L32
N33
K31
K30
G30
K32
G32
H30
F30
G31
H33
K35
K33
G34
K34
E33
E34
G33
AG30
AH31
AG32
AF31
AF30
AD30
AC32
AE30
AE32
AF33
AF34
AE35
AE33
AE34
AC35
AB32
AN33
AK32
AL33
AM33
AL31
AK30
AJ30
AH30
AM35
AH33
AH35
AH32
AH34
AM34
AL35
AJ33
P29
NC
R29
NC
L29
NC
M29
NC
AD29
NC
AE29
NC
AG29
NC
AH29
NC
SYMBOL 3 OF 9
FBA_D0
FBA_CMD0
FBA_CMD1
FBA_D1
FBA_CMD2
FBA_D2
FBA_D3
FBA_CMD3
FBA_D4
FBA_CMD4
FBA_D5
FBA_CMD5
FBA_D6
FBA_CMD6
FBA_D7
FBA_CMD7
FBA_D8
FBA_CMD8
FBA_D9
FBA_CMD9
FBA_CMD10
FBA_D10
FBA_CMD11
FBA_D11
FBA_CMD12
FBA_D12
FBA_CMD13
FBA_D13
FBA_D14
FBA_CMD14
FBA_D15
FBA_CMD15
FBA_D16
FBA_CMD16
FBA_D17
FBA_CMD17
FBA_D18
FBA_CMD18
FBA_D19
FBA_CMD19
FBA_D20
FBA_CMD20
FBA_D21
FBA_CMD21
FBA_D22
FBA_CMD22
FBA_D23
FBA_CMD23
FBA_D24
FBA_CMD24
FBA_CMD25
FBA_D25
FBA_CMD26
FBA_D26
FBA_CMD27
FBA_D27
FBA_CMD28
FBA_D28
FBA_CMD29
FBA_D29
FBA_CMD30
FBA_D30
FBA_D31
FBA_CLK0
FBA_D32
FBA_CLK0*
FBA_D33
FBA_CLK1
FBA_D34
FBA_CLK1*
FBA_D35
FBA_D36
FBA_DQM0
FBA_D37
FBA_DQM1
FBA_D38
FBA_DQM2
FBA_D39
FBA_DQM3
FBA_D40
FBA_DQM4
FBA_D41
FBA_DQM5
FBA_D42
FBA_DQM6
FBA_D43
FBA_DQM7
FBA_D44
FBA_D45
FBA_DQS_RN0
FBA_D46
FBA_DQS_RN1
FBA_D47
FBA_DQS_RN2
FBA_D48
FBA_DQS_RN3
FBA_D49
FBA_DQS_RN4
FBA_D50
FBA_DQS_RN5
FBA_D51
FBA_DQS_RN6
FBA_D52
FBA_DQS_RN7
FBA_D53
FBA_D54
FBA_DQS_WP0
FBA_D55
FBA_DQS_WP1
FBA_D56
FBA_DQS_WP2
FBA_D57
FBA_DQS_WP3
FBA_D58
FBA_DQS_WP4
FBA_D59
FBA_DQS_WP5
FBA_D60
FBA_DQS_WP6
FBA_D61
FBA_DQS_WP7
FBA_D62
FBA_D63
FB_DLLAVDD0
FB_PLLAVDD0
FBA_RFU0
FBA_RFU1*
FBA_DEBUG
FBA_RFU2
FB_CAL_PD_VDDQ
FBA_RFU3*
FB_CAL_PU_GND
FBA_RFU4
FB_CAL_TERM_GND
FBA_RFU5*
FBA_RFU6
FBA_RFU7*
BGA
V32
W31
W29
FB_A_LMA<4>
FB_A_RAS_L
FB_A_LMA<5>
FB_A_BA<1>
FB_A_UMA<2>
FB_A_UMA<4>
FB_A_UMA<3>
NC_FB_A_CS1_L
FB_A_CS0_L
FB_A_MA<11>
FB_A_CAS_L
FB_A_WE_L
FB_A_BA<0>
FB_A_UMA<5>
FB_A_MA<12>
FB_A_DRAM_RST
FB_A_MA<7>
FB_A_MA<10>
FB_A_CKE
FB_A_MA<0>
FB_A_MA<9>
FB_A_MA<6>
FB_A_LMA<2>
FB_A_MA<8>
FB_A_LMA<3>
FB_A_MA<1>
NC_FBA_MA<13>
FB_A_BA<2>
NC_FBA_CMD28
NC_FBA_CMD29
NC_FBA_CMD30
T32
T31
AC31
AC30
FB_A_CLK_P<0>
FB_A_CLK_N<0>
FB_A_CLK_P<1>
FB_A_CLK_N<1>
U31
Y32
AB35
AB34
W35
W33
W30
T34
T35
AB31
Y30
Y34
W32
AA30
AA32
Y33
U32
Y31
U34
Y35
W34
V30
U35
U30
U33
AB30
AB33
T33
P30
P32
J30
H34
AF32
AF35
AL32
AL34
N32
L35
H31
G35
AD32
AC34
AJ31
AJ35
FB_A_DQM_L<0>
FB_A_DQM_L<1>
FB_A_DQM_L<2>
FB_A_DQM_L<3>
FB_A_DQM_L<4>
FB_A_DQM_L<5>
FB_A_DQM_L<6>
FB_A_DQM_L<7>
FB_A_RDQS<0>
FB_A_RDQS<1>
FB_A_RDQS<2>
FB_A_RDQS<3>
FB_A_RDQS<4>
FB_A_RDQS<5>
FB_A_RDQS<6>
FB_A_RDQS<7>
OUT
74 95
95 75
BI
OUT
74 95
95 75
BI
OUT
74 95
95 75
BI
OUT
74 95
95 75
BI
OUT
74 95
95 75
BI
OUT
74 95
95 75
BI
OUT
74 95
95 75
OUT
77
95 75
BI
OUT
74
95 75
BI
OUT
74 95
95 75
BI
OUT
74 95
95 75
BI
OUT
74 95
95 75
BI
OUT
95 75
74 95
L34
J32
H35
AE31
AC33
AJ32
AJ34
FB_A_WDQS<0>
FB_A_WDQS<1>
FB_A_WDQS<2>
FB_A_WDQS<3>
FB_A_WDQS<4>
FB_A_WDQS<5>
FB_A_WDQS<6>
FB_A_WDQS<7>
74 95
95 75
OUT
74 95
95 75
BI
95 75
BI
OUT
74 95
95 75
BI
OUT
OUT
74 95
OUT
74 95
OUT
OUT
74 95
OUT
74 95
OUT
74 95
R8201
74 95
R8200
95 75
BI
10K
95 75
BI
95 75
BI
5%
1/16W
MF-LF
402
10K
5%
1/16W
MF-LF
402
FBA_DEBUG
FBCAL_PD_VDDQ
FBCAL_PU_GND
FBCAL_TERM_GND
M27
BI
95 75
BI
95 75
BI
74 95
95 75
BI
74 95
95 75
BI
77
95 75
BI
OUT
OUT
OUT
74 95
95 75
BI
77
95 75
BI
77
95 75
BI
77
OUT
74 95
OUT
74 95
OUT
OUT
74 95
BI
74 95
BI
74 95
BI
74 95
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
74 95
BI
74 95
BI
74 95
BI
74 95
IN
74 95
IN
74 95
IN
74 95
IN
74 95
IN
74 95
IN
74 95
IN
74 95
IN
74 95
83 78 76 73 71 8
OUT
74 95
OUT
74 95
OUT
74 95
OUT
74 95
OUT
BI
95 75
74 95
BI
BI
95 75
74 95
PP1V1_S0GPU_REG
0.1UF
74 95
OUT
74 95
OUT
74 95
OUT
74 95
C8202
20%
10V
CERM
402
C8201
20%
10V
CERM
402
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
2
0402
0.1UF
2
BI
L8200
1
95 75
FERR-220-OHM
VOLTAGE=1.1V
95 75
BI
95 75
BI
95 75
BI
C8200
95 75
BI
1UF
95 75
BI
95 75
BI
95 75
BI
10%
6.3V
CERM
402
73 72 47 9 8
75 74
PP1V8_S0GPU_ISNS
R8293
1%
1/16W
MF-LF
402 2
R82901
48.7
95 75
BI
95 75
BI
95 75
95 75
BI
BI
1%
1/16W
MF-LF
402 2
1%
1/16W
U8000.MF-LF
402
R8291 1
33.2
40.2
1%
1/16W
MF-LF
402
D11
E11
F10
D8
F8
F9
E8
F12
B11
C13
A11
B8
A8
C8
C11
C10
D12
E13
F17
F15
F16
E16
F14
F13
D13
A13
B13
A14
C16
A17
B16
D16
D24
D26
E25
F25
F27
E28
F28
D29
A25
B25
D25
C26
C28
B28
A28
A29
E29
F29
D30
E31
C33
D33
F32
E32
B29
C29
B31
C31
B32
C32
B34
B35
G11
PLACEMENT_NOTE=Place close to U8000.
R8292
PLACEMENT_NOTE=Place close to
95 75
BI
74 95
60.4
K27
L27
BI
95 75
OUT
OUT
74
AG27
AF27
T30
BI
OUT
PP1V1_GPU_FBPLLAVDD0_F
N31
BI
FB_B_DQ<0>
FB_B_DQ<1>
FB_B_DQ<2>
FB_B_DQ<3>
FB_B_DQ<4>
FB_B_DQ<5>
FB_B_DQ<6>
FB_B_DQ<7>
FB_B_DQ<8>
FB_B_DQ<9>
FB_B_DQ<10>
FB_B_DQ<11>
FB_B_DQ<12>
FB_B_DQ<13>
FB_B_DQ<14>
FB_B_DQ<15>
FB_B_DQ<16>
FB_B_DQ<17>
FB_B_DQ<18>
FB_B_DQ<19>
FB_B_DQ<20>
FB_B_DQ<21>
FB_B_DQ<22>
FB_B_DQ<23>
FB_B_DQ<24>
FB_B_DQ<25>
FB_B_DQ<26>
FB_B_DQ<27>
FB_B_DQ<28>
FB_B_DQ<29>
FB_B_DQ<30>
FB_B_DQ<31>
FB_B_DQ<32>
FB_B_DQ<33>
FB_B_DQ<34>
FB_B_DQ<35>
FB_B_DQ<36>
FB_B_DQ<37>
FB_B_DQ<38>
FB_B_DQ<39>
FB_B_DQ<40>
FB_B_DQ<41>
FB_B_DQ<42>
FB_B_DQ<43>
FB_B_DQ<44>
FB_B_DQ<45>
FB_B_DQ<46>
FB_B_DQ<47>
FB_B_DQ<48>
FB_B_DQ<49>
FB_B_DQ<50>
FB_B_DQ<51>
FB_B_DQ<52>
FB_B_DQ<53>
FB_B_DQ<54>
FB_B_DQ<55>
FB_B_DQ<56>
FB_B_DQ<57>
FB_B_DQ<58>
FB_B_DQ<59>
FB_B_DQ<60>
FB_B_DQ<61>
FB_B_DQ<62>
FB_B_DQ<63>
NC
G12
NC
G14
NC
G15
NC
G24
NC
G25
NC
G27
NC
NCG28
SYMBOL 4 OF 9
FBC_CMD0
FBC_D0
FBC_D1
FBC_CMD1
FBC_D2
FBC_CMD2
FBC_D3
FBC_CMD3
FBC_D4
FBC_CMD4
FBC_D5
FBC_CMD5
FBC_D6
FBC_CMD6
FBC_D7
FBC_CMD7
FBC_D8
FBC_CMD8
FBC_D9
FBC_CMD9
FBC_CMD10
FBC_D10
FBC_CMD11
FBC_D11
FBC_D12
FBC_CMD12
FBC_CMD13
FBC_D13
FBC_CMD14
FBC_D14
FBC_D15
FBC_CMD15
FBC_CMD16
FBC_D16
FBC_CMD17
FBC_D17
FBC_D18
FBC_CMD18
FBC_CMD19
FBC_D19
FBC_CMD20
FBC_D20
FBC_CMD21
FBC_D21
FBC_CMD22
FBC_D22
FBC_CMD23
FBC_D23
FBC_D24
FBC_CMD24
FBC_D25
FBC_CMD25
FBC_CMD26
FBC_D26
FBC_D27
FBC_CMD27
FBC_D28
FBC_CMD28
FBC_D29
FBC_CMD29
FBC_D30
FBC_CMD30
FBC_D31
FBC_CLK0
FBC_D32
FBC_CLK0*
FBC_D33
FBC_CLK1
FBC_D34
FBC_CLK1*
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
FBC_RFU0
FBC_RFU1*
FBC_RFU2
FBC_RFU3*
FBC_RFU4
FBC_RFU5*
FBC_RFU6
FBC_RFU7*
C17
B19
D18
F21
A23
D21
FB_B_LMA<4>
FB_B_RAS_L
FB_B_LMA<5>
FB_B_BA<1>
FB_B_UMA<2>
FB_B_UMA<4>
FB_B_UMA<3>
NC_FB_B_CS1_L
FB_B_CS0_L
FB_B_MA<11>
FB_B_CAS_L
FB_B_WE_L
FB_B_BA<0>
FB_B_UMA<5>
FB_B_MA<12>
FB_B_DRAM_RST
FB_B_MA<7>
FB_B_MA<10>
FB_B_CKE
FB_B_MA<0>
FB_B_MA<9>
FB_B_MA<6>
FB_B_LMA<2>
FB_B_MA<8>
FB_B_LMA<3>
FB_B_MA<1>
NC_FBB_MA<13>
FB_B_BA<2>
NC_FBC_CMD28
NC_FBC_CMD29
NC_FBC_CMD30
B23
E20
G21
F20
F19
F23
A22
C22
B17
F24
C25
E22
C20
B22
A19
D22
D20
E19
D19
F18
C19
F22
C23
B20
A20
E17
D17
D23
E23
FB_B_CLK_P<0>
FB_B_CLK_N<0>
FB_B_CLK_P<1>
FB_B_CLK_N<1>
FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7
F11
D10
FB_B_DQM_L<0>
FB_B_DQM_L<1>
FB_B_DQM_L<2>
FB_B_DQM_L<3>
FB_B_DQM_L<4>
FB_B_DQM_L<5>
FB_B_DQM_L<6>
FB_B_DQM_L<7>
FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7
D9
B10
E14
D15
A16
D27
D28
D34
A34
F26
A26
D31
A31
E10
A10
B26
D32
A32
FB_DLLAVDD1
FB_PLLAVDD1
J19
J18
FBC_DEBUG
G19
FB_VREF
J27
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
77
OUT
75
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
FB_B_WDQS<0>
FB_B_WDQS<1>
FB_B_WDQS<2>
FB_B_WDQS<3>
FB_B_WDQS<4>
FB_B_WDQS<5>
FB_B_WDQS<6>
FB_B_WDQS<7>
D14
C14
E26
75 95
OUT
OUT
75 95
OUT
75 95
OUT
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
77
OUT
75 95
R8250
10K
75
R8251
5%
1/16W
MF-LF
402
10K
5%
1/16W
MF-LF
402
77
77
77
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
BI
75 95
BI
75 95
BI
75 95
BI
75 95
BI
75 95
BI
75 95
BI
75 95
BI
FB_B_RDQS<0>
FB_B_RDQS<1>
FB_B_RDQS<2>
FB_B_RDQS<3>
FB_B_RDQS<4>
FB_B_RDQS<5>
FB_B_RDQS<6>
FB_B_RDQS<7>
B14
FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7
OUT
75 95
PP1V1_S0GPU_REG
IN
75 95
IN
75 95
IN
75 95
IN
75 95
PP1V1_GPU_FBPLLAVDD1_F
IN
75 95
IN
75 95
VOLTAGE=1.1V
1
IN
75 95
IN
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
83 78 76 73 71 8
L8290
FERR-220-OHM
C8290
C8291
75 74 73 72 47 9 8
20%
10V
CERM
402
C8292
1UF
10%
6.3V
CERM
402
PP1V8_S0GPU_ISNS
R82941
FBC_DEBUG
R8295 1
60.4
1.07K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
GPU_FB_VREF
NO STUFF
C8296
NO STUFF
1
1
10%
16V
X5R
402
R8296 1
R8297
1.02K
0.1uF
PLACEMENT_NOTE=Place close to U8000.
0.1UF
20%
10V
CERM
402
2
0402
0.1UF
2
1%
1/16W
MF-LF
402
2.49K
1%
1/16W
MF-LF
402
GPU_FB_VREF_UNTERM_L
NO STUFF
Q8295
SSM6N15FEAPE
NV G96 Frame Buffer I/F
SOT563
SYNC_MASTER=MUXGFX
2
77 76 75 74
IN
FB_VREF_UNTERM

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
73
97
5
OMIT
CRITICAL
PP1V8_S0GPU_ISNS
75 74 73 72 47 9 8
10UF
20%
6.3V
X5R
603
C8401
C8402
C8403
C8404
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
U8400
BGA
(2 OF 2)
K1 VDDA0
K12 VDDA1
D
1
C8410
C8415
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
U8400.J1
A1 VDDQ0
A12 VDDQ1
C1 VDDQ2
C4 VDDQ3
C9 VDDQ4
C12 VDDQ5
E1 VDDQ6
E4 VDDQ7
E9 VDDQ8
E12 VDDQ9
J4 VDDQ10
J9 VDDQ11
N1 VDDQ12
N4 VDDQ13
N9 VDDQ14
N12 VDDQ15
R1 VDDQ16
R4 VDDQ17
R9 VDDQ18
R12 VDDQ19
V1 VDDQ20
V12 VDDQ21
U8400.J12
Connect to designated pin, then GND

74 73 72 47 9 8
75
PP1V8_S0GPU_ISNS
C8420
10UF
20%
6.3V
X5R
603
74 27 9
C8421
C8422
C8423
C8424
C8425
C8426
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
GPU_FB_A_VREF_DIV
R8430
R8433
549
549
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
FB_A0_VREF
R8431
R8432
1.33K
1%
1/16W
MF-LF
402 2
C8431
R8434
0.01UF
931
1%
1/16W
MF-LF
402 2
R8435
1.33K
10%
16V
CERM
402
C8450
VSS2 G1
VSS3 G12
VSS4 L1
10UF
20%
6.3V
X5R
603
VSS5 L12
VSS6 V3
1%
1/16W
MF-LF
402 2
A2
A11
F1
F12
M1
M12
V2
V11
C8451
C8452
C8453
C8454
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
VSS7 V10
VSSA0 J1
VSSA1 J12
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
C8460
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
U8400.J1
U8400.J12

75 74 73 72 47 9 8
PP1V8_S0GPU_ISNS
C8470
10UF
L11
P1
P4
P9
P12
T1
T4
T9
T12
20%
6.3V
X5R
603
74 27 9
C8471
C8472
C8473
C8474
C8475
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
C8476
0.1uF
10%
16V
X5R
402
GPU_FB_A_VREF_DIV
R8480 1
R8483 1
549
549
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
FB_A1_VREF
C8432
R8481
R8482
1.33K
10%
16V
CERM
402
C8481
R8484
0.01uF
931
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
R8485
1.33K
10%
16V
CERM
402
1%
1/16W
MF-LF
402 2
VRAM4
IN
95 73
IN
95 73
IN
95 73
IN
95 73
IN
95 74 73
IN
95 74 73
IN
95 74 73
IN
95 74 73
IN
95 74 73
IN
95 74 73
IN
74 73
IN
95 74 73
95 73
95 73
IN
IN
IN
74 73
IN
95 74 73
IN
95 74 73
95 74 73
IN
IN
R8443
VRAM4
1
R8445
121
121
243
1%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
2
OUT FB_A_RDQS<2>
95 73
95 73
CK*
CS0*
WE*
CAS*
RAS*
A4 ZQ
A9 MF
V4 SEN
V9 RESET
D3 RDQS0
D10 RDQS1
P10 RDQS2
D2 WDQS0
D11 WDQS1
IN
95 73
IN
95 74 73
IN
95 74 73
IN
95 74 73
IN
DM2
DM3
E10
N10
P11 WDQS2
P2 WDQS3
G9 BA0
G4 BA1
H3 BA2
FB_A_BA<0>
FB_A_BA<1>
FB_A_BA<2>
NC
R8448 1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
N3
B2
B3
C2
C3
E2
F3
F2
G3
B11
DQ9
DQ10
B10
C11
DQ11
C10
E11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
FB_A_WDQS<3>
FB_A_WDQS<2>
FB_A_WDQS<0>
FB_A_WDQS<1>
IN
E3
DM1
J11 CK
J10
F4
H4
F9
H10
P3 RDQS3
95 73
DM0
BGA
J3 A12/CS1*
OUT FB_A_RDQS<1>
IN
U8400
(1 OF 2)
L9 A11
H9 CKE
OUT FB_A_RDQS<0>
95 73
R8492
DQ18
DQ19
DQ20
DQ21
F10
F11
G10
M11
L10
N11
M10
R11
R10
DQ22 T11
DQ23 T10
DQ24 M2
DQ25 L3
DQ26 N2
DQ27 M3
DQ28 R2
DQ29 R3
DQ30 T2
DQ31 T3
FB_A_DQM_L<3>
FB_A_DQM_L<2>
FB_A_DQM_L<0>
FB_A_DQM_L<1>
FB_A_DQ<24>
FB_A_DQ<30>
FB_A_DQ<29>
FB_A_DQ<31>
FB_A_DQ<28>
FB_A_DQ<27>
FB_A_DQ<25>
FB_A_DQ<26>
FB_A_DQ<20>
FB_A_DQ<22>
FB_A_DQ<21>
FB_A_DQ<23>
FB_A_DQ<19>
FB_A_DQ<18>
FB_A_DQ<16>
FB_A_DQ<17>
FB_A_DQ<5>
FB_A_DQ<4>
FB_A_DQ<6>
FB_A_DQ<7>
FB_A_DQ<2>
FB_A_DQ<3>
FB_A_DQ<1>
FB_A_DQ<0>
FB_A_DQ<13>
FB_A_DQ<15>
FB_A_DQ<14>
FB_A_DQ<12>
FB_A_DQ<10>
FB_A_DQ<9>
FB_A_DQ<8>
FB_A_DQ<11>
IN
73 95
95 74 73
IN
IN
73 95
95 74 73
IN
IN
73 95
95 73
IN
IN
73 95
95 73
IN
95 73
IN
BI
73 95
BI
73 95
BI
73 95
BI
95 73
IN
95 74 73
IN
95 74 73
IN
95 74 73
IN
95 74 73
IN
95 74 73
IN
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
95 74 73
IN
74 73
IN
95 74 73
IN
95 73
IN
BI
73 95
95 73
BI
73 95
74 73
IN
BI
73 95
95 74 73
IN
BI
73 95
95 74 73
BI
73 95
95 74 73
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
IN
IN
IN
VOLTAGE=0.9V
VRAM4
1
R8494
R8496
1K
121
121
243
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
VRAM4
1
K3 A6
L4 A7
K2 A8/AP
M4 A9
K11 A10
FB_A_DRAM_RST
95 73
FB_VREF_UNTERM
2
K9 A0
H11 A1
K10 A2
M9 A3
K4 A4
H2 A5
FB_A_CLK_P<0>
FB_A_CLK_N<0>
FB_A_CS0_L
FB_A_WE_L
FB_A_CAS_L
FB_A_RAS_L
OUT FB_A_RDQS<3>
R8490
OMIT
CRITICAL
FB_A_MA<0>
FB_A_MA<1>
FB_A_LMA<2>
FB_A_LMA<3>
FB_A_LMA<4>
FB_A_LMA<5>
FB_A_MA<6>
FB_A_MA<7>
FB_A_MA<8>
FB_A_MA<9>
FB_A_MA<10>
FB_A_MA<11>
FB_A_CKE
FB_A_MA<12>
95 73
95 73
IN
IN
VRAM4
1
R8447
FB_A0_ZQ
FB_A0_MF
FB_A0_SEN
95 74 73
SOT563
MFHIGH
IN
95 74 73
SOT563
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
VRAM4
1
R8493
IN
10%
16V
CERM
402
R8495
121
121
243
1%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
2
OUT FB_A_RDQS<5>
95 73
OUT FB_A_RDQS<6>
95 73
K9 A0
H11 A1
K10 A2
M9 A3
K4 A4
H2 A5
IN
BI
95 73
IN
BI
73 95
95 73
IN
BI
73 95
95 73
IN
BI
73 95
95 74 73
73 95
IN
BI
BI
73 95
95 74 73
IN
95 74 73
IN
DM0
E3
BGA
DM1
DM2
DM3
E10
N10
J11 CK
J10
F4
H4
F9
H10
CK*
CS0*
WE*
CAS*
RAS*
DQ6
N3
B2
B3
C2
C3
E2
F3
F2
G3
B11
DQ9
DQ10
B10
C11
DQ11
C10
E11
DQ17
DQ18
DQ19
DQ20
DQ21
F10
F11
G10
M11
L10
N11
M10
R11
R10
DQ22 T11
DQ23 T10
DQ24 M2
DQ25 L3
DQ26 N2
P11 WDQS2
P2 WDQS3
NC
DQ4
DQ5
DQ15
DQ16
D3 RDQS0
D10 RDQS1
P10 RDQS2
J2 RFU
DQ3
DQ14
V9 RESET
G9 BA0
G4 BA1
H3 BA2
DQ1
DQ2
DQ12
DQ13
A4 ZQ
A9 MF
V4 SEN
FB_A_BA<0>
FB_A_BA<1>
FB_A_BA<2>
DQ0
DQ7
DQ8
J3 A12/CS1*
D2 WDQS0
D11 WDQS1
95 73
U8450
L9 A11
H9 CKE
FB_A_WDQS<7>
FB_A_WDQS<5>
FB_A_WDQS<6>
FB_A_WDQS<4>
73 95
FB_VREF_UNTERM
(1 OF 2)
K3 A6
L4 A7
K2 A8/AP
M4 A9
K11 A10
P3 RDQS3
73 95
SOT563
OUT FB_A_RDQS<4>
BI
IN
Q8450
SSM6N15FEAPE
OMIT
CRITICAL
FB_A_DRAM_RST
95 73
75 74 73
77 76
SOT563
R8497
FB_A_CLK_P<1>
FB_A_CLK_N<1>
FB_A_CS0_L
FB_A_WE_L
FB_A_CAS_L
FB_A_RAS_L
OUT FB_A_RDQS<7>
SSM6N15FEAPE
FB_A_MA<0>
FB_A_MA<1>
FB_A_UMA<2>
FB_A_UMA<3>
FB_A_UMA<4>
FB_A_UMA<5>
FB_A_MA<6>
FB_A_MA<7>
FB_A_MA<8>
FB_A_MA<9>
FB_A_MA<10>
FB_A_MA<11>
FB_A_CKE
FB_A_MA<12>
95 73
0.01UF
FB_A1_ZQ
FB_A1_MF
FB_A1_SEN
95 74 73
Q8450
C8496
K4J10324QD-HC11
75 74 73
77 76
Q8400
MFHIGH
10%
16V
CERM
402
SSM6N15FEAPE
0.01UF
SSM6N15FEAPE
32MX32-900MHZ-MFH
243
1%
1/16W
MF-LF
402
VSSA0 J1
VSSA1 J12
10%
16V
CERM
402
MFHIGH
121
1%
1/16W
MF-LF
402

VRAM4
VSS7 V10
C8482
DQ27 M3
DQ28 R2
DQ29 R3
MFHIGH
121
1%
1/16W
MF-LF
402
C8446
K4J10324QD-HC11
1K
5%
1/16W
MF-LF
402
95 74 73
R8446
32MX32-900MHZ-MFH
R8444
MFHIGH
R8442
VSS5 L12
VSS6 V3
FB_A3_VREF_UNTERM_L
FB_A1_VREF_UNTERM_L
Q8400
MFHIGH
R8440

(NONE)
0.01uF
931
1%
1/16W
MF-LF
402 2
VSS2 G1
VSS3 G12
VSS4 L1
FB_A_CLK1_TERM
VOLTAGE=0.9V
VRAM4
1
BGA
(2 OF 2)

- =PP1V8_S0_FB_VDD
- =PP1V8_S0_FB_VREFA
VSS0 A3
VSS1 A10
H1 VREF0
H12 VREF1
FB_A3_VREF
FB_A_CLK0_TERM
VRAM4
U8450
A1 VDDQ0
A12 VDDQ1
C1 VDDQ2
C4 VDDQ3
C9 VDDQ4
C12 VDDQ5
E1 VDDQ6
E4 VDDQ7
E9 VDDQ8
E12 VDDQ9
J4 VDDQ10
J9 VDDQ11
N1 VDDQ12
N4 VDDQ13
N9 VDDQ14
N12 VDDQ15
R1 VDDQ16
R4 VDDQ17
R9 VDDQ18
R12 VDDQ19
V1 VDDQ20
V12 VDDQ21
C8465
0.1uF
FB_A2_VREF_UNTERM_L
FB_A0_VREF_UNTERM_L
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
K1 VDDA0
K12 VDDA1
0.01UF
931
1%
1/16W
MF-LF
402 2
CRITICAL
PP1V8_S0GPU_ISNS
VSS0 A3
VSS1 A10
H1 VREF0
H12 VREF1
FB_A2_VREF
K4J10324QD-HC11
C8400
A2
A11
F1
F12
M1
M12
V2
V11
32MX32-900MHZ-MFH
74 73 72 47 9 8
75
1
Page Notes
OMIT
K4J10324QD-HC11
32MX32-900MHZ-MFH
DQ30 T2
DQ31 T3
FB_A_DQM_L<7>
FB_A_DQM_L<5>
FB_A_DQM_L<6>
FB_A_DQM_L<4>
FB_A_DQ<59>
FB_A_DQ<58>
FB_A_DQ<63>
FB_A_DQ<60>
FB_A_DQ<57>
FB_A_DQ<56>
FB_A_DQ<61>
FB_A_DQ<62>
FB_A_DQ<40>
FB_A_DQ<47>
FB_A_DQ<46>
FB_A_DQ<45>
FB_A_DQ<42>
FB_A_DQ<44>
FB_A_DQ<43>
FB_A_DQ<41>
FB_A_DQ<54>
FB_A_DQ<55>
FB_A_DQ<53>
FB_A_DQ<52>
FB_A_DQ<49>
FB_A_DQ<51>
FB_A_DQ<50>
FB_A_DQ<48>
FB_A_DQ<36>
FB_A_DQ<37>
FB_A_DQ<32>
FB_A_DQ<38>
FB_A_DQ<39>
FB_A_DQ<34>
FB_A_DQ<33>
FB_A_DQ<35>
IN
73 95
IN
73 95
IN
73 95
IN
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
GDDR3 Frame Buffer A (Top)
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
SYNC_MASTER=MUXGFX

J2 RFU

R8449
243
100
1%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402
2
R8498 1
243
1%
1/16W
MF-LF
402
R8499
SIZE
100
DRAWING NUMBER
5%
1/16W
MF-LF
402
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
74
97
5
OMIT
CRITICAL
PP1V8_S0GPU_ISNS
75 74 73 72 47 9 8
10UF
20%
6.3V
X5R
603
C8501
C8502
C8503
C8504
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
U8500
BGA
(2 OF 2)
K1 VDDA0
K12 VDDA1
D
C8510
C8515
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
U8500.J1
A1 VDDQ0
A12 VDDQ1
C1 VDDQ2
C4 VDDQ3
C9 VDDQ4
C12 VDDQ5
E1 VDDQ6
E4 VDDQ7
E9 VDDQ8
E12 VDDQ9
J4 VDDQ10
J9 VDDQ11
N1 VDDQ12
N4 VDDQ13
N9 VDDQ14
N12 VDDQ15
R1 VDDQ16
R4 VDDQ17
R9 VDDQ18
R12 VDDQ19
V1 VDDQ20
V12 VDDQ21
U8500.J12

74 73 72 47 9 8
75
PP1V8_S0GPU_ISNS
C8520
10UF
20%
6.3V
X5R
603
75 27 9
C8521
C8522
C8523
C8524
C8525
C8526
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
GPU_FB_B_VREF_DIV
R8530
R8533 1
549
1%
1/16W
MF-LF
402
549
1%
1/16W
MF-LF
402 2
FB_B0_VREF
R8531
R8532
1.33K
1%
1/16W
MF-LF
402 2
C8531
R8534
0.01uF
931
1%
1/16W
MF-LF
402 2
R8535
1.33K
10%
16V
CERM
402
C8550
VSS2 G1
VSS3 G12
VSS4 L1
10UF
20%
6.3V
X5R
603
VSS5 L12
VSS6 V3
C8551
C8552
C8553
C8554
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
C8560
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
U8500.J1
U8500.J12

75 74 73 72 47 9 8
PP1V8_S0GPU_ISNS
C8570
10UF
L11
P1
P4
P9
P12
T1
T4
T9
T12
20%
6.3V
X5R
603
75 27 9
C8571
C8572
C8573
C8574
C8575
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
C8576
0.1uF
10%
16V
X5R
402
GPU_FB_B_VREF_DIV
R8580 1
R8583 1
549
1%
1/16W
MF-LF
402
549
1%
1/16W
MF-LF
402 2
FB_B1_VREF
R8581
R8582
1.33K
C8581
R8584
0.01uF
931
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
R8585
1.33K
10%
16V
CERM
402
1%
1/16W
MF-LF
402 2
VRAM4
IN
95 73
IN
95 73
IN
95 73
IN
95 73
IN
95 75 73
IN
95 75 73
IN
95 75 73
IN
95 75 73
IN
95 75 73
IN
95 75 73
IN
75 73
IN
95 75 73
95 73
95 73
IN
IN
IN
75 73
IN
95 75 73
IN
95 75 73
95 75 73
IN
IN
R8543
VRAM4
1
R8545
121
121
243
1%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
2
OUT FB_B_RDQS<0>
95 73
95 73
A4 ZQ
A9 MF
V4 SEN
95 73
IN
IN
95 75 73
IN
95 75 73
IN
DM2
DM3
E10
N10
V9 RESET
D3 RDQS0
D10 RDQS1
P10 RDQS2
P11 WDQS2
P2 WDQS3
G9 BA0
G4 BA1
H3 BA2
FB_B_BA<0>
FB_B_BA<1>
FB_B_BA<2>
NC
R8548 1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
N3
B2
B3
C2
C3
E2
F3
F2
G3
B11
DQ9
DQ10
B10
C11
DQ11
C10
E11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
D2 WDQS0
D11 WDQS1
IN
95 75 73
CK*
CS0*
WE*
CAS*
RAS*
FB_B_WDQS<1>
FB_B_WDQS<0>
FB_B_WDQS<2>
FB_B_WDQS<3>
IN
E3
DM1
J11 CK
J10
F4
H4
F9
H10
P3 RDQS3
95 73
DM0
BGA
J3 A12/CS1*
OUT FB_B_RDQS<3>
IN
U8500
(1 OF 2)
L9 A11
H9 CKE
OUT FB_B_RDQS<2>
95 73
DQ18
DQ19
DQ20
DQ21
F10
F11
G10
M11
L10
N11
M10
R11
R10
DQ22 T11
DQ23 T10
DQ24 M2
DQ25 L3
DQ26 N2
DQ27 M3
DQ28 R2
DQ29 R3
DQ30 T2
DQ31 T3
FB_B_DQM_L<1>
FB_B_DQM_L<0>
FB_B_DQM_L<2>
FB_B_DQM_L<3>
FB_B_DQ<12>
FB_B_DQ<8>
FB_B_DQ<11>
FB_B_DQ<10>
FB_B_DQ<13>
FB_B_DQ<15>
FB_B_DQ<14>
FB_B_DQ<9>
FB_B_DQ<6>
FB_B_DQ<5>
FB_B_DQ<3>
FB_B_DQ<4>
FB_B_DQ<0>
FB_B_DQ<2>
FB_B_DQ<1>
FB_B_DQ<7>
FB_B_DQ<21>
FB_B_DQ<16>
FB_B_DQ<19>
FB_B_DQ<17>
FB_B_DQ<20>
FB_B_DQ<22>
FB_B_DQ<18>
FB_B_DQ<23>
FB_B_DQ<26>
FB_B_DQ<27>
FB_B_DQ<31>
FB_B_DQ<28>
FB_B_DQ<24>
FB_B_DQ<25>
FB_B_DQ<29>
FB_B_DQ<30>
IN
73 95
95 75 73
IN
IN
73 95
95 75 73
IN
IN
73 95
95 73
IN
IN
73 95
95 73
IN
95 73
IN
BI
73 95
BI
73 95
BI
73 95
BI
95 73
IN
95 75 73
IN
95 75 73
IN
95 75 73
IN
95 75 73
IN
95 75 73
IN
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
95 75 73
IN
75 73
IN
95 75 73
IN
95 73
100
5%
1/16W
MF-LF
402
2
IN
BI
73 95
95 73
BI
73 95
75 73
IN
BI
73 95
95 75 73
IN
BI
73 95
95 75 73
BI
73 95
95 75 73
BI
73 95
R8594
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
IN
IN
IN
R8596
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
1K
121
121
243
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
VRAM4
R8593
VRAM4
1
95 75 73
IN
10%
16V
CERM
402
R8595
OUT FB_B_RDQS<5>
95 73
OUT FB_B_RDQS<4>
95 73
75 74 73
77 76
121
121
243
1%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
2
K9 A0
H11 A1
K10 A2
M9 A3
K4 A4
H2 A5
IN
BI
95 73
IN
BI
73 95
95 73
IN
BI
73 95
95 73
IN
BI
73 95
95 75 73
73 95
IN
BI
BI
73 95
95 75 73
IN
95 75 73
IN
U8550
DM0
E3
BGA
DM1
DM2
DM3
E10
N10
L9 A11
H9 CKE
J11 CK
J10
F4
H4
F9
H10
CK*
CS0*
WE*
CAS*
RAS*
NC
1
243
1%
1/16W
MF-LF
402 2
DQ6
N3
B2
B3
C2
C3
E2
F3
F2
G3
B11
DQ9
DQ10
B10
C11
DQ11
C10
E11
DQ17
DQ18
DQ19
DQ20
DQ21
F10
F11
G10
M11
L10
N11
M10
R11
R10
DQ22 T11
DQ23 T10
DQ24 M2
DQ25 L3
DQ26 N2
P11 WDQS2
P2 WDQS3
R8598 1
DQ4
DQ5
DQ15
DQ16
D3 RDQS0
D10 RDQS1
P10 RDQS2
J2 RFU
DQ3
DQ14
V9 RESET
G9 BA0
G4 BA1
H3 BA2
DQ1
DQ2
DQ12
DQ13
A4 ZQ
A9 MF
V4 SEN
FB_B_BA<0>
FB_B_BA<1>
FB_B_BA<2>
DQ0
DQ7
DQ8
J3 A12/CS1*
D2 WDQS0
D11 WDQS1
95 73
FB_VREF_UNTERM
(1 OF 2)
K3 A6
L4 A7
K2 A8/AP
M4 A9
K11 A10
FB_B_WDQS<6>
FB_B_WDQS<5>
FB_B_WDQS<4>
FB_B_WDQS<7>
73 95
SOT563
OMIT
CRITICAL
P3 RDQS3
73 95
Q8550
SSM6N15FEAPE
OUT FB_B_RDQS<7>
BI
IN
SOT563
R8597
FB_B_DRAM_RST
95 73
SSM6N15FEAPE
FB_B_CLK_P<1>
FB_B_CLK_N<1>
FB_B_CS0_L
FB_B_WE_L
FB_B_CAS_L
FB_B_RAS_L
OUT FB_B_RDQS<6>
0.01UF
FB_B_MA<0>
FB_B_MA<1>
FB_B_UMA<2>
FB_B_UMA<3>
FB_B_UMA<4>
FB_B_UMA<5>
FB_B_MA<6>
FB_B_MA<7>
FB_B_MA<8>
FB_B_MA<9>
FB_B_MA<10>
FB_B_MA<11>
FB_B_CKE
FB_B_MA<12>
95 73
Q8550
C8596
FB_B1_ZQ
FB_B1_MF
FB_B1_SEN
R8549
243
1%
1/16W
MF-LF
402 2
R8592
VOLTAGE=0.9V
VRAM4
1
K3 A6
L4 A7
K2 A8/AP
M4 A9
K11 A10
FB_B_DRAM_RST
95 73
R8590
FB_VREF_UNTERM
IN
K9 A0
H11 A1
K10 A2
M9 A3
K4 A4
H2 A5
FB_B_CLK_P<0>
FB_B_CLK_N<0>
FB_B_CS0_L
FB_B_WE_L
FB_B_CAS_L
FB_B_RAS_L
OUT FB_B_RDQS<1>
VRAM4
1
OMIT
CRITICAL
FB_B_MA<0>
FB_B_MA<1>
FB_B_LMA<2>
FB_B_LMA<3>
FB_B_LMA<4>
FB_B_LMA<5>
FB_B_MA<6>
FB_B_MA<7>
FB_B_MA<8>
FB_B_MA<9>
FB_B_MA<10>
FB_B_MA<11>
FB_B_CKE
FB_B_MA<12>
95 73
95 73
IN
R8547
FB_B0_ZQ
FB_B0_MF
FB_B0_SEN
95 75 73
SOT563
MFHIGH
IN
95 75 73
SOT563
K4J10324QD-HC11
75 74 73
77 76
Q8500
MFHIGH
SSM6N15FEAPE
0.01UF
10%
16V
CERM
402
SSM6N15FEAPE
32MX32-900MHZ-MFH
243
1%
1/16W
MF-LF
402
VSSA0 J1
VSSA1 J12
10%
16V
CERM
402
MFHIGH
121
1%
1/16W
MF-LF
402

VRAM4
VSS7 V10
C8582
DQ27 M3
DQ28 R2
DQ29 R3
MFHIGH
121
1%
1/16W
MF-LF
402
K4J10324QD-HC11
1K
5%
1/16W
MF-LF
402
95 75 73
R8546
32MX32-900MHZ-MFH
R8544
MFHIGH
R8542
VSS5 L12
VSS6 V3
FB_B3_VREF_UNTERM_L
FB_B1_VREF_UNTERM_L
Q8500
C8546
MFHIGH
R8540

(NONE)
0.01uF
931
1%
1/16W
MF-LF
402 2
VSS2 G1
VSS3 G12
VSS4 L1
FB_B_CLK1_TERM
VOLTAGE=0.9V
VRAM4
1
BGA
(2 OF 2)

- =PP1V8_S0_FB_VDD
- =PP1V8_S0_FB_VREF_B
VSS0 A3
VSS1 A10
H1 VREF0
H12 VREF1
FB_B3_VREF
FB_B_CLK0_TERM
VRAM4
U8550
A1 VDDQ0
A12 VDDQ1
C1 VDDQ2
C4 VDDQ3
C9 VDDQ4
C12 VDDQ5
E1 VDDQ6
E4 VDDQ7
E9 VDDQ8
E12 VDDQ9
J4 VDDQ10
J9 VDDQ11
N1 VDDQ12
N4 VDDQ13
N9 VDDQ14
N12 VDDQ15
R1 VDDQ16
R4 VDDQ17
R9 VDDQ18
R12 VDDQ19
V1 VDDQ20
V12 VDDQ21
C8565
0.1uF
FB_B2_VREF_UNTERM_L
FB_B0_VREF_UNTERM_L
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
K1 VDDA0
K12 VDDA1
10%
16V
CERM
402
0.1uF
VSSA0 J1
VSSA1 J12
0.01uF
1%
1/16W
MF-LF
402 2
A2
A11
F1
F12
M1
M12
V2
V11
VSS7 V10
C8532
931
1%
1/16W
MF-LF
402 2
CRITICAL
PP1V8_S0GPU_ISNS
VSS0 A3
VSS1 A10
H1 VREF0
H12 VREF1
FB_B2_VREF
K4J10324QD-HC11
C8500
A2
A11
F1
F12
M1
M12
V2
V11
32MX32-900MHZ-MFH
74 73 72 47 9 8
75
1
Page Notes
OMIT
K4J10324QD-HC11
32MX32-900MHZ-MFH
DQ30 T2
DQ31 T3
FB_B_DQM_L<6>
FB_B_DQM_L<5>
FB_B_DQM_L<4>
FB_B_DQM_L<7>
FB_B_DQ<49>
FB_B_DQ<50>
FB_B_DQ<48>
FB_B_DQ<51>
FB_B_DQ<53>
FB_B_DQ<55>
FB_B_DQ<54>
FB_B_DQ<52>
FB_B_DQ<41>
FB_B_DQ<42>
FB_B_DQ<40>
FB_B_DQ<47>
FB_B_DQ<44>
FB_B_DQ<45>
FB_B_DQ<43>
FB_B_DQ<46>
FB_B_DQ<34>
FB_B_DQ<35>
FB_B_DQ<33>
FB_B_DQ<32>
FB_B_DQ<37>
FB_B_DQ<38>
FB_B_DQ<39>
FB_B_DQ<36>
FB_B_DQ<56>
FB_B_DQ<57>
FB_B_DQ<63>
FB_B_DQ<59>
FB_B_DQ<58>
FB_B_DQ<62>
FB_B_DQ<61>
FB_B_DQ<60>
IN
73 95
IN
73 95
IN
73 95
IN
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
GDDR3 Frame Buffer B (Top)
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
SYNC_MASTER=MUXGFX

J2 RFU
R8599
100
SIZE
5%
1/16W
MF-LF
402
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
75
97
8
Page Notes
7
110mA

- =PP3V3_GPU_VDD33
- =PP3V3_GPI_MIO
- =PP1V2_GPU_PLLVDD
- =PP1V2_GPU_H_PLLVDD
- =PP1V2_GPU_VID_PLLVDD
81 79 77 76 70 69 8 6
U8000
NB9P-GS
BGA
J10
1
2

(NONE)
1
PP3V3_S0GPU
76 70 69 8 6
81 79 77
Typically <??mA
C8600
C8601
0.47UF
0.47UF
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
C8692
C8694
C8696
1UF
10%
2 6.3V
CERM
0.022UF
0.022UF
0.1UF
0.47UF
10%
16V
CERM-X5R
402
10%
16V
CERM-X5R
402
20%
10V
CERM
402
10%
6.3V
CERM-X5R
402
C8691
C8693
C8695
0.1UF
0.47UF
10%
16V
CERM-X5R
402
20%
10V
CERM
402
10%
6.3V
CERM-X5R
402
J13
402
J25
RFU0
J26
RFU1
NC
0.022UF
10%
16V
CERM-X5R
402
C8698
C8697
0.022UF
2
J11
J12
NC
AK14
K9
77
77
77
R8696
1%
1/16W
MF-LF
2 402
C3
NC_GPU_ROM_CS_L
GPU_ROM_SCLK
GPU_ROM_SI
GPU_ROM_SO
D4
D3
C4
40.2K
1%
1/16W
MF-LF
2 402
GPU_STRAP_REF_3V3_PD
GPU_STRAP_REF_MIOB_PD
PP3V3_S0GPU
C8610
C8611
1UF
1
49.9
1%
1/16W
MF-LF
402
10%
6.3V
CERM
402
R8621
1%
1/16W
MF-LF
402
N9
M9
R8616 1
GPU_MIOA_PU_GND
GPU_MIOB_PU_GND
1
R8623
49.9
49.9
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
U9
1UF
10%
6.3V
CERM
402
R9
T9
10K
5%
1/16W
MF-LF
402
76
76
R8618
10K
5%
1/16W
MF-LF
402
GPU_TESTMODE_PD
76
GPU_MIOA_VREF
GPU_MIOB_VREF
76
R8617
1
1
10K
5%
1/16W
MF-LF
402
C8617
1
1
10K
0.1uF
2
R8619
10%
16V
X5R
402
5%
1/16W
MF-LF
402
C8619
R8660
76
10K
76
0.1uF
2
10%
16V
X5R
402
5%
1/16W
MF-LF
402
76
GPU_MIOA_PD_VDDQ
GPU_MIOA_PU_GND
GPU_MIOB_PD_VDDQ
GPU_MIOB_PU_GND
AP35
N5
AF1
U5
T5
AA7
AA6
AF9
L8630
FERR-220-OHM
PP1V1_S0GPU_REG
VOLTAGE=1.2V
0402
C8633
AE9
65mA
PP1V1_GPU_PLLVDD_F
AD9
C8630
4.7UF
4.7UF
20%
6.3V
CERM
603
20%
6.3V
CERM
603
MIOA_VDDQ_1
MIOA_VDDQ_2
MIOA_VDDQ_3
MIOA_VDDQ_4
MIOB_VDDQ_1
MIOB_VDDQ_2
MIOB_VDDQ_3
MIOB_VDDQ_4
TESTMODE
MIOA_VREF
MIOB_VREF
MIOA_CAL_PD_VDDQ
MIOA_CAL_PU_GND
MIOB_CAL_PD_VDDQ
MIOB_CAL_PU_GND
SP_PLLVDD
PLLVDD
VID_PLLVDD
C8631
0.1uF
10%
16V
X5R
402
B
L8635
83 78 76 73 71 8
FERR-220-OHM
PP1V1_S0GPU_REG
C8637
25mA
PP1V1_GPU_H_PLLVDD_F
VOLTAGE=1.2V
0402
C8635
4.7UF
4.7UF
20%
6.3V
CERM
603
20%
6.3V
CERM
603
95 77
77
77
10%
16V
X5R
402
95 77
OUT
IN
D1
GPU_CLK27M_SS
D2
FERR-220-OHM
PP1V1_S0GPU_REG
2
0402
C8643
C8640
4.7UF
4.7UF
20%
6.3V
CERM
603
20%
6.3V
CERM
603
50mA
PP1V1_GPU_VID_PLLVDD_F
VOLTAGE=1.2V
C8641
0.1uF
B2
GPU_XTALOUTBUFF
L8640
83 78 76 73 71 8
B1
XTAL_IN
XTAL_OUT
C8636
0.1uF
IN
OUT
GPU_CLK27M
GPU_XTALOUT
10%
16V
X5R
402
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
K1
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
H4
HDA_SDI
HDA_SDO
HDA_SYNC
HDA_BCLK
HDA_RST*
C7
B7
D7
D6
NC_CPU_HDA_SDI
NC_CPU_HDA_SD0
NC_CPU_HDA_SYNC
NC_CPU_HDA_BCLK
NC_CPU_HDA_RST_L
SPDIF
A5
NC_GPU_SPDIF
A4
TP_GPU_BUFRST_L
AP14
AN14
JTAG_MCP_TCK
GPU_JTAG_TDI
TP_GPU_JTAG_TDO
GPU_JTAG_TMS
JTAG_MCP_TRST_L
BUFRST*
AA9
W9
Y9
76
83 78 76 73 71 8
STRAP_REF_3V3
STRAP_REF_MIOB
(IPD)
AB9
GPU_MIOA_PD_VDDQ
GPU_MIOB_PD_VDDQ
R8622 1
ROM_CS*
ROM_SCLK
ROM_SI
ROM_SO
R8697
P9
49.9
RFU1_GND
PP3V3_S0GPU
81 79 77 76 70 69 8 6
R8620 1
RFU0_GND
40.2K
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
SYMBOL 6 OF 9
C8602
0.47UF
2
C8690
77
81 79 77 76 70 69 8 6
OMIT
PP3V3_S0GPU
J9

(NONE)
XTAL_OUTBUFF
XTAL_SSIN
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST*
MIOA_CLKIN
MIOA_CLKOUT
MIOA_CLKOUT*
MIOA_CTL3
MIOA_DE
MIOA_D0
MIOA_D1
MIOA_D2
MIOA_D3
MIOA_D4
MIOA_D5
MIOA_D6
MIOA_D7
MIOA_D8
MIOA_D9
MIOA_D10
MIOA_D11
MIOA_D12
MIOA_D13
MIOA_D14
MIOA_HSYNC
MIOA_VSYNC
K2
K3
H3
H2
H1
H5
H6
J7
K4
K5
H7
J4
J6
L1
L2
L4
M4
L7
L5
K6
L6
M6
A7
AN16
AR14
AP16
N4
R4
T4
P5
N2
N1
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6
N3
L3
AE1
NC_GPU_GPIO_0
DP_EG_HPD
TP_LVDS_EG_BKL_PWM
EG_LCD_PWR_EN
EG_BKLT_EN
TP_GPU_GSTATE<0>
GPU_GPIO_6
GPIO7_FBVDD_ALTVO
SMC_GFX_OVERTEMP_R_L
SMC_GFX_THROTTLE_R_L
FB_VREF_UNTERM
GPU_VCORE_VID0
GPU_VCORE_VID1
GPU_VCORE_VID2
TP_GPU_VCORE_VID3
NC_GPU_GPIO_15
GPU_GPIO_16
NC_GPU_GPIO_17
NC_GPU_GPIO_18
NC_GPU_GPIO_19
NC_GPU_GPIO_20
NC_GPU_GPIO_21
NC_GPU_GPIO_22
NC_GPU_GPIO_23
BI
77
BI
77 81
BI
77
BI
77 84
BI
77 84
BI
77
BI
77
BI
77 83
BI
77
BI
77
BI
73 74 75 77
BI
77 79
BI
77 79
BI
77 79
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
OUT
77
OUT
77
OUT
77
OUT
77
OUT
77
IN
77
OUT
NC_GPU_MIOA_CLKIN
NC_GPU_MIOA_CLKOUT_P
NC_GPU_MIOA_CLKOUT_N
NC_GPU_MIOA_CTL3
TP_GPU_MIOA_DE
TP_GPU_MIOA_D<0>
TP_GPU_MIOA_D<1>
TP_GPU_MIOA_D<2>
TP_GPU_MIOA_D<3>
TP_GPU_MIOA_D<4>
TP_GPU_MIOA_D<5>
TP_GPU_MIOA_D<6>
TP_GPU_MIOA_D<7>
TP_GPU_MIOA_D<8>
TP_GPU_MIOA_D<9>
NC_GPU_MIOA_D<10>
NC_GPU_MIOA_D<11>
NC_GPU_MIOA_D<12>
NC_GPU_MIOA_D<13>
NC_GPU_MIOA_D<14>
NC_GPU_MIOA_HSYNC
NC_GPU_MIOA_VSYNC
IN
6 13 21
IN
OUT
IN
IN
6 13 21
IN
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
W2
THERMDP
THERMDN
B5
B4
GPU_TDIODE_P
GPU_TDIODE_N
IN
48 77 96
OUT
48 77 96
PGOOD_OUT*
C5
TP_GPU_PGOOD_OUT_L
OUT
V4
W4
W3
Y5
Y1
Y2
Y3
AB3
AB2
AB1
AC4
AC1
AC2
AC3
AE3
AE2
U6
W6
Y6
W5
W7
V7
W1
IN
77
NC_GPU_MIOB_CLKIN
NC_GPU_MIOB_CLKOUT_P
NC_GPU_MIOB_CLKOUT_N
NC_GPU_MIOB_CTL3
NC_GPU_MIOB_DE
NC_GPU_MIOB_D<0>
NC_GPU_MIOB_D<1>
NC_GPU_MIOB_D<2>
NC_GPU_MIOB_D<3>
NC_GPU_MIOB_D<4>
NC_GPU_MIOB_D<5>
NC_GPU_MIOB_D<6>
NC_GPU_MIOB_D<7>
NC_GPU_MIOB_D<8>
NC_GPU_MIOB_D<9>
NC_GPU_MIOB_D<10>
NC_GPU_MIOB_D<11>
NC_GPU_MIOB_D<12>
NC_GPU_MIOB_D<13>
NC_GPU_MIOB_D<14>
GPU_STRAP<0>
GPU_STRAP<1>
GPU_STRAP<2>
NC_GPU_MIOB_HSYNC
NC_GPU_MIOB_VSYNC
MIOB_CLKIN
MIOB_CLKOUT
MIOB_CLKOUT*
MIOB_CTL3
MIOB_DE
MIOB_D0
MIOB_D1
MIOB_D2
MIOB_D3
MIOB_D4
MIOB_D5
MIOB_D6
MIOB_D7
MIOB_D8
MIOB_D9
MIOB_D10
MIOB_D11
MIOB_D12
MIOB_D13
MIOB_D14
MIOB_D15
MIOB_D16
MIOB_D17
MIOB_HSYNC
MIOB_VSYNC
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
BI
77
NV G96 GPIO/MIO/Misc
SYNC_MASTER=MUXGFX

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
76
97
Renamed signals
Native Func
76
77
81
76
77
76
77
NC_GPU_GPIO_0
DP_EG_HPD
IN
MAKE_BASE=TRUE
LCD0_BL_PWM
TP_LVDS_EG_BKL_PWM
TP_LVDS_EG_BKL_PWM
76 77 81
76 77
NC_GPU_GPIO_17
77 76
77 76
EG_LCD_PWR_EN
84
76
77
EG_BKLT_EN
NC_GPU_GPIO_18
77 76
76 77 84
DVI_MODE1
76 77 84
77 76
NC_GPU_GPIO_19
76 77
77 76
NC_GPU_GPIO_20
HDMI_DETECT1
83
76
77
GPIO7_FBVDD_ALTVO
76 77
HPDD
77 76
NC_GPU_GPIO_21
77 76
NC_GPU_GPIO_22
77 76
NC_GPU_GPIO_23
HPDF
76 77 83
SWAPRDY_A
GP
79
76
77
GPU_VCORE_VID1
79
76
77
GPU_VCORE_VID2
76
77
GPU_VCORE_VID1
MAKE_BASE=TRUE
GPU_VCORE_VID2
MAKE_BASE=TRUE
TP_GPU_VCORE_VID3
76 77
81 78 77
DP_EG_DDC_CLK
76 77
81 78 77
DP_EG_DDC_DATA
MAKE_BASE=TRUE
NC_GPU_GPIO_23
NO_TEST=TRUE
GPU_ROM_SCLK
DP_EG_DDC_DATA
Unused I2C Buses
77 73
78 77
NC_GPU_I2CC_SCL
78 77
NC_GPU_I2CC_SDA
NC_GPU_I2CC_SCL
NO_TEST=TRUE
76 77 79
78 77
NC_GPU_I2CD_SCL
OUT
76 77 79
78 77
NC_GPU_I2CD_SDA
NC_GPU_I2CC_SDA
MAKE_BASE=TRUE
NC_GPU_I2CD_SCL
NC_GPU_I2CD_SDA
NC_GPU_I2CE_SCL
NC_GPU_I2CE_SCL
MAKE_BASE=TRUE
Strapping Bit 3
Strapping Bit 2
Strapping Bit 1
R87091
R87111
2.0K
4.99K
4.99K
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
XCLK_277
PCI_DEVID[4]
ROM_SI
NC_GPU_I2CE_SDA
78 77
NC_GPU_I2CH_SCL
R8712
2.0K
15.0K
3GIO_PADCFG[3]
3GIO_PADCFG[2]
USER[3]
USER[2]
Strap S1/S2 Bit[3:0] PU/PD Rval

0 0000 PD 5k
1 0001 PD 10k
2 0010 PD 15k
3 0011 PD 20k
4 0100 PD 25k
5 0101 PD 30k
6 0110 PD 35k
7 0111 PD 45k
1%
1/16W
MF-LF
402 2
USER[1]
NC_GPU_I2CH_SCL
NO STUFF
MAKE_BASE=TRUE
1%
1/16W
MF-LF
402 2
77
78
NO_TEST=TRUE
(I2CS requires pullups even if not used)
78 77
TP_LVDS_EG_B_CLK_P
78 77
TP_LVDS_EG_B_CLK_N
GPU_STRAP<0>
BI
GPU_STRAP<1>
78 77
NC_LVDS_EG_A_DATA_P<3>
78 77
NC_LVDS_EG_A_DATA_N<3>
77 76
77 76
NC_GPU_MIOA_CTL3
77 76
TP_GPU_MIOA_DE
2.0K
76
76
BOM OPTION
R8708
VRAM_512_SAMSUNG
R8708
VRAM_512_HYNIX
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
114S0361
RES,MTL FILM,1/16W,30.1K,1,0402,SMD,LF
R8708
VRAM_512_QIMONDA
114S0343
R8708
VRAM_256_SAMSUNG
1%
1/16W
MF-LF
402 2
114S0331
R8708
VRAM_256_HYNIX
114S0378
R8707
VRAM_1024_SAMSUNG
NC_GPU_MIOA_CLKIN
NC_GPU_MIOA_CLKIN
NC_GPU_MIOA_HSYNC
77 76
NC_GPU_MIOA_VSYNC
95 77 76
PP3V3_S0
GPU_CLK27M
IN
NO STUFF
R8782
10M
R8750
R8751
R8752
R8753
4.7K
4.7K
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
CRITICAL
Y8780
81 78 77
Q8742
DP_CA_DET_EG_FET
1
R8742
77 76
81 79 77 76 70 69 8 6
OUT
DP_CA_DET
IN
PP3V3_S0GPU
DP_CA_DET_EG
IN
NC_GPU_MIOB_VSYNC
MAKE_BASE=TRUE
NC_GPU_MIOB_VSYNC
76 77
NC_GPU_MIOB_HSYNC
76 77
NO_TEST=TRUE
NC_GPU_MIOB_HSYNC
MAKE_BASE=TRUE
NO_TEST=TRUE
Unused Clocks
2
95 77 76
76
GPU_CLK27M_SS
GPU_XTALOUTBUFF
GPU_SS_INT
R8797
R8780 1
R8781 1
2.2K
10K
10K
BI
DP_EG_DDC_DATA
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
IN
DP_IG_DDC_CLK
DP_IG_DDC_DATA
77 76
77 76
84
5%
1/16W
MF-LF
402
R8793
R8798
R8799
R8794
NO STUFF
R8795
10K
10K
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SMC_GFX_OVERTEMP_L
OUT
42
OUT
42
OUT
76 77 84
EG_BKLT_EN
OUT
76 77 84
GPIO7_FBVDD_ALTVO
OUT
76 77 83
OUT
73 74 75 76 77
5%
1/16W MF-LF 402
5%
SMC_GFX_THROTTLE_L
1/16W MF-LF 402
EG_LCD_PWR_EN
G96 GPIOs & Straps

SYNC_MASTER=MUXGFX

DP_CA_DET_EG_PLD
SIZE
Isolation FETs for DP MUX inputs
DRAWING NUMBER
D
APPLE INC.
REV.
051-7892
SCALE
SHT
NONE
18 81 82 84
R8792
76
77
76
77
2.2K
BI
GPU_MIOB_D<14..0>
NO_TEST=TRUE
DP_EG_DDC_CLK
R8743
0
76 77
MAKE_BASE=TRUE
5%
50V
CERM
402
FB_VREF_UNTERM
NC_GPU_MIOB_D<14..0>
SOD-VESM-HF
EG_DP_CA_DET
76 77
NC_GPU_MIOB_DE
C8781
1%
1/16W
MF-LF
402 2
81 18 9
76 77
NC_GPU_MIOB_CTL3
NO_TEST=TRUE
12pF
GPU_XTALOUT
SSM3K15FV
100K
81 18 9
SM-2
5%
50V
CERM
402
IN
PP3V3_S0GPU
DP_CA_DET_EG_FET
27MHZ
NC
NC
R8796
81 78 77
GPU_CLK27M_XTALOUT_R
76 77
NO_TEST=TRUE
NC_GPU_MIOB_DE
MAKE_BASE=TRUE
76
76 77
NO_TEST=TRUE
MAKE_BASE=TRUE
12pF
NC_GPU_MIOB_CLKIN
NO_TEST=TRUE
MAKE_BASE=TRUE
C8780
5%
1/16W
MF-LF
402
PP3V3_S0GPU
76 77
NO_TEST=TRUE
NC_GPU_MIOB_CTL3
77 76
76 77
NC_GPU_MIOA_VSYNC
NO_TEST=TRUE
GPU 27MHz Crystal
NC_GPU_MIOA_HSYNC
NO_TEST=TRUE
NC_GPU_MIOB_CLKIN
77 76
76 77
GPU_MIOA_D<14..10>
NO_TEST=TRUE
77 76
G96 HDCP ROM APN is 341S2272, blank device is 335S0574.
VRAM_1024_QIMONDA
82 81 80 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84
76 77
NO_TEST=TRUE
NC_GPU_MIOA_D<14..10>
MAKE_BASE=TRUE
R8783
81 79 77 76 70 69 8 6
76 77
TP_GPU_MIOA_DE
GPU_MIOA_D<9..0>
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402 2
TP_GPU_MIOA_D<9..0>
MAKE_BASE=TRUE
R87061
1%
1/16W
MF-LF
402 2
76 77
NC_GPU_MIOA_CTL3
NO_TEST=TRUE
MAKE_BASE=TRUE
45.3K
76 77
MAKE_BASE=TRUE
10K
5%
1/16W
MF-LF
402 2
MAKE_BASE=TRUE
R87041
NO_TEST=TRUE
MAKE_BASE=TRUE
R87021
77 78
NO_TEST=TRUE
MAKE_BASE=TRUE
R8707
77 78
NC_LVDS_EG_B_DATA_N<3>
NO_TEST=TRUE
MAKE_BASE=TRUE
NO STUFF
77
MAKE_BASE=TRUE
77 78
NC_LVDS_EG_B_DATA_P<3>
G96 MIOA_DE and MIOA_D<9..0> are used as Debug Port.
114S0368
77 78
NO_TEST=TRUE
77 76
GPU_STRAP<2>
81 79 77 76 70 69 8 6
MAKE_BASE=TRUE
114S0378
114S0361
77 78
NO_TEST=TRUE
MAKE_BASE=TRUE
BI
77 78
NO_TEST=TRUE
MAKE_BASE=TRUE
2 4
76
TP_LVDS_EG_B_CLK_P
TP_LVDS_EG_B_CLK_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
10K
R87051
73 77
NO_TEST=TRUE
MAKE_BASE=TRUE
BI
76
NO STUFF
73 77
NC_FB_B_CS1_L
NO_TEST=TRUE
MAKE_BASE=TRUE
3GIO_PADCFG[0]
CRITICAL
76 77
NC_FB_A_CS1_L
NO_TEST=TRUE
NC_FB_B_CS1_L
I2CS ties into SMBus connection page
10K
R87031
MAKE_BASE=TRUE
NC_FB_A_CS1_L
USER[0]
REFERENCE DES
73 77
NC_GPU_ROM_CS_L
77 78
NC_GPU_I2CH_SDA
Strap S1/S2 Bit[3:0] PU/PD Rval

8 1000 PU 5k
9 1001 PU 10k
A 1010 PU 15k
B 1011 PU 20k
C 1100 PU 25k
D 1101 PU 30k
E 1110 PU 35k
F 1111 PU 45k
DESCRIPTION
73 77
NC_FBC_CMD30
NO_TEST=TRUE
MAKE_BASE=TRUE
QTY
73 77
NC_FBA_CMD30
NO_TEST=TRUE
NC_GPU_ROM_CS_L
PCI_DEVID[0]
3GIO_PADCFG[1]
73 77
NC_FBC_CMD29
NO_TEST=TRUE
NC_GPU_I2CH_SDA
77 76
PART NUMBER
45.3K
MAKE_BASE=TRUE
NC_FBC_CMD30
RAMCFG[0]
PCI_DEVID[1]
73 77
77 78
PP3V3_S0GPU
R87011
NC_FBA_CMD30
78 77
R8710
5%
1/16W
MF-LF
402 2
PCI_DEVID[2]
NC_FBC_CMD28
NC_FBA_CMD29
NO_TEST=TRUE
PEX_PLLEN_TERM100
RAMCFG[1]
73
77
NO_TEST=TRUE
MAKE_BASE=TRUE
77 78
NC_GPU_I2CE_SDA
MAKE_BASE=TRUE
TVMODE[0]
SLOT_CLK_CFG
RAMCFG[2]
PCI_DEVID[3]
STRAP 1
45.3K
76
NC_FBC_CMD29
78 77
R8708
1%
1/16W
MF-LF
402 2
TVMODE[1]
SUB_VENDOR
RAMCFG[3]
STRAP 2
NO STUFF
1
TVMODE[2]
77 73
NO_TEST=TRUE
78 77
Strapping Bit 0
77
78
76
77
73 77
NO_TEST=TRUE
MAKE_BASE=TRUE
77 78
NO_TEST=TRUE
73
77
77 73
NO_TEST=TRUE
MAKE_BASE=TRUE
78 77
77
78
NO_TEST=TRUE
MAKE_BASE=TRUE
76 77
77 78
73 77
NC_FBA_CMD28
NO_TEST=TRUE
NC_FBA_CMD29
MAKE_BASE=TRUE
77 73
73 77
NC_FBB_MA<13>
NO_TEST=TRUE
MAKE_BASE=TRUE
OUT
ROM_SCLK
NO STUFF
OMIT
81 79 77 76 70 69 8 6
MAKE_BASE=TRUE
NC_FBC_CMD28
77 78 81
76 77
NC_FBA_MA<13>
NO_TEST=TRUE
NC_FBA_CMD28
MAKE_BASE=TRUE
76 77 79
STRAP 0
GPU_ROM_SO
77 73
77
78 81
76 77
NC_CPU_HDA_RST_L
NO_TEST=TRUE
MAKE_BASE=TRUE
DP_EG_DDC_CLK
76 77
NC_CPU_HDA_BCLK
NO_TEST=TRUE
NC_FBB_MA<13>
77 78 81
NC_CPU_HDA_SYNC
NO_TEST=TRUE
NC_CPU_HDA_RST_L
MAKE_BASE=TRUE
OUT
ROM_SO
R87071
IN
LVDS_EG_DDC_DATA
MAKE_BASE=TRUE
OMIT
IN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
LVDS_EG_DDC_DATA
76 77
NO_TEST=TRUE
NC_CPU_HDA_BCLK
NC_FBA_MA<13>
77 78 81
76 77
NC_CPU_HDA_SD0
NO_TEST=TRUE
MAKE_BASE=TRUE
77 76
48
76 77 96
LVDS_EG_DDC_CLK
MAKE_BASE=TRUE
GPU_VCORE_VID0
PP3V3_S0GPU
76
LVDS_EG_DDC_CLK
81 78 77
78 77
76
GPU_TDIODE_N
76 77
73 74 75 76 77
Physical
Strapping Pin
OUT GPU_ROM_SI
GPU_TDIODE_N
MAKE_BASE=TRUE
NC_CPU_HDA_SYNC
48 76 77
96
NC_CPU_HDA_SDI
NO_TEST=TRUE
NC_CPU_HDA_SD0
MAKE_BASE=TRUE
Config Straps
76
GPU_TDIODE_P
76 77
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PWR_CTL1
NC_GPU_SPDIF
MAKE_BASE=TRUE
MAKE_BASE=TRUE
81 78 77
76 77
MAKE_BASE=TRUE
GPU_TDIODE_P
77 76
MAKE_BASE=TRUE
PWR_CTL0
81 79 77 76 70 69 8 6
76
77 76
77 95
76 77
FB_VREF_UNTERM
AC_DET
TP_GPU_VCORE_VID3
GPU_CLK27M_SS
76 77
NC_GPU_SPDIF
NC_CPU_HDA_SDI
MAKE_BASE=TRUE
SLI_SYNC
GPU_VCORE_VID0
GPU_CLK27M_SS
76 77
MAKE_BASE=TRUE
MEM_VREF
FB_VREF_UNTERM
76
77
MAKE_BASE=TRUE
MAKE_BASE=TRUE
FAN_PWM
76 77 95
MAKE_BASE=TRUE
NC_GPU_GPIO_22
MAKE_BASE=TRUE
76
77
77
75
73
74
76
79
76
77
96 77 76 48
MAKE_BASE=TRUE
GPIO7_FBVDD_ALTVO
THERM
96 77 76 48
76 77
NC_GPU_GPIO_21
MAKE_BASE=TRUE
76 77
GPU_CLK27M
MAKE_BASE=TRUE
NC_GPU_GPIO_20
MAKE_BASE=TRUE
76
77
95 77 76
MAKE_BASE=TRUE
TP_GPU_GSTATE<1>
VID2/MEM_VID
GPU_XTALOUT
MAKE_BASE=TRUE
TP_GPU_GSTATE<0>
VID1
GPU_GPIO_6
NC_GPU_GPIO_17
NC_GPU_GPIO_19
MAKE_BASE=TRUE
76
77
MAKE_BASE=TRUE
MAKE_BASE=TRUE
VID0
TP_GPU_GSTATE<0>
EG_DP_CA_DET
NC_GPU_GPIO_18
MAKE_BASE=TRUE
EG_BKLT_EN
GPU_CLK27M
MAKE_BASE=TRUE
MAKE_BASE=TRUE
EG_LCD_PWR_EN
LCD0_BL_EN
95 77 76
76 77
MAKE_BASE=TRUE
HDMI_DETECT0
MAKE_BASE=TRUE
LCD0_VDD
GPU_XTALOUT
MAKE_BASE=TRUE
NC_GPU_GPIO_15
MAKE_BASE=TRUE
DVI_MODE0
GPU_GPIO_16
76
GPIOs
HPDE
NC_GPU_GPIO_15
77 76
76 77
MAKE_BASE=TRUE
HPDC
DP_EG_HPD
84
76
77
76
77
Native Func
GPIOs
GP
NC_GPU_GPIO_0
Unused signals
A.0.0
OF
77
97
Page Notes
Sum of peak currents: 240mA

- =PP1V8_GPU_IFPX
- =PP3V3_GPU_IFPCD_IOVDD
70 8
L8800
?mA peak per diff pair

?mA peak for all pairs
FERR-220-OHM
PP1V8_GPUIFPX
PP1V8_GPU_IFPAB_IOVDD_F
VOLTAGE=1.8V
0402
C8800

(NONE)

(NONE)
C8801
C8803
0.1UF
4.7UF
20%
6.3V
CERM
603
20%
10V
CERM
402
OMIT
0.1UF
20%
10V
CERM
402
Place at AG9
U8000
NB9P-GS
BGA
Place at AG10
AG9
AG10
GPU_IFPEF_RSET
GPU_IFPCD_RSET
GPU_IFPAB_RSET
L8805
78
78
R8855
1K
R8850
1K
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
PP1V1_GPU_IFPCD_IOVDD_F
78
PP1V1_GPU_IFPEF_IOVDD_F
FERR-220-OHM
1
78
PP1V8_GPU_IFPAB_PLLVDD_F
0402
1
C8806
4.7UF
0.1UF
20%
6.3V
CERM
603
20%
10V
CERM
402
VOLTAGE=1.8V
78
78
78
1%
1/16W
MF-LF
2 402
78
78
L8810
PP1V1_S0GPU_REG
?mA peak per diff pair

?mA peak for all pairs
C8810
20%
6.3V
CERM
603
C8811
C8813
0.1UF
4.7UF
20%
10V
CERM
402
VOLTAGE=1.1V
0.1UF
20%
10V
CERM
402
Place at AJ8
81 77
BI
PP1V8_GPU_IFPCD_PLLVDD_F
GPU_IFPCD_RSET
AJ9
AK7
PP1V8_GPU_IFPEF_PLLVDD_F
GPU_IFPEF_RSET
AJ6
81 77
BI
AL1
78
G1
G4
LVDS_EG_DDC_CLK
LVDS_EG_DDC_DATA
Place at AK8
I2CS must be pulled up if not used

I2CS addr fixed at 0x9E,0x9F
L8815
GPU_IFPAB_RSET
PP1V1_GPU_IFPCD_IOVDD_F
0402
1
AJ11
1K
FERR-220-OHM
AE7
AD7
AK9
R8851
83 76 73 71 8
AJ8
AK8
80mA peak
C8805
78
SYMBOL 5 OF 9
IFPA_TXC
IFPA_IOVDD
IFPB_IOVDD
IFPA_TXC*
IFPC_IOVDD
IFPA_TXD0
IFPD_IOVDD
IFPA_TXD0*
IFPE_IOVDD
IFPA_TXD1
IFPF_IOVDD
IFPA_TXD1*
IFPAB_PLLVDD
IFPA_TXD2
IFPAB_RSET
IFPA_TXD2*
IFPA_TXD3
IFPCD_PLLVDD
IFPA_TXD3*
IFPCD_RSET
IFPB_TXC
IFPEF_PLLVDD
IFPB_TXC*
IFPEF_RSET
IFPB_TXD4
IFPB_TXD4*
IFPB_TXD5
IFPB_TXD5*
IFPB_TXD6
IFPB_TXD6*
I2CA_SCL
I2CA_SDA
IFPB_TXD7
IFPB_TXD7*
77
BI
77
BI
E3
NC_GPU_I2CC_SCL
NC_GPU_I2CC_SDA
E4
I2CC_SCL
I2CC_SDA
FERR-220-OHM
1
160mA peak
PP1V8_GPU_IFPCD_PLLVDD_F
0402
C8815
78
PP1V8_GPU_IFPEF_PLLVDD_F
78
20%
6.3V
CERM
603
0.1UF
4.7UF
PP1V1_GPU_IFPEF_IOVDD_F
C8816
VOLTAGE=1.8V
20%
10V
CERM
402
94 53 48 45 42
BI
94 53 48 45 42
BI
R8856
E2
E1
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
I2CS_SCL
I2CS_SDA
I2CS must be pulled up if not used.

I2CS addr fixed at 0x9E,0x9F
Power inputs must be pulled down if not used

1
78
77
BI
77
BI
F6
NC_GPU_I2CH_SDA
NC_GPU_I2CH_SCL
G6
I2CH_SCL
I2CH_SDA
R8857
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
81 77
BI
81 77
BI
77
BI
77
BI
77
BI
77
BI
G3
G2
DP_EG_DDC_CLK
DP_EG_DDC_DATA
F4
G5
NC_GPU_I2CD_SCL
NC_GPU_I2CD_SDA
D5
NC_GPU_I2CE_SCL
NC_GPU_I2CE_SDA
E5
I2CB_SCL
I2CB_SDA
I2CD_SCL
I2CD_SDA
I2CE_SCL
I2CE_SDA
AK12
NC
AK13
NC
AC6
GPU_DACA_VDD
GPU_DACB_VDD
GPU_DACC_VDD
1
R8852
R8853
AC5
NCAB6
NC
R8854
10K
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
AG7
AK6
NC
AH7
NC
AM12
AM8
AL8
AM10
AM9
AK10
AL10
AK11
AL11
AP13
AN13
AN8
AP8
AP10
AN10
AR11
AR10
AN11
AP11
IFPC_AUX
IFPC_AUX*
AP2
IFPC_L0
IFPC_L0*
IFPC_L1
IFPC_L1*
IFPC_L2
IFPC_L2*
IFPC_L3
IFPC_L3*
AM7
AM6
IFPD_AUX
IFPD_AUX*
AP4
IFPD_L0
IFPD_L0*
IFPD_L1
IFPD_L1*
IFPD_L2
IFPD_L2*
IFPD_L3
IFPD_L3*
IFPE_AUX
IFPE_AUX*
IFPE_L0
IFPE_L0*
IFPE_L1
IFPE_L1*
IFPE_L2
IFPE_L2*
IFPE_L3
IFPE_L3*
IFPF_AUX
IFPF_AUX*
AJ12
AM11
AN3
AL5
AM5
AM3
AM4
AP1
AR2
OUT
84 95
OUT
84 95
OUT
84 95
OUT
84 95
OUT
84 95
OUT
84 95
OUT
77
OUT
77
OUT
77
OUT
77
OUT
84 95
OUT
84 95
OUT
84 95
OUT
84 95
OUT
84 95
OUT
84 95
OUT
77
OUT
77
DP_EG_AUX_CH_P
DP_EG_AUX_CH_N
DP_EG_ML_P<0>
DP_EG_ML_N<0>
DP_EG_ML_P<1>
DP_EG_ML_N<1>
DP_EG_ML_P<2>
DP_EG_ML_N<2>
DP_EG_ML_P<3>
DP_EG_ML_N<3>
OUT
81 95
OUT
81 95
OUT
81 95
OUT
81 95
OUT
81 95
OUT
81 95
OUT
81 95
OUT
81 95
OUT
81 95
OUT
81 95
NO STUFF
1
R8861
1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R8860
1K
NC
NC
AN7
NC
AN5
NC
AP5
NC
AR5
NC
NC
AR4
AE4
NC
NC
AD4
AH6
NC
AH5
NC
NC
AH4
AG4
NC
AF4
NC
AF5
NC
AE6
NC
NC
AE5
AF3
NC
NC
AF2
AM15
NC
AM14
DACA_VREF
DACA_RSET
DACA_HSYNC
DACA_VSYNC
AM13
DACB_VDD
DACB_RED
DACB_GREEN
DACB_BLUE
AA4
DACB_CSYNC
AB5
DACC_VREF
DACC_RSET
LVDS_EG_B_DATA_P<0>
LVDS_EG_B_DATA_N<0>
LVDS_EG_B_DATA_P<1>
LVDS_EG_B_DATA_N<1>
LVDS_EG_B_DATA_P<2>
LVDS_EG_B_DATA_N<2>
84 95
AP7
DACA_RED
DACA_GREEN
DACA_BLUE
DACC_VDD
TP_LVDS_EG_B_CLK_P
TP_LVDS_EG_B_CLK_N
84 95
OUT
AR8
NC
AR7
IFPF_L0
IFPF_L0*
IFPF_L1
IFPF_L1*
IFPF_L2
IFPF_L2*
IFPF_L3
IFPF_L3*
DACB_VREF
DACB_RSET
LVDS_EG_A_DATA_P<0>
LVDS_EG_A_DATA_N<0>
LVDS_EG_A_DATA_P<1>
LVDS_EG_A_DATA_N<1>
LVDS_EG_A_DATA_P<2>
LVDS_EG_A_DATA_N<2>
OUT
NC
AN4
NC
AL2
NC
AL3
DACA_VDD
LVDS_EG_A_CLK_P
LVDS_EG_A_CLK_N
NC
NC
AJ3
AJ2
NC
AJ1
NC
AH1
NC
AH2
NC
NC
AH3
NC
NC
AL14
NC
NC
AL13
NC
AB4
NC
Y4
NV G96 Video Interfaces
NC
NC
DACC_RED
DACC_GREEN
DACC_BLUE
AK4
NC
AL4
DACC_HSYNC
DACC_VSYNC
AM1
SYNC_MASTER=MUXGFX
NC
AJ4
NC

NC
NC
AM2

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
78
97
8
70 65
51 43 41
9 8 7
40 39 31
64 55 53
6
5
GPU VCore Regulator
7
1
PP5V_S5_GFXIMVP6_PVCC
VOLTAGE=5V
C8902 1
C8903
4.7UF
PPBUS_G3H
83 67 66 65 64 62 61 46 37 8 7
86
0.01uF
20%
6.3V
X5R-CERM 2
402
10%
2 16V
CERM
402
CRITICAL
10
PP5V_S5_GFXIMVP6_VDD
16
1UF
VDD
R8905
2
GFXIMVP6_RBIAS
C8904
1
69
PP3V3_S0GPU
OUT
79
R8910
79
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
79
79
84 69
IN
R8924
100
1%
1/16W
MF-LF
402 2
GPU_GND_SENSE
VOLTAGE=0V
1
71
R8925
20
C8923
C8920
14
UGATE
18
BOOT
17
31
23
24
25
26
27
29
30
32
8
9
R8909
R8950
374K
7.15K
GFXIMVP6_UGATE
CRITICAL
Q8950
CSD58856Q5A
SOFT
MLP5X6-LFPAK-Q5A
DIDT=TRUE
GFXIMVP6_BOOT
CRITICAL
C8956 1
1 2 3
0.22UF
IMON
10%
16V 2
X7R
603
PGOOD
VID0
VID1
VID2
VID3
VID4
VR_ON
AF_EN
FDE
PHASE
0.6UH-30A-1.5MOHM
1
2 PPVCORE_GPU_REG_R
D
LGATE
GFXIMVP6_LGATE
21
MLP5X6-LFPAK-Q5
VSEN
RTN
10%
6.3V
2 X5R-CERM
603
GFXIMVP6_COMP
1
VW
COMP
VO
OCSET
12
FB
ISP
ISN
13
ICOMP
10
11
10%
50V
CERM
402
1%
1/16W
MF-LF
402
VDIFF
330PF
5%
50V 2
COG
402
1%
1/16W
MF-LF
402
R8901
9.76K
THRM_PAD
VSS
20
PGND
C8906 1
GFXIMVP6_DFB
R8902
GFXIMVP6_VDIFF
33
15
560PF
5.11K
C8971
1
68PF
1
GFXIMVP6_DROOP
(PPVCORE_GPU_REG)
1%
1/16W
MF-LF
2 402
5%
50V
CERM
402-1
C8972 1
0.1uF
10%
16V 2
X5R
402
VOLTAGE=0V
GPU VCore Setpoints
VID3 VID2 VID1 VID0

0
R8990
0
GPUVID0_1 GPUVID1_1
R8984
R89821
R8980
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402
2.2K
1
1
1
GPUVID2_1
R89871
2.2K
5%
1/16W
MF-LF
402
2.2K
GFXIMVP6_VID0
GFXIMVP6_VID1
GFXIMVP6_VID2
GFXIMVP6_VID3
GFXIMVP6_VID4
5%
1/16W
MF-LF
402
R8994
GPU_VCORE_VID2
Voltage
Max Batt
0.90125V
0.92700V
1.00425V
K19
-
Balanced
Max perf
K19
-
K19
PP3V3_S0GPU
R8986
IN
20%
3 2 2.0V
POLY-TANT
D2T-SM2
8.66K2
1%
1/16W
MF-LF
2 402
XW8900
SM
77 76
330UF
GND_GFXIMVP6_AGND
C8943
R8900
GFXIMVP6_OCSET
GFXIMVP6_VO
2.21K
C8951
GPU_VCORE_VID1
CRITICAL
10UF
20%
2 6.3V
X5R
603
1%
1/16W
MF-LF
402 2
GFXIMVP6_VSUM
6
R8953
GFXIMVP6_VDIFF_RC
IN
C8965
1K
C8952
5%
2 50V
CERM
402-1
1%
1/16W
MF-LF
402
2
R89031
10%
2 50V
CERM
402
68PF
4.99K
77 76
330UF
20%
2.0V 2 3
POLY-TANT
D2T-SM2
GFXIMVP6_PHASE_VSUM
C8953
680pF
R8951
C8967
4.7UF
1 2 3
GPU_VCORE_VID0
20%
6.3V 2
X5R
603
C8942 1
20%
6.3V 2
X5R
603
10UF
10%
50V 2
X7R
402
8 46 72 79
30A max output

(L8920 limit)
CRITICAL
10UF
C8968 1
0.001UF
CSD58857Q5
C8966 1
C8969 1
CRITICAL
Q8951
PPVCORE_GPU
2
4
DIDT=TRUE
IN
1
3
C8922
GFXIMVP6_FB
77 76
1%
1W
MF-1
0612
10%
2 50V
X7R
402
5%
50V
CERM
402
1%
1/16W
MF-LF
2 402
81 79 77 76 70 69 8 6
MPL104-SM
SWITCH_NODE=TRUE
DIDT=TRUE
Vout = 0.90V - 1.00V
0.001
L8920
GFXIMVP6_PHASE
19
R8940
CRITICAL
0.001UF
1%
1/16W
MF-LF
402 2
180PF
GFXIMVP6_COMP_RC
1
10%
50V
CERM 2
402
1
PLACEMENT_NOTE=Place R8920 at U8900

PLACEMENT_NOTE=Place R8908 at U8900
GFXIMVP6_VIN
C8921 1
GFXIMVP6_VW
5%
1/16W
MF-LF
402
C8950
2
VIN
10%
2 50V
CERM
402
(GFXIMVP6_AGND)
10%
2 50V
CERM
402
100
1%
1/16W
MF-LF
402
1K
5%
1/16W
MF-LF
402 2
0.001UF 0.001UF
0.001UF
R8908
1
5%
1/16W
MF-LF
402
GFXIMVP6_SOFT
GFXIMVP6_VSEN_P
96 GFXIMVP6_VSEN_N
96
R8920
GPU_VDD_SENSE
10%
50V
2 X7R
402
R89301
U8900
ISL6263C
GPUVCORE_PGOOD
GFXIMVP6_VID0
GFXIMVP6_VID1
GFXIMVP6_VID2
GFXIMVP6_VID3
GFXIMVP6_VID4
GPUVCORE_EN
GFXIMVP6_AF_EN
GFXIMVP6_FDE
79
VOLTAGE=1.25V
C8934
0.001UF
10%
25V 2
X5R
603-1
PVCC
QFN
GFXIMVP6_IMON28
47
10K
10%
16V
X5R
402
R89071
RBIAS
0.033UF
2
PPVCORE_GPU
1UF
X5R
603-1
CRITICAL
150K 1
1%
1/16W
MF-LF
402
71
C8932
1UF
10% C8933 1
2 25V
1
C8901
10%
2 10V
X5R
402-1
20
20%
25V
POLY-TANT 2
CASE-D2-SM
22UF
VOLTAGE=5V
1%
1/16W
MF-LF
402
C8930 1
20%
25V
POLY-TANT 2
CASE-D2-SM
22
CRITICAL
C8931 1
22UF
R8904
79 72 46 8
R8911
PP5V_S3
5%
1/16W
MF-LF
402
81
76 70 69 8 6
79 77
GPUVID1_0
GPUVID2_0
R8985
R8983
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2.2K
5%
1/16W
MF-LF
402
1
1
0
1
1
1
1
0
1
Other VID states may not be valid

79
GPU (G96) CORE SUPPLY
79
79
79
K19 Default Vcore Setpoints
SYNC_MASTER=M87_MLB
TABLE_BOMGROUP_HEAD
2.2K
R8988
0
5%
1/16W
MF-LF
2 402
79
BOM GROUP
BOM OPTIONS
GPUVID_0P90V
GPUVID2_1,GPUVID1_1,GPUVID0_1
GPUVID_1P00V
GPUVID2_0,GPUVID1_1,GPUVID0_1

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
79
97
D
84
LCD_PWR_EN
IN
R90941
10K
LCD (LVDS) INTERFACE
5%
1/16W
MF-LF
402 2
CRITICAL
U9000
CRITICAL
FPF1009
1 ON
81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84 82
PP3V3_S0
C9009
0.1UF
L9000
MFET-2X2
FERR-250-OHM
2 VIN_1
VOUT_1 4
3 VIN_2
VOUT_2 5
GND
6
THRM
PAD
7
PP3V3_SW_LCD_UF
C9011
0.1UF
SM
C9001 1
C9012
C9002 1
0.1UF
10UF
10%
2 16V
X5R
402
10%
16V
2 X5R
402
VOLTAGE=3.3V
0.001UF
10%
16V 2
X5R
402
20%
2 6.3V
X5R
603
10%
50V 2
X7R
402
CRITICAL
J9000
20474-040E-11
81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84 82
F-RT-SM
41
42
PP3V3_S0
R90101
100K pull-ups are for
100K
5%
1/16W
MF-LF
402 2
no-panel case (development).

Panel has 2K pull-ups
81 7
81 7
R9011
100K
PP3V3_SW_LCD
VOLTAGE=3.3V
5%
1/16W
MF-LF
2 402
NC
LVDS_DDC_CLK
LVDS_DDC_DATA
95 81 7
C9010 1
95 81 7
0.001UF
10%
50V 2
X7R
402
95 81 7
95 81 7
CRITICAL
L9010
90-OHM-100MA
95 81 7
DLP11S
SYM_VER-1
95 81 7
95 81
LVDS_CONN_A_CLK_N
95 81
LVDS_CONN_A_CLK_P
95 7
95 7
Place close to the connector
95 81 7
95 81 7
95 81 7
95 81 7
CRITICAL
L9011
90-OHM-100MA
95 81 7
DLP11S
SYM_VER-1
95 81 7
95 81
LVDS_CONN_B_CLK_N
95 81
LVDS_CONN_B_CLK_P
LVDS_CONN_A_CLK_F_N
LVDS_CONN_A_CLK_F_P
LVDS_CONN_B_CLK_F_N
LVDS_CONN_B_CLK_F_P
LED_RETURN_6
LED_RETURN_5
LED_RETURN_4
LED_RETURN_3
LED_RETURN_2
LED_RETURN_1
95 7
95 7
85 7
Place close to the connector
85 7
85 7
85 7
85 7
85 7
NC
85 53 7
PPVOUT_S0_LCDBKLT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
518S0651
43
44
LVDS Display Connector
SYNC_MASTER=DDR

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
80
97
DisplayPort Mux
A2
LVDS Transmitter Termination

90 9
All emulated LVDS outputs require this termination

PLACEMENT_NOTE=Place
at U9600
OMIT
LVDS_CONN_A_CLK_P
GMUX_2V5
1
R9321
133
1%
SIGNAL_MODEL=EMPTY
1/16W
MF-LF
2 402
OMIT
R9322
95 84
IN
LVDS_A_CLK_N
270
LVDS_CONN_A_CLK_N
1%
1/16W
MF-LF
402
95 84
IN
270
LVDS_A_DATA_N<0>
R9330
LVDS_A_DATA_P<1>
270
133
1%
1/16W
MF-LF
2 402
95 84
IN
LVDS_A_DATA_N<1>
IN
1%
1/16W
MF-LF
2 402
IN
IN
LVDS_B_CLK_P
IN
LVDS_B_CLK_N
95 84
IN
133
1%
1/16W
MF-LF
2 402
133
1%
1/16W
MF-LF
IN
LVDS_B_DATA_N<1>
IN
IN
77 18 9
BI
0.1uF
DP_IG_DDC_CLK
DP_IG_DDC_DATA
0.1uF
2 96 DP_IG_AUX_CH_C_P
10% 16V X5R 402
H9
J9
2 96 DP_IG_AUX_CH_C_N
10% 16V X5R 402
H8
IN
95 78
IN
95 78
IN
95 78
IN
95 78
IN
95 78
IN
95 78
IN
95 78
IN
95 78
BI
95 78
BI
DP_ML_P<0>
DP_ML_N<0>
OUT
82 95
OUT
82 95
DAUX1+
DAUX1-
DOUT_1+
DOUT_1-
D2
DP_ML_P<1>
DP_ML_N<1>
OUT
82 95
D1
OUT
82 95
DOUT_2+
DOUT_2-
E2
E1
DP_ML_P<2>
DP_ML_N<2>
OUT
82 95
OUT
82 95
DOUT_3+
DOUT_3-
F2
DP_ML_P<3>
DP_ML_N<3>
OUT
82 95
OUT
82 95
AUX+
AUX-
H2
J8
DDC_CLK1
DDC_DAT1
J2
HPD_1
78 77
IN
78 77
BI
B9
DIN2_0+
DIN2_0-
DP_EG_ML_P<1>
DP_EG_ML_N<1>
D8
D9
DIN2_1+
DIN2_1-
DP_EG_ML_P<2>
DP_EG_ML_N<2>
E8
E9
DIN2_2+
DIN2_2-
DP_EG_ML_P<3>
DP_EG_ML_N<3>
F8
F9
DIN2_3+
DIN2_3-
H6
DAUX2+
DAUX2-
0.1uF
C9336
DP_EG_DDC_CLK
DP_EG_DDC_DATA
0.1uF
OUT
80 95
H5
J5
R9305
84
DP_MUX_SEL_EG
IN
80 77 70 69 68 63 60 59 55
25 24 22 21 19 18 13 8 7 6
51 49 48 47 45 43 39 37 29 28
96 85 84 82 81
DP_MUX_XSD_L
DPMUX_EN_HPD
PP3V3_S0
10K
R9303
84
IN
DP_MUX_EN
84 82 81
OUT
81 77 18
84 82
OUT
BI
82 95
BI
82 95
J1
DP_HPD_R
1K
DP_HOTPLUG_DET
81
IN
82 84
5%
1/16W
MF-LF
402
A1
HPD_2
LO=PORT1
HI=PORT2
GPU_SEL
B7
XSD*
C9301
DP_AUX_CH_C_P
DP_AUX_CH_C_N
H1
R9307
HPDIN
DDC_CLK2
DDC_DAT2
1UF
LO=AUX_CH
HI=DDC
DDC_AUX_SEL
C2
TST0
G2
GND
DP_CA_DET
IN
MAKE_BASE=TRUE
18 77 81 82 84
10%
2 6.3V
CERM-X5R
402
1%
1/16W
MF-LF
402 2
10K
1%
1/16W
MF-LF
402 2
F1
PLACEMENT_NOTE=Place at U9320
MUXGFX
DPMUX_EN_HPD
R93011
R93021
7 80 95
J6
2 95 DP_EG_AUX_CH_C_N
10% 16V X5R 402
H3
5%
1/16W
MF-LF
402 2
OUT
2 95 DP_EG_AUX_CH_C_P
10% 16V X5R 402
BGA
B2
B1
DP_EG_ML_P<0>
DP_EG_ML_N<0>
C9335
402
U9320
CBTL06141EE
DIN1_2+
CRITICAL
DIN1_2SIGNAL_MODEL=DPMUX
DOUT_0+
DIN1_3+
DIN1_3DOUT_0-
B8
DP_EG_AUX_CH_P
DP_EG_AUX_CH_N
20%
2 10V
CERM
DP_HOTPLUG_DET
MAKE_BASE=TRUE
DP_CA_DET
5%
1/16W
MF-LF
402
270
LVDS_CONN_B_CLK_N
OUT
80 95
OUT
7 80 95
133
1%
1/16W
MF-LF
SIGNAL_MODEL=EMPTY
OUT
7 80 95
R93701
OUT
7 80 95
82 81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84
133
1%
1/16W
MF-LF
2 402
OMIT
270
1
LVDS_B_DATA_N<2>
5%
1/16W
MF-LF
402 2
C9370
R93721
20K
0.1UF
SIGNAL_MODEL=EMPTY
OMIT
R9355
270 2
1
20K
PP3V3_S0
R9351
LVDS_B_DATA_P<2>
PP3V3_S0GPU
79 77 76 70 69 8 6
GMUX_2V5
1
OMIT
R9352
270 2
1
LVDS DDC MUX
2 402
20%
10V
CERM 2
402
OUT
7 80 95
OUT
7 80 95
VCC
IN
LVDS_DDC_SEL_EG
13
84
IN
LVDS_DDC_SEL_IG
R9356
133
U9370
QFN1
C1
C2
C3
SIGNAL_MODEL=EMPTY
1%
1/16W
MF-LF
12
2 402
OUT
7 80 95
5%
1/16W
MF-LF
402 2
14
84
GMUX_2V5
1
R9357
95 84
IN
DP_IG_AUX_CH_P
C9330
DP_EG_HPD
R9346
1%
1/16W
MF-LF
402
77 18 9
A8
A9
DPMUX_EN_S0&DPMUX_EN_PLD
1%
1/16W
MF-LF
402
95 84
7 80 95
OUT
GMUX_2V5
1
1%
1/16W
MF-LF
402
95 84
OUT
1%
1/16W
MF-LF
402
OMIT
IN
BI
DP_IG_ML_P<3>
DP_IG_ML_N<3>
MUXGFX
C9321
0.1UF
20%
2 10V
CERM
402
VDD
SIGNAL_MODEL=EMPTY
OMIT
R9345
270 2
1
R9350
95 84
90 18
B6
A6
2 402
LVDS_B_DATA_N<0>
270
7 80 95
DPMUX_EN_PLD
OMIT
1K
R9341
LVDS_B_DATA_P<0>
LVDS_B_DATA_P<1>
OUT
SIGNAL_MODEL=EMPTY
R9347
IN
R93061
7 80 95
R9336
1%
1/16W
MF-LF
402
95 84
OUT
GMUX_2V5
1
OMIT
R9342
270 2
1
IN
DP_IG_ML_P<2>
DP_IG_ML_N<2>
100K
LVDS_CONN_B_CLK_P
1%
1/16W
MF-LF
402
7 80 95
GMUX_2V5
1
1%
1/16W
MF-LF
402
95 84
OUT
1%
1/16W
MF-LF
402
OMIT
IN
90 9
95 78
5%
1/16W
MF-LF
402 2
77 76
OMIT
R9337
270 2
1
LVDS_A_DATA_N<2>
90 9
DIN1_1+
DIN1_1-
DP_IG_HPD
R93041
OMIT
R9335
R9340
95 84
OUT
5%
1/16W
MF-LF
402 2
270
18 9
SIGNAL_MODEL=EMPTY
1%
1/16W
MF-LF
402
95 84
7 80 95
100K
133
LVDS_A_DATA_P<2>
IN
B5
A5
C9331
R9331
270
IN
90 9
DP_IG_ML_P<1>
DP_IG_ML_N<1>
DP_IG_AUX_CH_N
GMUX_2V5
1
1%
1/16W
MF-LF
402
95 84
BI
SIGNAL_MODEL=EMPTY
OMIT
R9332
270 2
1
90 9
R9326
1%
1/16W
MF-LF
402
90 18
1%
1/16W
MF-LF
402
OMIT
IN
270
OUT
IN
A4
DIN1_0+
DIN1_0-
GMUX_2V5
1
OMIT
95 84
80 95
R9325
LVDS_A_DATA_P<0>
R9327
IN
OUT
OMIT
1%
1/16W
MF-LF
402
95 84
OUT
90 9
80 95
MUXGFX
C9320
H7
1%
1/16W
MF-LF
402
IN
B4
G8
H4
270
90 9
DP_IG_ML_P<0>
DP_IG_ML_N<0>
C8
IN
MUXGFX
1
0.1UF
B3
IN
LVDS_A_CLK_P
90 9
(All 24 resistors)
R9320
95 84
IN
SN74LV4066A
PP3V3_S0
J4
82 81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84
20K
5%
1/16W
MF-LF
2 402
R9373
20K
5%
1/16W
MF-LF
2 402
LVDS_EG_DDC_CLK
IN
77 78
LVDS_IG_DDC_CLK
LVDS_DDC_CLK
IN
18
OUT
A2 3
B2
8
LVDS_EG_DDC_DATA
11
LVDS_IG_DDC_DATA
LVDS_DDC_DATA
A3
9
B3
A4
B4 10
GND THRM
7
R9371
A1 2
B1
C4
BI
7 80
77 78
BI
18
BI
7 80
Muxed Graphics Support

15
1%
1/16W
MF-LF
402

TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
114S0517
16
RES,MTL FILM,270 OHM,1%,1/16W,0402,SMD,L
GMUX_2V5
114S0174
16
RES,MTL FILM,1/16W,357 OHM,1,0402,SMD,LF
GMUX_1V8
BOM OPTION
TABLE_5_ITEM
R9320,R9322,R9325,R9327,R9330,R9332,R9335,R9337,R9340,R9342,R9345,R9347,R9350,R9352,R9355,R9357
SIZE
DRAWING NUMBER
TABLE_5_ITEM
R9320,R9322,R9325,R9327,R9330,R9332,R9335,R9337,R9340,R9342,R9345,R9347,R9350,R9352,R9355,R9357
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
81
97
Port Power Switch

CRITICAL
PP3V3_S5
PM_SLP_S3_L
IN
84 69 42 37 34 21 7
SOT23
5 IN
96
34 30 26 24 22 20 18 8 7
87 70 69 68 64 54 44 38 37
4 EN
OUT 1
OC* 3
0603
1
C9400
VOLTAGE=3.3V
5 IO
6 NC
C9480
10UF
C9481
C9485 1
0.1UF
0.1UF
20%
2 10V
CERM
402
20%
6.3V 2
X5R
603
C9486
2 IO
9 NC
IO 4
NC 7
GND
0.01UF
20%
2 50V
CERM
603
CRITICAL
1
SLP2510P8
SLP2510P8
FERR-120-OHM-3A
1
2
PP3V3_S0_DPPWR
GND
2
RCLAMP0524P
RCLAMP0524P
L9400
D9410
D9410
PP3V3_S0_DPILIM
TP_DPPWR_OC_L
VOLTAGE=3.3V
IO 1
NC 10
GND
DP_ESD
CRITICAL
DP_ESD
CRITICAL
U9480
TPS2051B
22UF
20%
10V
CERM 2
402
20%
2 6.3V
X5R-CERM
603
R94201
100K
5%
1/16W
MF-LF
402 2
NO STUFF
R9401
CRITICAL
HDMI_CEC
R9403
R9413
5%
R9425
IN
DP_ML_P<3>
C9414
95 81
IN
DP_ML_N<3>
C9415
95 81
BI
DP_AUX_CH_C_P
BI
DP_AUX_CH_C_N
95 81
2
DP_ML_C_P<3>
10% 16V X5R 402
0.1uF
1
0.1uF
95 81
96
68 63 60 59 55 51 49 48
24 22 21 19 18 13 8 7 6
47 45 43 39 37 29 28 25
85 84 82 81 80 77 70 69
DP_CA_DET
TOP ROW
TH PINS
SM PINS
95
DP_ML_CONN_P<3>
95
DP_ML_CONN_N<3>
2
4
6
8
10
12
14
16
18
20
GND
AUX_CHP
AUX_CHN
DP_PWR
5%
1/16W
MF-LF
402 2
2 IO
9 NC
DP_CA_DET_L_Q
DP_ESD
CRITICAL
95
DP_ML_CONN_P<1>
DP_ML_CONN_N<1>
TCM1210-4SM
SYM_VER-2
1
4
95
DP_ML_CONN_P<2>
95
DP_ML_CONN_N<2>
FL9402
12-OHM-100MA
TCM1210-4SM
SYM_VER-2
1
4
2
DP_ML_P<0>
10% 16V X5R 402
IN
81 95
2
DP_ML_N<0>
10% 16V X5R 402
IN
81 95
2
DP_ML_P<1>
10% 16V X5R 402
IN
81 95
2
DP_ML_N<1>
10% 16V X5R 402
IN
81 95
2
DP_ML_P<2>
10% 16V X5R 402
IN
81 95
2
DP_ML_N<2>
10% 16V X5R 402
IN
81 95
NO STUFF
R9402
R9432
2
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
NO STUFF
1
D9411
SC70-6-1
RCLAMP0524P
SLP2510P8
SOT-363
DP_CA_DET_Q
R94221
1M
5%
1/16W
MF-LF
402 2
Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm
DP to DVI/HDMI
Cable Adapter
(CA) has 100k
pull-up to DP_PWR.
6
5 IO
6 NC
IO 4
NC 7
PP3V3_S0
R94451
R94441
10K
84 81
FL9401
12-OHM-100MA
95
DP_ML_C_P<0> C9410 1
0.1uF
1
95 DP_ML_C_N<0> C9411
0.1uF
95 7 DP_ML_C_P<1>
C9412 1
0.1uF
95 DP_ML_C_N<1>
C9413 1
0.1uF
95 7 DP_ML_C_P<2>
C9416 1
0.1uF
C9417 1
95 DP_ML_C_N<2>
0.1uF
95 7
DP_ESD
CRITICAL
D9400
2N7002DW-X-G
96 85 84 82 81
59 55 51 49 48 47 45
22 21 19 18 13 8 7 6
43 39 37 29 28 25 24
80 77 70 69 68 63 60
95
IO 1
NC 10
RCLAMP0504F
Q9440
1/16W MF-LF 402
TCM1210-4SM
SYM_VER-2
1
4
22 21
1/16W MF-LF 402
1/16W MF-LF 402
5%
SHIELD PINS
GND
2N7002DW-X-G
5%
DP_ML_CONN_P<0>
DP_ML_CONN_N<0>
100K
SOT-363
1/16W MF-LF 402
5%
SLP2510P8
R94211
5%
1/16W
MF-LF
402 2
Q9440
RCLAMP0524P
100K
5%
1/16W
MF-LF
402 2
GND
ML_LANE2P
ML_LANE2N
RETURN
D9411
R94421
95
1
3
5
7
9
11
13
15
17
19
HOT_PLUG_DETECT
GND
CONFIG1
ML_LANE0P
CONFIG2
ML_LANE0N
GND
GND
ML_LANE3P
ML_LANE1P
ML_LANE3N
ML_LANE1N
DP_ESD
CRITICAL
100K
OUT
PP3V3_S0
R94431
84 81 77 18
TCM1210-4SM
SYM_VER-2
1
2 95 DP_ML_C_N<3>
10% 16V X5R 402
5%
FL9400
BOT ROW
1/16W MF-LF 402
12-OHM-100MA
4
GND
5%
1/16W
MF-LF
2 402
NO STUFF
12-OHM-100MA
FL9403
1M
1/16W MF-LF 402
R9430
F-RT-THSM
NO STUFF
1
DSPLYPRT-M97-1
2
5%
NO STUFF
R9431
J9400
NO STUFF
NO STUFF
R9400
OUT
DP_HOTPLUG_DET
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
Q9441
2N7002DW-X-G
SOT-363
DP_HPD_L_Q
3
Q9441
DisplayPort Connector
2N7002DW-X-G
SOT-363
DP_HPD_Q
SYNC_MASTER=MUXGFX
R94231
100K
5%
1/16W
MF-LF
402 2
DP Source must pull
down HPD input with

greater than or equal

to 100K (DPv1.1a).

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
82
97
D
PPBUS_G3H
CRITICAL
C9540 1
C9545
CRITICAL
1UF
22UF
10%
2 25V
X5R
603-1
20%
25V 2
POLY-TANT
CASE-D2-SM
C9590 1
Q9510
CRITICAL
SI7904BDN
PWRPK-1212-8
4.7
5%
1/16W
MF-LF
402
P1V1GPU_DRVH
GATE_NODE=TRUE
DIDT=TRUE
10%
25V 2
X5R
805
Q9510
CRITICAL
7 8 39 44 49 51 63 66 67 70 85
C9501 1
1UF
10%
10V 2
X5R
402-1
(Internal 10-ohm path

from PVCC to VCC)
CRITICAL
PP5V_S0GPU_P1V1P1V8_VCC
PWRPK-1212-8
PP5V_S0
C9500 1
10UF
SI7904BDN
1UF
10%
2 25V
X5R
603-1
20%
25V 2
POLY-TANT
CASE-D2-SM
PVIN_S0GPU_P1V1
C9595
22UF
R9500
5
67 66 65 64 62 61 46 37 8 7
86 79
Q9560
VOLTAGE=5V
FDMS9600S
P1V1GPU_DRVL
GATE_NODE=TRUE
DIDT=TRUE
PP1V1_S0GPU_REG
f = 400 kHz
1
10%
50V 2
X7R
603-1
L9510
3.3UH-3.5A
(Q9510 limit)
CRITICAL
C9510
330UF
P1V1GPU_VBST
P1V1GPU_LL
PCMB053T
SWITCH_NODE=TRUE
20%
2 2.0V
POLY-TANT
B2-SM
DIDT=TRUE
P1V1GPU_VFB
P1V1GPU_TRIP
C9515 1
10UF
6
17
15
16
18
10
14
9
11
12
29
4
20
2
PLACEMENT_NOTE=Place XW9515 next to C7615
20%
6.3V 2
X5R
603
U9500
R9520
5.76K
1%
1/16W
MF-LF
2 402
<Rb>
1
R9521
C9520
21
P1V1S0_VSNS
<Ra>
NO STUFF
1
33
THRM_PAD GND
7
8
24
26
25
23
30
27
Q1
10
SW
C9560 1
Q2
C9580
GATE_NODE=TRUE
C9565
10UF
20%
2 6.3V
X5R
603
DIDT=TRUE
7 6 5
10%
2 50V
X7R
603-1
GPU_P1V8_REFIN
P1V8FB_TRIP
P1V8FB_LL
PP2V_S0GPU_P1V8_REF
VOLTAGE=2V
<Ra>
P1V8_GPU_VSNS
PLACEMENT_NOTE=Place next to C7665
14.0K
R95851
XW9565
SM
SWITCH_NODE=TRUE DIDT=TRUE
R95631
PGND
20%
2.5V 2
POLY-TANT
CASE-B2-SM2
1
1
13
28
f = 300 kHz
220UF
(=PP1V8FB_S0_REG)
(Q9560 limit)
CRITICAL
P1V8FB_VBST
P1V8FB_DRVL
8 47
10.5A max output
2
MMD06CZ-SM
8
1%
1/16W
MF-LF
402 2
130K
1%
1/16W
MF-LF
402 2
R9535
5%
50V
CERM 2
402
L9560
2.2UH-14A
0.1UF
32
31
PP1V8_S0GPU_ISNS_R
Vout = 1.8V
CRITICAL
DIDT=TRUE
(SGND)
100PF
GATE_NODE=TRUE
NC
22
6A max output
XW9515
SM
0.1UF
CRITICAL
LDO
LDOREFIN
VIN
BOOT1
OMIT
BOOT2
UGATE1
UGATE2
PHASE1
PHASE2
ISL6236
LGATE1
LGATE2
QFN
OUT1
OUT2
EN1
EN2
BYP
FB1
REFIN2
ILIM1
ILIM2
SKIP*
EN_LDO
REF
SECFB
POK1
TON
POK2
10%
10V
X5R 2
402-1
10%
10V 2
X5R
402-1
P1V8FB_DRVH
1UF
1UF
PVCC VCC VREF3
C9530 1
Vout = 1.103V
C9503 1
C9504 1
1
73 71 8
78 76
G
S
19
9 4 3 2
MLP
PP5V_S0GPU_VREF
XW9500
SM
280K
1%
1/16W
MF-LF
2 402
GND_P1V1P1V8_SGND
0.1UF
R9562
78.7K
<Rb>
1
R9564
20%
2 10V
CERM
402
VOLTAGE=0V
Vout = 0.7V * (1 + Ra / Rb)

(Rb should be between 10K and 100K)
C9585
127K
1%
1/16W
MF-LF
402 2
C9561
1%
1/16W
MF-LF
0.0022UF 2 402
10%
GPUFB_VID_L
50V
2 CERM
402
Q9565
3 D
10K
SSM3K15FV
SOD-VESM-HF
1%
1/16W
MF-LF
2 402
2 S
84 69
IN
69
OUT
84 69 9
OUT
84 70 69
IN
P1V1_GPU_EN
P1V1GPU_PGOOD
PM_ALL_GPU_PGOOD
P1V8_S0GPU_EN
PART NUMBER
353S2312
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
IC,ISL6236,DUAL PWM CTRL,QFN32
U9500
CRITICAL
G 1
GPIO7_FBVDD_ALTVO 76
77
BOM OPTION
1.1V / 1V8 FB Power Supply
SYNC_MASTER=MUXGFX

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
83
97
8
80 77 70
55 51 49
37 29 28
18 13 8 7
24 22 21
47 45 43
68 63 60
85 84 82
96
69
48
25
6
19
39
59
81
LVDS Receiver Termination
GMUX CPLD
PP3V3_S0
C9610
0.1UF
C9621
C9622
0.1UF
20%
2 10V
CERM
402
0.1UF
20%
2 10V
CERM
402
C9623
0.1UF
20%
2 10V
CERM
402
C9624
0.1UF
20%
2 10V
CERM
402
C9625
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C9626
0.1UF
C9628
0.1UF
20%
2 10V
CERM
402
C9629
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
59 60 63 68 69 70 77 80 81 82
6 7 8 13 18 19 21 22 24 25 28
29 37 39 43 45 47 48 49 51 55
84 85 96
90 84 18
C9630
0.1UF
90 84 18
20%
2 10V
CERM
402
90 84 18
90 84 18
L9631
90 84 18
FERR-220-OHM
1
2
PP3V3_S0_ULC_F
PP1V8_S0
D
C9611
0.1UF
C9612
0.1UF
20%
10V
2 CERM
402
C9613
0.1UF
20%
10V
2 CERM
402
C9614
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
C9615
0.1UF
C9616
0.1UF
20%
10V
2 CERM
402
0.1UF
0.1UF
20%
10V
2 CERM
402
90 84 18
MIN_LINE_WIDTH=0.2 mm 0402
VOLTAGE=3.3V
C9631 1
C9617
90 84 18
95 84 78
20%
10V
CERM 2
402
20%
10V
2 CERM
402
L9627
95 84 78
FERR-220-OHM
1
2
PP3V3_S0_LRC_F
95 84 78
95 84 78
MIN_LINE_WIDTH=0.2 mm0402
VOLTAGE=3.3V
87 8
95 84 78
95 84 78
PP1V2_S0
C9627
95 84 78
PLACEMENT_NOTE=Place at U9200
LVDS_IG_A_CLK_P
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_P<2>
LVDS_EG_A_CLK_P
LVDS_EG_A_DATA_P<0>
LVDS_EG_A_DATA_P<1>
LVDS_EG_A_DATA_P<2>
LVDS_EG_B_DATA_P<0>
LVDS_EG_B_DATA_P<1>
LVDS_EG_B_DATA_P<2>
R9650
R9651
R9652
R9653
R9654
R9655
R9656
100
100
100
100
1
1
1
1
100
100
100
1
1
1
R9660
R9661
R9662
R9663
R9664
R9665
R9666
100
100
100
100
1
1
1
1
100
100
100
1
1
1
2
1%
2
1%
2
1%
2
1%
2
1%
2
1%
2
1%
2
1%
2
1%
2
1%
2
1%
2
1%
2
1%
2
1%
0.1UF
C9600 1
4.7UF
20%
4V
X5R 2
402
C9604
0.1UF
C9605
0.1UF
20%
2 10V
CERM
402
C9606
0.1UF
20%
2 10V
CERM
402
C9607
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C9608
0.1UF
20%
2 10V
CERM
402
C9609
0.1UF
20%
2 10V
CERM
402
84
GMUX_CFG0
1%
1/16W
MF-LF
2 402
OUT
84 81
OUT
84 71 9
OUT
84
OUT
84
OUT
84
OUT
84
OUT
84 9
OUT
77
OUT
80
OUT
91 44 42 19
BI
BI
BI
BI
91 44 42 19
BI
91 26 19
IN
26
84 18 9
R9647
10K
1%
1/16W
MF-LF
2 402
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
90 84 18
IN
OUT
IN
IN
IN
84
IN
PL2A
PL2B
PL10A
PL10B
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
PL14B
PL15A
PL15B
PL16A
PL16B
PL18A
PL18B
PL19A
PL19B
PL32A
PL32B
(Tie/strap low if EGPU doesnt provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU)
GND
J1
PM_SLP_S3_L Isolation
82 81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 85 84
PP3V3_S0
Q9670
PM_SLP_S3_L
K12
A4
P11
ULC_VCCPLL
LRC_VCCPLL
VCCIO7
VCCIO6
VCCIO5
VCCIO4
VCCIO3
1/16W
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
MF-LF
402
402
402
402
1/16W MF-LF 402

1/16W MF-LF 402
1/16W MF-LF 402
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_N<2>
LVDS_EG_A_CLK_N
LVDS_EG_A_DATA_N<0>
LVDS_EG_A_DATA_N<1>
LVDS_EG_A_DATA_N<2>
LVDS_EG_B_DATA_N<0>
LVDS_EG_B_DATA_N<1>
LVDS_EG_B_DATA_N<2>
R9680
1K
JTAG_GMUX_TCK
R9690
4.7K
EG_CLKREQ_OUT_L
NO STUFF
R9695
10K
10K
A2
A3
A1
B3
C5
A5
B6
C7
A6
A7
C8
C9
A8
B9
A9
C10
B10
A10
A11
B12
B13
A13
LVDS_B_DATA_P<0>
LVDS_B_DATA_N<0>
LVDS_B_DATA_P<1>
LVDS_B_DATA_N<1>
LVDS_B_DATA_P<2>
LVDS_B_DATA_N<2>
GMUX_PM_SLP_S3_L
GMUX_DEBUG_RESET_L
LVDS_A_CLK_P
LVDS_A_CLK_N
LVDS_B_CLK_P
LVDS_B_CLK_N
LVDS_A_DATA_P<0>
LVDS_A_DATA_N<0>
LVDS_A_DATA_P<1>
LVDS_A_DATA_N<1>
LVDS_A_DATA_P<2>
LVDS_A_DATA_N<2>
TP_GMUX_PT20A
TP_GMUX_PT20B
TP_GMUX_PT32A
TP_GMUX_PT32B
PR2A
PR2B
PR10A
PR10B
PR11A
PR11B
PR12A
PR12B
PR13A
PR13B
PR14A
PR14B
PR15A
PR15B
PR16A
PR16B
PR18A
PR18B
PR30A
PR30B
A14
B14
D12
D13
D14
E14
E12
F12
F14
G14
G12
G13
H13
H12
H14
J12
L14
M13
N14
N13
DP_CA_DET
DP_HOTPLUG_DET
LVDS_EG_A_DATA_P<0>
LVDS_EG_A_DATA_N<0>
LVDS_EG_A_DATA_P<1>
LVDS_EG_A_DATA_N<1>
LVDS_EG_A_DATA_P<2>
LVDS_EG_A_DATA_N<2>
LVDS_EG_B_DATA_P<0>
LVDS_EG_B_DATA_N<0>
LVDS_EG_B_DATA_P<1>
LVDS_EG_B_DATA_N<1>
LVDS_EG_B_DATA_P<2>
LVDS_EG_B_DATA_N<2>
LVDS_EG_A_CLK_P
LVDS_EG_A_CLK_N
LVDS_IG_PANEL_PWR
EG_LCD_PWR_EN
LVDS_IG_BKL_ON
EG_BKLT_EN
OUT
81 95
OUT
81 95
OUT
81 95
OUT
81 95
OUT
81 95
OUT
84 81
84 81
84 81
81 95
IN
84
IN
84
18 84 90
18 84 90
18 84 90
18 84 90
18 84 90
18 84 90
78 84 95
78 84 95
78 84 95
78 84 95
78 84 95
78 84 95
78 84 95
PP3V3_S0
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
1%
1/16W
MF-LF
402 2
PLACEMENT_NOTE=Place on top side at U9200
DP_MUX_SEL_EG
R9681
10K
LVDS_DDC_SEL_IG
R9682
10K
LVDS_DDC_SEL_EG
R9683
10K
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
(Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rails source is valid)
OUT
81 95
OUT
81 95
OUT
81 95
OUT
81 95
OUT
81 95
OUT
81 95
OUT
81 95
OUT
81 95
OUT
81 95
OUT
81 95
84 71 9
84 18 9
85 84
84
NO STUFF
EG_RESET_L
R9691
100K
GMUX_INT
R9692
20K
LCD_BKLT_PWM
R9693
100K
EG_CLKREQ_IN_L
R9694
R9630
100K 1
EG_PWRSEQ_HW
0 1
2
5%
IN
18 77 81 82
IN
81 82
IN
78 84 95
IN
78 84 95
IN
78 84 95
IN
78 84 95
IN
78 84 95
IN
78 84 95
IN
78 84 95
IN
78 84 95
IN
78 84 95
IN
78 84 95
IN
78 84 95
IN
78 84 95
IN
78 84 95
IN
78 84 95
EG_RAIL1_EN
EG_PWRSEQ_GMUX
R9631 0 1
2
EG_RAIL2_EN
EG_PWRSEQ_GMUX
R9632 0 1
2
84
EG_RAIL3_EN
EG_PWRSEQ_GMUX
R9633 0 1
2
84
EG_RAIL4_EN
R9634
84
5%
5%
5%
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
5%
1/16W MF-LF 402
EXTGPU_PWR_EN
OUT
1/16W MF-LF 402
P1V1_GPU_EN
OUT
69 83
P3V3GPU_EN
OUT
69 70
GPUVCORE_ENOUT
69 79
1/16W MF-LF 402
1/16W MF-LF 402
1/16W MF-LF 402
EG_PWRSEQ_GMUX
0 1
2
5%
69
P1V8_S0GPU_EN
69
OUT
1/16W MF-LF 402
70 83
The MAKE BASE properties for these signals are on the POWER CONTROL page.
IN
9 18
IN
76 77
IN
9 18
IN
76 77
NO STUFF
NO STUFF
C9691
0.1UF
C9693
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
NO STUFF
1
C9692
NO STUFF
1
0.1UF
C9694
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
Graphics MUX (GMUX)
GMUX_JTAG_TCK Inversion
JTAG_GMUX_TCK
SYNC_MASTER=MUXGFX
G 2
GMUX_PM_SLP_S3_L
1%
1/16W
MF-LF
2 402
GMUX_PM_SLP_S3_L
MAKE_BASE=TRUE

84
3 D
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
BOM OPTION
IC,XP2-5,HF,CPLD,BLANK
U9600
CRITICAL
GMUX_5K_BLANK
341S2479
IC,CPLD,LATTICE,132CSBGA,K19
U9600
CRITICAL
GMUX_PROG
Q9670

SSM6N15FEAPE
TABLE_5_ITEM
336S0025
SOT563

TABLE_5_ITEM
84
4 S
G 5
GMUX_JTAG_TCK_L
IN
SIZE
17
DRAWING NUMBER
D
APPLE INC.
REV.
051-7892
SCALE
SHT
NONE
18 84 90
1 S
IN
6 D
42 37 34 21 7
82 69
1/16W MF-LF 402

1/16W MF-LF 402
1/16W MF-LF 402
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_N<2>
96 85 84 82
81 80 77 70 69 68 63 60 59
55 51 49 48 47 45 43 39 37 29
28 25 24 22 21 19 18 13 8 7 6
GMUX_DEBUG_RESET_L
SILK_PART=GMUX_RST
PT2A
PT2B
PT3A
PT3B
PT4A
PT4B
PT14A
PT14B
PT15A
PT15B
PT16A
PT16B
PT17A
PT17B
PT18A
PT18B
PT19A
PT19B
PT20A
PT20B
PT32A
PT32B
84 6
SSM6N15FEAPE R9670
10K
SOT563
B5
B7
A12
C14
F13
M12
M9
M3
N5
M1
C3
F2
BANK6
26
84
83 69 9
B1
B2
C2
D3
D1
E1
D2
E3
F1
G1
F3
G2
H2
G3
H1
H3
L1
L3
K3
L2
N1
P1
402
402
402
402
R96791
84
LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<2>
TP_GMUX_PL10A
TP_GMUX_PL10B
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<2>
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_N<1>
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
TP_LVDS_MUX_SEL_EG
TP_GMUX_PL18B_VSYNC
GMUX_PCIE_RESET_L
GMUX_PM_SLP_S3_L
PM_ALL_GPU_PGOOD
EG_CLKREQ_IN_L
BANK7
NO STUFF
IN
OUT
BANK4
91 44 42 19
91 44 42 19
91 44 42 19
MF-LF
MF-LF
MF-LF
MF-LF
Required Pulldowns
BANK0
10K
OUT
81
CSBGA-HF
BANK5
10K
1%
1/16W
MF-LF
402 2
R9646
OUT
84 81
U9600
PB2A
PB2B
PB14A
PB14B
PB15A (OD)
PB15B
PB16A
PB16B
PB17A
PB17B
PB18A
PB18B (OD)
PB19A
PB19B
PB20A
PB20B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B
BANK1
R9641
NO STUFF
1
OUT
84 81
CFG0
84 9
XP28
P2
N2
P4
N4
N3
M4
P5
M5
P6
M6
P7
M7
N7
N8
P9
N9
P10
M10
P12
P13
N12
P14
BANK2
85 84
K1
LCD_BKLT_EN
LCD_BKLT_PWM
LVDS_DDC_SEL_EG
LVDS_DDC_SEL_IG
DP_MUX_EN
DP_MUX_SEL_EG
EG_RESET_L
EG_RAIL1_EN
EG_RAIL2_EN
EG_RAIL3_EN
EG_RAIL4_EN
EG_CLKREQ_OUT_L
DP_CA_DET_EG
LCD_PWR_EN
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
LPC_RESET_L
LPC_CLK33M_GMUX
GMUX_INT
BANK3
NO STUFF
OUT
ULC_GNDPLL
LRC_GNDPLL
86 9
B4
M11
VCCJ
OMIT
CRITICAL
GNDIO7
IN
VCCIO2
19 9 6
TCK
TDI
TDO
TMS
TOE
GNDIO6
OUT
K14
L13
K13
L12
K2
VCCIO1
17 9 6
JTAG_GMUX_TCK
JTAG_GMUX_TDI
JTAG_GMUX_TDO
JTAG_GMUX_TMS
GMUX_TOE
GNDIO5
IN
GNDIO3
GNDIO4
19 9 6
GNDIO2
1%
1/16W
MF-LF
2 402
GNDIO1
84 6
10K
GNDIO0
R9645
VCCAUX
B8
C6
C12
C13
E13
M14
N10
N6
P3
M2
C1
E2
10K
1%
1/16W
MF-LF
402 2
VCCIO0
C11
J2
J14
M8
B11
C4
J3
J13
N11
P8
R9640
(All 14 resistors)
Required Pullups
20%
2 10V
CERM
402
VCC
1
1/16W
1/16W
1/16W
1/16W
SIGNAL_MODEL=EMPTY
84 6
PP3V3_S0
1
55 25 18 8 7
87 70 69
A.0.0
OF
84
97
*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.
*PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
* LVDS_IG_BKL_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
BKL_VLDO_EN_L
CRITICAL
Q9701
NTZD3155C
3
SOT-563-HF
P-CHN
R9735
5
100K 2
1%
1/16W
MF-LF
402
4
6
PP5V_S0
7 8 39 44 49 51 63 66 67 70 83
BKLT_EN
85
R9701
BKLT_EN_R
5%
1/16W
MF-LF
402
N-CHN
VOLTAGE=5V
R9702
0
5%
1/16W
MF-LF
2 402
CRITICAL
PPBUS_S0_LCDBKLT_PWR
XW9722
SM
C9712
0.1UF
10UF
NO
1 STUFF
10%
25V
2 X5R
402
10%
2 25V
X5R
805
BKL_VLDO
PP3V3_S0
1
100K
5%
1/16W
MF-LF
402 2
C9714
0.01UF
10%
2 16V
CERM
402
PPVOUT_S0_LCDBKLT
C9710
1UF
10%
2 25V
X5R
603-1
C9711
0.1UF
10%
2 16V
X5R
402
VDDIO
7 53 80
VOLTAGE=50V
1
C9796
220PF
10%
2 50V
X7R-CERM
402
5%
1/16W
MF-LF
2 402
ISNS_LCDBKLT_N
R97161
SWITCH_NODE=TRUE
RB160M-60G
ISNS_LCDBKLT_P
81 80 77 70 69 68 63 60 59
28 25 24 22 21 19 18 13 8 7 6
55 51 49 48 47 45 43 39 37 29
96 84 82
VOLTAGE=50V
R9703
23
OUT
XW9721
SM
C9713
22
OUT
96 53
PPBUS_S0_LCDBKLT_PWR_SW
C9799
2.2UF
10%
2 100V
X7R
1210
C9797
2.2UF
10%
2 100V
X7R
1210
PPVIN_BKL_R
96 53
1
2
VOLTAGE=6V
IHLP2525CZ-SM
PPVIN_BKL
CRITICAL
D9701
SOD-123
22UH-2.5A
86 85
CRITICAL
L9701
XW9720
SM
VLDO
VIN
CRITICAL
U9701
R9714
IF_SEL=1 FOR SMBUS
NC
100K
5%
1/16W
MF-LF
402 2
20 ADR
2
5%
R9757
SMBUS_MCP_1_DATA
1/16W MF-LF 402
OUT2 13
BKL_ISEN2
OUT3 14
BKL_ISEN3
OUT4 16
BKL_ISEN4
2 PWM
OUT5 17
BKL_ISEN5
TP_BKL_FAULT
7 FAULT
OUT6 18
BKL_ISEN6
BKLT_EN
4 EN
OUT7 19
3 IF_SEL
5%
85
BKL_SDA
11 SDA
OMIT
NO STUFF
1
C9723
0.1UF
10%
2 25V
X5R
402
BKL_ISEN1
R9715
100K
1%
1/16W
MF-LF
402
10.2 2
LED_RETURN_1
OUT
7 80
OUT
7 80
OUT
7 80
OUT
7 80
OUT
7 80
OUT
7 80
0.1%
1/16W
TF
402
R9718
1
10.2 2
LED_RETURN_2
0.1%
1/16W
TF
402
R9719
NC
1
1 GND_SW
1%
1/16W
MF-LF
402
301K
10 SCLK
1/16W MF-LF 402
R9731
86 85
BKL_SCL
LVDS_BKL_PWM_RC
1
7
15 GND_L
R9717
FB 21
THRM
PAD
10.2 2
LED_RETURN_3
0.1%
1/16W
TF
402
R9720
25
SW 24
OUT1 12
9 GND_S
91 60 45 21
R9753
SMBUS_MCP_1_CLK
6 ALSO
5 ALSI
BKL_IF_SEL
91 60 45 21
LP8543SQX
LLP
NO STUFF
1
1
10.2 2
LED_RETURN_4
0.1%
1/16W
TF
402
R9721
R9704
84
IN
LCD_BKLT_PWM
1
5%
1/16W
MF-LF
402
XW9710
SM
C9704
33PF
5%
2 50V
CERM
402
BKL_SGND
LED_RETURN_5
0.1%
1/16W
TF
402
NO STUFF
R9704 SHOULD BE 47K IF RC FILTER IS USED
10.2 2
R9722
1
PLACE XW9700 CLOSE TO C9712 AND C9713
10.2 2
LED_RETURN_6
0.1%
1/16W
TF
402
LCD BACKLIGHT DRIVER

TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
U9701
CRITICAL
SYNC_MASTER=DDR
BOM OPTION
TABLE_5_ITEM
353S2670
IC,LP8543,WHT LED BKLT,PROD

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
85
97
CRITICAL
Q9806
FDC638APZ_SBMS001
CRITICAL
1 2 5 6
F9800
IN
2
0402-HF
PPBUS_S0_LCDBKLT_FUSED
VOLTAGE=12.6V
R9808
301K
C9802
0.1UF
1%
1/16W
MF-LF
2 402
MOSFET
FDC638APZ
CHANNEL
P-TYPE
RDS(ON)
LOADING
10%
16V
2 X5R
402
43 mOhm @4.5V
0.4 A (EDP)
PPBUS_G3H
2AMP-32V
67 66 65 64 62 61 46 37 8 7
83 79
PPBUS S0 LCDBkLT FET
SSOT6-HF
PPBUS_S0_LCDBKLT_EN_DIV
R9809
147K
1%
1/16W
MF-LF
2 402
PPBUS_S0_LCDBKLT_EN_L
Q9807
D 3
SSM6N15FEAPE
SOT563
86 84 9
IN
5 G
LCD_BKLT_EN
S 4
OUT
VOLTAGE=12.6V
BKLT_EN_L
Q9807
85
D 6
SSM6N15FEAPE
SOT563
C
26
IN
2 G
BKLT_PLT_RST_L
S 1
LCD_BKLT_EN 9
84 86
R9840
4.7K
5%
1/16W
MF-LF
2 402
LCD Backlight Support
SYNC_MASTER=YITE_M98_MLB

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
86
97
1.8V/1.2V S0 SWITCHER
D
37 34 30 26 24 22 20 18 8 7
96 82 70 69 68 64 54 44 38
PP3V3_S5
CRITICAL
C9900 1
L9980
10UF
2.2UH-1.2A
20%
6.3V 2
X5R
603
PP1V2_S0
1
2
PCAA031B-SM
P1V2S0_SW
SWITCH_NODE=TRUE
DIDT=TRUE
<Ra>
C9982 1
10PF
5%
50V
CERM 2
402
R9982
(Switcher limit)
1%
1/16W
MF-LF
2 402
69
IN
P1V2R1V8S0_EN
3 MODE
<Rb>
R9983
SW2 6
1 VFB1
20%
2 6.3V
X5R
603
280K
DFN RUN2
CRITICAL
4 SW1
C9985
10UF
U9900
f = 2.25 MHz
1
1%
1/16W
MF-LF
2 402
LTC3419
2 RUN1
0.6A max output
280K
P1V2S0_VFB
5
VIN
8 84
Vout = 1.2V
VFB2 8
CRITICAL
L9900
P1V8S0_SW
SWITCH_NODE=TRUE
DIDT=TRUE
2.2UH-1.2A
PP1V8_S0
1
2
PCAA031B-SM
Vout = 1.8V
C9901 1
10PF
THRM
PAD
5%
50V
CERM 2
402
P2V5S0_VFB
<Ra>
0.6A max output
R9900
475K
(Switcher limit)
1%
1/16W
MF-LF
2 402
f = 2.25 MHz
1
<Rb>
1
R9901
237K
7 8 18 25 55 69 70 84
C9905
10UF
20%
6.3V
603
2 X5R
1%
1/16W
MF-LF
2 402
Vout = 0.6V * (1 + Ra/Rb)
Misc Power Supplies
SYNC_MASTER=MUXGFX

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
87
97
FSB (Front-Side Bus) Constraints
CPU / FSB Net Properties

TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
FSB_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
TABLE_SPACING_RULE_ITEM
FSB_DATA
=2x_DIELECTRIC
FSB_DSTB
=3x_DIELECTRIC
FSB_DATA
TOP,BOTTOM
=4x_DIELECTRIC
FSB_DSTB
TOP,BOTTOM
=5x_DIELECTRIC
FSB_ADDR
=STANDARD
FSB_ADDR
TOP,BOTTOM
=3x_DIELECTRIC
FSB_ADSTB
=2x_DIELECTRIC
FSB_ADSTB
TOP,BOTTOM
=4x_DIELECTRIC
FSB_1X
=STANDARD
FSB 4X Signal Groups
FSB_DSTB_50S
FSB_1X
TOP,BOTTOM
=3x_DIELECTRIC
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
FSB 2X
Signals
FSB 4X signals / groups shown in signal table on right.

Signals within each 4x group should be matched within 5 ps of strobe.
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.
FSB 2X signals / groups shown in signal table on right.
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.
FSB 1X signals shown in signal table on right.
Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.
FSB 1X Signals
Design Guide recommends each strobe/signal group is routed on the same layer.
Intel Design Guide recommends FSB signals be routed only on internal layers.
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
CPU Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
CPU_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
CPU_27P4S
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
7 MIL
7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
SPACING_RULE_SET
WEIGHT
CPU_AGTL
LAYER
*
=STANDARD
CPU_8MIL
8 MIL
SPACING_RULE_SET
LAYER
WEIGHT
=2x_DIELECTRIC
CPU_AGTL
TOP,BOTTOM
CPU_COMP
25 MIL
CPU_GTLREF
25 MIL
SR DG recommends at least 25 mils, >50 mils preferred

CPU_ITP
=2:1_SPACING
CPU_VCCSENSE
25 MIL
Most CPU signals with impedance requirements are 55-ohm single-ended.

Some signals require 27.4-ohm single-ended impedance.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
MCP FSB COMP Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MCP_50S
=50_OHM_SE
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
MCP_FSB_COMP
8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4
FSB Clock Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
CLK_FSB
=3x_DIELECTRIC
CLK_FSB
TOP,BOTTOM
=4x_DIELECTRIC
FSB_50S
FSB_50S
FSB_DSTB_50S
FSB_DSTB_50S
FSB_DATA
FSB_DATA
FSB_DSTB
FSB_DSTB
FSB_D_L<15..0>
FSB_DINV_L<0>
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
FSB_DATA_GROUP1
FSB_DATA_GROUP1
FSB_DSTB1
FSB_DSTB1
FSB_50S
FSB_50S
FSB_DSTB_50S
FSB_DSTB_50S
FSB_DATA
FSB_DATA
FSB_DSTB
FSB_DSTB
FSB_D_L<31..16>
FSB_DINV_L<1>
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
FSB_DATA_GROUP2
FSB_DATA_GROUP2
FSB_DSTB2
FSB_DSTB2
FSB_50S
FSB_50S
FSB_DSTB_50S
FSB_DSTB_50S
FSB_DATA
FSB_DATA
FSB_DSTB
FSB_DSTB
FSB_D_L<47..32>
FSB_DINV_L<2>
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_DATA_GROUP3
FSB_DATA_GROUP3
FSB_DSTB3
FSB_DSTB3
FSB_50S
FSB_50S
FSB_DSTB_50S
FSB_DSTB_50S
FSB_DATA
FSB_DATA
FSB_DSTB
FSB_DSTB
FSB_D_L<63..48>
FSB_DINV_L<3>
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_ADDR_GROUP0
FSB_ADDR_GROUP0
FSB_ADSTB0
FSB_50S
FSB_50S
FSB_50S
FSB_ADDR
FSB_ADDR
FSB_ADSTB
FSB_A_L<16..3>
FSB_REQ_L<4..0>
FSB_ADSTB_L<0>
FSB_ADDR_GROUP1
FSB_ADSTB1
FSB_50S
FSB_50S
FSB_ADDR
FSB_ADSTB
FSB_A_L<35..17>
FSB_ADSTB_L<1>
FSB_1X
FSB_BREQ0_L
FSB_BREQ1_L
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_CPURST_L
FSB_1X
FSB_1X
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_ADS_L
FSB_BREQ0_L
FSB_BREQ1_L
FSB_BNR_L
FSB_BPRI_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_CPURST_L
FSB_RS_L<2..0>
FSB_TRDY_L
CPU_ASYNC
CPU_BSEL
CPU_FERR_L
CPU_ASYNC
CPU_INIT_L
CPU_ASYNC_R
CPU_ASYNC_R
CPU_PROCHOT_L
CPU_PWRGD
CPU_ASYNC
CPU_ASYNC
PM_THRMTRIP_L
FSB_CPUSLP_L
CPU_FROM_SB
CPU_DPRSTP_L
CPU_ASYNC
MCP_CPU_COMP
MCP_CPU_COMP
MCP_CPU_COMP
MCP_CPU_COMP
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
MCP_50S
MCP_50S
MCP_50S
MCP_50S
CPU_AGTL
CPU_AGTL
CPU_8MIL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_8MIL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
MCP_FSB_COMP
MCP_FSB_COMP
MCP_FSB_COMP
MCP_FSB_COMP
CPU_A20M_L
CPU_BSEL<2..0>
CPU_FERR_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_PROCHOT_L
CPU_PWRGD
CPU_SMI_L
CPU_STPCLK_L
PM_THRMTRIP_L
FSB_CPUSLP_L
CPU_DPSLP_L
CPU_DPRSTP_L
FSB_DPWR_L
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND
FSB_CLK_CPU
FSB_CLK_CPU
FSB_CLK_ITP
FSB_CLK_ITP
FSB_CLK_MCP
FSB_CLK_MCP
CLK_FSB_100D
CLK_FSB_100D
CLK_FSB_100D
CLK_FSB_100D
CLK_FSB_100D
CLK_FSB_100D
CLK_FSB
CLK_FSB
CLK_FSB
CLK_FSB
CLK_FSB
CLK_FSB
FSB_CLK_CPU_P
FSB_CLK_CPU_N
FSB_CLK_ITP_P
FSB_CLK_ITP_N
FSB_CLK_MCP_P
FSB_CLK_MCP_N
CPU_IERR_L
CPU_50S
PM_DPRSLPVR
(See above)
CPU_50S
CPU_50S
CPU_AGTL
CPU_AGTL
PM_DPRSLPVR
IMVP_DPRSLPVR
CPU_GTLREF
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_50S
CPU_50S
CPU_27P4S
CPU_50S
CPU_27P4S
CPU_GTLREF
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_GTLREF
CPU_COMP<3>
CPU_COMP<2>
CPU_COMP<1>
CPU_COMP<0>
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM_L
XDP_BPM_L5
(FSB_CPURST_L)
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM_L<4..0>
XDP_BPM_L<5>
XDP_CPURST_L
CPU_VCCSENSE
CPU_VCCSENSE
(CPU_VCCSENSE)
(CPU_VCCSENSE)
CPU_50S
CPU_50S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_8MIL
CPU_8MIL
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VID<6..0>
IMVP6_VID<6..0>
CPU_VCCSENSE_P
CPU_VCCSENSE_N
IMVP6_VSEN_P
IMVP6_VSEN_N
CPU_IERR_L
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
7 10 14
10 14
7 10 14
7 10 14
7 10 14
7 10 14
9 10 14
14
10 14
10 14
10 14
10 14
10 14
7 10 14
7 10 14
7 10 14
9 10 13 14
10 14
10 14
10 14
9 10
10 14
10 14
10 14
9 10 14
9 10 14
10 14 43 63
10 13 14
10 14
10 14
10 14 43
10 14
10 14
9 10 14 63
10 14
14
14
14
14
10 14
10 14
13 14
13 14
14
14
10
21 63
63
DIFFPAIR NECK GAP

CLK_FSB_100D
FSB_DATA_GROUP0
FSB_DATA_GROUP0
FSB_DSTB0
FSB_DSTB0
10 27
10
10
10
10
6 10 13
6 10
6 10 13
6 10 13
6 10 13
10 13
10 13
13
9 11
CPU/FSB Constraints
9 63
11 63
SYNC_MASTER=MUXGFX
11 63
63
63

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
88
97
Memory Bus Constraints
Memory Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
MEM_40S
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
PHYSICAL
SPACING
MEM_40S_VDD
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
MEM_A_CLK
MEM_A_CLK
MEM_70D_VDD
MEM_70D_VDD
MEM_CLK
MEM_CLK
MEM_A_CLK_P<5..0>
MEM_A_CLK_N<5..0>
MEM_A_CNTL
MEM_A_CNTL
MEM_A_CNTL
MEM_40S_VDD
MEM_40S_VDD
MEM_40S_VDD
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_A_CKE<3..0>
MEM_A_CS_L<3..0>
MEM_A_ODT<3..0>
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_40S_VDD
MEM_40S_VDD
MEM_40S_VDD
MEM_40S_VDD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_A_A<14..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
MEM_A_DQ_BYTE0
MEM_A_DQ_BYTE1
MEM_A_DQ_BYTE2
MEM_A_DQ_BYTE3
MEM_A_DQ_BYTE4
MEM_A_DQ_BYTE5
MEM_A_DQ_BYTE6
MEM_A_DQ_BYTE7
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>
MEM_A_DQ_BYTE0
MEM_A_DQ_BYTE1
MEM_A_DQ_BYTE2
MEM_A_DQ_BYTE3
MEM_A_DQ_BYTE4
MEM_A_DQ_BYTE5
MEM_A_DQ_BYTE6
MEM_A_DQ_BYTE7
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>
MEM_A_DQS0
MEM_A_DQS0
MEM_A_DQS1
MEM_A_DQS1
MEM_A_DQS2
MEM_A_DQS2
MEM_A_DQS3
MEM_A_DQS3
MEM_A_DQS4
MEM_A_DQS4
MEM_A_DQS5
MEM_A_DQS5
MEM_A_DQS6
MEM_A_DQS6
MEM_A_DQS7
MEM_A_DQS7
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_B_CLK
MEM_B_CLK
MEM_70D_VDD
MEM_70D_VDD
MEM_CLK
MEM_CLK
MEM_B_CLK_P<5..0>
MEM_B_CLK_N<5..0>
MEM_B_CNTL
MEM_B_CNTL
MEM_B_CNTL
MEM_40S_VDD
MEM_40S_VDD
MEM_40S_VDD
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_B_CKE<3..0>
MEM_B_CS_L<3..0>
MEM_B_ODT<3..0>
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_40S_VDD
MEM_40S_VDD
MEM_40S_VDD
MEM_40S_VDD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_B_A<14..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_DQ_BYTE0
MEM_B_DQ_BYTE1
MEM_B_DQ_BYTE2
MEM_B_DQ_BYTE3
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_B_DQ_BYTE6
MEM_B_DQ_BYTE7
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>
MEM_B_DQ_BYTE0
MEM_B_DQ_BYTE1
MEM_B_DQ_BYTE2
MEM_B_DQ_BYTE3
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_B_DQ_BYTE6
MEM_B_DQ_BYTE7
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
MEM_B_DQS0
MEM_B_DQS0
MEM_B_DQS1
MEM_B_DQS1
MEM_B_DQS2
MEM_B_DQS2
MEM_B_DQS3
MEM_B_DQS3
MEM_B_DQS4
MEM_B_DQS4
MEM_B_DQS5
MEM_B_DQS5
MEM_B_DQS6
MEM_B_DQS6
MEM_B_DQS7
MEM_B_DQS7
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
15 28
15 28
MEM_70D
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
MEM_70D_VDD
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
=4:1_SPACING
MEM_CLK2MEM
MEM_CTRL2CTRL
=2:1_SPACING
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
MEM_CTRL2MEM
=2.5:1_SPACING
MEM_CMD2CMD
=1.5:1_SPACING
MEM_CMD2MEM
=3:1_SPACING
?
MEM_DATA2DATA
=1.5:1_SPACING
?
MEM_DATA2MEM
=3:1_SPACING
MEM_DQS2MEM
=3:1_SPACING
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
MEM_2OTHER
25 MIL
Memory Bus Spacing Group Assignments

TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CLK
MEM_CLK2MEM
MEM_CMD
MEM_CLK
MEM_CMD2MEM
MEM_CLK
MEM_CTRL
MEM_CLK2MEM
MEM_CMD
MEM_CTRL
MEM_CMD2MEM
MEM_CLK
MEM_CMD
MEM_CLK2MEM
MEM_CLK
MEM_DATA
MEM_CLK2MEM
MEM_CLK
MEM_DQS
MEM_CLK2MEM
MEM_CMD
MEM_CMD
MEM_CMD2CMD
MEM_CMD
MEM_DATA
MEM_CMD2MEM
MEM_CMD
MEM_DQS
MEM_CMD2MEM
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CTRL
MEM_CLK
MEM_CTRL2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DATA
MEM_CLK
MEM_DATA2MEM
MEM_CTRL
MEM_CTRL
MEM_CTRL2CTRL
MEM_CTRL
MEM_CMD
MEM_CTRL2MEM
MEM_DATA
MEM_CTRL
MEM_DATA2MEM
MEM_DATA
MEM_CMD
MEM_DATA2MEM
MEM_CTRL
MEM_DATA
MEM_CTRL2MEM
MEM_DATA
MEM_DATA
MEM_DATA2DATA
MEM_CTRL
MEM_DQS
MEM_CTRL2MEM
MEM_DATA
MEM_DQS
MEM_DATA2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DQS
MEM_CLK
MEM_DQS2MEM
MEM_DQS
MEM_CTRL
MEM_DQS2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
MEM_2OTHER
MEM_CTRL
MEM_2OTHER
MEM_CMD
MEM_DQS2MEM
MEM_CMD
MEM_2OTHER
MEM_DQS
MEM_DATA
MEM_DQS2MEM
MEM_DATA
MEM_DQS
MEM_DQS2MEM
MEM_DQS
MEM_2OTHER
Need to support MEM_*-style wildcards!
DDR2:
DQ signals should be matched within 20 ps of associated DQS pair.

DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.
All DQS pairs should be matched within 100 ps of clocks.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.
A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
DDR3:
DQ signals should be matched within 5 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps
No DQS to clock matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
A/BA/cmd signals should be matched within 5 ps of CLK pairs.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
MCP MEM COMP Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

MCP_MEM_COMP
7 MIL
7 MIL
=STANDARD
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
MCP_MEM_COMP
8 MIL
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 28
15 29
15 29
15 29
15 29
15 29
MEM_2OTHER
MEM_DQS
15 28
MEM_DQS
15 28
NET_SPACING_TYPE1
15 28
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
15 29
Memory Constraints
15 29
15 29
SYNC_MASTER=MUXGFX
15 29
15 29
15 29

16
16

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
89
97
PCI-Express
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCIE_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
13.1 MM
=90_OHM_DIFF
=90_OHM_DIFF
NET_TYPE
PHYSICAL
SPACING
CLK_PCIE_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
PEG_R2D
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
PCIE
=3X_DIELECTRIC
PEG_D2R
PCIE
TOP,BOTTOM
=4X_DIELECTRIC
CLK_PCIE
20 MIL
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PEG_R2D_P<15..0>
PEG_R2D_N<15..0>
PEG_R2D_C_P<15..0>
PEG_R2D_C_N<15..0>
PEG_D2R_P<15..0>
PEG_D2R_N<15..0>
PEG_D2R_C_P<15..0>
PEG_D2R_C_N<15..0>
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE_MINI_R2D_P
PCIE_MINI_R2D_N
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE_EXCARD_R2D_P
PCIE_EXCARD_R2D_N
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
MCP_PEX_COMP
PEG_CLK100M_P
PEG_CLK100M_N
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
MCP_PEX_CLK_COMP
CRT
CRT
CRT
CRT_SYNC
CRT_SYNC
MCP_DAC_COMP
MCP_DAC_COMP
NC_CRT_IG_R_C_PR
NC_CRT_IG_G_Y_Y
NC_CRT_IG_B_COMP_PB
NC_CRT_IG_HSYNC
NC_CRT_IG_VSYNC
NC_MCP_TV_DAC_RSET
NC_MCP_TV_DAC_VREF
71
71
9 71
9 71
9 71
9 71
71
71
MCP_PEX_COMP
8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4

PCIE_MINI_R2D
Analog Video Signal Constraints

PCIE_MINI_D2R
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
CRT_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
7 31 96
7 31 96
17 31
17 31
7 17 31
7 17 31
SPACING_RULE_SET
LAYER
WEIGHT
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
CRT
=4:1_SPACING
PCIE_FW_R2D
SPACING_RULE_SET
CRT
CRT
CRT_2CRT
PCIE_FW_D2R
CRT_2CRT
=STANDARD
?
CRT_2CLK
50 MIL
36
36
17 36
17 36
17 36
17 36
36
36
CRT_2SWITCHER
250 MIL
?
CRT_SYNC
16 MIL
MCP_DAC_COMP
=2:1_SPACING
PCIE_EXCARD_R2D
CRT signal single-ended impedence varies by location:

- 37.5-ohm from MCP to first termination resistor.
- 50-ohm from first to second termination resistor.
- 75-ohm from output of three-pole filter to connector (if possible).
R/G/B signals should be matched as close as possible and < 10 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2.
PCIE_EXCARD_D2R
Digital Video Signal Constraints
MCP_PE2_REFCLK
MCP_PE0_REFCLK
MCP_PE1_REFCLK
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
MCP_PE3_REFCLK
DIFFPAIR NECK GAP

DP_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
LVDS_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
MCP_DV_COMP
20 MIL
20 MIL
=STANDARD
=STANDARD
=STANDARD
MCP_PEX_CLK_COMP
96
96
9 17
9 17
9 17
9 17
17 71
17 71
17 31
17 31
17 36
17 36
9 17
9 17
17
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
DISPLAYPORT
=3x_DIELECTRIC
DISPLAYPORT
TOP,BOTTOM
=4x_DIELECTRIC
LVDS
=3x_DIELECTRIC
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
SATA Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SATA_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
WEIGHT
SATA
LAYER
*
=4x_DIELECTRIC
SATA_TERMP
8 MIL
SPACING_RULE_SET
LAYER
WEIGHT
=3x_DIELECTRIC
SATA
TOP,BOTTOM
CRT_50S
CRT_50S
CRT_50S
CRT_50S
CRT_50S
TMDS_IG_TXC
TMDS_IG_TXC
TMDS_IG_TXD
TMDS_IG_TXD
DP_100D
DP_100D
DP_100D
DP_100D
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
TMDS_IG_TXC_P
TMDS_IG_TXC_N
TMDS_IG_TXD_P<2..0>
TMDS_IG_TXD_N<2..0>
DP_ML
DP_ML
DP_AUX_CH
DP_AUX_CH
DP_100D
DP_100D
DP_100D
DP_100D
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DP_IG_ML_P<3..0>
DP_IG_ML_N<3..0>
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
MCP_HDMI_RSET
MCP_HDMI_VPROBE
MCP_DV_COMP
MCP_DV_COMP
LVDS_IG_A_CLK
LVDS_IG_A_CLK
LVDS_IG_A_DATA
LVDS_IG_A_DATA
LVDS_IG_A_DATA3
LVDS_IG_A_DATA3
LVDS_IG_B_CLK
LVDS_IG_B_CLK
LVDS_IG_B_DATA
LVDS_IG_B_DATA
LVDS_IG_B_DATA3
LVDS_IG_B_DATA3
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
MCP_DV_COMP
SATA_HDD_R2D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
18 25
18 25
18 25
18 25
18 25
18 25
18 25
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
CRT_RED
CRT_GREEN
CRT_BLUE
CRT_SYNC
CRT_SYNC
MCP_DAC_RSET
MCP_DAC_VREF
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
SATA_HDD_D2R
SATA_ODD_R2D
SATA_ODD_D2R
MCP_SATA_TERMP
MCP_HDMI_RSET
MCP_HDMI_VPROBE
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA_N<2..0>
NC_LVDS_IG_B_CLKP
NC_LVDS_IG_B_CLKN
LVDS_IG_B_DATA_P<2..0>
LVDS_IG_B_DATA_N<2..0>
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA_TERMP
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
MCP_SATA_TERMP
9 81
9 81
18 81
18 81
18 25
18 25
18 84
18 84
18 84
18 84
9 18
9 18
9 18
9 18
18 84
18 84
9 18
9 18
18 25
18 25
20 39
20 39
7 39
7 39
20 39
20 39
7 39
7 39
20 39
20 39
7 39
MCP Constraints 1
7 39
20 39
SYNC_MASTER=MUXGFX
20 39
7 39
7 39

20

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
90
97
PCI Bus Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
PHYSICAL
SPACING
CLK_PCI_55S
SPACING_RULE_SET
LAYER
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
WEIGHT
PCI
=STANDARD
CLK_PCI
8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.
LPC Bus Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
LPC_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
CLK_LPC_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
WEIGHT
LPC
LAYER
*
6 MIL
CLK_LPC
8 MIL
MCP_DEBUG
PCI_AD
PCI_AD24
PCI_AD
PCI_AD
PCI_C_BE_L
PCI_CNTL
PCI_CNTL
PCI_CNTL
PCI_CNTL
PCI_CNTL
PCI_CNTL
PCI_CNTL
PCI_REQ0_L
PCI_GNT0_L
PCI_REQ1_L
PCI_GNT1_L
PCI_INTW_L
PCI_INTX_L
PCI_INTY_L
PCI_INTZ_L
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
MCP_DEBUG<7..0>
PCI_AD<23..8>
PCI_AD<24>
PCI_AD<31..25>
PCI_PAR
PCI_C_BE_L<3..0>
PCI_IRDY_L
PCI_DEVSEL_L
PCI_PERR_L
PCI_SERR_L
PCI_STOP_L
PCI_TRDY_L
PCI_FRAME_L
PCI_REQ0_L
PCI_GNT0_L
PCI_REQ1_L
PCI_GNT1_L
PCI_INTW_L
PCI_INTX_L
PCI_INTY_L
PCI_INTZ_L
MCP_PCI_CLK2
CLK_PCI_55S
CLK_PCI_55S
CLK_PCI
CLK_PCI
PCI_CLK33M_MCP_R
PCI_CLK33M_MCP
LPC_AD
LPC_FRAME_L
LPC_RESET_L
LPC_55S
LPC_55S
LPC_55S
LPC
LPC
LPC
LPC_AD<3..0>
LPC_FRAME_L
LPC_RESET_L
MCP_LPC_CLK0
CLK_LPC_55S
CLK_LPC_55S
CLK_LPC_55S
CLK_LPC
CLK_LPC
CLK_LPC
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB_EXTA_P
USB_EXTA_N
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
NC_USB_MINIP
NC_USB_MININ
NC_USB_EXTDP
NC_USB_EXTDN
USB_CAMERA_P
USB_CAMERA_N
USB_BT_P
USB_BT_N
USB_TPAD_P
USB_TPAD_N
USB_IR_P
USB_IR_N
USB_EXTB_P
USB_EXTB_N
NC_USB_EXCARDP
NC_USB_EXCARDN
NC_USB_EXTCP
NC_USB_EXTCN
USB 2.0 Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
13 19
D
19
19
19
19
19 42 44 84
19 42 44 84
19 26 84
MCP_USB_RBIAS
=STANDARD
8 MIL
8 MIL
=STANDARD
=STANDARD
=STANDARD
USB_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
=2x_DIELECTRIC
LAYER
WEIGHT
=4x_DIELECTRIC
USB
USB_EXTA
SPACING_RULE_SET
USB
TOP,BOTTOM
USB_MINI
SMBus Interface Constraints
USB_EXTD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SMB_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
USB_CAMERA
USB_BT
SPACING_RULE_SET
LAYER
WEIGHT
USB_TPAD
SMB
=2x_DIELECTRIC
USB_IR
USB_EXTB
HD Audio Interface Constraints

USB_EXCARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
=55_OHM_SE
=55_OHM_SE
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

HDA_55S
=55_OHM_SE
=55_OHM_SE
=STANDARD
USB_EXTC
=STANDARD
19 26
26 42
26 44
20 40
20 40
9 20
9 20
9 20
9 20
7 20 31
7 20 31
7 20 31
7 20 31
20 50
20 50
20 41
20 41
20 40
20 40
9 20
9 20
9 20
9 20
SPACING_RULE_SET
LAYER
WEIGHT
MCP_USB_RBIAS_GND
MCP_USB_RBIAS
MCP_USB_RBIAS
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
SMB_55S
SMB_55S
SMB_55S
SMB_55S
SMB
SMB
SMB
SMB
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
HDA_BIT_CLK
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
HDA_SDIN_CODEC
HDA_SDOUT
HDA_SDOUT_R
MCP_HDA_COMP
MCP_HDA_PULLDN_COMP
21
CLK_SLOW_55S
CLK_SLOW_55S
CLK_SLOW
CLK_SLOW
PM_CLK32K_SUSCLK_R
PM_CLK32K_SUSCLK
26 42
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_MISO_R
SPI_CS0_R_L
SPI_CS0_L
20
HDA
=2x_DIELECTRIC
MCP_HDA_COMP
8 MIL
SIO Signal Constraints

HDA_SYNC
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

CLK_SLOW_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
HDA_RST_L
=STANDARD
HDA_SDIN0
SPACING_RULE_SET
LAYER
WEIGHT
8 MIL
CLK_SLOW
HDA_SDOUT
MCP_HDA_PULLDN_COMP
SPI Interface Constraints
MCP_SUS_CLK
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SPI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPI_CLK
SPI_MOSI
SPACING_RULE_SET
LAYER
WEIGHT
8 MIL
SPI_MISO
SPI
SPI_CS0
13 21 28 29 45
13 21 28 29 45
21 45 60 85
21 45 60 85
21 55
21
21 55
21
21
21 55
21 55
21 55
21
21 26
21 44
54
21 44
54
21 44
54
21 44
MCP Constraints 2
SYNC_MASTER=MUXGFX

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
91
97
MCP RGMII (Ethernet) Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
MCP_MII_COMP
=STANDARD
7.5 MIL
7.5 MIL
=STANDARD
=STANDARD
=STANDARD
NET_TYPE
PHYSICAL
SPACING
ENET_MII_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
MCP_MII_COMP
MCP_MII_COMP
MCP_CLK25M_BUF0
ENET_MII_55S
ENET_MII_55S
MCP_BUF0_CLK
MCP_BUF0_CLK
MCP_CLK25M_BUF0_R
ENET_INTR_L
ENET_MDIO
ENET_MDC
ENET_PWRDWN_L
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII
ENET_MII
ENET_MII
ENET_MII
ENET_INTR_L
ENET_MDIO
ENET_MDC
ENET_PWRDWN_L
ENET_RXD
ENET_RXD_STRAP
ENET_RXD
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII
ENET_MII
ENET_MII
ENET_MII
ENET_MII
ENET_MII
ENET_CLK125M_RXCLK_R
ENET_CLK125M_RXCLK
ENET_RXD_R<3..0>
ENET_RXD<0>
ENET_RXD<3..1>
ENET_RX_CTRL
ENET_TXCLK
ENET_TXD0
ENET_TXD
ENET_TXD
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII_55S
ENET_MII
ENET_MII
ENET_MII
ENET_MII
ENET_CLK125M_TXCLK
ENET_TXD<0>
ENET_TXD<3..1>
ENET_TX_CTRL
ENET_MII_55S
ENET_MII
ENET_RESET_L
SPACING_RULE_SET
LAYER
MCP_MII_COMP_VDD
MCP_MII_COMP_GND
MCP_MII_COMP
MCP_MII_COMP
WEIGHT
18
18
18 34
33 34
MCP_BUF0_CLK
=3:1_SPACING
ENET_MII
12 MIL
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4
88E1116R (Ethernet PHY) Constraints
ENET_RXCLK
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
ENET_MDI_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
18 33
18 33
33
18 33
33
18 33
18 33
18 33
SPACING_RULE_SET
LAYER
WEIGHT
25 MIL
ENET_MDI
ENET_MDI
ENET_MDI_100D ENET_MDI
ENET_MDI_100D ENET_MDI
ENET_MDI_P<3..0>
ENET_MDI_N<3..0>
18 33
18 33
18 33
18 33
18 33
33 35
33 35
Ethernet Constraints
SYNC_MASTER=MUXGFX

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
92
97
FireWire Interface Constraints
FireWire Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
FW_110D
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
NET_TYPE
PHYSICAL
SPACING
FW_P0_TPA
FW_P0_TPA
FW_P0_TPB
FW_P0_TPB
FW_P1_TPA
FW_P1_TPA
FW_P1_TPB
FW_P1_TPB
SPACING_RULE_SET
LAYER
WEIGHT
FW_TP
=3:1_SPACING
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
NC_FW0_TPAP
NC_FW0_TPAN
NC_FW0_TPBP
NC_FW0_TPBN
FW_PORT1_TPA_P
FW_PORT1_TPA_N
FW_PORT1_TPB_P
FW_PORT1_TPB_N
36 38
36 38
36 38
36 38
36 38
36 38
36 38
36 38
D
Port 2 Not Used
SD CARD NET PROPERTIES

NET_TYPE
PHYSICAL
SPACING
SD CARD INTERFACE CONSTRAINTS

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
I32
SD_DATA
SD_55S
SD_INTERFACE
I31
SD_DATA
SD_55S
SD_INTERFACE
I30
SD_DATA
SD_55S
SD_INTERFACE
I29
SD_DATA
SD_55S
SD_INTERFACE
I28
SD_DATA
SD_55S
SD_INTERFACE
I27
SD_DATA
SD_55S
SD_INTERFACE
I26
SD_DATA
SD_55S
SD_INTERFACE
I25
SD_DATA
SD_55S
SD_INTERFACE
I23
SD_CLK
SD_55S
SD_INTERFACE
I24
SD_CMD
SD_55S
SD_INTERFACE
SD_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
SD_INTERFACE
=3X_DIELECTRIC
SD_D<0>
SD_D<1>
SD_D<2>
SD_D<3>
SD_D<4>
SD_D<5>
SD_D<6>
SD_D<7>
7 32
7 32
7 32
7 32
7 32
7 32
7 32
7 32
SD_CLK
SD_CMD
7 32
7 32
FireWire Constraints
SYNC_MASTER=MUXGFX

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
93
97
SMC SMBus Net Properties

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
1TO1_DIFFPAIR
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
NET_TYPE
SPACING
PHYSICAL
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
SMB_55S
SMB_55S
SMB_55S
SMB_55S
SMB_55S
SMB_55S
SMB_55S
SMB_55S
SMB_55S
SMB_55S
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
7 31 42 45 51
7 31 42 45 51
42 45 48
42 45 48
42 45 48 53 78
42 45 48 53 78
7 42 45 61 62
7 42 45 61 62
27 39 42 45
27 39 42 45
SMBus Charger Net Properties

NET_TYPE
PHYSICAL
SPACING
CHGR_CSI
1TO1_DIFFPAIR
1TO1_DIFFPAIR
CHGR_CSI_P
CHGR_CSI_N
CHGR_CSO
1TO1_DIFFPAIR
1TO1_DIFFPAIR
CHGR_CSO_P
CHGR_CSO_N
62
62
62
62
SMC Constraints
SYNC_MASTER=MUXGFX

SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
94
97
GDDR3 Frame Buffer Signal Constraints
GDDR3 FB A/B Net Properties
GDDR3 FB C/D Net Properties
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

GDDR3_40R55SE
=55_OHM_SE
=40_OHM_SE
0.095 MM
12.7 MM
=STANDARD
=STANDARD
GDDR3_40SE
=40_OHM_SE
=40_OHM_SE
0.095 MM
=40_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
GDDR3_CLK
GDDR3_CLK
GDDR3_CLK
GDDR3_CLK
FB_A_CLK_P<0>
FB_A_CLK_N<0>
FB_A_CLK_P<1>
FB_A_CLK_N<1>
FB_AB_CMD
FB_AB_CMD
FB_AB_CMD
FB_AB_CMD
FB_AB_CMD
FB_AB_CMD
FB_AB_CMD_PD
FB_AB_CMD_PD
FB_AB_CS0
FB_AB_CMD_PD
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
FB_A_MA<1..0>
FB_A_MA<12..6>
FB_A_BA<2..0>
FB_A_RAS_L
FB_A_CAS_L
FB_A_WE_L
FB_A_UCKE
FB_A_LCKE
FB_A_LCS0_L
FB_A_DRAM_RST
FB_A_CMD
FB_B_CMD
GDDR3_40SE
GDDR3_40SE
GDDR3_CMD
GDDR3_CMD
FB_A_LMA<5..2>
FB_A_UMA<5..2>
FB_A_WDQS0
FB_A_WDQS1
FB_A_WDQS2
FB_A_WDQS3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
FB_A_WDQS<0>
FB_A_WDQS<1>
FB_A_WDQS<2>
FB_A_WDQS<3>
FB_A_RDQS0
FB_A_RDQS1
FB_A_RDQS2
FB_A_RDQS3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
FB_A_RDQS<0>
FB_A_RDQS<1>
FB_A_RDQS<2>
FB_A_RDQS<3>
FB_A_DQ_BYTE0
FB_A_DQ_BYTE1
FB_A_DQ_BYTE2
FB_A_DQ_BYTE3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
FB_A_DQ<7..0>
FB_A_DQ<15..8>
FB_A_DQ<23..16>
FB_A_DQ<31..24>
FB_A_DQM0
FB_A_DQM1
FB_A_DQM2
FB_A_DQM3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
FB_A_DQM_L<0>
FB_A_DQM_L<1>
FB_A_DQM_L<2>
FB_A_DQM_L<3>
FB_B_WDQS0
FB_B_WDQS1
FB_B_WDQS2
FB_B_WDQS3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
FB_A_WDQS<4>
FB_A_WDQS<5>
FB_A_WDQS<6>
FB_A_WDQS<7>
FB_B_RDQS0
FB_B_RDQS1
FB_B_RDQS2
FB_B_RDQS3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
FB_A_RDQS<4>
FB_A_RDQS<5>
FB_A_RDQS<6>
FB_A_RDQS<7>
FB_B_DQ_BYTE0
FB_B_DQ_BYTE1
FB_B_DQ_BYTE2
FB_B_DQ_BYTE3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
FB_A_DQ<39..32>
FB_A_DQ<47..40>
FB_A_DQ<55..48>
FB_A_DQ<63..56>
FB_B_DQM0
FB_B_DQM1
FB_B_DQM2
FB_B_DQM3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
FB_A_DQM_L<4>
FB_A_DQM_L<5>
FB_A_DQM_L<6>
FB_A_DQM_L<7>
GDDR3_80D
=80_OHM_DIFF
=80_OHM_DIFF
0.095 MM
=80_OHM_DIFF
=80_OHM_DIFF
FB_B_CLK_P
=80_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
GDDR3_CLK
=2.5:1_SPACING
?
GDDR3_CMD
=2.5:1_SPACING
GDDR3_DATA
=2.5:1_SPACING
GDDR3_DQS
=2.5:1_SPACING
I205
From T18 MXM:

Digital Video Signal Constraints
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

DP_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
LVDS_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
NET_TYPE
SPACING
GDDR3_80D
GDDR3_80D
GDDR3_80D
GDDR3_80D
FB_A_CLK_P
PHYSICAL
GDDR3_CLK
GDDR3_CLK
GDDR3_CLK
GDDR3_CLK
FB_B_CLK_P<0>
FB_B_CLK_N<0>
FB_B_CLK_P<1>
FB_B_CLK_N<1>
FB_CD_CMD
FB_CD_CMD
FB_CD_CMD
FB_CD_CMD
FB_CD_CMD
FB_CD_CMD
FB_CD_CMD_PD
FB_CD_CMD_PD
FB_CD_CS0
FB_CD_CMD_PD
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_40R55SE
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
GDDR3_CMD
FB_B_MA<1..0>
FB_B_MA<12..6>
FB_B_BA<2..0>
FB_B_RAS_L
FB_B_CAS_L
FB_B_WE_L
FB_B_UCKE
FB_B_LCKE
FB_B_LCS0_L
FB_B_DRAM_RST
FB_C_CMD
FB_D_CMD
GDDR3_40SE
GDDR3_40SE
GDDR3_CMD
GDDR3_CMD
FB_B_LMA<5..2>
FB_B_UMA<5..2>
FB_C_WDQS0
FB_C_WDQS1
FB_C_WDQS2
FB_C_WDQS3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
FB_B_WDQS<0>
FB_B_WDQS<1>
FB_B_WDQS<2>
FB_B_WDQS<3>
FB_C_RDQS0
FB_C_RDQS1
FB_C_RDQS2
FB_C_RDQS3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
FB_B_RDQS<0>
FB_B_RDQS<1>
FB_B_RDQS<2>
FB_B_RDQS<3>
FB_C_DQ_BYTE0
FB_C_DQ_BYTE1
FB_C_DQ_BYTE2
FB_C_DQ_BYTE3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
FB_B_DQ<7..0>
FB_B_DQ<15..8>
FB_B_DQ<23..16>
FB_B_DQ<31..24>
FB_C_DQM0
FB_C_DQM1
FB_C_DQM2
FB_C_DQM3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
FB_B_DQM_L<0>
FB_B_DQM_L<1>
FB_B_DQM_L<2>
FB_B_DQM_L<3>
FB_D_WDQS0
FB_D_WDQS1
FB_D_WDQS2
FB_D_WDQS3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
FB_B_WDQS<4>
FB_B_WDQS<5>
FB_B_WDQS<6>
FB_B_WDQS<7>
FB_D_RDQS0
FB_D_RDQS1
FB_D_RDQS2
FB_D_RDQS3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
GDDR3_DQS
FB_B_RDQS<4>
FB_B_RDQS<5>
FB_B_RDQS<6>
FB_B_RDQS<7>
FB_D_DQ_BYTE0
FB_D_DQ_BYTE1
FB_D_DQ_BYTE2
FB_D_DQ_BYTE3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
FB_B_DQ<39..32>
FB_B_DQ<47..40>
FB_B_DQ<55..48>
FB_B_DQ<63..56>
FB_D_DQM0
FB_D_DQM1
FB_D_DQM2
FB_D_DQM3
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_40SE
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
GDDR3_DATA
FB_B_DQM_L<4>
FB_B_DQM_L<5>
FB_B_DQM_L<6>
FB_B_DQM_L<7>
73 74
FB_D_CLK_P
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 74
I204
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 74
SPACING
GDDR3_80D
GDDR3_80D
GDDR3_80D
GDDR3_80D
FB_C_CLK_P
73 74
PHYSICAL
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
=3x_DIELECTRIC
LVDS
=3x_DIELECTRIC
73 74
73 74
73 74
73 75
73 75
73 75
73 75
WEIGHT
DISPLAYPORT
73 74
DISPLAYPORT
TOP,BOTTOM
=4x_DIELECTRIC
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
MUXGFX Net Properties
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 74
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
73 75
G96 Net Properties

NET_TYPE
I148
I149
I199
I198
I152
I153
I201
I200
LVDS_A_CLK
LVDS_A_CLK
LVDS_A_DATA
LVDS_A_DATA
NET_TYPE
PHYSICAL
SPACING
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS
LVDS
LVDS
LVDS
LVDS_A_CLK_P
LVDS_A_CLK_N
81 84
LVDS_B_CLK
LVDS_B_CLK
LVDS_100D
LVDS_100D
LVDS
LVDS
LVDS_B_CLK_P
LVDS_B_CLK_N
LVDS_B_DATA
LVDS_B_DATA
LVDS_100D
LVDS_100D
LVDS
LVDS
LVDS_B_DATA_P<2..0>
LVDS_B_DATA_N<2..0>
81 84
81 84
81 84
81 84
I142
81 84
I144
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
I183
I182
I184
I185
I190
I191
I192
I193
I194
I195
I196
I197
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
CK505_CLK27MSS
LVDS_EG_A_CLK
LVDS_EG_A_CLK
LVDS_EG_A_DATA
LVDS_EG_A_DATA
CLK_SLOW
CLK_SLOW
LVDS
LVDS
LVDS
LVDS
GPU_CLK27M
GPU_CLK27M_SS
LVDS_EG_A_CLK_P
LVDS_EG_A_CLK_N
LVDS_EG_A_DATA_P<2..0>
LVDS_EG_A_DATA_N<2..0>
LVDS_EG_B_DATA
LVDS_EG_B_DATA
LVDS_100D
LVDS_100D
LVDS
LVDS
LVDS_EG_B_DATA_P<2..0>
LVDS_EG_B_DATA_N<2..0>
DP_ML
DP_ML
DP_AUX_CH
DP_AUX_CH
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
81 84
81 84
LVDS_CONN_A_CLK_F_P
7 80
LVDS_CONN_A_CLK_F_N
7 80
LVDS_CONN_B_CLK_F_P
7 80
LVDS_CONN_B_CLK_F_N
7 80
LVDS_CONN_A_CLK_P
80 81
LVDS_CONN_A_CLK_N
80 81
LVDS_CONN_A_DATA_P<2..0> 7 80
LVDS_CONN_A_DATA_N<2..0> 7 80
LVDS_CONN_B_CLK_P
80 81
LVDS_CONN_B_CLK_N
80 81
LVDS_CONN_B_DATA_P<2..0> 7 80
LVDS_CONN_B_DATA_N<2..0> 7 80
I145
I143
SPACING
CLK_SLOW_55S
CLK_SLOW_55S
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
(CK505_DOT96)
LVDS_A_DATA_P<2..0>
LVDS_A_DATA_N<2..0>
PHYSICAL
I139
I138
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DP_EG_ML_P<3..0>
DP_EG_ML_N<3..0>
DP_EG_AUX_CH_P
DP_EG_AUX_CH_N
DP_EG_AUX_CH_C_P
DP_EG_AUX_CH_C_N
76 77
76 77
78 84
78 84
78 84
78 84
78 84
78 84
78 81
78 81
78 81
78 81
81
81
81
81
81
81
GPU (G96) CONSTRAINTS
I161
DP_ML
I160
I155
DP_ML
I157
I202
DP_ML
I203
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DP_ML_C_P<3..0>
DP_ML_C_N<3..0>
DP_ML_P<3..0>
DP_ML_P<3..0>
DP_ML_N<3..0>
DP_ML_N<3..0>
DP_ML_CONN_P<3..0>
DP_ML_CONN_N<3..0>
SYNC_MASTER=MUXGFX
7 82
82
81 82

81 82
82
82

I159
I158
DP_AUX_CH
DP_AUX_CH
DP_100D
DP_100D
DISPLAYPORT
DISPLAYPORT
DP_AUX_CH_C_P
DP_AUX_CH_C_N
SIZE
81 82
DRAWING NUMBER
81 82
APPLE INC.
SCALE
SHT
NONE
REV.
051-7892
A.0.0
OF
95
97
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
5
K19 Specific Net Properties
K19 Specific Net Properties

NET_TYPE
NET_TYPE
SENSE_1TO1_55S
=55_OHM_SE
=1:1_DIFFPAIR
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
THERM_1TO1_55S
=55_OHM_SE
=1:1_DIFFPAIR
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
I146
I145
I144
I142
SPACING_RULE_SET
LAYER
WEIGHT
I143
I140
SENSE
=2:1_SPACING
THERM
=2:1_SPACING
I141
I139
SENSE_DIFFPAIR
AUDIO
=2:1_SPACING
SPACING_RULE_SET
LAYER
I124
WEIGHT
I125
ENETCONN
25 MILS
CPUTHMSNS_D2_DP
I127
CPU_THERMD_DP
I126
SPACING_RULE_SET
LAYER
I128
WEIGHT
I130
GND
=STANDARD
PP1V8_MEM
=STANDARD
GPUTHMSNS_D_DP
I129
GPU_THERMD_DP
I138
SPACING_RULE_SET
LAYER
MCPTHMSNS_D_DP
I137
WEIGHT
I135
MCP_THERMD_DP
I136
GND_P2MM
0.20 MM
1000
PWR_P2MM
0.20 MM
1000
I156
SENSE_DIFFPAIR
I157
SPACING
PHYSICAL
ENET_MDI_100D
ENET_MDI_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SENSE_1TO1_55S
SENSE_1TO1_55S
ENETCONN
ENETCONN
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SENSE
SENSE
ENETCONN_P<3..0>
ENETCONN_N<3..0>
SATA_ODD_R2D_UF_P
SATA_ODD_R2D_UF_N
SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N
SATA_HDD_D2R_UF_P
SATA_HDD_D2R_UF_N
SATA_HDD_R2D_UF_P
SATA_HDD_R2D_UF_N
GFXIMVP6_VSEN_P
GFXIMVP6_VSEN_N
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
THERM
THERM
THERM
THERM
THERM
THERM
THERM
THERM
THERM
THERM
THERM
THERM
SENSE
SENSE
CPUTHMSNS_D2_P
CPUTHMSNS_D2_N
CPU_THERMD_P
CPU_THERMD_N
GPUTHMSNS_D_P
GPUTHMSNS_D_N
GPU_TDIODE_P
GPU_TDIODE_N
MCPTHMSNS_D_P
MCPTHMSNS_D_N
MCP_THMDIODE_P
MCP_THMDIODE_N
CPUVTTISNS_R_P
CPUVTTISNS_R_N
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE
SENSE
SENSE
SENSE
GPUISENS_P
GPUISENS_N
CPUVTT_ISNS_P
CPUVTT_ISNS_N
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE
SENSE
SENSE
SENSE
SB_POWER
SB_POWER
35
I164
(PCIE_EXCARD)
I162
(PCIE_EXCARD)
35
39
I163
39
I161
7 39
(PCIE_MINI)
(PCIE_MINI)
I160
7 39
I159
39
I168
39
I166
39
I167
39
I165
79
I182
(USB_EXTA)
I181
(USB_EXTA)
I179
(USB_EXTA)
I180
(USB_EXTA)
I177
(USB_EXTD)
I178
(USB_EXTD)
I176
(USB_CAMERA)
I175
(USB_CAMERA)
79
48
48
10 48
10 48
48
I174
48
I172
48 76 77
I173
48 76 77
I171
48
I169
USB_CARDREADER
48
I170
21 48
I183
21 48
I184
PHYSICAL
SPACING
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
CLK_PCIE_100D CLK_PCIE
CLK_PCIE_100D CLK_PCIE
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
PCIE_EXCARD_R2D_P
PCIE_EXCARD_R2D_N
PCIE_MINI_R2D_P
PCIE_MINI_R2D_N
CHGR_CSI_R_P
62
CHGR_CSI_R_N
62
CHGR_CSO_R_P
46
CHGR_CSO_R_N
46
USB2_EXTA_MUXED_P
USB2_EXTA_MUXED_N
USB2_LT1_P
USB2_LT1_N
USB_TPAD_R_P
USB_TPAD_R_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
CONN_USB2_BT_P
CONN_USB2_BT_N
USB_LT2_P
USB_LT2_N
USB_CARDREADER_P
USB_CARDREADER_N
DP_IG_AUX_CH_C_P
DP_IG_AUX_CH_C_N
90
90
7 31 90
7 31 90
7 31
7 31
D
62
62
40
40
40
40
50
50
7 31
7 31
7 31
7 31
40
40
9 20 32
9 20 32
81
81
47
47
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
GND
GND_P2MM
I153
I151
MEM_CMD
GND
SENSE_DIFFPAIR
GND_P2MM
I150
SENSE_DIFFPAIR
I152
MEM_CTRL
GND
GND_P2MM
MEM_DATA
GND
GND_P2MM
47
47
47 67
47 67
I158
MEM_DQS
GND
GND_P2MM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
SENSE_DIFFPAIR
I147
I186
SENSE_DIFFPAIR
I185
CLK_PCIE
GND
GND_P2MM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CLK_FSB
GND
GND_P2MM
P1V8GPU_P
P1V8GPU_N
ISNS_CPU_P
ISNS_CPU_N
PP3V3_S5
PP3V3_S0
47
I198
47
I197
46
I201
46
82 87
37 38 44 54 64 68 69 70
7 8 18 20 22 24 26 30 34
48 49 51 55 59 60 63 68
6 7 8 13 18 19 21 22 24
25 28 29 37 39 43 45 47
69 70 77 80 81 82 84 85
PCIE
GND
GND_P2MM
GND
SPK_OUT
I200
I199
SPK_OUT
I202
I206
SATA
SPK_OUT
GND_P2MM
I207
CPU_COMP
GND
GND_P2MM
CPU_GTLREF
GND
GND_P2MM
USB
GND
GND_P2MM
I134
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
CLK_PCIE
SB_POWER
I133
PWR_P2MM
CPU_VCCSENSE
GND
GND_P2MM
FSB_DSTB
FSB_DSTB
GND_P2MM
I214
SENSE_DIFFPAIR
SATA
SB_POWER
PWR_P2MM
USB
SB_POWER
PWR_P2MM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
I209
I215
I216
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SENSE_DIFFPAIR
SPACING_RULE_SET
I218
SENSE_DIFFPAIR
I217
LVDS
GND
ENET_MDI
GND
GND_P2MM
GND_P2MM
I210
SENSE_DIFFPAIR
I211
Memory Constraint Relaxations
I212
SENSE_DIFFPAIR
I213
I219
Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout.

PHYSICAL_RULE_SET
LAYER
MEM_70D
BOTTOM
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
0.127 MM
6.35 MM
SENSE_DIFFPAIR
I220
P1V8GPUISNS_R_P
P1V8GPUISNS_R_N
ISNS_AIRPORT_P
ISNS_AIRPORT_N
ISNS_AIRPORT_R_P
ISNS_AIRPORT_R_N
ISNS_1V5_S3_R_P
ISNS_1V5_S3_R_N
ISNS_1V5_S3_P
ISNS_1V5_S3_N
ISNS_LCDBKLT_P
ISNS_LCDBKLT_N
ISNS_LCDBKLT_R_P
ISNS_LCDBKLT_R_N
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
I204
47
I205
47
I208
31 53
I203
31 53
I223
SENSE_DIFFPAIR
53
I224
53
I226
SENSE_DIFFPAIR
53
I225
53
I221
SENSE_DIFFPAIR
53 65
I222
53 65
I227
SENSE_DIFFPAIR
53 85
I228
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
SPKRCONN_S_OUT_P
SPKRCONN_S_OUT_N
SPKRCONN_R_OUT_P
SPKRCONN_R_OUT_N
SPKRAMP_L_OUT_P
SPKRAMP_L_OUT_N
SPKRAMP_R_OUT_P
SPKRAMP_R_OUT_N
SPKRAMP_S_OUT_P
SPKRAMP_S_OUT_N
ISNS_ODD_P
39
ISNS_ODD_N
39
ISNS_ODD_R_P
53
ISNS_ODD_R_N
53
ISNS_HDD_P
39
ISNS_HDD_N
39
ISNS_HDD_R_P
53
ISNS_HDD_R_N
53
7 58 59
7 58 59
7 58 59
7 58 59
7 58 59
7 58 59
58
58
58
58
58
58
53
53
53
53
53 85
GND
GND
DIFFPAIR NECK GAP

PHYSICAL_RULE_SET
Graphics ,SATA Constraint Relaxations
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

MEM_40S
OVERRIDE
OVERRIDE
MEM_40S_VDD
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.09 MM
5.8 MM
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
LVDS_100D
BGA
100_DIFF_BGA
DP_100D
BGA
100_DIFF_BGA
0.09 MM
5.8 MM
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.09 MM
5.8 MM
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.09 MM
100 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.09 MM
100 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.09 MM
500 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.1 MM
500 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.1 MM
500 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.1 MM
500 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.1 MM
500 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.25 MM
250 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.23 MM
100 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
MEM_70D
OVERRIDE
OVERRIDE
TABLE_PHYSICAL_ASSIGNMENT_ITEM
MEM_70D_VDD
OVERRIDE
OVERRIDE
SATA_100D
BGA
100_DIFF_BGA
PCIE_90D
OVERRIDE
OVERRIDE
PGA CONSTRAINT RELAXATIONS
USB_90D
OVERRIDE
OVERRIDE
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

PGA_50SE
=50_OHM_SE
0.073 MM
=50_OHM_SE
=1:1_DIFFPAIR
TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
FSB_50S
PGA
PGA_50SE
FSB_DSTB_50S
PGA
PGA_50SE
CPU_50S
PGA
PGA_50SE
MCP_DV_COMP
TOP
OVERRIDE
OVERRIDE
0.073 MM
MCP_MEM_COMP
TOP
OVERRIDE
OVERRIDE
MCP_MII_COMP
TOP
OVERRIDE
OVERRIDE
MCP_USB_RBIAS
TOP
OVERRIDE
OVERRIDE
MCP_DV_COMP
OVERRIDE
OVERRIDE
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
FSB_DATA
PGA
CPU_27P4S
BOTTOM
OVERRIDE
OVERRIDE
PGA
SYNC_MASTER=MUXGFX
PHYSICAL_RULE_SET
PGA_CPU
FSB_ADDR
PGA
PGA_CPU
FSB_ADSTB
PGA
PGA_CPU
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

MEM_40S
ISL4,ISL9
OVERRIDE
OVERRIDE
OVERRIDE
MEM_40S_VDD
ISL3,ISL10
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
FSB_1X
PGA
PGA_CPU
CPU_AGTL
PGA
PGA_CPU
CPU_8MIL
PGA
PGA_CPU
MEM_70D
ISL4,ISL9
OVERRIDE
OVERRIDE
OVERRIDE
MEM_70D_VDD
ISL3,ISL10
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
SIZE
DRAWING NUMBER
REV.
D
APPLE INC.
Ground-referenced memory signals (DQ,DQM,DQS) MAY route on ISL9 (VDD-referenced plane)but not next to VDD island.
Forces power-referenced memory signals (CLK,ADDR,CTRL) to not route on ISL3, ISL4 & ISL10(GND-referenced planes).
PGA_CPU
FSB_DSTB
Project Specific Constraints
SPACING_RULE_SET
051-7892
SCALE
SHT
NONE
A.0.0
OF
96
97
K19 Board-Specific Spacing & Physical Constraints

TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS
(MIL or MM)
ALLEGRO
VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
NO_TYPE,BGA,PGA
MM
15.5.1
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SPACING_RULE_SET
LAYER
WEIGHT
DEFAULT
=50_OHM_SE
=50_OHM_SE
33.6 MM
0 MM
0 MM
DEFAULT
0.1 MM
=DEFAULT
=DEFAULT
10 MM
=DEFAULT
=DEFAULT
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
BGA
BGA_P1MM
MEM_CLK
BGA
BGA_P2MM
CLK_FSB
BGA
BGA_P2MM
CLK_PCIE
BGA
BGA_P2MM
CLK_SLOW
BGA
BGA_P2MM
FSB_DSTB
FSB_DSTB
BGA
BGA_P3MM
STANDARD
NET_SPACING_TYPE1
STANDARD
=DEFAULT
BGA_P1MM
=DEFAULT
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
55_OHM_SE
TOP,BOTTOM
0.090 MM
0.090 MM
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
BGA_P2MM
=DEFAULT
BGA_P3MM
=DEFAULT
PGA_CPU
0.073 MM
WEIGHT
55_OHM_SE
0.076 MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD
NOTE:From T18 MLB, changed to reflect M99 stackup.

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SPACING_RULE_SET
LAYER
50_OHM_SE
TOP,BOTTOM
0.110 MM
0.095 MM
1.5:1_SPACING
0.15 MM
SPACING_RULE_SET
LAYER
WEIGHT
0.140 MM
3X_DIELECTRIC
0.210 MM
4X_DIELECTRIC
0.280 MM
5X_DIELECTRIC
0.350 MM
?
50_OHM_SE
0.090 MM
0.090 MM
=STANDARD
=STANDARD
=STANDARD
1.8:1_SPACING
0.18 MM
2:1_SPACING
0.2 MM
2X_DIELECTRIC
2.5:1_SPACING
0.25 MM
?
3:1_SPACING
0.3 MM
4:1_SPACING
0.4 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
40_OHM_SE
TOP,BOTTOM
0.165 MM
0.095 MM
40_OHM_SE
0.135 MM
0.135 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
27P4_OHM_SE
TOP,BOTTOM
0.310 MM
0.095 MM
27P4_OHM_SE
0.250 MM
0.250 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
70_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
1:1_DIFFPAIR
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
70_OHM_DIFF
ISL3,ISL4
0.160 MM
0.160 MM
0.175 MM
0.175 MM
70_OHM_DIFF
ISL9,ISL10
0.160 MM
0.160 MM
0.175 MM
0.175 MM
70_OHM_DIFF
ISL2,ISL11
0.170 MM
0.170 MM
0.150 MM
0.150 MM
70_OHM_DIFF
TOP,BOTTOM
0.170 MM
0.095 MM
0.150 MM
0.150 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
80_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
80_OHM_DIFF
ISL3,ISL4
0.125 MM
0.125 MM
0.180 MM
0.180 MM
80_OHM_DIFF
ISL9,ISL10
0.125 MM
0.125 MM
0.180 MM
0.180 MM
80_OHM_DIFF
ISL2,ISL11
0.140 MM
0.140 MM
0.190 MM
0.190 MM
80_OHM_DIFF
TOP,BOTTOM
0.140 MM
0.095 MM
0.190 MM
0.190 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
90_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
90_OHM_DIFF
ISL3,ISL4
0.102 MM
0.102 MM
0.220 MM
0.220 MM
90_OHM_DIFF
ISL9,ISL10
0.102 MM
0.102 MM
0.220 MM
0.220 MM
90_OHM_DIFF
ISL2,ISL11
0.115 MM
0.115 MM
0.230 MM
0.230 MM
90_OHM_DIFF
TOP,BOTTOM
0.115 MM
0.095 MM
0.230 MM
0.230 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
DIFFPAIR NECK GAP
MAXIMUM NECK LENGTH
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
100_DIFF_BGA
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
100_DIFF_BGA
ISL3,ISL4
0.075 MM
0.075 MM
0.125 MM
0.125 MM
100_DIFF_BGA
ISL9,ISL10
0.075 MM
0.075 MM
0.125 MM
0.125 MM
100_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
100_OHM_DIFF
ISL3,ISL4
0.080 MM
0.080 MM
0.200 MM
0.200 MM
100_OHM_DIFF
ISL9,ISL10
0.080 MM
0.080 MM
0.200 MM
0.200 MM
PCB Rule Definitions
100_OHM_DIFF
ISL2,ISL11
0.089 MM
0.089 MM
0.220 MM
SYNC_MASTER=M99_MLB
100_OHM_DIFF
TOP,BOTTOM
0.089 MM
0.089 MM
0.220 MM
NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.
0.220 MM
0.220 MM

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
110_OHM_DIFF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD


110_OHM_DIFF
ISL3,ISL4
0.077 MM
0.077 MM
0.330 MM
0.330 MM
110_OHM_DIFF
ISL9,ISL10
0.077 MM
0.077 MM
0.330 MM
0.330 MM
110_OHM_DIFF
ISL2,ISL11
0.077 MM
0.077 MM
0.330 MM
0.330 MM
SIZE
APPLE INC.
110_OHM_DIFF
TOP,BOTTOM
0.077 MM
0.077 MM
0.330 MM
DRAWING NUMBER
SCALE
SHT
0.330 MM
NONE
REV.
051-7892
A.0.0
OF
97
97

Apple Macbook Pro A1386 K19

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Apple Macbook Pro A1386 K19

Uploaded by

Copyright:

Available Formats

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DIMENSIONS ARE IN MILLIMETERS

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DO NOT SCALE DRAWING

LAST_MODIFIED=Fri Apr 24 15:23:24 2009

2.X OR 3.X GHZ

FAN CONN AND CONTROL

(UP TO FOUR PORTS)

System Block Diagram

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

M98 POWER SYSTEM ARCHITECTURE

(18A MAX CURRENT)

(6A MAX CURRENT)

(8A MAX CURRENT)

(5.5A MAX CURRENT)

(12A MAX CURRENT)

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

(25A MAX CURRENT)

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

(5A MAX CURRENT)

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

Power Block Diagram

Power Block Diagram

NOTICE OF PROPRIETARY PROPERTY

Murata alt to Samsung

Maglayers alt to Dale/Vishay

Macronix alt to SST

Toko alt to Delta

Delta alt to TDK Magnetics

Maglayers alt to Cyntec IND

KEMET ALT TO SANYO

ROHM ALT TO KEMET

Maglayer alt to Delta

Low Leakage G96 GPU

CYNTEC alt to YDS

CYNTEC alt to YDS

K19 MLB DEVELOPMENT

K19 BOM Groups

C Bar Code Labels / EEE #s

IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P LQFP

IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12

IR,ENCORE II, CY7C63803-LQXC

IC,32MBIT 8-PIN SPI SERIAL FLASH,SOIC8

K19 MLB DEVELOPMENT

NOTICE OF PROPRIETARY PROPERTY

1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE)

From XDP connector

PLACEMENT_NOTE=Place near pin U1000.AB3

From XDP connector

PLACEMENT_NOTE=Place near pin U1400.F19

GMUX CPLD Programming Port

PLACEMENT_NOTE=Place close to U8000

PLACEMENT_NOTE=Place close to U0600

JTAG Scan Chain

NOTICE OF PROPRIETARY PROPERTY

SATA ODD Connectors