SMT-20 Asmbly PKG CD

2001 by Prentice Hall Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda

Semiconductor
Manufacturing Technology

Michael Quirk & Julian Serda
October 2001 by Prentice Hall

Chapter 20

Assembly and Packaging

Objectives
1. Describe the general trends and design constraints
of assembly and packaging.
2. State and discuss the traditional assembly
methods.
3. Describe the different traditional packaging
options.
4. Discuss the benefits and limitations of seven
advanced assembly and packaging techniques.

Four Important Functions of IC Packaging
1. Protection from the environment and
handling damage.
2. Interconnections for signals into and out of
the chip.
3. Physical support of the chip.
4. Heat dissipation.

Traditional Assembly and Packaging
Wafer Test and Sort
Wire Bond
Die Separation
Plastic Package Final Package and Test
Die Attach
Figure 20.1

Typical IC Packages
Quad flat pack
(QFP)
Leadless chip carrier
(LCC)
Plastic leaded chip carrier
(PLCC)
Dual in-line package
(DIP)
Thin small outline package
(TSOP)
Single in-line package
(SIP)
Figure 20.2

Design Constraints for IC Packaging
Performance
RC Time delay
Number of signal I/Os
Wirebond vs. bump attachment
Package impedance
Signal rise time
Switching transients
Thermal
Size/weight/form
Chip size
Package size
Bond pads size and pitch
Package leads size and pitch
Substrate carrier pads size and pitch
Design of heat sink
Materials
Chip substrate (plastic, ceramic, metal)
Carrier (organic, ceramic)
Thermal expansion mismatch
Lead metallurgy
Cost
Integration into existing process
Package materials
Yield
Assembly
Method of die attach
Package attach (through hole, surface
mount, bumped)
Heat sink assembly
Encapsulation

Levels of IC Packaging
2nd level packaging:
Printed circuit board
assembly
First level packaging:
IC packaging
Final product assembly:
Final assembly of circuit
boards into system

Metal leads for mounting
onto printed circuit board
Pins
Pins are
inserted into
holes then
soldered on
rear of PCB.
Surface-
mount chips
are soldered
on top of
tinned pads
on the PCB.
Edge connector plugs into main system.
PCB subassembly
Main electronics
assembly board
Leads
Figure 20.3

Traditional Assembly
Wafer preparation (backgrind)
Die separation
Die attach
Wire bonding

Schematic of the Backgrind Process
Rotating and
oscillating spindle
Wafer on
rotating chuck
Downforce
Table rotates only during
indexing of wafers
Figure 20.4

Wafer Saw and Sliced Wafer
Wafer
Stage
Blade
Figure 20.5

Typical Leadframe for Die Attach
Die Lead Leadframe
Plastic DIP
Figure 20.6

Epoxy Die Attach
Die
Epoxy
Leadframe
Figure 20.7

Au-Si Eutectic Attach
Silicon
Gold film
Gold/silicon
eutectic alloy
Al
2
O
3

Figure 20.8

Wires Bonded from Chip Bonding Pads to
Leadframe
Moulding compound
Leadframe
Bonding pad
Die
Bond wire
Pin tip
Figure 20.9

Wirebonding Chip to Leadframe

Photo 20.1

Thermocompression Bonds
Post
Device bond pad
Figure 20.10

Ultrasonic Wirebonding Sequence
Wire
Wedge tool
(1)
Tool moves upward.
More wire is
fed to tool.
(3)
Ultrasonic energy
Pressure
Lead frame
(4)
Tool moves upward.
Wire breaks at
the bond.
(5)
(2)
Al bonding
pad
Ultrasonic energy
Pressure
Die
Figure 20.11

Thermosonic Ball Bond
(2)
H2 torch
Ball
(1)
Gold wire
Capillary
tool
(5)
Pressure and heat
form bond.
Lead frame
(6)
Tool moves upward.
Wire breaks at
the bond.
Bonding ball
on pad
Pressure and
ultrasonic energy
Die
(3)
Tool moves
up and more
wire is fed.
Die
(4)
Figure 20.12

Wirebond Pull Test
Post
Device
Chip under test
Hook
Specimen clamp
Figure 20.13

Traditional Packaging
Plastic Packaging
Ceramic Packaging

TO-Style Metal Package
Figure 20.14

Tie Bar Removal from Leadframe
Die
Leadframe
Tie bar
Tie bar
removal lines
Figure 20.15

Plastic Dual In-Line Package (DIP) for
Pin-In-Hole (PIH)
Figure 20.16A

Single In-Line Package (SIP)
Figure 20.16B

Thin Small Outline Package (TSOP) with
Gull wing Surface Mount Leads
Figure 20.16C

Single In-Line Memory Module (SIMM)
Figure 20.16D

Quad Flatpack (QFP) with Gull Wing
Surface Mount Leads
Figure 20.16E

Plastic Leaded Chip Carrier (PLCC) with
J-Leads for Surface Mount
Figure 20.16F

Leadless Chip Carrier (LCC)
Figure 20.16G

Laminated Refractory Ceramic Process
Sequence
Ceramic interconnect layers
4-layer laminate
Figure 20.17

Ceramic with Pin Grid Array
Courtesy of Advanced Micro Devices

Photo 20.2

CERDIP Package
Ceramic lid
Glass seal
Ceramic base
Metal lead
Chip on
epoxy and
leadframe
Cross-section
Indexing
notch
Plane of cross-section
Figure 20.18

Test Socket for IC Package
Figure 20.19

Advanced Packaging
Flip chip
Ball grid array (BGA)
Chip on board (COB)
Tape automated bonding (TAB)
Multichip modules (MCM)
Chip scale packaging (CSP)
Wafer-level packaging

Flip Chip Package
Solder bump
on bonding pad
Silicon chip
Substrate
Connecting pin
Metal interconnection
Via
Figure 20.20

C4 Solder Bump on Wafer Bonding Pad
Reflow
Process
Metal
Deposition
and Etch
2-layer metal deposition

Sn

Pb
(3)
Solder bumps form
during reflow
(4)
Oxide
Nitride
Al
Bonding pad
(1)
3-layer metal stack
Cu-Sn
Cr+Cu
Cr
(2)
Figure 20.21

Epoxy Underfill for Flip chip
Solder bump

Chip

Epoxy

Substrate
Figure 20.22

Flip Chip Area Array Solder Bumps
Versus Wirebond
Bonding pad
perimeter array
Flip chip bump
area array
Figure 20.23

Chip with Ball Grid Array

Photo 20.3

Ball Grid Array
Molded cover

Wire

Substrate

Metal via

Solder ball
Chip
Bonding pad
Epoxy
Thermal via
Figure 20.24

Chip on Board (COB)
IC chip Printed circuit board
Figure 20.25

Tape Automated Bonding (TAB)
Poyimide tape
Copper leads
Figure 20.26

Multichip Module (MCM)
MCM substrate Individual die
Figure 20.27

Trends for Advanced Packaging
1996 2001 1997 1998 1999 2000
0
1800
600
900
1200
1500
300
Direct Chip Attach
Flip Chip on Board
Tape Auto. Bonding
Other
U
n
i
t
s

(
m
i
l
l
i
o
n
s
)

Years
Redrawn from S. Winkler, Advanced IC Packaging Markets and Trends,
Solid State Technology, (June 1998): p. 63.
Figure 20.28

Diversity of Chip Scale Packages
18

General CSP Approach CSP Package Name Company
Area array, bumped CSP Amkor/Anam
Small outline no-lead/C-lead (SON/SOC) Fujitsu
Bump chip carrier (BCC) Fujitsu
Micro-stud-array (MSA) Hitachi
Bottom leaded plastic (BLP) LG Semicon
Quad flat no-lead (QFN) Matsushita
Memory CSP TI Japan
Custom Leadframe
Quad outline non-leaded Toshiba
Enhanced flex CSP 3M
FleXBGA Amkor/Anam
FBGA Fujitsu
Chip-on-flex CSP GE
Multi chip scale package (MCSP) Hightec MC AG
CSP for memory devices Hitachi
IZM flexPAC Fraunhofer Institute
Molded Ball Grid Array Mitsubishi Electric
Chip-on-flex Chip Size Package Motorola Singapore
Fine-pitch BGA (FPBGA) NEC
Interposer (flexible material
with interconnects) between
die and substrate
MicroBGA Tessera
Chip Array Package (CABGA) Amkor/Anam
CSP Cypress Semiconductor
Ceramic mini-BGA IBM
Molded array process CSP Motorola
Plastic chip carrier National
CSP Oki Electric
Transformed grid array package Sony
Rigid Substrate
Ceramic/plastic fine-pitch BGA Toshiba
Table 20.2

Wafer-Level Packaging
Single chip with C4 bumps
Figure 20.29

C4 Bumped Wafer
Photograph provided courtesy of Advanced Micro Devices

Photo 20.4

Design Concept for Wafer-Level
Packaging
Redrawn from V. Di Caprio, M. Liebhard, and L. Smith, The Evolution of a New
Wafer-level Chip Size Package, Chip Scale Review, (May/June 1999).
Chip
Adhesive
Bonded wire
Solder bump
Figure 20.30

Comparison of Standard Test Flow with
Wafer-Level Package Test Flow

WLP fabrication
In-situ WLBI
Wafer-level
functional test
Dicing
Wafer-level pick at
board assembly
WLP Test Flow
Load into tape
and reel
Wafer probe
Dice wafer
Package
individual ICs
Socket/burn-in
at package level
Functional test at
package level
Standard Test Flow
Figure 20.31

Wafer-Level Packaging Features and Benefits
Parameter Benefits
Package size
The package is equal to the chip size in x and y dimensions. It is the
smallest possible IC package and minimizes the package weight.
Mounted package height
It is extremely thin with a total height < 1.0 mm as measured from the
circuit board surface after 2
nd
level assembly.
Component reliability
Test results indicate that wafer-level packaging components pass
existing reliability tests for passivated components.
Solder joint reliability
Test results indicated solder joint reliability meets standard thermal
cycle (-65 to 125C) reliability tests.
Electrical performance
Electrical simulation tests indicates that the die face-down (flip chip)
configuration of wafer-level packaging with its short circuit traces
results in very good electrical performance for minimizing inductance
and parasitic capacitance losses.
Integration with existing
SMT infrastructure
The wafer-level package is compatible with existing surface mount
technology and uses standard solder balls and ball pitches.
Alpha-particle protection
Radioactive elements occurring naturally in packaging materials emit
alpha-particles that can cause voltage loss in memory cells. The use of
polyimide tape and film adhesive provides alpha-particle protection for
memory chips.
Low system cost
The use of existing materials with wafer integration to reduce handling
and a wafer test strategy to minimize duplicate testing provides for a
low overall system cost.
Table 20.3

Chapter 20 Review
Quality Measures 596
Troubleshooting 597
Summary 597
Key Terms 598
Review Questions 598
Equipment Suppliers Web Sites 599
References 600

SMT-20 Asmbly PKG CD

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

SMT-20 Asmbly PKG CD

Uploaded by

Copyright:

Available Formats

2001 by Prentice Hall Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda

You might also like