VLSI

CHAROTAR INSTITUTE OF TECHNOLOGY
V.T.PATEL DEPARTMENT OF E & C

EC-602
VLSI TECHNOLOGY & DESIGN

V.T.PATEL DEPARTMENT OF E & C

CHAROTAR INSTITUTE OF TECHNOLOGY, CHANGA
EC602: VLSI TECHNOLOGY & DESIGN V.T.PATEL DEPARTMENT OF E & C
Classified e-Material Copyrights Charotar Institute of Technology, Changa 2
Syllabus:
1.Introduction: Overview of VLSI design mythology, VLSI
design flow, Design hierarchy, Concept of regularity,
Modularity ,and Locality, VLSI design style, Design quality,
package technology, ,computer aided design technology.

2. Fabrication of MOSFET: Introduction, Fabrication
Process flow: Basic steps, C-MOS n-Well Process, Layout
Design rules, full custom mask layout design.

3. MOS Transistor: The Metal Oxide Semiconductor (MOS)
structure, The MOS System under external bias, Structure
&Operation of MOS transistor, MOSFET Current-Voltage
characteristics, MOSFET scaling & small-geometry effects,
MOSFET capacitances

4. MOS inverters: Static characteristics: Introduction,
Resistive load Inverter, Inverter with n-type MOSFET load
(Enhancement & Depletion type MOSFET load), CMOS Inverter

5. MOS inverters Switching characteristics and
Interconnect Effects: Introduction, Delay-time definitions,
Calculation of Delay times, Inverter design with delay
constraints, Estimation of Interconnect Parasitics, Calculation
of interconnect delay, Switching Power Dissipation of CMOS
Inverters

6. Combinational MOS Logic circuits: Introduction,
MOS logic circuits with Depletion nMOS Loads, CMOS logic
circuits, Complex logic circuits, CMOS, Transmission Gates
(TGs)

7. Sequential MOS Logic circuits :Introduction,
Behaviour of Bistable elements, The SR latch circuit, Clocked
latch & Flip-flop circuit, CMOS D-latch & Edge triggered flip-flop

8. Dynamic Logic Circuits :Introduction, Basic Principles
of pass transistor circuits, Voltage Bootstrapping, Synchronous
Dynamic Circuit Techniques, CMOS Dynamic Circuit
Techniques, High-performance Dynamic CMOS circuits
9. Chip I/P and O/P circuits :On chip Clock Generation
and Distribution, Latch Up and its Prevention

10. Design for testability :Introduction, Fault types and
models, Controllability and observability, Ad Hoc Testable
design techniques, Scan based techniques, built-in Self Test
(BIST) techniques, current monitoring IDDQ test

Text Book :
CMOS Digital Integrated circuits Analysis and Design by Sung
Mo kang, Yusuf Leblebici, TATA McGraw-Hill Pub. Company
Ltd. Third Edition.

Reference Books:
Basic VLSI Design By Pucknell & Eshraghian, PHI, 3rd ed.
Introduction to VLSI Systems by Mead C & Conway, Addison
Wesley
Digital Integrated Circuits: A Design Perspective By Jan M.
Rabaey, PHI

Book for Laboratory :
VHDL primer by J.Bhaskar , Addision Wesley , Pearson Ed.
Introduction:
VLSI : Very Large Scale Integration

Although new terms like ULSI, GSI have been coined
lately, the term VLSI has continued to be un-displaced

Typical VLSI Systems
VLSI Trends: Moores Law
In 1965 Gordon Moore noted that Number of
Transistors on a chip doubled every 18 to 24 months.

Gordon Moore
Intel Co-Founder
Image source: Intel Corporation www.intel.com
Microprocessor Trends (Intel)
Source: http://www.intel.com/pressroom/kits/quickreffam.htm
Microprocessor Trends (Intel) Contd
Source: http://www.intel.com/pressroom/kits/quickreffam.htm

Microprocessor Trends (Log Scale) contd

0.001
0.01
0.1
1
10
100
1970 1975 1980 1985 1990 1995 2000 2005
T
r
a
n
s
i
s
t
o
r
s

(
M
i
l
l
i
o
n
s
)
Intel
Motorola
DEC/Compaq
Alpha (R.I.P)
P4N
G4
P4
Sources: http://www.intel.com/pressroom/kits/quickreffam.htm, www.geek.com
Design Abstraction levels:

IC Classification:
Design Style (Standard cell, Gate array, Full custom,
FPGA)

Circuit Technology (BJT, CMOS, NMOS, BiCMOS)

Design Type (Digital, Analog, Mixed-Signal)

Circuit Size (SSI,MSI,LSI,VLSI,ULSI,GSI)

Classification of Circuit Size:
The VLSI design process
May be part of larger product design.

Major levels of abstraction:
Specification: function, cost, etc.
Architecture: large blocks
logic design: gates + registers
circuit design: transistor sizes for speed, power.
Layout: determines parasitics.

VLSI Design Cycle:

System Specification
Architectural Design
Logic Design
Circuit Design
Physical Design
Functional Design Fabrication
Packaging
VLSI Design Cycle
System Specification Specification of the size,
speed, power and functionality of the VLSI system.
Architectural Design Decisions on the architecture,
e.g., RISC/CISC, # of ALUs, pipeline structure, cache
size, etc. Such decisions can provide an accurate
estimation of the system performance, die size, power
consumption, etc.
Functional Design Identify main functional units and
their interconnections. No details of implementation.

Logic Design Design the logic, e.g., Boolean
expressions, control flow, word width, register
allocation, etc. The outcome is called an RTL (Register
Transfer Level) description. RTL is expressed in a HDL
(Hardware Description Language), e.g., VHDL and
Verilog.

X = (AB+CD)(E+F)
Y= (A(B+C) + Z + D)

Circuit Design Design the circuit including gates,
transistors, interconnections, etc. The outcome is
called a netlist.

Physical Design Convert the netlist into a geometric
representation. The outcome is called a layout.

Fabrication Process includes lithography, polishing,
deposition, diffusion, etc., to produce a chip.
Packaging Put together the chips on a PCB (Printed
Circuit Board) or an MCM (Multi-Chip Module)

System Specification
Architectural
Specification
RTL in HDL
Netlist
Layout
Timing & relationship
between functional units
Chips
Packaged and
tested chips
Architectural
Design
Functional
Design
Logic
Design
Physical
Design
Fabrication
Packaging
Circuit Design
or
Logic Synthesis
VLSI DESIGN FLOW - 3 DOMAIN REPRESENTATIONS
IMPACT OF DIFFERENT VLSI DESIGN STYLES ON DESIGN
CYCLE TIME AND ACHIEVABLE CHIP PERFORMANCE

Chip Performance Vs. Time:
Structured Design Strategies:
Strategies common for complex hardware and
software projects.
Hierarchy: Subdivide the design into many levels of
sub-modules
Modularity: The various functional blocks which make
up the larger system must have well-defines functions
and interfaces.
Regularity: Subdivide to max number of similar sub-
modules at each level
Locality: Connections are mostly between neighboring
modules, avoiding long distance connections as much
as possible.

VLSI Technology: Advantages
LESS AREA, MORE COMPACTNESS AT ALL SYSTEM
LEVELS
LESS POWER CONSUMPTION
FEWER CHIPS/COMPONENTS PER BOARD AND
SYSTEM
HIGHER RELIABILITY, DUE TO IMPROVED ON-CHIP
INTERCONNECTS
HIGHER SPEED DUE TO REDUCED INTERCONNECT
LENGTH
SIGNIFICANT COST REDUCTIONS

Fabrication of MOSFETs
Introduction:
IC fabrication is generally carried out in Clean room
environment. Here the first questions arise what is
clean room?
A room in which the concentration of Air borne particles
are controlled to specified limits.

Why clean room facility is required?
The extremely small size of components are used in
ICs, greatly increases the requirements for cleanliness
in all aspects of fabrication Small dust particles in the
environment create defects in the IC wafers and make
the circuits unfunctional therefore clean room
environment is necessary.
A View of the Cleanroom
How to regulate the dust particles?

In clean rooms generally two types of filters are used
With centrally air-conditioner system
1) HEPA (High Efficiency Particulate Air Filters)
2) ULPA (Ultra Low Penetration Air filter)

Both filters are used for the dual purpose for
removing the dust particles and regulate the airflow.
MOSFET Structure
PMOS Transistor
NMOS Transistor
NMOS Fabrication Steps :
Wafer Cleaning
Oxidation
Photolithography-
(a) optical (b) e-beam (c) ion beam
Diffusion
(a) Using Furnace (b) Ion implantation
Etching - (a) Wet (b) Dry
Metallization - (a) PVD (b) CVD
Testing
Device Separation
Oxidation:
When cleaned silicon wafer is placed in a furnace at
high temperature and oxygen is flowing through it the
silicon dioxide is formed on the surface of the silicon
wafer.

Why it is required?
Surface Passivation

Diffusion Barrier

Field Oxide

MOS Gate Oxide
Oxidation contd.
Types of Oxidation:

Oxide
Photolithography
Photolithography is a technique and part of the processing
steps where predetermined patterns are reproduced on a
given substrate (wafers).
Next, the wafer is then coated with a polymer which is
sensitive to ultraviolet light called a photoresist.
There are two basic types of Photoresists Positive and
Negative.

With Positive Photo resist (PR)

The exposed areas becomes soluble.
Now the SiO2 not covered by photoresist can be etched
away by using a chemical solvent HF acid.

Deposition of Thin Gate Oxide
Poly Deposition
Etching of Poly
Etching of Gate Oxide

This process opens windows for Source and Drain Diffusions
Diffusion of N+ Impurities by Implantation


Metal Deposition for Contacts
NMOS Transistor
Device Isolation Techniques
MOS transistors must be electrically isolated from
each other in order to:
prevent unwanted conduction paths between devices
avoid creation of inversion layers outside the channel
regions
reduce the leakage currents

Each device is created in dedicated regions - active
areas
Each active area is surrounded by a field oxide barrier
using few techniques:
Etched field-oxide isolation

1) grow a field oxide over the entire surface of the chip
2) pattern the oxide and define active areas

Drawbacks:
-large oxide steps at the boundaries between active areas
and field regions!
-cracking of polysilicon/metal
subsequent deposited layers!

To prevent this, most manufacturers prefer isolation
techniques that partially recess the field oxide into the silicon
surface.
Local Oxidation of Silicon (LOCOS)
More planar surface topology
Selectively growing the field oxide in certain regions -
process flow:
1) grow a thin pad oxide (SiO
2
) on the silicon surface
2) define active area : deposition and patterning a
silicon nitride (Si
3
N
4
) layer

The thin pad oxide - protect the silicon surface from
stress caused by nitride

3) channel stop implant: p-type regions that surround the
transistors
To prevent the formation of nay unwanted channels between two
neighboring N
+
diffusion regions.

4) Grow a thick field oxide

Field oxide is partially recessed into the surface (oxidation
consume some of the silicon)
Field oxides forms a lateral extension under the nitride layer
birds beak region
Birds beak region limits device scaling and device density
in VLSI circuits!

5) Etch the nitride layer and the thin oxide pad layer
CMOS Fabrication Process:
CMOS fabrication technology
requires that both n-channel
(nMOS) and p-channel (pMOS)
transistors be built on the same
chip substrate.
To accommodate both nMOS
and pMOS devices, special
regions must be created in
which the semiconductor type is
opposite to the substrate type.
These regions are called wells of
tubs.
A p-well is created in an n-type
substrate or, alternatively , an
n-well is created in a p-type
substrate.
V
DD
A Y
GND
CMOS Inverter
n-Well CMOS Fabrication process :
The n-well CMOS process starts with
a moderately doped (impurity
concentration ~10
16
/cm
3
) p-type
silicon substrate.

Then, an initial thick field oxide
layer (5000A) is grown on the
entire surface. The first lithographic
mask defines the n-well region.

Donor atoms, usually phosphorus,
are implanted through this window
in the oxide. Once the n-well is
created, the active areas of the
nMOS and pMOS transistors can be
defined.

Following the creation of the n-well
region, a thick field oxide is grown
around the transistor active regions,
and a thin gate oxide (25A) is
grown on top of the active regions.
The polysilicon layer
(3000A) is deposited
using chemical vapor
deposition (CVD) and
patterned by dry
plasma etching.
The created polysilicon
lines will function as the
gate electrodes of the
nMOS and the pMOS
transistors and their
interconnects.
Also, the polysilicon
gates act as self-aligned
masks for the source
and drain implantations
that follow this step

Using a set of two
masks, the n+ and
p+ Source and
Drain regions are
implanted into the
substrate and into the
n- well, respectively.

The ohmic contacts to
the substrate and to
the n-well are
implanted in this
process step.

An insulating silicon dioxide layer
is deposited over the entire wafer
using CVD (5000A). This is for
passivation, the protection of all
the active components from
contamination.
The contacts are defined and
etched away to expose the silicon
or polysilicon contact windows.
These contact windows are
necessary to complete the circuit
interconnections using the metal
layer, which is patterned in the
next step.
(CVD = Chemical Vapor
Deposition, where reactive gases
collide above the wafer, and
chemical reaction products then
fall onto the wafer creating a new
layer.)

Metal (aluminum,
>5000A) is deposited over
the entire chip surface
using metal evaporation,
and the metal lines are
patterned through etching.

Since the wafer surface is
non-planar, the quality and
the integrity of the metal
lines created in this step
are very critical and are
ultimately essential for
circuit reliability.

The composite layout and
the resulting cross-sectional
view of the chip, showing
one nMOS and one pMOS
transistor (built-in n-well),
the polysilicon and metal
interconnections.

The final step is to deposit a
full SiO
2
passivation layer
(5000A), for protection,
over the chip, except for
wire-bonding pad areas.

If the wafer will be stored
for some months, a final
thin blanket layer of Si
3
N
4

may be applied to prevent
penetration by water vapor.
Inverter Layout:

a
out
+
transistors
GND
VDD
a out
tub ties
Design Rule:
DESIGN RULE SPECS:
a. 'micron' rules - minimum feature sizes and spacings in
mm units (normal spec in industry)
b. 'lambda ()' rules - minimum feature sizes and
spacing spaced in terms of a single parameter
Intra-Layer Design Rules ()
Inter-Layer Design Rules - Transistor Layout ()
Inter-Layer Design Rules - Contact and Via ()
Typical design flow for the production of an IC mask set:
CMOS CHIP DESIGN OPTIONS:
-> Programmable Logic - P, DSP
-> Programmable Logic Structures - FPGA
-> Programmable Interconnect - FPGA
-> Mask Programmable Gate Arrays
-> Standard Cell Design
-> Mixed Standard Cell & Custom Design
-> Full Custom Mask Design
FIELD PROGRAMMABLE GATE ARRAY (FPGA):

Configurable Logic Block:
Standard cell based design:
Predominant full-custom design style.
Standardization is achieved at the logic or function
level.
Specific designs for each gate can developed and
stored in a software database or cell library.
Behavioral, Structural, and Physical Domain
descriptions per cell
Layout is usually automatically placed and routed
using CAD software.

Typical Standard Cell Library contents:
-> SSI logic: e.g. nand, nor, xor, inverters, buffers,
latches, registers
+ Each gate can have multiple implementations to
provide proper drive for different fan-outs, e.g.
standard size, 2x, 4x
-> MSI logic: e.g. decoders, encoders, adders,
comparators
-> Datapath: e.g. ALUs, adders, register files, shifters
-> Memories: e.g. RAM, ROM
-> System level blocks: e.g. multipliers,
microcontrollers
MOS Inverters :
Static Characteristics

Ideal Inverter Voltage Transfer Characteristic (VTC)
Inverter Symbol
Truth table
VTC of Ideal Inverter
Actual Inverter VTC

Generalized circuit structure of an
nMOS inverter
V
in
= V
GS
V
out
= V
DS
V
SB
= 0
Applying KCL to this simple
circuit,

I
D
(V
in
,V
out
)=I
L
(V
L
)
Actual Inverter VTC (cont)
Actual inverter VTC
V
OH
and V
OL
represent the high and low output
voltages of the inverter.
Ideally,
V
OH
= Vcc
V
OL
= 0
Noise Margin
V
OH
-> max output voltage when output is 1
V
OL
-> min output voltage when output is 0
V
IL
-> max input voltage which can be interpreted as 0
V
IH
-> min input voltage which can be interpreted as 1

Noise Margin (Cont)
NM
H
= V
OH
- V
IH
NM
L
= V
IL
- V
OL
Figure shows graphical illustration of the noise margins.
Noise Margins are shown as the amount of variation in the
signal levels that can be allowed while the signal is
transmitted from the output of one gate to the input of the
next gate.
For any inverter circuit, the five critical voltage
points V
OL
, V
OH
, V
IL
, V
IH
, V
th
determine

--> DC Output Voltage Behavior
--> Noise Margins
--> Width and Location of Transition Region

Actual inverter VTC
Power Dissipation & Die Area
P
DC
= V
DD
I
DC

ASSUME: Vin = 1 50% of Op Time,
0 50% of Op Time
P
DC
= V
DD
/2 [I
DC
(V
in
="0")+ I
DC
(V
in
="1")]

DIE AREA --> W x L

Resistive-Load Inverter

Current-Voltage equation of the nMOS:

CUTOFF: V
in
= V
GS
< V
T0,n
, I
D
= 0

LINEAR: V
in
= V
GS
> V
T0,n
,
V
out
= V
DS
< V
GS
- V
T0,n
I
D
= k
n
/2 [2(V
GS
- V
T
)V
DS
- V
DS
2
]

SATURATION:V
in
= V
GS
> V
T0,n

V
out
= V
DS
> V
GS
- V
T0,n
I
D
= k
n
/2 (V
GS
- V
T
)
2

Where: k
n
=
n
C
ox
W/L


Requires only NMOS transistor and resistor
Source & Substrate terminals of the driver transistor are
connected to the ground. V
SB
= 0

V
T
= V
T0

When V
in
= 0:
NMOS is OFF (V
GS
= 0)
No current through NMOS or
resistor
V
out
~ V
DD
When V
in
= V
DD
:
NMOS is ON (V
GS
= V
DD
)
NMOS on resistance << R
V
out

~ 0

Resistive load inverter circuit
Resistive-Load Inverter (Cont)

Resistive-Load Inverter VTC:
V
OH
=V
DD
=5V
=1V
Typical VTC of Resistive load inverter circuit
CALCULATION OF V
OH

V
in
= 0: NMOS transistor off, no
current flows in circuit
No voltage drop across R

V
out
= V
DD
- R
L
I
L

V
in
< V
T0,n
=> nMOS Cut-off

I
D
= I
L
= 0 => V
OH
= V
DD
Calculation of V
OL
V
in
= V
DD
: NMOS transistor on (linear mode)

| |
| |
] ) [(
) (
) (
) (
) (
2
2
1
2
2
1
2
2
1
OL OL T DD L
W
ox n
L
OL DD
L D
L
OL DD
L
OL OL T DD L
W
ox n D
OL DS
DD IN GS
DS DS T GS L
W
ox n D
V V V V C
R
V V
I I
R
V V
I
V V V V C I
V V
V V V
V V V V C I
=
=
=
=
= =
=

0
2
]
1
[ 2
, 0
2
= + +
DD
L n
OL
L n
n T DD OL
V
R k
V
R k
V V V
By solving this quadratic equation,
L n
DD
L n
T DD
L n
T DD OL
R k
V
R k
V V
R k
V V V
2 1 1
2
0 0

|
|
.
|
\
|
+ + =
Where
L
W
C k
ox n n
=
Calculation of V
OL
(Cont)
Calculation of V
OL
(Cont)
Note that the value of V
OL
depends on the size of the
NMOS device and on R
Increase W to reduce V
OL

Increase R to reduce V
OL

Logic with this property is called ratioed logic
Requires careful sizing for correct logic levels

Ratioless logic: output levels do not depend on
transistor sizes

Calculation of V
IL
:
V
IL
= low unity gain point of VTC
When V
in
= V
IL
, NMOS in saturation:

I
L
= I
D

Differentiate wrt to V
in
, i.e.

( )
2
2
1
T in n
L
out DD
V V k
R
V V
=
) (
1
, 0 n T IL n
in
out
L
V V k
dV
dV
R
=
@ V
in
= V
IL ,
1 =
in
out
dV
dV
Calculation of V
IL
(Cont)
) ( ) 1 (
1
, 0 n T IL n
L
V V k
R
=
Solving above equation for V
IL,
L n
n T IL
R k
V V
1
, 0
+ =
Calculation of V
IH
:
V
IH
= high unity gain point of VTC
When V
in
= V
IH
, NMOS in linear region:

( ) | |
( )
2
2
1
, 0
2
2
1
, 0
out L n out n T in L n out DD
out out n T in n
L
out DD
V R k V V V R k V V
V V V V k
R
V V
=
=
Take derivative of V
out
with respect to V
in
, set to -1
( )
( )
out L n out L n n T IH L n
in
out
out L n out L n
in
out
n T IH L n
in
out
V R k V R k V V R k
dV
dV
V R k V R k
dV
dV
V V R k
dV
dV
+ + =
+ =
, 0
, 0
1
(1)
(2)
Calculation of V
IH
(Cont)

By Solving equation (1) & (2) simultaneously,

L n L n
DD
T IH
R k R k
V
V V
1
3
8
+ =
Calculation of V
th
:
Point on VTC where V
in
= V
out
:

( )
( )
2
, 0 2
1
2
, 0 2
1
) (
) (
n T TH L
W
ox n
L
TH DD
TH out in
n T in L
W
ox n D
L
out DD
L
L D
V V C k
R
V V
V V V
V V C k I
R
V V
I
I I
=
= =
=
=
=
Power Dissipation-Resistive load inverter:
| | ) " 1 " ( ) " 0 " (
2
= + = =
in DC in DC
DD
DC
V I V I
V
P
When V
in
= V
OL
: DRIVER nMOS in CUT-OFF
I
L
=I
D
=0 -> P(V
in
=0) = 0
When V
in
= V
OH
L
OL DD
D L in DC
R
V V
I I V I

= = = = ) " 1 " (
L
OL DD DD
DC
R
V V V
P

=
2

Inverters with n-type MOSFET load:
MOSFET load
Enhancement type
Depletion type
Saturated Linear
Saturated Enhancement-load inverter


Linear Enhancement-load inverter


Depletion Load Inverter:


Depletion-load inverter: uses
depletion NMOS transistor as load
Depletion transistor has V
T
< 0
Load is always on:
V
GS
= 0 > V
T

Body effect of depletion
transistor is significant
V
SB
= V
out
Calculation of V
OH
:
Calculation of V
OL
:
( ) ( )
OL load T
driver
load
T OH T OH OL
V V
k
k
V V V V V
,
2
0 0
=
Calculation of V
IL
:

IL
:

( ) ( )
out load T DD out
driver
load
T IL
V V V V
k
k
V V
, 0
+ + =
Calculation of V
IH
:
( ) ( )
out
load T
out load T
driver
load
out T IH
dV
dV
V V
k
k
V V V
,
, 0
2
|
|
.
|
\
|
+ + =

IH
:

Typical VTCS for depletion load inverters with different k
R
values
Depletion load Inverter (Cont)
POWER DISSIPATION CONSIDERATIONS
35 . 3 6
56 . 0 167 . 0 ) 36 . 2 5 )(
6
1
( 1 ) (
=
+ = + + =
IL out
out out out IL
V V
V V V V
35 . 3 6
56 . 0 167 . 0 ) 36 . 2 5 )(
6
1
( 1 ) (
=
+ = + + =
IL out
out out out IL
V V
V V V V
CMOS Inverter:
Complementary NMOS and
PMOS devices
In steady-state, only one
device is on (no static power
consumption)
Vin=1: NMOS on, PMOS off
Vout = V
OL
= 0
Vin=0: PMOS on, NMOS off
Vout = V
OH
= Vcc
Ideal V
OL
and V
OH
!
Ratioless logic
Latch Up in CMOS circuits:
Current-Voltage equation of
the nMOS:

CUTOFF: V
GS
< V
T0,n
, I
D
= 0

LINEAR: V
GS
> V
T0,n
,
V
DS
< V
GS
- V
T0,n

I
D
=k
n
/2 [2(V
GS
- V
T0,n
)V
DS
- V
DS
2
]

SATURATION:
V
GS
> V
T0,n

V
DS
> V
GS
- V
T0,n
I
D
= k
n
/2 (V
GS
- V
T0, n
)
2

Where: k
n
=
n
C
ox
W/L

Current-Voltage equation of
the pMOS:

CUTOFF: V
GS
> V
T0,
p , I
D
= 0

LINEAR: V
GS
< V
T0,p,
V
DS
> V
GS
- V
T0,
p
I
D
= k
p
/2 [2(V
GS
- V
T0,p
)V
DS
- V
DS
2
]

SATURATION:
V
GS
< V
T0,
p
V
DS
< V
GS
- V
T0,
p
I
D
= kp/2 (V
GS
- V
T0,P)
2

Where: kp = p C
OX
W/L

CMOS inverter VTC
V
OH
and V
OL
Calculation:
V
IL
Calculation:

V
IH
Calculation:


V
th
Calculation:

POWER DISSIPATION CONSIDERATIONS:

Chapter -7

COMBINATIONAL MOS LOGIC
CIRCUITS



V
OH
CALCULATION:
Calculation Of V
OL
GENERALIZED NOR STRUCTURE

2-INPUT NAND GATE





GENEARALIZED NAND GATE
CMOS LOGIC GATES





CMOS NAND Gate:
COMPLEX LOGIC GATES:
OR OPS PERFORMED BY PARALLEL CONECTED DRIVERS.
AND OPS PERFORMED BY SERIES CONNECTED DRIVERS.
INVERSION IS PROVIDED BY NATURE OF MOS CIRCUIT OP.



Full CMOS XOR Gate:
AOI and OAI Gates:

The large area requirements of
Complex CMOS gates present a
Problem in high density designs,
Since two complementary
transistors, one nMOS and one
pMOS, are needed for every input.
One possible approach to reduce
the no. of transistors is to use a
single pMOS transistor with its gate
terminal connected to ground, as
the load device.
With this simple pull-up
arrangement, the complex gate can
be implemented with much fewer
transistors.
The similarities of pseudo-nMOS
gates to depletion-load nMOS logic
gates are obvious.
Disadvantage of it is the nonzero
static power dissipation.
CMOS Transmission Gate (TG):

Equivalent Resistance:
Text Book :
1. Book: CMOS Digital Integrated circuits Analysis
and Design by Sung Mo kang, Yusuf Leblebici,
TATA McGraw-Hill Pub. Company Ltd. Third Edition.

Reference Books:
(1) Basic VLSI Design By Pucknell & Eshraghian,
PHI,3rd ed.
(2) Introduction to VLSI Systems by Mead C & Conway,
Addison Wesley
(3) Digital Integrated Circuits: A Design Perspective By
Jan M. Rabaey, PHI


Chapter-9
DYNAMIC LOGIC CIRCUITS
STATIC LOGIC GATES: valid logic levels are steady-state op
points. Outputs are generated in response to input voltage
levels after a certain time delay. Output levels are preserved
as long as there is power, i.e. no refresh is needed.
DYNAMIC LOGIC GATES: depends on temporary storage of
charge in parasitic node capacitances. Requires periodic
updating of internal node voltage levels.
ADVANTAGES:
1. Allows implementation of simple sequential circuits with
memory functions.
2. Use of common clock signals throughout the system enables
the synchronization of various circuit blocks.
3. Implementation of complex functions genearlly use less die
area than static circuits.
4. Often dissipates less dynamic power than static designs, due
to smaller parasitic capacitances.

BASIC PRNCIPLES OF PASS TRANSISTOR CIRCUITS
THANK YOU

VLSI

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CHAROTAR INSTITUTE OF TECHNOLOGY

V.T.PATEL DEPARTMENT OF E & C

Resistive load inverter circuit

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