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1.- ESCRIBIR EN VHDL EL CDIGO DE LOS SIGUIENTES CIRCUITOS: a) CIRCUITO INTEGRADO 74595 library ieee; use ieee.std_logic_1164.

all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ci74595 is port ( srclrn,srclk,ser: in std_logic; gn, rclk : in std_logic; q : out std_logic_vector(7 downto 0) ); qhn : out std_logic ) ; end ci74595; architecture comportamiento of ci74595 is signal x,y: std_logic_vector(7 downto 0); begin process (srclk,srclrn) begin if srclrn='0' then x <= (others => '0'); elsif srclk='1' and srclk'event then x(0)<=ser; for i in 1 to 7 loop x(i)<=x(i-1); end loop; end if; end process; process(rclk) begin if rclk='1' and rclk'event then for j in 0 to 7 loop y(j) <= x(j); end loop; end if; end process; q <= "ZZZZZZZZ" when gn='1' else y; qhn <= x(7); end comportamiento;

Simulacin:

Comprobando as que el circuito funciona de manera adecuada, cabe recalcar que internamente las seales se van desplazando y con cada flanco de subida del rclk estas se visualizan en la salida, si en caso gn est en 0, si no es as la salida ser alta impedancia.

b) CIRCUITO INTEGRADO 74468

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ci74468 is port( gn_A, gn_B : in std_logic; A , B : in std_logic_vector(3 downto 0); yA , yB : out std_logic_vector(3 downto 0) ); end ci74468; architecture comportamiento of ci74468 is begin process(A,gn_A) begin if gn_A='0' then for i in 3 downto 0 loop yA(i) <= not A(i); end loop; else yA <= "ZZZZ"; end if;

end process; process(B,gn_B) begin if gn_B='0' then for i in 3 downto 0 loop yB(i) <= not B(i); end loop; else yB <= "ZZZZ"; end if; end process; end comportamiento;

Simulando:

c) CIRCUITO INTEGRADO 74395 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ci74395 is port ( oen : in std_logic; load_shift : in std_logic; ser,clrn, clk: in std_logic; d : in std_logic_vector(3 downto 0); q : out std_logic_vector(3 downto 0); qb : out std_logic ); end ci74395;

architecture solucion of ci74395 is signal x,y : std_logic_vector(3 downto 0); begin process(clk,clrn) begin if clrn = '0' then y <= "0000"; elsif clk='0' and clk'event then for i in 0 to 3 loop y(i) <= x(i); end loop; end if; end process; process(load_shift,ser,d) begin x(0)<= ( load_shift and d(0) ) or ( ser and (not load_shift)); for i in 1 to 3 loop x(i) <= (load_shift and d(i)) or (y(i-1) and (not load_shift)); end loop; end process; with oen select q <= y when '0', "ZZZZ" when others; qb <= y(3); end solucion; Simulacin:

d) CIRCUITO INTEGRADO 74845

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ci74845 is port( oen : in std_logic_vector(2 downto 0); d : in std_logic_vector(7 downto 0); clrn,pren,ena : in std_logic; q : out std_logic_vector(7 downto 0) ); end ci74845; architecture comportamiento of ci74845 is component latch_d port( d,ena: in std_logic; q: out std_logic ); end component; signal x,y : std_logic_vector(7 downto 0); signal enab, oent: std_logic; begin enab <= ena or (not pren) or (not clrn); oent <= (not oen(0)) and (not oen(1)) and (not oen(2) ); LT: for i in 7 downto 0 generate x(i)<= (d(i) and clrn ) or (not pren); U0: latch_d port map ( x(i), enab , y(i) ); end generate;

with oent select q <= y when '1', "ZZZZZZZZ" when others; end comportamiento;

Simulacin:

2) Utilizando la biblioteca lpm component, disee un circuito de control que permita escribir un dato en la memoria tipo FIFO.

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library lpm; use lpm.lpm_components.all; entity control is port ( dato_in : in std_logic_vector(7 downto 0); dato_out : out std_logic_vector(7 downto 0); inicio,reset : in std_logic; selRW : in std_logic ); end control; architecture sol of control is signal RD,WR : std_logic; signal direcw,direcr : std_logic_vector(4 downto 0); begin U0: lpm_ram_dp generic map( lpm_width => 8, lpm_widthad=> 5,

lpm_file => "unregistered") port map ( DATA => dato_in, Q => dato_out, RDADDRESS => direcr, WRADDRESS => direcw, RDEN => RD, WREN => WR, RDCLOCK => inicio, WRCLOCK => inicio );

process(reset, inicio) begin if reset = '1' then direcr <= (others => '0'); direcw <= (others => '0'); elsif inicio ='1' and inicio'event then if selRW='0' then -- Cuando es 0 est escribiendo WR <= '1'; RD <= '0'; direcw <= direcw + 1; elsif selRW = '1' then WR <= '0'; RD <= '1'; direcr <= direcr +1; end if; end if; end process; end sol;

Simulacin:

* Notar que se usa un ciclo de reloj para configurar la operacin, adems que aproximadamente demora 80ns en realizarse cada operacin.

3) Utilizando el Mega- wizard implemente el cdigo VHDL de un multiplicador de 2 nmeros de 8 bits. En vhdl: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY multi8p8 IS PORT ( dataa datab result ); END multi8p8;

: IN STD_LOGIC_VECTOR (7 DOWNTO 0); : IN STD_LOGIC_VECTOR (7 DOWNTO 0); : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)

ARCHITECTURE SYN OF multi8p8 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);

COMPONENT lpm_mult GENERIC ( lpm_widtha

: NATURAL;

lpm_widthb lpm_widthp lpm_widths input_b_is_constant lpm_representation use_eab ); PORT (

: NATURAL; : NATURAL; : NATURAL; : STRING; : STRING; : STRING

dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END COMPONENT; BEGIN result

<= sub_wire0(15 DOWNTO 0);

lpm_mult_component : lpm_mult GENERIC MAP ( LPM_WIDTHA => 8, LPM_WIDTHB => 8, LPM_WIDTHP => 16, LPM_WIDTHS => 16, INPUT_B_IS_CONSTANT => "NO", LPM_REPRESENTATION => "UNSIGNED", USE_EAB => "OFF" ) PORT MAP ( dataa => dataa, datab => datab, result => sub_wire0 ); END SYN;

4) Implemente una mac (multiplicador acumulador)

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mac is port( data : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(15 downto 0) );

end mac; architecture comportamiento of mac is

component multi8p8 PORT ( dataa datab result ); END component;

: IN STD_LOGIC_VECTOR (7 DOWNTO 0); : IN STD_LOGIC_VECTOR (7 DOWNTO 0); : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)

signal A : std_logic_vector(15 downto 0); signal multi: std_logic_vector(15 downto 0); signal b: std_logic_vector(7 downto 0) := "00000001"; begin

U0: multi8p8 port map ( dataa => data , datab => b, result => multi ); A <= A + multi; b <= A(7 downto 0); data_out <= A; end comportamiento;