Rangkaian Elektronika

RANGKAIAN ELEKTRONIKA
(ELECTRONIC CIRCUITS)
oleh: Dr. Ir. Retno Wigajatri Purnamaningsih, MT

Tomy Abuzairi, ST, MT, M.Sc
Reference Books: 1. Robert L. Boylestad and Louis Nashelsky, Electronic Devices and Circuit Theory, Pearson Education, Inc., Uppersaddle River, New Jersey 07458, USA, 2006. 2. Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, Inc., Singapore, 2003.
KULIAH RANGKAIAN ELEKTRONIKA (SEMESTER III S1 INTERNATIONAL 2008) DEPARTEMEN TEKNIK ELEKTRO FTUI
1/89
ELECTRONIC CIRCUIT
CHAPTER 1. CHAPTER 2. CHAPTER 3. CHAPTER 4. CHAPTER 5. CHAPTER 6. CHAPTER 7. CHAPTER 8. CHAPTER 9. CHAPTER 10. CHAPTER 11. Semiconductor Diodes Diode Applications Bipolar Junction Transistors DC Biasing - BJTs BJT AC Analysis Field-Effect Transistors FET Biasing FET Amplifier BJT and JFET Frequency Response Operational Amplifier Op-Amp Applications
2/89
ELECTRONIC CIRCUIT
CHAPTER 1. CHAPTER 2. CHAPTER 3. CHAPTER 4. CHAPTER 5. CHAPTER 6. CHAPTER 7. CHAPTER 8. CHAPTER 9. CHAPTER 10. CHAPTER 11. Semiconductor Diodes Diode Applications Bipolar Junction Transistors DC Biasing - BJTs BJT AC Analysis Field-Effect Transistors FET Biasing FET Amplifier BJT and JFET Frequency Response Operational Amplifier Op-Amp Applications
3/89
ELECTRONIC CIRCUIT
CHAPTER 7. FET Biasing
1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 15)
Introduction Fixed-Bias Configuration Self-Bias Configuration Voltage-Divider Biasing Depletion-Type MOSFETs Enhancement-Type MOSFETs Summary Table Combination Networks Design Troubleshooting p-Channel FETs Universal JFET Bias Curve Practical Applications Summary Computer Analysis
404 405 409 415 420 425 430 430 434 436 437 439 442 453 454
4/89
ELECTRONIC CIRCUIT
CHAPTER 6. FIELD-EFFECT TRANSISTORS SUMMARY TABLE
5/60
ELECTRONIC CIRCUIT
6/60
ELECTRONIC CIRCUIT
7/60
ELECTRONIC CIRCUIT
CHAPTER 6. FIELD-EFFECT TRANSISTORS SUMMARY
8/60
For the FET, the relationship between input and output quantities is NONLINEAR due to the squared term in Shockleys Equation. Linear relationships result in straight lines when plotted on a graph of one variable versus the other, whereas nonlinear functions result in curves as obtained for the transfer characteristics of a JFET.
ELECTRONIC CIRCUIT
CHAPTER 7. FET BIASING 7.1. Introduction
The nonlinear relationship between ID vs VGS can complicate the mathematical approach to the dc analysis of FET configurations. THE INPUT CONTROLLING VARIABLE FOR A BJT TRANSISTOR IS A CURRENT LEVEL, WHEREAS FOR THE FET A VOLTAGE IS THE CONTROLLING VARIABLE. The general relationships that can be applied to the dc analysis of all FET amplifiers are
For JFETs and depletion-type MOSFETs and MESFETs, Shockleys equation is applied to relate the input and output quantities:
9/89
For enhancement-type MOSFETs and MESFETs, the following equations is applicable:
ELECTRONIC CIRCUIT
CHAPTER 7. FET BIASING 7.2. FIXED-BIAS CONFIGURATION
The simplest of biasing arrangements for the n-channel JFET appears in FIG. 7.1. Referred to as the fixedbias configuration, it is one of the few FET configurations that can be solved just as directly using either a mathematical or a graphical approach. The configuration of FIG. 7.1 includes the ac levels Vi and Vo and the coupling capacitors (C1 and C2).
10/89
Recall the coupling capacitors are OPEN CIRCUIT for the dc analysis and low impedances (essentially short circuits) for the ac analysis. The resistor RG is present to ensure that Vi appears at the input to the FET amplifier for the ac amplifier. For the dc analysis,
ELECTRONIC CIRCUIT
The zero-drop across RG permits replacing RG by a shortcircuit equivalent,as appearing in the network of FIG. 7.2, specifically redrawn for the dc analysis.
11/89
The fact that the negative terminal of the battery is connected directly to the defined positive potential of VGS clearly reveals that the polarity of VGS is directly opposite to that of VGG. Applying Kirchhoffs voltage law in the clockwise direction of the indicated loop of FIG. 7.2 results in
ELECTRONIC CIRCUIT
Since VGG is a fixed dc supply, the voltage VGS is fixed in magnitude, resulting in the designation FIXED-BIAS CONFIGURATION. The resulting level of drain current ID is now controlled by Shockleys equation:
Since VGS is a fixed quantity for this configuration, its magnitude and sign can simply be substituted into Shockleys equation and the resulting level of ID calculated.
12/89
(See FIG. 7.3) Recall that choosing VGS = VP/2 will result in a drain current of IDSS/4 when plotting the equation. For the analysis of this chapter, the three points defined by IDSS, VP, and the intersection just described will be sufficient for plotting the curve.
ELECTRONIC CIRCUIT
In FIG. 7.4, the fixed level of VGS has been superimposed as a vertical line at VGS = -VGG. At any point on the vertical line, the level of VGS is VGG the level of ID must simply be determined on this vertical line.
13/89
The point where the two curves intersect is the common solution to the configuration commonly referred to as the quiescent or operating point.
ELECTRONIC CIRCUIT
14/89
It is important to realize that once the network of FIG. 7.1 is constructed and operating, the dc levels of ID and VGS that will be measured by the meters of FIG. 7.5 are the quiescent values defined by FIG. 7.4. The drain-to-source voltage of the output section can be determined by applying Kirchhofs voltage law as follows:
ELECTRONIC CIRCUIT
15/89
ELECTRONIC CIRCUIT
16/89
17/89
The self-bias configuration eliminates the need for two dc supplies. The controlling gate-to-source voltage is now determined by the voltage across a resistor RS introduced in the source leg of the configuration a shown in FIG. 7.8.
ELECTRONIC CIRCUIT
CHAPTER 7. FET BIASING 7.3. SELF-BIAS CONFIGURATION
For the dc analysis, the capacitor can again be replaced by OPEN CIRCUIT and the resistor RG replaced by a short-circuit equivalent since IG = 0 A.
The current through RS is the source current ISS = ID and
For the indicated closed loop of FIG.7.9, we find that
In this case that VGS is a function of the output current ID and not fixed in magnitude as occurred for the fixed-bias configuration.
20/89
A mathematical solution could be obtained simply by substituting Eq. (7.10) into Shockleys equation as follows
ELECTRONIC CIRCUIT
Let us now identify two points on the graph that are on the line and simply draw a straight line between the two points. The most obvious condition to apply is ID = 0 A since it results in VGS = -IDRS = (0 A)RS = 0 V.
For Eq. (7.10), therefore, one point on the straight line is defined by ID = 0 A and VGS = 0 V, as appearing on FIG 7.10.
The second point for Eq. (7.10) requires that a level of VGS or ID be chosen and the corresponding level of the other quantity be determined suing Eq. (7.10).
Suppose, for example, that we choose a level of ID equal to one-half the saturation level. That is,
21/89
(See FIG. 7.11) The straight line as defined by Eq. (7.10) is then drawn and the quiescent point obtained at the intersection of the straight-line plot and the device characteristic curve. The level of VDS can be determined by applying Kirchhoffs voltage law to the output circuit, with the result that
ELECTRONIC CIRCUIT
22/89
23/89
24/89
25/89
26/89
27/89
28/89
29/89
ELECTRONIC CIRCUIT
30/89
The voltage-divider bias arrangement applied to BJT transistor amplifiers is also applied to FET amplifiers as demonstrated by FIG. 7.21. The network of FIG. 7.21 is redrawn as shown in FIG. 7.22 for DC analysis. All the capacitors, including the bypass capacitor CS, has been replaced by an OPEN CIRCUIT equivalent. The source VDD was separated into two equivalent sources to permit a further separation of the input and output regions of the network.
ELECTRONIC CIRCUIT
CHAPTER 7. FET BIASING 7.4. VOLTAGE-DIVIDER CONFIGURATION Since IG = 0 A, Kirchhoffs current low requires that IR1 = IR2, and the series equivalent circuit appearing to the left of the figure can be used to find the level of VG.
31/89
Applying Kirchhoggs voltage law in clockwise direction to indicate loop of FIG. 7.22 result in
ELECTRONIC CIRCUIT
CHAPTER 7. FET BIASING 7.4. VOLTAGE-DIVIDER CONFIGURATION
Substituting
32/89
ELECTRONIC CIRCUIT
33/89
ELECTRONIC CIRCUIT
34/89
35/89
ELECTRONIC CIRCUIT
36/89
37/89
38/89
ELECTRONIC CIRCUIT
39/89
ELECTRONIC CIRCUIT
CHAPTER 7. FET BIASING 7.5. DEPLETION-TYPE MOSFETs
40/89
41/89
42/89
43/89
44/89
45/89
46/89
ELECTRONIC CIRCUIT
CHAPTER 7. FET BIASING 7.5. DEPLETION-TYPE MOSFETs
47/89
For the n-channel enhancement-type MOSFET, the drain current is ZERO for levels of gate-to-source voltage less than the threshold level VGS(Th), as shown in FIG. 7.36. For levels VGS greater than VGS(Th), the drain current is defined by
ELECTRONIC CIRCUIT
CHAPTER 7. FET BIASING 7.6. ENHANCEMENT-TYPE MOSFETs
Since specification sheets typically provide the threshold voltage and a level of drain current (ID(on)) and its corresponding level of VGS(on), two points are defined immediately as shown in FIG. 7.36.
48/89
Feedback Biasing Arrangement A popular biasing arrangement for enhancement-type MOSFETs is provided in FIG. 7.37. The resistor RG brings a suitably large voltage to the gate to drive the MOSFET ON. Since IG = 0 mA and VRG = 0 V, the DC equivalent network appears as shown in FIG. 7.38.
ELECTRONIC CIRCUIT
For the output circuit,
49/89
Feedback Biasing Arrangement (contd) Since Eq. (7.28) is that of a straight line, the same procedure described earlier can be employed to determine the two points that will define the plot on the graph ( ID = 0 mA an VGS = 0 V)
ELECTRONIC CIRCUIT
50/89
ELECTRONIC CIRCUIT
51/89
52/89
ELECTRONIC CIRCUIT
53/89
Voltage-Divider Biasing Arrangement A second popular biasing arrangement for the enhancementtype MOSFET appears in FIG. 7.43. The fact that IG = 0 mA results in the following equation for VGG as derived from an application of the voltage-divider rule:
ELECTRONIC CIRCUIT
Applying Kirchhoffs voltage law around the indicated loop of FIG. 7.43 results in
For output section
54/89
55/89
ELECTRONIC CIRCUIT
56/89
ELECTRONIC CIRCUIT
57/89
ELECTRONIC CIRCUIT
58/89
ELECTRONIC CIRCUIT
CHAPTER 7. FET BIASING 7.7. SUMMARY TABLE
59/89
ELECTRONIC CIRCUIT
CHAPTER 7. FET BIASING 7.8. COMBINATION NETWORK
60/89
61/89
ELECTRONIC CIRCUIT
62/89
ELECTRONIC CIRCUIT
63/89
ELECTRONIC CIRCUIT
64/89
ELECTRONIC CIRCUIT
65/89
The design process is not limited solely to DC applications. The area of application, level of amplification desired, signal strength, and operating conditions are just a few of the conditions that enter into the total design process. For example, if the levels of VD and ID are specified for the network of FIG. 7.50, the level of VGSQ can be determined from a plot of the transfer curve and RS can then be calculated from
ELECTRONIC CIRCUIT
CHAPTER 7. FET BIASING 7.9. DESIGN
If VDD is specified, the level of RD can then be calculated from
The values of RS and RD may not be standard commercial values, requiring that the nearest commercial values be employed. However, with the tolerance (range of values) normally specified for the parameters of a network, with slight variation due to the choice of standard values will seldom cause a real concern in the design process. In general, it is good design practice for linear amplifier to choose operating points that do not crowd the saturation level (IDSS) or cutoff (VP) region. Level of VGSQ close to VP/2 or level of IDQ near IDSS/2 are certainly reasonable starting points in the design.
66/89
67/89
ELECTRONIC CIRCUIT
68/89
ELECTRONIC CIRCUIT
69/89
ELECTRONIC CIRCUIT
70/89
For the n-channel JFET amplifier, it is clearly understood that the quiescent value of VGSQ is limited to 0 V or a negative voltage. For the network of FIG. 7.55, VGSQ is limited to negative values in the range 0 V to VP.
ELECTRONIC CIRCUIT
CHAPTER 7. FET BIASING 7.10. TROUBLESHOOTING
If a meter is hookep up as shown in FIG. 7.55, with the positive lead (normally red) to the gate and the negative lead (usually black) to the source, the resulting reading should have a negative sign in a magnitude of a few volt. The level of VDS is typically between 25% to 75% of VDD. A reading of 0 V for VDS clearly indicates that either the output circuit has an OPEN or the JFET is internally short-circuited between drain and source. If VD is VDD volts, there is obviously no drop across RD, due to the lack of the current through RD, and the connections should be checked for continuity. If the level of VDS seems inappropriate, the continuity of the output circuit can easily be checked by grounding the negative lead of the voltmeter and measuring the voltage levels from VDD to ground using the positive lead. If VS = VDD, the device is not open between drain and source, but it is also not ON. In this case, it is possible that there is a poor ground that may not be obvious. The internal connection between the wire of the lead and the terminal connector may have separated. Other possibilities also exist, such as shorted device from drain to source.
The continuity of a network can also be checked simply by measuring the voltage across any resistor of the network (except RG in the JFET configuration). An indication of 0 V immediately reveals the lack of current through the element due to an open circuit in the network.
71/89
For p-channel FETs, a mirror image of the transfer curves is employed, and the defined current directions are reversed as shown in FIG. 7.56 for the various types of FETs.
ELECTRONIC CIRCUIT
CHAPTER 7. FET BIASING 7.11. p-CHANNEL FETs
72/89
73/89
ELECTRONIC CIRCUIT
CHAPTER 7. FET BIASING 7.11. p-CHANNEL FETs
74/89
75/89
Since the DC solution of a FET configuration requires drawing the transfer curve for each analysis, a universal curve was developed that can be used for any level of IDSS and VP. The unversal curve for an n-channel JFET or depletion-type MOSFET (for negative values of VGSQ) is provided in FIG. 7.59. Note that the horizontal axis is not that of VGS but of a normalized level defined by VGS/|VP|, the |VP| indicating that only the magnitude of VP is to be employed, not its sign. For the vertical axis, the scale is also normalized level of ID/IDSS. The additional two scales are m and M. The vertical scale labeled m can in itself be used to find the solution to fixed-bias configurations. The other scale, labeled M, is employed along with the m scale to find the solution to voltage-divider configurations.
ELECTRONIC CIRCUIT
CHAPTER 7. FET BIASING 7.12. UNIVERSAL JFET BIAS CURVE
76/89
77/89
ELECTRONIC CIRCUIT
78/89
ELECTRONIC CIRCUIT
79/89
ELECTRONIC CIRCUIT
80/89
ELECTRONIC CIRCUIT
81/89
Voltage-Controlled Resistor (Noninverting Amplifier) One of the most common applications of the JFET is as a variable resistor whose resistance value is controlled by the applied DC voltage at the gate terminal. The plot of a fixed resistor is nothing more than a straight line with its origin at the intersection of the axes.
ELECTRONIC CIRCUIT
CHAPTER 7. FET BIASING 7.13. PRACTICAL APPLICATIONS
For an I-V plot where the current is the vertical axis and the voltage the horizontal axis, the steeper the slope, the less is the resistance; and the more horizontal the curve, the greater the resistance. The linear region of a JFET is defined by VDS VDSmax and |VGS| |VP|. The drain-to-source resistance increases as the gate-to-source voltage approaches the pinch-off value.
82/89
ELECTRONIC CIRCUIT
CHAPTER 7. FET BIASING 7.13. PRACTICAL APPLICATIONS
83/89
84/89
85/89
TUGAS RANGKAIAN ELEKTRONIKA

Chapter 7. FET Biasing
(1) 7.2 Fixed-Bias Configuration (Nomor 2) (2) Analisa rangkaian di soal nomor (1) dengan software simulasi (3) 7.4 Voltage-Divider Biasing (Nomor 12) (4) 7.5 Depletion-Type MOSFETs (Nomor 17) (5) 7.6 Enhancement-Type MOSFETs (Nomor 19)
86/89

Rangkaian Elektronika - Chapter 07 2013

Uploaded by

Document Information

Original Description:

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Rangkaian Elektronika - Chapter 07 2013

Uploaded by

Copyright:

Available Formats

oleh: Dr. Ir. Retno Wigajatri Purnamaningsih, MT

1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 15)

For enhancement-type MOSFETs and MESFETs, the following equations is applicable:

The current through RS is the source current ISS = ID and

For the indicated closed loop of FIG.7.9, we find that

For output section

If VDD is specified, the level of RD can then be calculated from

TUGAS RANGKAIAN ELEKTRONIKA

You might also like