&

A/D Converters

2000
!"#

A/D Converters

2/30

A/D Converters

1.
1. .............................................................................................................. 3

2. A/D CONVERTER .................................................. 4

3. DUAL SLOPE A/D CONVERTER ................................................................................. 6

4. CHARGE BALANCING DUAL SLOPE A/D CONVERTER ................................... 10

5. TRACKING ANALOG TO DIGITAL CONVERTER ............................................... 12

6. SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER ........ 14

6.1
6.2
6.3
6.4
6.5

SAR .............................................................................................. 14
A/D............................................................................................. 16
A/D .......................................... 18
LADDER ...................................................................................... 19
LADDER ......................................................................................... 22

7. A/D MODULATOR.................................. 24
7.1

........................ 26

8. ............................................................................................................. 30

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A/D Converters

2. A/D Converter

A/D .
bits . ,
(bits) bits
Vref, :
bits
Vin = Vref Q n 2 n
n =1

1/2 LSB
:
bits
Vref
Vref
Vq = Vref Q n 2 n = bits +1 ... + bits +1 Vin
2
n =1
2

,
(quantization noise).
11
10

Vin

01

Va/d

00

Vq

1/4

2/4

3/4 4/4

Vin

+Vref/8
-Vref/8

RMS :
2

VLSB
1 T/2
1 T/2 2 t
Vq(RMS) =
Vqdt
=
=
V

LSB

T T / 2
T T / 2
12
T

4/30

A/D Converters

A/D
bits resolution A/D
.
(Dynamic Range) A/D . A/D
RMS
RMS .
() :
Vref

Vin (RMS)
2 2 = 6.02 bits + 1.76dB
= 20 log
Vq(RMS)
VLSB

12

A/D
:
Offset Error: DC
.
.
Gain Error:
(Vref/2bits).
1:1.
Integral Non Linearity (INL):
, Gain Offset Error.
Differential Non Linearity (DLN):
.
Monotonicity: A/D '
.
A/D INL LSB.
Missing Codes: missing codes
A/D.
Conversion Time:
.
0.5 LSB
. , pipeline
- ,
' .

5/30

A/D Converters

3. Dual Slope A/D Converter

. 1 Dual Slope A/D Converter.
(2)
Vin -Vref, (3) N bit
(5).
:
10nF
C1
X6
SW-ON-ON
Vin

D1
1N4148
R1

X2

X3
TP1

10K

TP2

EOC

X1
TP3

V1
Vref

GND

OPAMP

GND

OPAMP

OR

DCLK1
GND

10.24MHz
X5

Q[N-1..0]

X4

Clk

TC

N bit Counter
Reset

Q[N-1..0]
R

COUNTER

SR_FF
Reset

SOC

Switch

. 1. Dual Slope A/D Converter

:
(X4) SR-FF Q=1
(X6)
R1
(-Vref)
(TP1) +0.7 V,
D1 .
(2) (3) (High) (;)
(3) OR (High) (;)
(=0) (. . 2) (High)
SOC (Start Of Conversion) .
SF-FF (Low) (6)
Vin.
Vin:

6/30

A/D Converters

dVTP1
Vin
=
dt
R1 C1

(=1)
(Low).
, .
(=2)
2
DCLK1 TC
(Terminal Count). SR-FF
(High).

:
dVTP1
Vref
=
dt
R1 C1

(=3)
(High).
.
0.7V
0.0V

TP1
SOC
TP2
Switch
TC
T=0 T=1

T=2 T=3

T=4

. 2. Dual Slope A/D

Converter
(=1) (=2)
.

(2) '
.
(=1) (=2):
VT12 =

Vin 2 N

R1 C1 Fref

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A/D Converters

(=2) (=3)
.

() ' .

(=2) (=3):
VT23 =

Vref
K

R1 C1 Fref

'
:
Vin = Vref

K
2N

EOC (End of
Conversion) (High)
(R1C1).

:
R1 C1 =

Vref
2N

Vmax Fref

A/D
A/D.
:
Vref

1
2

= 5V

1
= 4.883mV
1024

.
,
. (conversion time)
;
(Vref).
:
TA / D =

2N
Vin max 2 N +1
= 200sec
1 +

Fclk Vref
Fclk

8/30

A/D Converters

.
. '
Jfet MOS
Fet .
Vos
.
Vin Vos
Vin
N Vos (Vin + Vref )
Kerr = 2 N

= 2
Vref Vref + Vos
Vref (Vref + Vos)

:
2 Vos
2 Vos
Kerr = 2 N
2 N

Vref
(Vref + Vos)

bits A/D converter
Vos :
Vos

Vref
2 N +1

A/D converter

.

.

0.
0

2 0

4 0

6 0

8 0

1 0 0

1 0

1 0 0

. 3. ( DB)
. 0,1.

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A/D Converters

4. Charge Balancing Dual Slope A/D Converter

A/D Dual Slope A/D
converter.
Start of Conversion.
. 4 . Vin
(T1)
bits counter.
T1 =

2N
Fclk

1 :
Q=

T1
Vin
R1 C1

1 SR-FF (4)
(6).
. 1
2:
Q=

T2
Vin
Iref

C1
R1

:
T2
Vin = Iref R1

T1 + T 2
DCLK1

X5
Clk

C1

Vin

CAP1

N bit Counter
Reset

X2

R1

TC

DIGCLOCK

Q[N-1..0]

COUNTER
X3
X4

TP1

TP2
GND

OPAMP

GND

N bit Latch

OPAMP
SR_FF

GND

EOC

X?
Clk

R
SW-ON-ON

D[N-1..0]

Q[N-1..0]

Q[N-1..0]

N-BIT-LATCH

Switch

X6
I1
IREF
GND

. 4. 3. Charge balancing Dual Slope A/D Converter

(3)
SR-FF
Latch (X7) .

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A/D Converters

0.0V

TP1
Latch

TP2
Switch
TC
T=0

T=1
T1

T=2

T2

. 5. Charge
Balancing Dual Slope A/D Converter
. 5 A/D
converter. (=0-)
( TP2) Latch
( ) (High)
SR-FF. (=0 =1)
. =1
2 SR-FF.
(=1 =2)
.
(=2)
(=0-).

11/30

A/D Converters

5. Tracking Analog to Digital Converter

Tracking A/D converter
. 6. Up/Down Counter,
D/A Ladder.
D/A
Ladder .
,
A/D .

bits D/A
Ladder.

.
:
dV Vfs Fclk
=
dt
2N

:
Fclk
Fin MAX =
2N

Vfs peak to peak.


D/A ladder.

, Vfs/2.
Vin
X1

D/A Ladder

CLK

VDAC

QN

Q2

Q1

Q0

QN

Q2

Q1

Q0

Up/Down Counter

V?
VPULSE
GND

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Up/Down

OPAMP

A/D Converters

. 6. Tracking A/D Converter

. 7 .

.
bit
.
Tracking A/D
.

. 7. Tracking A/D Converter

. 8. . 7
.
. 8
. 1bit.

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A/D Converters

6. Successive Approximation Analog to Digital Converter

A/D
(Successive Approximation Register), D/A Ladder,
. A/D
.

( FF
SAR).

. '

.
Vfs/2N ( Vfs ).
bits o SAR

.
6.1 SAR
SAR JK-FF
AND. .
Q

X2A

X2C

9
16

8
10

X5A
15

3
2

P3
G74HC08

CLK
14

G74HC76

X2B
6

G74HC08

SD

P1

CD

G74HC08

P2

P4
COMP

SET

RESET

CLK

. 9. SAR
CLK
FF J K.
SET MSBit FF
SAR.
RESET
LSBits FFs SAR.
SAR 2-1 bit
.

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A/D Converters

COMP
A/D D/A Ladder.
COMP High Ladder
. COMP FF High,
COMP High
FF High FF
Low ( 3, 4).
1 3 (MS)
.
4 2 (LS)
.
3 High FF High
FF Low. 3 High
FF CLK
FF ' COMP High,
Ladder
A/D.
(MSB) SAR 1
Low SET Start of Conversion (SOC).
SAR RESET
SOC. Cascade. .
10 8 bit A/D converter.
R20 2K

+
VIN

Vcc
Out
+

R21
1K

V2
VSRC

OpAmp2
opamp.sch

VCOMP

OpAmp1
opamp.sch

Vcc
Out

GND

DCOMP

V1
VSIN
GND

R5
1K

GND
.CLK3
0
DIGPOWER0

R14

R13

1K

R4
2K

A/D_CELL1
A2DCELL.SCH
P1
P2
CLK
COMP
SET
RESET

DCLK1

Q
P3
P4

R11

1K

R1
2K

A/D_CELL2
A2DCELL.SCH
Q7
P1
P2
CLK
COMP
SET
RESET

Q
P3
P4

R12

1K

R2
2K

A/D_CELL3
A2DCELL.SCH
Q6
P1
P2

Q
P3
P4

R15

1K

R3
2K

A/D_CELL5
A2DCELL.SCH
Q5

CLK
COMP
SET
RESET

P1
P2

Q
P3
P4

R16

1K

R7
2K

A/D_CELL6
A2DCELL.SCH
Q4

CLK
COMP
SET
RESET

P1
P2
CLK
COMP
SET
RESET

Q
P3
P4

R17

1K

R8
2K

A/D_CELL7
A2DCELL.SCH
Q3
P1
P2
CLK
COMP
SET
RESET

Q
P3
P4

R18

1K

R9
2K

A/D_CELL8
A2DCELL.SCH
Q2
P1
P2
CLK
COMP
SET
RESET

Q
P3
P4

1K

R10
2K

A/D_CELL4
A2DCELL.SCH
Q1
P1
P2

Q
P3
P4

R6
2K

GND
Q0
.CLK2

VDAL
GND

DIGPOWER1

CLK
COMP
SET
RESET

CLK

DIGCLOCK
DCLK2

SOC

DIGNCLOCK
.CLK1
1
DIGPOWER1

. 10. 8 bit A/D converter

.
) High :
Low
.
High
SOC

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A/D Converters

) ( )
Low :
High
VCOMP High
Low
) SOC High
Low.
6.2 A/D
. 11 A/D converter.
V(Vcomp) OpAmp1
V(Vin) A/D converter.
CLK converter,
DCOMP (OpAmp2), SOC
AD.

. 11. A/D converter

. 12 . 11 51.2S
55S. . O
SOC SAR 128 D/A Ladder
2.5V. (DCOMP)
Low .
SAR 192
Ladder 3.75V.

16/30

A/D Converters

. 12. A/D
Converter
, A/D
.

. 12.

SOC
CLK
CLK
CLK
CLK
CLK
CLK
CLK

SAR
128
192
224
240
248
252
250
249

Ladder
2.50000000V
3.75000000V
4,37500000V
4,68750000V
4,84375000V
4,92187500V
4,88281250V
4,86328125V

Comparator
Vi>Vcomp
Vi>Vcomp
Vi>Vcomp
Vi>Vcomp
Vi>Vcomp
Vi<Vcomp
Vi>Vcomp
Vi>Vcomp

Ladder 0,01953125V (5V/256).
DCOMP
Ladder SAR 252
249.
. . 13
.

.

17/30

A/D Converters

. 13. (V(DCOMP))
.
6.3 A/D
. 11
6.5S 10S. A/D
.
. . 14
6.5S 10S.
0,0625V/S.
A/D 3,2S
,
0,01953125V
(5V/256).

. 14. A/D ''

.
18/30

A/D Converters

' A/D.


(Ct):
d ( Vfs sin(2Ft)) Vfs 1
1
N F N +1
dt
Ct
2
2
Ct

A/D

1
9

2 3.2S

= 194 z .

A/D S&H
A/D Niquist
F =

= 156.250z , 2
2 3.2S

S&H. S&H
A/D A/Ds
S&H.
6.4 Ladder
. 15 3 bit Ladder.
Q[2..0]
.
Vo

V1
1KR2
R1
1K

GND

V2
1KR3

V3
1KR4

R7
2K

R8
2K

Q2

Q1

1KR5
R9
2K

Q0

R6
1K

GND

. 15. 3 Bit Ladder

Q2.
ladder . 16
Q2.

19/30

A/D Converters

R7

V1
R2
1K

Q2

2K

Vo

2K

R1
1K

GND

GND

. 16.
Q2 Vo
. 16
R1, R2 R7
2.
V1 2.
1
3

V1 V1 = VQ2
1
2

Vo Vo = V1 = VQ 2

11
32

Q1.
ladder
Q1.
R3

V1

V2

1K

R2
1K

R8
2K

Q1

2K

Vo

R7
2K
R1
1K

GND

GND

GND

. 17.
Q1 Vo

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A/D Converters

. 17
R1, R2, R3, R7 R8
2.
V2
2. V2
1
3

1
2

V2 = VQ1 . V1 V1 = V2 = VQ2
1
2

Vo = V1 = VQ1

11
.
32

11
. Q1
34

Q2
Q0.
ladder
Q0.
V1 R3
1K
R2
1K

V2 R4
1K

R7
2K

R8
2K

V3 R9
2K

Q0

2K

Vo
R1
1K

GND

GND

GND

GND

. 18. ''
Q0 Vo
. 18 R5,
R6 2.
Q0
Vo Vo = VQ0

11
.
38

Q0 Q2.
Vo
Q[2..0].
Vo =

1
1
1
1
VQ2 + VQ1 + VQ0

3
2
4
8

21/30

A/D Converters

3.
. 10 OpAmp1.
6.5 Ladder
Ladder
. 19. C0-C3
.

bit.
.
(. . 19)
Vin.
(6) Vin (5).
(SOC) (High).
(SOC) (High) 0-3
5.
Vcmp
X6

C3
8C

GND

C2
4C
X3

C1
2C
X2

Q3

GND

C0
C
X1

Q2

GND

GND

X7

OPAMP

X0

Q1

GND

Q0

GND
X5
Vin
Vref

SOC
Q3
SOC

Q2

Q1

Successive Aproximation Register

Q0
CMP

. 19. Successive Approximation A/D converter

Ladder. ( )
(. . 20) (
) 6
, 5 Vref .

SAR:
Vcmp = Vref

K
2N

Vin

22/30

A/D Converters

SAR
Vcmp. CMP 7 High
Ladder Vin.
Vcmp
X6

C3
8C

GND

C2
4C
X3

C1
2C
X2

Q3

GND

C0
C
X1

Q2

GND

GND

X7

OPAMP

X0

Q1

GND

Q0

GND
X5
Vin
Vref

SOC
Q3
SOC

Q2

Q1

Successive Aproximation Register

Q0
CMP

. 20. Successive Approximation A/D converter

Ladder. ( , )

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A/D Converters

7. A/D MODULATOR
. 23 ()
Modulator. (3,C1,R1,R2)
( R1=R2):
VINT =

1
Vin + VDAC Vref
R1 C1

VDAC D-FF (2)

threshold NOT (1).
100N
X1
VIN R1

X3

VINT

X2
VCMP

1K
V1
VSIN
GND

DCLK1
DIGCLOCK

R2
1K

PR

R3

VADC

2K

NOT

OPAMP
Vref/2

CLK

CLR

100

C2

Q
D_FF

GND

VDAC

. 21 modulator
NOT (X1) D-FF (X2)
.
D-FF ( 0V 5V)
one bit D/A converter.
Vref/2
5V/2, Vref
D/A converter D-FF.
threshold
(1) :
Vin = Vref VDAC = NOT( VDAC)

D-FF
.
modulator

one Bit A/D converter. one bit D/A
converter .

D/A converter.
.

24/30

A/D Converters

. 22 modulator

modulator .
DFF .

. 23 . 22

25/30

A/D Converters

. 24 1.2V -
7.1


. 25 .
Vi

Vo
R
C
GND

. 25
+1

:
T

Vo(( K + 1) T ) = Vo( K T ) + (Vi( K T ) Vo( K T ) ) 1 e RC

Fo=1/2RC
Fs 1/.

.
- (Over Sampling Ratio OSR):
OSR =

26/30

Fs
2 Fo

A/D Converters

:
Vo(( K + 1) T ) = Vo( K T ) e

OSR

+ Vi( K T ) 1 e OSR

.

modulator,
modulator.

1 e

OSR

= 2 M e

OSR

= 1 2 M

:
Vo(( K + 1) T ) = Vo( K T ) (1 2 M ) + Vi( K T ) 2 M

M
adder Parallel
Shift Register.
modulator (0 Vfs) (0 - 2) Bits
.

2-M modulator High.
clock
1-2-M.
M bits -
bits
bits .
M
OSR, bits - M
bits +1 MSBits .

27/30

A/D Converters

4
1 10

1000

OSR( M)

100

10

10

. 26 bits
-
. 27 block
. '
.
N-M

2
0

Parallel
Shift
Register
+

N
N-M

. 27 block

Assembly 8051. =8
=24. 24 bits MSB LSB
R0, R1 R2. R0.

28/30

A/D Converters

ADDRESS
LPF:

LPF1:

MNEMONIC
CLC
MOV A,R2
SUBB A,R1
MOV R2, A
MOV A,R1
SUBB A,R0
MOV R1, A
MOV A, R0
SUBB A, #0
JNB TB,LPF1
ADC A,#1
MOV R0,A
RET

COMMENT
Clear carry
Move to A the LSByte
Subtract the medium byte
Restore
Get the medium byte
Subtract the MSByte
Restore
Get the MSByte
Subtract the carry
Test output of modulator
If high add 1 to MSByte
Restore the MSByte
-R0 now holds the digital word

CYCLES
12
12
12
12
12
12
12
12
12
24
12
12
24
180

' 8051
12 MHz, 15 sec
65000 .

modulators
processor FPGA '
.
sin(x)/x.

29/30

A/D Converters

8.
, R. C, Jaeger , 16.8, . 1262 1293
, SEDRA/SMITH, ,
. 10.9, . 982-1000
, MILMAN/GRABEL, , . 16.4,
. 783-798

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