UNIT01 Defects and Yield

DFT Basics
UNIT 1 : Defects & Yield

FTM- Central CAD & Design Solutions
STMicroelectronics
FTM- Central CAD & Design Solutions DFT Design Methodologies STMicroelectronics - 2005
Course Breakup
CONFIDENTIAL
DAY 1
Defects & Yield
DAY 2
Memory DFT
Defects & Faults
ATPG Concepts
Scan DFT
Test Cost Reduction
Scan Diagnostics
At-Speed Testing
Conclusion
FTM- Central CAD & Design Solutions DFT Design Methodologies
STMicroelectronics - 2005
Lesson Outline
CONFIDENTIAL
- Design Flow, Defects & Faults
- Test
- Cost of Test
- Yield
- Defect Level
Lesson Objectives
CONFIDENTIAL
At the end of this course you will be able to :
Define Defects and Faults Describe the meaning of Test and to understand the Test Cost Define Defect Level as a function of Yield and Fault Coverage
Semicustom die birth to CONFIDENTIAL maturity

Specs. RTL. Synthesis Gate Level Netlist Place n Route
GDS II
FAB Wafer Out Die packaging Board testing
Definitions
CONFIDENTIAL
Design synthesis
Given an I/O function, develop a procedure to manufacture a device using known materials and processes.
Verification
Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function.
Test
A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.
Physical Defects & Faults
STMicroelectronics
What Is a Physical Defect?
CONFIDENTIAL
Physical Defect: A on-chip flaw introduced during fabrication or packaging of an individual ASIC that leads to a logical malfunction.
Short Circuit
Typical Examples
Open Circuit
Transistor Stuck ON
Oxide Pinholes
Physical Defects in CMOS CONFIDENTIAL

Power Rail
0.18 m m
p-Type Transistor n-Type Transistor

0.18 m m
Micron Dust Particle
Ground Rail
Physical Defects in CMOS (contd). CONFIDENTIAL

POWER
Output Shorted to 1
Input Open
IN
Input Shorted to 0
OUT
GROUND
What is a Fault ?
CONFIDENTIAL
Fault is the manifestation of a physical defect or defects. A Fault Model abstracts the defects at the logic gate level. Fault Models represent different types of fault
Test Type
Functional Structural
Fault Model
Functional Model Single Stuck-at, Multiple Stuck-at, Bridging, Stuck Open Transition, path delay
Defects
Opens/Shorts in circuit CMOS Transistor stuck-open, short, resistive bridging, Leaky transistors. Partially conducting transistors, resistive contacts, failing vias.
At-Speed
An Example
CONFIDENTIAL
Physical Defect : A metal via may be missing between VDD supply and the drain of an CMOS inverter.
POWER POWER
Two Vias Missing
IN
OUT
IN
OUT
GROUND
GROUND
This defect can be a Functional Fault in a Memory, but only a Transition Fault in a CMOS Inverter.
Test
STMicroelectronics
Problems of Ideal Test

CONFIDENTIAL
Ideal tests detect all defects produced in the manufacturing process.
Ideal tests pass all functionally good devices.
Very large numbers and varieties of possible defects need to be tested.
Difficult to generate tests for some real defects.
Defect-oriented testing is an open problem.
Real Tests
CONFIDENTIAL
Based on analyzable fault models, which may not map on real defects. Incomplete coverage of modeled faults due to high complexity. Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. Some bad chips pass tests.The fraction (or percentage) of bad chips among all passing chips is called the defect level.
Testing as a Filter Process

CONFIDENTIAL
Good chips Prob. (good) = y
Mostly Good chips
Fabricated chips
Sold Chips
Bad chips
Prob. (bad) = 1-y
Mostly Bad chips
Cost of Test
CONFIDENTIAL
Design for testability (DFT)

Chip area overhead and yield reduction Performance overhead
Software processes of test

Test generation and fault simulation Test programming and debugging
Manufacturing test

Automatic test equipment (ATE) capital cost Test center operational cost
Cost of Test
CONFIDENTIAL
Low number of DPM is very critical Cost to replace parts grows exponentially through a design cycle Cost of bad part in critical device(for example, a pacemaker or airplane is immeasurable)
$10000
$1000 $100
$10
$1
SPEC Analysis Design Test Production Field
Yield
STMicroelectronics
VLSI CHIP YIELD

CONFIDENTIAL
A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. A chip with no manufacturing defect is called a good chip. Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y.
Cost of a chip:
Cost of fabricating and testing a wafer Yield x Number of chip sites on the wafer
Clustered VLSI Defects

CONFIDENTIAL
Good chips
Faulty chips
Defects Wafer Unclustered Defects

Wafer yield = 12/22 = 0.55
Clustered Defects
Wafer yield = 17/22 = 0.77
YIELD Parameters
CONFIDENTIAL
Defect density (d ) = Average number of defects per unit of chip area Chip area (A) Clustering parameter ()
Negative binomial distribution of defects,

P (x ) = Probability (number of defects on a chip = x )
(a+x ) P(x) = x ! (a)
(Ad /) x
(1+Ad /) +x
Where is the gamma function = 0, P(x ) is a delta function (maximum clustering) = , P(x ) is Poisson distribution (no clustering)
YIELD Equation
CONFIDENTIAL
Y = Probability ( zero defect on a chip ) = P(0)
Y = ( 1 + Ad / )
Example: Ad = 1.0, = 0.5, Y = 0.58
Unclustered defects: =
Y = e Ad
Example: Ad = 1.0, = , Y = 0.37
Defect Level
STMicroelectronics
Determination of DL
CONFIDENTIAL
From field return data
Chips failing in the field are returned to the manufacturer. The number of returned chips per million chips shipped is the DL.
From test data
Fault coverage of tests and chip fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the DL.
Determination of DL
Three parameters:

CONFIDENTIAL
Fault density, f = average number of faults per unit chip area Fault clustering parameter, Fault coverage, T
The modified yield equation:
Y (T ) = (1 + TAf / ) (1 Af)T
Assuming that tests with 100% fault coverage (T = 1.0) remove all faulty chips,
Y = Y (1) = (1 + Af / ) (1-Af)
DL(T) =
Y (T) - Y(1) Y(T)
DL(T) = 1 Y
(1-T)
Defect Level or Rejection Ratio

CONFIDENTIAL
Defect level (DL) is the ratio of faulty chips among the chips that pass tests. DL is measured as parts per million (ppm). DL is a measure of the effectiveness of tests. DL is a quantitative measure of the manufactured product quality. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable.
Summarizing DL
CONFIDENTIAL
IC Fabrication
Yield Y (Fraction of good parts)
DL(T) =
Y (T) - Y(1)
Y(T)
where Y = Yield T = Fault Coverage Passed die Yield = --------------------------Passed + Failed die
Test
Reject / Diagnose
Shipped parts (good & bad) bad => Defect Level (DL) in Defective parts per million (DPM)
The number of DEFECTIVE PARTS sold as good is DL
Is High Coverage Needed?

CONFIDENTIAL
STIL 1.0; nnnnnnnnnnn nnnnnnnnnnn nnnnnnnnnnn nnnnnnnnnnn nnnnnnnnnnn nnnnnnnnnnn nnnnnnnnnnn nnnnnnnnnnn nnnnnnnnnnn nnnnnnnnnnn
Test Program
Test Escapes: Parts that pass every test, but still have undetected defectsand reach users!
ATE
Defect Level: The fraction of test escapes, in defective parts per million (DPM).
Failed Any Test
Example : SEMATECH Chip

CONFIDENTIAL
Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont 116,000 equivalent (2-input NAND) gates 304-pin package, 249 I/O Clock: 40MHz, some parts 50MHz
0.8 CMOS, 3.3V, 9.4mm x 8.8mm area

Full scan, 99.79% fault coverage Advantest 3381 ATE, 18,466 chips tested at 2.5MHz test clock Data obtained courtesy of Phil Nigh (IBM)
Stuck-At Fault coverage

CONFIDENTIAL
Data Taken from : Copyright 2001, Agrawal & Bushnell

Defect Level vs. SAF Coverage

CONFIDENTIAL
Data Taken from : Copyright 2001, Agrawal & Bushnell

ST Chip Features
CONFIDENTIAL
Project A
130 nm process Consumer market High-runner product >1M EGates logic 5 clock domains 100MHz (max) Full-scanned no compression ~50k flip-flops 32 scan chains
Project B
90nm process Network application High-volume product 2M EGates logic 17 clock domains 250MHz (max) Full-scanned with compression 141k flip-flops 1611 internal scan chains 30 external chains
Structural Test Pattern Suite

CONFIDENTIAL
Project A Top-off BF

Project B BF

4.2k patterns TC = 90.76%
31k patterns TC = 84.5%
Preliminary Results
CONFIDENTIAL
Project A Test type: EWS #Tested dices: ~ 111k Yield ~ 80% Bridging fault test

Project B Test type: EWS #Tested dices: ~ 250k Yield ~ 50% Bridging fault test

Failing dices = 2
Failing dices = 84
dppm = 18
dppm = 337
Failing dices @ all Vdd = 1
Failing dices @ all Vdd = 41
dppm = 9
dppm = 164
Data collection completion is expected by Q3 2006
Pre-production just started
Defect Coverage Defect Level Level vs vs Test Coverage

CONFIDENTIAL
100% 100% 100% 90% 90% 90% 80% 80% 80%
Level Defect Defect Level
DL = 1 -Y Y
(1-T) (1-T)
70% 70% 70% 60% 60% 60%

50% 50%
Y = 10% Y = 10%
Y = 30% 70% Y =Y 90% = 90%
1 10 10 0 00 0
40% 40% 40% 30% 30% 30% 20% 20% 20% 10% 10% 10%
0% 0%
10 1 10
2 20 0 2 0
3 3 30 0 0
40 0
5 50 0
6 60 0
7 70 0
8 80 8 0 0
Test Coverage Coverage (% Test (%))

9 90 0 9 0
0 0 0
Lesson Review
CONFIDENTIAL
What is a Physical Defect ?
What is a Fault ?
What is the difference between Test and Verification ?
What is the difference between Real Test and Ideal Test ?

What has Clustering to do with Yield ? What is DL and how does it depend upon Fault Coverage ? What will happen if we choose a wrong Fault Model ?
Summary
CONFIDENTIAL
VLSI yield depends on two process parameters, defect density (d ) and clustering parameter (). Yield drops as chip area increases; low yield means high cost. Fault coverage measures the test quality. The number of DEFECTIVE PARTS sold as good is Defect level (DL). DL or reject ratio is a measure of chip quality. DL can be determined by an analysis of test data.
For high quality: DL < 500 ppm, fault coverage ~ 99%
Backup Slides
STMicroelectronics
Defect Level after Test

CONFIDENTIAL
DL
= Defect Level after Test
Yield = Probability of Chip Manufactured Correctly T = Test Coverage
DL = 1 - Y
(1-T)
Defect Level Level vs vs Test Test Coverage Coverage Defect

100% 100% 100% 90% 90% 80% 80% 80% 70% 70% 70% 60% 60% 60% 50% 50% 50% 40% 40% 40% 30% 30% 30% 20% 20% 20% 10% 10% 0% 0%
CONFIDENTIAL
Defect Level Level Defect DefectLevel
DL = =1 1-Y DL
(1-T) (1-T) Y
Y = 30% 70% Y = 90%

11 00
22 00
$
55 00 66 00 77 00
Y = 10%
Test Test Coverage Coverage (% (% ) )

11 00 00
33 00
44 00
88 00
99 00
00
Voids in Cu CONFIDENTIAL
Results in Delay Defects!

Source: Infineon - ChiPPS Meeting, 13.-17.10.2002, Prague, Czech Rep.

UNIT01 Defects and Yield

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DFT Basics

UNIT 1 : Defects & Yield

Defects & Faults

Test Cost Reduction

FTM- Central CAD & Design Solutions DFT Design Methodologies

- Design Flow, Defects & Faults

FTM- Central CAD & Design Solutions DFT Design Methodologies

At the end of this course you will be able to :

FTM- Central CAD & Design Solutions DFT Design Methodologies

Semicustom die birth to CONFIDENTIAL maturity

FTM- Central CAD & Design Solutions DFT Design Methodologies

FTM- Central CAD & Design Solutions DFT Design Methodologies

Physical Defects & Faults

FTM- Central CAD & Design Solutions

What Is a Physical Defect?

FTM- Central CAD & Design Solutions DFT Design Methodologies

Physical Defects in CMOS CONFIDENTIAL

p-Type Transistor n-Type Transistor

Micron Dust Particle

Physical Defects in CMOS (contd). CONFIDENTIAL

FTM- Central CAD & Design Solutions DFT Design Methodologies

Two Vias Missing

FTM- Central CAD & Design Solutions DFT Design Methodologies

FTM- Central CAD & Design Solutions

Problems of Ideal Test

Ideal tests detect all defects produced in the manufacturing process.

Ideal tests pass all functionally good devices.

Very large numbers and varieties of possible defects need to be tested.

Difficult to generate tests for some real defects.

Defect-oriented testing is an open problem.

FTM- Central CAD & Design Solutions DFT Design Methodologies

FTM- Central CAD & Design Solutions DFT Design Methodologies

Testing as a Filter Process

Good chips Prob. (good) = y

Mostly Good chips

Prob. (bad) = 1-y

Mostly Bad chips

FTM- Central CAD & Design Solutions DFT Design Methodologies

Design for testability (DFT)

Chip area overhead and yield reduction Performance overhead

Software processes of test

Test generation and fault simulation Test programming and debugging

FTM- Central CAD & Design Solutions DFT Design Methodologies

FTM- Central CAD & Design Solutions DFT Design Methodologies

VLSI CHIP YIELD

Clustered VLSI Defects

Defects Wafer Unclustered Defects

FTM- Central CAD & Design Solutions DFT Design Methodologies

Negative binomial distribution of defects,

(a+x ) P(x) = x ! (a)

Y = Probability ( zero defect on a chip ) = P(0)

Example: Ad = 1.0, = 0.5, Y = 0.58

Example: Ad = 1.0, = , Y = 0.37

FTM- Central CAD & Design Solutions DFT Design Methodologies

FTM- Central CAD & Design Solutions

From field return data

From test data

FTM- Central CAD & Design Solutions DFT Design Methodologies

The modified yield equation:

Y (T) - Y(1) Y(T)

FTM- Central CAD & Design Solutions DFT Design Methodologies

Defect Level or Rejection Ratio

FTM- Central CAD & Design Solutions DFT Design Methodologies

The number of DEFECTIVE PARTS sold as good is DL