Sistemas Digitales Deber #3

Alejandro Zambrano 105024 3 de Noviembre de 2013

1) Write an HDL module called minority. It receives three inputs, a, b, and c. It produces one output, y, that is TRUE if at least two of the inputs are FALSE. 

Algorithm 1 Minority
module m i n o r i t y ( input a , b , c , output y ) ; a s s i g n y=~a & ~b | ~a & ~c | ~b & ~c ;

endmodule 

2) Write an 8:1 multiplexer module called mux8 with inputs s2:0, d0, d1, d2, d3, d4, d5, d6, d7, and output y. 

Algorithm 2 Mux 8
module mux8 #(parameter width = 4) ( input [ width 1:0] d0 , d1 , d3 , d3 , d4 , d5 , d6 , d7 , input [ 2 : 0 ] s , output r e g [ width 1:0] y ) ; always @( ) case ( s )

endcase endmodule 

0: 1: 2: 3: 4: 5: 6: 7:

y=d0 ; y=d1 ; y=d2 ; y=d3 ; y=d4 : y=d5 ; y=d6 ; y=d7 ;

3) Write a structural module to compute the logic function, y = ab + bc + abc, using multiplexer logic. Use the 8:1 multiplexer from Exercise 4.8. 

Algorithm 3 Ejercicio 9
module e j e r c i c i o 9 ( input a , b , c , output y ) ;

mux8 #(1) mux8_1 ( 1 ' b1 , 1 ' b0 , 1 ' b0 , 1 ' b1 , 1 ' b1 , 1 ' b1 , 1 ' b0 , 1 ' b0 , {a , b , c } , y ) ; endmodule 

4) Sketch the state transition diagram for the FSM described by the following HDL code. 

Figure 1: maquina 5) Write an HDL module for the trac light controller from Section 3.4.1. 

Algorithm 4 Traco
module ex4_32 ( inpu t clk , r e s e t , ta , tb , output r e g [ 1 : 0 ] la , l b ) ; reg [ 2 : 0 ] state , nextstate ; parameter parameter parameter parameter parameter parameter parameter parameter parameter S0 = 3 ' b000 ; S1 = 3 ' b001 ; S2 = 3 ' b010 ; S3 = 3 ' b011 ; S4 = 3 ' b100 ; S5 = 3 ' b101 ; green = 2 ' b00 ; y e l l o w = 2 ' b01 ; red = 2 ' b10 ;

// S t a t e R e g i s t e r always @( posedge clk , posedge r e s e t ) i f ( r e s e t ) s t a t e <= S0 ; e l s e s t a t e <= n e x t s t a t e ; // Next S t a t e Logic always @( ) c a s e ( s t a t e ) S0 : i f ( ta ) n e x t s t a t e = S0 ; e l s e n e x t s t a t e = S1 ; S1 : n e x t s t a t e = S2 ; S2 : n e x t s t a t e = S3 ; S3 : i f ( tb ) n e x t s t a t e = S3 ; e l s e n e x t s t a t e = S4 ; S4 : n e x t s t a t e = S5 ; S5 : n e x t s t a t e = S0 ; endcase // Output Logic always @ ( ) case ( state ) S0 : { la , l b } = { green , red } ; S1 : { la , l b } = { yellow , red } ; S2 : { la , l b } = { red , red } ; S3 : { la , l b } = { red , green } ; S4 : { la , l b } = { red , y e l l o w } ; S5 : { la , l b } = { red , red } ; endcase endmodule

6) The following SystemVerilog modules show errors that the authors have seen students make in the laboratory. Explain the error in each module and show how to x it.  a) Problema: La seal d no est incluido en la lista de sensibilidad de la siempre declaracin. La correccin se muestra a continuacin

Algorithm 5 Arreglo
module l a t c h ( inp ut clk , input [ 3 : 0 ] d , output r e g [ 3 : 0 ] q ) ; always @( clk , d ) i f ( c l k ) q <= d ; endmodule  

b) Seal b no est incluido en la lista de sensibilidad de la declaracion always.

Algorithm 6 Arreglo
module g a t e s ( inp ut [ 3 : 0 ] a , b , output r e g [ 3 : 0 ] y1 , y2 , y3 , y4 , y5 ) ; always @( ) begin y1 = a & b ; y2 = a | b ; y3 = a ^ b ; y4 = ~( a & b ) ; y5 = ~( a | b ) ; end endmodule 

c)

Algorithm 7 Arreglo
module mux2( input [ 3 : 0 ] d0 , d1 , input s , output r e g [ 3 : 0 ] y ) ; always @( s , d0 , d1 ) i f ( s ) y = d1 ; e l s e y = d0 ; endmodule 

d)

Algorithm 8 Arreglo
module t w o f l o p s ( input clk , input d0 , d1 , output r e g q0 , q1 ) ; always @( posedge c l k ) begin q1 <= d1 ; q0 <= d0 ; / end endmodule 

e)

Algorithm 9 Arreglo
module FSM( in put clk , input r e s e t , input a , output r e g out1 , out2 ) ; reg state , nextstate ; always @( posedge clk , posedge r e s e t ) i f ( reset ) s t a t e <= 1 ' b0 ; else s t a t e <= n e x t s t a t e ; always @( ) case ( state ) 1 ' b0 : i f ( a ) s t a t e <= 1 ' b1 ; e l s e s t a t e <= 1 ' b0 ; 1 ' b1 : i f (~ a ) s t a t e <= 1 ' b0 ; e l s e s t a t e <= 1 ' b1 ; endcase always @ ( ) i f ( s t a t e == 0) { out1 , out2 } = {1 ' b1 , 1 ' b0 } ; e l s e { out1 , out2 } = {1 ' b0 , 1 ' b1 } ; endmodule 

f)

Algorithm 10 Arreglo
module p r i o r i t y ( input [ 3 : 0 ] a , output r e g [ 3 : 0 ] y ) ; always @( ) i f ( a [ 3 ] ) y = 4 ' b1000 ; e l s e i f ( a [ 2 ] ) y = 4 ' b0100 ; e l s e i f ( a [ 1 ] ) y = 4 ' b0010 ; e l s e i f ( a [ 0 ] ) y = 4 ' b0001 ; e l s e y = 4 ' b0000 ; endmodule 

g)

Algorithm 11 Arreglo
module divideby3FSM ( input clk , input r e s e t , output out ) ; reg [ 1 : 0 ] state , nextstate ; parameter S0 = 2 ' b00 ; parameter S1 = 2 ' b01 ; parameter S2 = 2 ' b10 ; always @( posedge clk , posedge r e s e t ) i f ( r e s e t ) s t a t e <= S0 ; e l s e s t a t e <= n e x t s t a t e ; / always @( s t a t e ) case ( state ) S0 : n e x t s t a t e = S1 ; S1 : n e x t s t a t e = S2 ; S2 : n e x t s t a t e = S0 ; d e f a u l t : n e x t s t a t e = S0 ; endcase a s s i g n out = ( s t a t e == S2 ) ; endmodule 

h)

Algorithm 12 Arreglo
module mux2tri ( inpu t [ 3 : 0 ] d0 , d1 , input s , output [ 3 : 0 ] y ) ; t r i s t a t e t0 ( d0 , ~s , y ) ; t r i s t a t e t1 ( d1 , s , y ) ; endmodule 

h)

Algorithm 13 Arreglo
module and3 ( input a , b , c , output r e g y ) ; r e g tmp ; always @ ( a , b , c ) begin tmp = a & b ; y = tmp & c ; end endmodule