---------------------------------------------------------------------------------- Company:

-- Engineer:
--- Create Date:
13:27:16 03/22/2010
-- Design Name:
-- Module Name:
xmatchpro64 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity xmatchpro64 is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
start : in STD_LOGIC;
udata : in STD_LOGIC_VECTOR (63 downto 0);
dataout : out STD_LOGIC_VECTOR (63 downto 0);
addrout : out STD_LOGIC_VECTOR (6 downto 0);
matchhit : out STD_LOGIC);
end xmatchpro64;
architecture Behavioral of xmatchpro64 is
component cam64
port
(clk
: in std_logic;
-- Clock
reset
: in std_logic;
-- Reset
start
: in std_logic;
-- Write
datain
: in std_logic_vector(63 downto 0);-- Tag Data
dataout
: out std_logic_vector(63 downto 0);-- Data out
mh0, mh1, mh2, mh3, mh4, mh5, mh6, mh7 : inout std_logic;
mh8,mh9,mh10,mh11,mh12,mh13,mh14,mh15 : inout std_logic;
mh16,mh17,mh18,mh19,mh20,mh21,mh22,mh23 : inout std_logic;
mh24,mh25,mh26,mh27,mh28,mh29,mh30,mh31 : inout std_logic;
mh32,mh33,mh34,mh35,mh36,mh37,mh38,mh39 : inout std_logic;
mh40,mh41,mh42,mh43,mh44,mh45,mh46,mh47 : inout std_logic;
mh48,mh49,mh50,mh51,mh52,mh53,mh54,mh55 : inout std_logic;
mh56,mh57,mh58,mh59,mh60,mh61,mh62,mh63 : inout std_logic;
mh64, mh65, mh66, mh67, mh68, mh69, mh70, mh71 : inout
std_logic;
mh72,mh73,mh74,mh75,mh76,mh77,mh78,mh79 : inout std_logic;

mh80,mh81,mh82,mh83,mh84,mh85,mh86,mh87 : inout std_logic;

mh88,mh89,mh90,mh91,mh92,mh93,mh94,mh95 : inout std_logic;
mh96,mh97,mh98,mh99,mh100,mh101,mh102,mh103 : inout
std_logic;
mh104,mh105,mh106,mh107,mh108,mh109,mh110,mh111 : inout std_logic;
mh112,mh113,mh114,mh115,mh116,mh117,mh118,mh119 : inout std_logic;
mh120,mh121,mh122,mh123,mh124,mh125,mh126,mh127 : inout std_logic;
matchhit
: out std_logic; --Found Match
addr_out : out std_logic_vector(6 downto 0));
end component;
begin
u3:cam64 port map (clk => clk,reset => reset,start => start,datain => udata,data
out => dataout,
mh0 => open, mh1 => open, mh2 => open, mh3 => open,
mh4 => open, mh5 => open, mh6 => open, mh7 => open,
mh8 => open, mh9 => open, mh10 => open, mh11 => open,
mh12 => open, mh13 => open, mh14 => open, mh15 => open,
mh16 => open, mh17 => open, mh18 => open, mh19 => open,
mh20 => open, mh21 => open, mh22 => open, mh23 => open,
mh24 => open, mh25 => open, mh26 => open, mh27 => open,
mh28 => open, mh29 => open, mh30 => open, mh31 => open,
mh32 => open, mh33 => open, mh34 => open, mh35 => open,
mh36 => open, mh37 => open, mh38 => open, mh39 => open,
mh40 => open, mh41 => open, mh42 => open, mh43 => open,
mh44 => open, mh45 => open, mh46 => open, mh47 => open,
mh48 => open, mh49 => open, mh50 => open, mh51 => open,
mh52 => open, mh53 => open, mh54 => open, mh55 => open,
mh56 => open, mh57 => open, mh58 => open, mh59 => open,
mh60 => open, mh61 => open, mh62 => open, mh63 => open,
mh64 => open,mh65 => open,mh66 => open,mh67 => open,mh68 => open,
mh69 => open,mh70 => open,mh71 => open,mh72 => open,mh73 => open,
mh74 => open,mh75 => open,mh76 => open,mh77 => open,mh78 => open,
mh79 => open,mh80 => open,mh81 => open,mh82 => open,mh83 => open,
mh84 => open,mh85 => open,mh86 => open,mh87 => open,mh88 => open,
mh89 => open,mh90 => open,mh91 => open,mh92 => open,mh93 => open,mh94 => open,
mh95 => open,mh96 => open,mh97 => open,mh98 => open,mh99 => open,mh100 => open,
mh101 => open,mh102 => open,mh103 => open,mh104 => open,mh105 => open,mh106 => o
pen,
mh107 => open,mh108 => open,mh109 => open,mh110 => open,mh111 => open,mh112 => o
pen,
mh113 => open,mh114 => open,mh115 => open,mh116 => open,mh117 => open,mh118 => o
pen,
mh119 => open,mh120 => open,mh121 => open,mh122 => open,mh123 => open,mh124 =>
open,mh125=> open,
mh126 => open,mh127 => open,
matchhit => matchhit,
addr_out => addrout);
end Behavioral;