IMPLEMENTATION OF ASYNCHRONOUS FIFO USING VHDL

BY B.V.KALYAN RAM ASST.PROFESSOR

PROJECT ABSTRACT
The Asynchronous FIFO is a First-In-First-Out memory queue with control logic that performs management of the read and write pointers, generation of status flags and optional handshake signals for interfacing with the user logic.

PROJECT ABSTRACT
FIFO is an acronym for First In, First Out. FIFO is a memory element and also provides synchronization between the input and output data To reach this requirement of synchronization we need a separate mechanism. In this project we are implementing the FIFO with a special architecture according to the requirement.

INTRODUCTION

ASYNCHRONOUS FIFO DESIGN

PROJECT DESIGN FLOW

IMPLEMENTATION

VHDL

INTRODUCTION TO FIFO
FIFO (First-in-first-out) memories are Special Purpose devices that implement a basic queue structure that has broad applications in Computer and Communication Architecture. FIFO memory is a Storage device in which data is read out from its memory array (SRAM) in same order in which it is written in memory. The first word written into the memory block is the first word that is read out of the memory block. Because of this operation it is referred as First-in-first-out memories.

INTRODUCTION TO FIFO
This type of memory is used to interface Slow input/output devices to fast operating computers. The FIFO memory is useful as a Data-rate Buffer in which reading and writing operations are done at independent data rates.

ASYNCHRONOUS FIFO
There are times when a designer needs to interface two systems working at two different clocks. This interfacing is difficult in the sense that design becomes asynchronous at the boundary of interface, which results in setup and hold violation, metastability and unreliable data transfers.

ASYNCHRONOUS FIFO
We know that any two systems can be asynchronous to each other when they operate at two different frequency(Case I) or when they operate at same frequency, but at two different clock phase angles (Case II)as shown.

CASE I

CASE II

ASYNCHRONOUS FIFO
In such a case if we need to do data transfer, there are very few methods to achieve this: 1. Handshake Signaling method. 2. Asynchronous FIFO.

BLOCK DIAGRAM OF ASYNCHRONOUS FIFO

ASYNCHRONOUS FIFO
Asynchronous FIFO has got two interfaces, one for writing the data into the FIFO and the other for reading the data out. It has got two clocks, one for writing and the other for reading. System A writes the data in the FIFO and System B reads out the data from it. To facilitate error free operations, we have FIFO full and FIFO empty signals(With respect to corresponding clock)

ASYNCHRONOUS FIFO
An asynchronous FIFO refers to a FIFO design where data values are written to a FIFO buffer from one clock domain and the data values are read from the same FIFO buffer from another clock domain, where the two clock domains are asynchronous to each other. Asynchronous FIFOs are used to safely pass data from one clock domain to another clock domain

ASYNCHRONOUS FIFO
There are many ways to do asynchronous FIFO design. Unfortunately, FIFOs that work properly most of the time have design flaws that are usually the most difficult to detect and debug or the most costly to diagnose and recall. In this project, FIFO, FIFO memory and synchronization modules are developed using VHDL language. All the modules are simulated and synthesized by using Xilinx ISE tool.

FIFO BASIC BLOCK DIAGRAM

FIFO

ASYNCHRONOUS FIFO DESIGN

ASYNCHRONOUS FIFO POINTERS

In order to understand FIFO design, one needs to understand how the FIFO pointers work. The write pointer always points to the next word to be written; therefore, on reset, both pointers are set to zero, which also happens to be the next FIFO word location to be written. On a FIFO-write operation, the memory location that is pointed to by the write pointer is written, and then the write pointer is incremented to point to the next location to be written.

ASYNCHRONOUS FIFO POINTERS

Similarly, the read pointer always points to the current FIFO word to be read. Again on reset, both pointers are reset to zero, the FIFO is empty and the read pointer is pointing to invalid data because the FIFO is empty and the empty flag is asserted.

FIFO EMPTY AND FULL CONDITIONS

FIFO POINTERS
The FIFO is empty when the read and write pointers are both equal. This condition happens when both pointers are reset to zero during a reset operation, or when the read pointer catches up to the write pointer, having read the last word from the FIFO. A FIFO is full when the pointers are again equal, that is, when the write pointer has wrapped around and caught up to the read pointer.

GRAY CODE COUNTER

In this project the flip flop in FIFO is implemented using Gray code counter. By using Gray code counter chances of data corruption when transferring the data from one clock domain to another clock domain can be vastly reduced. Because a Gray code is that the code distance between any two adjacent words is just 1 (only one bit can change from one Gray count to the next).

Gray code

GRAY CODE COUNTER

VHDL

HISTORY OF HARDWARE DESCRIPTION LANGUAGES

Designed by IBM, Texas Instruments, and Intermetrics as part of the DoD funded VHSIC program Standardized by the IEEE in 1987: IEEE 1076-1987 Enhanced version of the language defined in 1993: IEEE 1076-1993 Additional standardized packages provide definitions of data types and expressions of timing data
IEEE 1164 (data types) IEEE 1076.3 (numeric) IEEE 1076.4 (timing)

Traditional Vs HDLs
Procedural programming languages provide the how or recipes
for computation for data manipulation for execution on a specific hardware model

Hardware description languages describe a system

Systems can be described from many different points of view
Behavior: what does it do? Structure: what is it composed of? Functional properties: how do I interface to it? Physical properties: how fast is it?

Why do we Describe systems?

Design Specification
unambiguous definition of components and interfaces in a large design

Design Simulation
verify system/subsystem/chip performance prior to design implementation

Design Synthesis
automated generation of a hardware design

HARDWARE DESCRIPTION LANGUAGE

STEPS IN VLSI DESIGN FLOW

BEHAVIORAL MODELING
The process of directly describing the behavior or the functionality of a circuit is called as behavioral modeling. In this the behavior of the entity is expressed using sequentially executed, procedural code. The key mechanism used to model the behavior of the entity is a process statement.

Behavioral Modeling

IMPLEMENTATION

FUTURE SCOPE
In this project we are implementing the FIFO with a special architecture according to the requirement. In this project mainly we concentrated on FIFO design, FIFO memory and simulation results. In future we will make it to work for other applications and we increase the size of FIFO memory.

CONCLUSION
FIFO Status cannot be corrupted by invalid requests. What we claimed in the abstract our proposed project design met the intended the purpose.

REFERENCES
www.csee.umbc.edu www.sunburst-design.com www.edaboard.com

THANK YOU