10ECL77

10ECL77
VLSI LAB
MANUAL
August 2
2013
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Prepared by:
Vishvakiran RC
Asst. Prof.
Dept of E&C
City Engineering College,
Bangalore.
VLSI LAB PROGRAMS PART A

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------INVERTER.V
module invert(a,y);
input a;
output y;
reg y;
always@(a)
begin
if(a==1)
y=0;
else
y=1;
end
endmodule
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------INVERTER_TB.V
module invtest;
reg p;
wire q;
invert inv_t(.a(p),.y(q));
initial
begin
$display($time,"\t Simulation Starts");
p=1'b0;
#10 p=1'b1;
#5 $display("\n");
end
initial
#30 $finish;
initial
$monitor($time,"p_input=%b,q_inverted_output=%b",p,q);
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
http://www.scribd.com/doc/174536337/10ECL77-VLSI-Lab-Manual-CEC
BUFFER.V
module buff(a,y);
input a;
output y;
reg y;
always@(a)
begin
y=a;
end
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
BUFFER_TB.V
module bufft;
reg p;
wire q;
buff buf_t(.a(p),.y(q));
initial
begin
$display($time,"simulation starts");
p=1'b0;
#5 p=1'b1;
#5 $display("\n");
end
initial
#20 $finish;
initial
$monitor($time,"p_in=%b,q_out=%b",p,q);
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
TRANSMISSIONGATE.V
module trang(a,b,c,d);
input a,b,d;
output c;
reg c;
always@(a,b,d)
begin
d=~b;
if(b==1 & d==0)
c=a;
else
c=1'b0;
end
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
TRANSMISSION_TB
module trangt;
reg p,q,s;
wire r;
trang trans(.a(p),.b(q),.d(s),.c(r));
initial
begin
$display($time,"\t simulation starts");
p=1'b0;q=1'b0;s=1'b1;
#5 p=1'b0;q=1'b1;s=1'b0;
#5 p=1'b1;q=1'b0;s=1'b1;
#5 p=1'b1;q=1'b1;s=1'b0;
#5 $display("\n");
end
initial
#30 $finish;
initial
$monitor($time,"p_in=%b,q_ctrl=%b,s_ctrl2=%b,r_out=%b",p,q,s,r);
endmodule
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ALLBASICGATE.V
module abg1(a,b,c,d,e,f,g,h);
input a,b;
output c,d,e,f,g,h;
reg c,d,e,f,g,h;
always@(a,b)
begin
c=a&b;
d=a|b;
e=a^b;
f=~(a&b);
g=~(a|b);
h=~(a^b);
end
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ALLBASICGATE_TB.V
module abg1t;
reg p,q;
wire r_and,s_or,t_xor,u_nand,v_nor,w_xnor;
abg1 a_b_g_t(.a(p),.b(q),.c(r_and),.d(s_or),.e(t_xor),.f(u_nand),.g(v_nor),.h(w_xnor));
initial
begin
$display($time,"\t simulation starts");
p=1'b0;q=1'b0;
#10 p=1'b0;q=1'b1;
#10 p=1'b1;q=1'b0;
#10 p=1'b1;q=1'b1;
#5 $display("\n");
end
initial
#60 $finish;
initial
$monitor($time,"p=%b,q=%b,r_and=%b,s_or=%b,t_xor=%b,u_nand=%b,v_nor=%b,w_xnor=%b",p,q,r_and,s_or,t_xor
,u_nand,v_nor,w_xnor);
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
FULLADDER.V
module fulladd(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
reg sum,cout;
always@(a,b,cin)
begin
sum=a^b^cin;
cout=(a&b)|(b&cin)|(cin&a);
end
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
SERIALADDER.V
module serialadd(asa,bsa,sumsa,coutsa);
input [3:0] asa,bsa;
inout [3:0] sumsa;
inout coutsa;
reg [3:0] sumsa;
reg coutsa;
wire [2:0] c;
fulladd fa0(.a(asa[0]),.b(bsa[0]),.cin(1'b0),.sum(sumsa[0]),.cout(c[0]));
fulladd fa1(.a(asa[1]),.b(bsa[1]),.cin(c[0]),.sum(sumsa[1]),.cout(c[1]));
fulladd fa2(.a(asa[2]),.b(bsa[2]),.cin(c[1]),.sum(sumsa[2]),.cout(c[2]));
fulladd fa3(.a(asa[3]),.b(bsa[3]),.cin(c[2]),.sum(sumsa[3]),.cout(coutsa));
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
SERIALADDER_TB.V
module saddtest;
reg [3:0] at,bt;
wire [3:0] sumt;
wire coutt;
serialadd sa_t(.asa(at),.bsa(bt),sumsa(sumt),coutsa(coutt));
initial
begin
at=4'b1000; bt=4'b1001;
#10 at=4'b1110; bt=4'b1010;
#5 $display("\n");
end
initial
#30 $finish;
initial
$monitor($time,"at=%b,bt=%b,sumt=%b,coutt=%b",at,bt,sumt,coutt);
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
PARALLELADDER.V
module pad(x,y,z,cin,cout);
input [3:0] x,y;
input cin;
inout [3:0] z;
inout cout;
wire p3,g3,p2,g2,p1,g1,p0,g0,m1,m2,m3,m4,m6,m7,m8,m10,m11,m13,c3,c2,c1;
//Stage1
xor xor1(p3,x[3],y[3]);
and a1(g3,x[3],y[3]);
xor xor2(p2,x[2],y[2]);
and a2(g2,x[2],y[2]);
xor xor3(p1,x[1],y[1]);
and a3(g1,x[1],y[1]);
xor xor4(p0,x[0],y[0]);
and a4(g0,x[0],y[0]);
//Stage2
and a5(m1,cin,p3,p2,p1,p0);
and a6(m2,p3,p2,p1,g0);
and a7(m3,p3,p2,g1);
and a8(m4,p3,g2);
and a9(m6,p0,p1,p2,cin);
and a10(m7,p0,p1,p2);
and a11(m8,p2,g1);
and a12(m10,p1,p0,cin);
and a13(m11,p1,g0);
and a14(m13,p0,cin);
//Stage3
or or1(cout,m1,m2,m3,m4,g3);
or or2(c3,m6,m7,m8,g2);
or or3(c2,m10,m11,g1);
or or4(c1,m13,g0);
//Stage4
xor xor5(z[3],c3,x[3],y[3]);
xor xor6(z[2],c2,x[2],y[2]);
xor xor7(z[1],c1,x[1],y[1]);
xor xor8(z[0],cin,x[0],y[0]);
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
PARALLELADDER_TB.V
module paddtest;
reg [3:0] at,bt;
reg cint;
wire [3:0] sumt;
wire coutt;
pad sa_t(.x(at),.y(bt),.cin(cint),.z(sumt),.cout(coutt));
initial
begin
at=4'b1000; bt=4'b1001;cint=1'b0;
#10 at=4'b1110; bt=4'b1010;
#5 $display("\n");
end
initial
#30 $finish;
initial
$monitor($time,"at=%b,bt=%b,cint=%b,sumt=%b,coutt=%b",at,bt,cint,sumt,coutt);
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
SRFILP.V
module srf(s,r,clk,rst,q,q_bar);
input s,r,clk,rst;
output q,q_bar;
reg q,q_bar;
always@(posedge clk)
begin
if(rst==0)
q=0;
else
begin
if(s==0 & r==0)
q=q;
else if(s==0 & r==1)
q=1'b0;
else if(s==1 & r==0)
q=1'b1;
else
q=1'bZ;
end
q_bar=~q;
end
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
SRFLIP_TB.V
module srfftest;
reg a,b,c,d;
wire m_q,n_q_bar;
srf srf_t(.s(a),.r(b),.clk(c),.rst(d),.q(m_q),.q_bar(n_q_bar));
initial
begin
c=1'b1;
d=1'b0;
end
always
#5 c=~c;
initial
begin
a=1'b0;b=1'b0;d=1'b1;
#10 a=1'b0;b=1'b1;
#10 a=1'b1;b=1'b0;
#10 a=1'b1;b=1'b1;
#5 $display("\n");
end
initial
#60 $finish;
initial
$monitor($time, "clock=%b,rst=%b , s=%b , r=%b , q=%b , q_bar=%b",c,d,a,b,m_q,n_q_bar);
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DFLIP.V
module df(d,clk,rst,q,q_bar);
input d,clk,rst;
output q,q_bar;
reg q,q_bar;
begin
if(rst==0)
q=1'bZ;
else
q=d;
q_bar=~q;
end
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DFLIP_TB.V
module dfftest;
reg a,c,r;
wire m_q,n_q_bar;
df df_t(.d(a),.clk(c),.rst(r),.q(m_q),.q_bar(n_q_bar));
initial
c=1'b1;
always
#5 c=~c;
initial
begin
a=1'b0;r=1'b0;
#10 a=1'b0;r=1'b1;
#10 a=1'b1;
#5 $display("\n");
end
initial
#40 $finish;
initial
$monitor($time, "clock = %b ,rst = %b ,d = %b , q = %b , q_bar = %b",c,r,a,m_q,n_q_bar);
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
JKFLIP.V
module jkf(j,k,clk,rst,q,q_bar);
input j,k,clk,rst;
output q,q_bar;
reg q,q_bar;
begin
if(rst==0)
q=1'bZ;
else
begin
if(j==0 & k==0)
10
q=q;
else if(j==0 & k==1)
q=1'b0;
else if(j==1 & k==0)
q=1'b1;
else
q=~q;
end
q_bar=~q;
end
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
JKFLIP_TB.V
module jkfftest;
reg a,b,c,d;
wire m_q,n_q_bar;
jkf jkf_t(.j(a),.k(b),.clk(c),.rst(d),.q(m_q),.q_bar(n_q_bar));
initial
c=1'b1;
always
#5 c=~c;
initial
begin
a=1'b0;b=1'b0;d=1'b0;
#10 a=1'b0;b=1'b0;d=1'b1;
#10 a=1'b0;b=1'b1;
#10 a=1'b1;b=1'b0;
#10 a=1'b1;b=1'b1;
#10 a=1'b1;b=1'b1;
#5 $display("\n");
end
initial
#60 $finish;
initial
$monitor($time, "clock = %b ,rst = %b ,j = %b , k = %b , q = %b , q_bar = %b",c,d,a,b,m_q,n_q_bar);
endmodule
11
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
TFLIP.V
module tf(t,clk,rst,q,q_bar);
input t,clk,rst;
output q,q_bar;
reg q,q_bar;
begin
if(rst==0)
q=1'b0;
else
begin
if(t==1'b1)
q=~q;
else
q=q;
end
q_bar=~q;
end
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
TFLIP_TB.V
module tfftest;
reg a,c,r;
wire m_q,n_q_bar;
tf tf_t(.t(a),.clk(c),.rst(r),.q(m_q),.q_bar(n_q_bar));
initial
c=1'b1;
always
#5 c=~c;
initial
begin
a=1'b0;r=1'b0;
#10 a=1'b0;r=1'b1;
#10 a=1'b1;
#10 a=1'b1;
12
#10 a=1'b1;
#5 $display("\n");
end
initial
#60 $finish;
initial
$monitor($time, "clock = %b ,rst = %b ,t = %b , q = %b , q_bar = %b",c,r,a,m_q,n_q_bar);
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DFLIP.V
module df(d,clk,rst,q,q_bar);
input d,clk,rst;
output q,q_bar;
reg q,q_bar;
begin
if(rst==0)
q=1'bZ;
else
q=d;
q_bar=~q;
end
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MSFLIP.V
module msf(ms,clkms,rstms,qms);
input ms,clkms,rstms;
inout qms;
reg qms;
wire w;
df d_master(.d(ms),.clk(clkms),.rst(rstms),.q(w));
df d_slave(.d(w),.clk(~clkms),.rst(rstms),.q(qms));
endmodule
13
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MSFLIP_TB.V
module msftest;
reg a,c,r;
wire m_q;
msf msf_t(.ms(a),.clkms(c),.rstms(r),.qms(m_q));
initial
c=1'b1;
always
#5 c=~c;
initial
begin
a=1'b0;r=1'b0;
#10 a=1'b0;r=1'b1;
#10 a=1'b1;
#5 $display("\n");
end
initial
#30 $finish;
initial
$monitor($time, "clock = %b ,rst = %b ,ms = %b , q = %b ",c,r,a,m_q);
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ASYNCUDCNT.V
module asudc(clkaud,rstaud,count);
input clkaud,rstaud;
inout [3:0] count;
reg [3:0] count;
tf aud_tf0(.t(1'b1),.clk(clkaud),.rst(rstaud),.q(count[0]));
tf aud_tf1(.t(count[0]),.clk(clkaud),.rst(rstaud),.q(count[1]));
endmodule
14
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ASYNCUDCNT_TB.V
module asudct;
reg c,r;
wire [3:0] m_count;
asudc asudc_t(.clkaud(c),.rstaud(r),.count(m_count));
initial
c=1'b0;
always
#5 c=~c;
initial
begin
r=1'b0;
#10 r=1'b1;
end
initial
#100 $finish;
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
SYNCUDCNT.V
module synupdncntr(clk,rst,ud,count);
input clk,rst,ud;
output [3:0] count;
reg [3:0] count;
always@(posedge clk or posedge rst)
begin
if(rst)
count=4'b0000;
else
if(ud)
count=count+1;
else
count=count-1;
end
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
15
SYNCUDCNT_TB.V
module synupdncntr_test;
reg a_ud,c,r;
wire [3:0] m_count;
synupdncntr sudc_t(.ud(a_ud),.clk(c),.rst(r),.count(m_count));
initial
c=1'b0;
always
#5 c=~c;
initial
begin
a_ud=1'b1;r=1'b1;
#10 r=1'b0;
#100 a_ud=1'b0;r=1'b1;
#10 r=1'b0;
end
initial
#200 $finish;
initial
begin
$display("\n\t Synchronous up down counter");
$display("\n\t rst|up/down|count\t\t\tup -> 1 down -> 0");
$monitor($time,"\t%b| %b |%b",r,a_ud,m_count);
end
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
SAR_REG.V
module sar(clk,rst,a_gt_d,digi_out);
input clk,rst,a_gt_d;
output [3:0] digi_out;
reg [3:0] digi_out;
begin
if(rst)
digi_out=4'b0000;
else
if(a_gt_d)
16
digi_out=digi_out+1'b1;
else
digi_out=digi_out-1'b1;
end
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
SAR_REG_TB.V
module sart;
reg a_gt_d1,c,r;
wire [3:0] m_digi_out;
sar sar_t(.a_gt_d(a_gt_d1),.clk(c),.rst(r),.digi_out(m_digi_out));
initial
c=1'b0;
always
#5 c=~c;
initial
begin
$diplay($time,"\t Simulation starts");
a_gt_d1=1'b0;r=1'b1;
#10 a_gt_d1=1'b0;r=1'b0;
#60 a_gt_d1=1'b1;
end
initial
#120 $finish;
initial
$monitor($time,"analog>digital=%b,reset=%b,clock=%b,digital_output=%b",a_gt_d1,r,c,m_digi_out);
endmodule
17
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
SAR_REG2.V
// ADC controller
module controller(clk,go,valid,result, sample,value,cmp);
input
clk; // clock input
input
go; // go=1 to perform conversion
output
valid; // valid=1 when conversion finished output [7:0] result; // 8 bit
result output
output
sample; // to S&H circuit output [7:0] value; // to DAC
input
cmp; // from comparitor
reg
[1:0] state; // current state in state machine reg
test in binary search
reg
[7:0] result; // hold partially converted result
[7:0] mask; // bit to
// state assignment
parameter
sWait=0, sSample=1, sConv=2, sDone=3;
// synchronous design
always @(posedge clk) begin
if (!go) state <= sWait; // stop and reset if go=0
else case (state)
// choose next state in state machine sWait
: state <= sSample;
sSample :
begin
// start new conversion so state <= sConv;
//
enter convert state next mask
<= 8b10000000; // reset mask to MSB only result <=
8b0;
// clear result
end sConv
:
begin
// set bit if comparitor indicates input larger than
// value currently under consideration, else leave bit clear if (cmp) result <= result |
mask;
// shift mask to try next bit next time mask <= mask>>1;
// finished once LSB has been done if (mask[0]) state <= sDone;
end
sDone
:;
endcase end
assign sample = state==sSample;
// drive sample and hold
18
assign value
assign valid
endmodule
= result | mask;
= state==sDone;
// (result so far) OR (bit to try)

// indicate when finished
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
SAR_REG2_TB.V
module testbench();
// registers to hold inputs to circuit under test, wires for outputs reg clk,go;
wire valid,sample,cmp;
wire [7:0] result;
wire [7:0] value;
// instance controller circuit
controller c(clk,go,valid,result, sample,value,cmp);
// generate a clock with period of 20 time units always begin
#10;
clk=clk;
end
initial clk=0;
// simulate analogue circuit with a digital model reg [7:0] hold;
always @(posedge sample) hold = 8b01000110;
assign cmp = ( hold >= value);
// monitor some signals and provide input stimuli initial begin
$monitor($time, " go=%b valid=%b result=%b sample=%b value=%b cmp=%b
state=%b mask=%b", go,valid,result,sample,value,cmp,c.state,c.mask);
#100; go=0;
#100; go=1;
#5000; go=0;
#5000; go=1;
#40;
go=0;
#5000;
$stop;
end
endmodule
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
19
1.3
V(VOUT)
1.2
1.1
1.0
0.9
0.8
Voltage (V)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
0.0
0.2
0.4
0.6
0.8
Voltage (V)
1.0
1.1
1.0
V(VIN)
0.9
Voltage (V)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
1.6
V(VOUT)
1.4
1.2
Voltage (V)
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
0.0
.0N
10.0N
20.0N
30.0N
Time (s)
40.0N
2.52
V(VOUT)
2.50
2.48
2.46
Voltage (V)
2.44
2.42
2.40
2.38
2.36
2.34
2.32
0.0
0.4
0.8
1.2
1.6
Voltage (V)
2.0
db(V(VOUT))
0.2
cphase(V(VOUT))
-0.2
-0.6
-1.0
Phase (degrees)
Magnitude (dB)
-1.766
-1.768
-1.770
-1.772
-1.774
-1.776
-1.778
-1.780
-1.782
-1.784
-1.786
-1.788
-1.790
-1.792
-1.4
-1.8
-2.2
-2.6
-3.0
1.0
10.0
100.0
1.0K 10.0K
Frequency (Hz)
10.0M
Voltage (V)
2.506
2.505
2.504
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
2.495
2.494
V(VIN)
2.330
2.329
V(VOUT)
Voltage (V)
2.328
2.327
2.326
2.325
2.324
2.323
2.322
2.321
0.0U
0U
10.0U
20.0U
Time (s)
30.0U
40.0U
1.2
V(VOUT)
1.0
0.8
0.6
0.4
Voltage (V)
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
0.0
0.2
0.4
0.6
0.8
Voltage (V)
1.0
40.5
db(V(VOUT))
40.0
39.5
39.0
Magnitude (dB)
38.5
38.0
37.5
37.0
36.5
36.0
35.5
35.0
185.0
180.0
cphase(V(VOUT))
175.0
170.0
165.0
Phase (degrees)
160.0
155.0
150.0
145.0
140.0
135.0
130.0
125.0
120.0
1.0
10.0
100.0
1.0K
10.0K
Frequency (Hz)
10.0M
Voltage (V)
Voltage (V)
702.0M
701.8M
701.6M
701.4M
701.2M
701.0M
700.8M
700.6M
700.4M
700.2M
700.0M
699.8M
699.6M
V(VIN)
520.0M
500.0M
480.0M
460.0M
440.0M
420.0M
400.0M
380.0M
360.0M
340.0M
320.0M
300.0M
V(VOUT)
0.0U
0U
100.0U
200.0U
Time (s)
300.0U
400.0U
1.3
V(VOUT2)
1.2
1.1
1.0
Voltage (V)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Voltage (V)
0.7
0.8
0.9
1.0
1.1
1.2
58.0
56.0
db(V(VOUT2))
54.0
Magnitude (dB)
52.0
50.0
48.0
46.0
44.0
42.0
40.0
38.0
36.0
34.0
32.0
190.0
cphase(V(VOUT2))
180.0
170.0
Phase (degrees)
160.0
150.0
140.0
130.0
120.0
110.0
100.0
90.0
80.0
70.0
1.0
3 4
10.0
20
40
100.0
200
400
1.0K
3 4
10.0K
Frequency (Hz)
20
40
100.0K
200
400
1.0MEG
3 4
10.0M
Voltage (V)
Voltage (V)
Voltage (V)
750.5M
750.4M
750.3M
750.2M
750.1M
750.0M
749.9M
749.8M
749.7M
749.6M
749.5M
V(VIN1)
750.5M
750.4M
750.3M
750.2M
750.1M
750.0M
749.9M
749.8M
749.7M
749.6M
749.5M
V(VIN2)
950.0M
900.0M
850.0M
800.0M
750.0M
700.0M
650.0M
600.0M
550.0M
500.0M
V(VOUT2)
0.0U
.0U
50.0U
100.0U
150.0U
200.0U
250.0U
Time (s)
300.0U
350.0U
400.0U
450.0U
500.0U
95.0
db(V(VOUT))
90.0
85.0
80.0
Magnitude (dB)
75.0
70.0
65.0
60.0
55.0
50.0
45.0
40.0
200.0
cphase(V(VOUT))
180.0
160.0
Phase (degrees)
140.0
120.0
100.0
80.0
60.0
40.0
20.0
1.0
10.0
100.0
1.0K
10.0K
Frequency (Hz)
100.0K
10.0M
750.0012M
V(VIN1)
750.0010M
750.0008M
750.0006M
750.0004M
750.0000M
749.9998M
749.9996M
749.9994M
749.9992M
749.9990M
749.9988M
430.0M
V(VOUT)
425.0M
420.0M
415.0M
410.0M
405.0M
Voltage (V)
Voltage (V)
750.0002M
400.0M
395.0M
390.0M
385.0M
380.0M
375.0M
370.0M
365.0M
360.0M
0.0M
.0M
0.2M
0.4M
0.6M
Time (s)
0.8M
1.2
V(VOUT)
1.1
1.0
0.9
0.8
Voltage (V)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
0.0
.0N
20.0N
40.0N
Time (s)
60.0N

10ECL77 - VLSI Lab Manual CEC

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10ECL77 - VLSI Lab Manual CEC

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DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

VLSI LAB PROGRAMS PART A

[7:0] mask; // bit to

// drive sample and hold

// (result so far) OR (bit to try)

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