Interrupt Signal

SID

SOD

Interrupt Control

Serial I/O Control

Accumulator

Temporary Register

Status Flags

Instruction Register

B D H SP PC

C E L

ALU

Instruction Decoder

Timing and Control Unit

Incrementor / Decrementor

Clock

Control

Signals

Address Buffer

Data Buffer

A8 A15 AD7 Address Bus Bus

ADO Address/ Data

CONTROL WORD
According to the requirement a port cab be programmed to act either as an input port or an output port. The bits of the control word case as shown in figure. Control word is written into control word register, which is within 8255. No read operation of the control word register is allowed. If a particular port is to be make input port, the bit corresponding to that port is set to one. For making a port an output port, the corresponding bit for the port is set to zero.

Bit No.

Control Word Bit Port C Lower Input=1, Output=0 Port B Input=1, Output=0 Mode Selection For Mode B Port C Upper Input=1, Output=0 I/O Port = 1 BSR = 0 Mode Selection for Port A Port A Input=1, Output=0
63

CIRCUIT TO SENSE THE O/P (BELL CIRCUIT)

The circuit, which is used for bell is as shown in figure. Transistor BC547 have been uses to act as NOT gate and input from pin no. 21 of 8255 is given to its base When the voltage at port no.21 is high, Transistor T1 outputs goes low which energies the relay, which is connected to 5V battery. Relay is connected to the step down transformer, which is connected to 220V. As relay get energized 220V AC is applied to this transformer and we will get a output of around 3V which will then drives the bell system using UM66 and BC547 transistor. Speaker

~ ~
N/C +5V Power Supply In N/O

UM 66
3 2 4 GND 1 Out 1 K

T2

Relay Coil 2 K

From Pin 21 of 8255

T1

Transistor

IC

BC 547
1

UM-66
2 3

E 65

Out

+Vcc

GND

X1 X2 RESET OUT SOD SID TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Vss

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8085A

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

Vcc HOLD HLDA CLK (OUT) RESET IN READY IO/M S1 RD WR ALE S0 A15 A14 A13 A12 A11 A10 A9 A8

8085 PINOUT

PIN CONFIGURATION PC3 PC4 TIMER IN RESET PC5 TIMER OUT IO/M CE RD WR ALE AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

8155 PINOUT

Port A IO/M AD0-7 CE ALE B RD WR C RESET Timer CLK TIMER OUT TIMER Port C 6 PC0-5 Port B 8 PB0-7 256 X 8 STATIC RAM A 8 PA0-7

Vcc (+5V) Vss (0V)

Block diagram

41

PIN CONFIGURATION RL2 RL3 CLK IRQ RL4 RL5 RL6 RL7 RESET RD WR DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8279 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc RL1 RL0 CNTL/STB SHIFT SL3 SL2 SL1 SL0 OUT B0 OUT B1 OUT B2 OUT B3 OUT A0 OUT A1 OUT A2 OUT A3 BD CS A0

8279 PINOUT

DB0-7 CLK RESET CS RD WR A0 IRO SL0-3 RL0-7 SHIFT CNTL/STB OUT A0-3 OUT B0-3 BD

I/O I I I I I I O O I I I O O O

Data Bus (Bidirectional) Clock Input Reset Input Chip Select Read Input Write Input Buffer Address Interrupt Request Output Scan Lines Return Lines Shift Input Control Strobe Input Display (A) Outputs Display (B) Outputs Blank Display Output Logic System

IRQ

RL0-7

DATA BUS SHIFT RD CNTL/STB WR

Key Data

CPU Interface

CS SL0-3 A0 OUT A0-3 RESET OUT B0-3 CLK BD

Scan

Display Data

Port A Cu 8255A CL Port B Port C

8255A Ports

Control Word
D7 D6 D5 D4 D3 D2 D1 D0 0/1

BSR Mode (Bit Set/Reset) No effect on I/O Mode Mode 0 Simple I/O for ports A, B and C Mode 1 Handshake I/O for ports A and/or B Port C bits are used for handshake Mode 2 Bidirectional data bus for port A Port B either in Mode 0 or 1 Port C bits are used for handshake

The 8255A Modes

46

PIN CONFIGURATION PA3 PA2 PA1 PA0 RD CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB PB2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8255A 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PA4 PA5 PA6 PA7 WR RESET D0 D1 D2 D3 D4 D5 D6 D7 VCC PB7 PB6 PB5 PB4 PB3

8255 PINOUT
PIN NAMES D7 D0 RESET CS RD WR A0, A1 PA7 PA0 PB7 PB0 PC7 PC0 Vcc GND Data Bus(Bidirectional) Reset Input Chip Input Read Input Write Input Port Address Port A (Bit) Port B (Bit) Port C (Bit) + 5 Volts 0 Volts
Group A Port A (8) I/O PA7-PA0

Power Supplier

+5V GND

Group A Control

Bidirectional Data Bus D7-D0 Data Bus Buffer 8Bit Internal Data Bus

Group A Port C Upper (4)

I/O PC7-PC4

Group B Port C Lower (4)

I/O PC3-PC0

RD WR A1 A0 RESET Read Write Control Logic Group B Control Group B Port B (8) I/O PB7-PB0

8255A BLOCK DIAGRAM

CS 49

RD WR Port A 00 RD WR Control Register EN 10 WR Port C EN EN

Internal Decoding A1 A0

11 10
01 00

RD
WR

Port B 01 EN

EXPENDED VERSION OF THE CONTROL LOGIC AND I/O PORT

50

PIN CONFIGURATION D7 D6 D5 D4 D3 D2 D1 D0 CLK0 OUT0 GATE0 GND 1 2 3 4 5 6 7 8 9 10 11 12 8253 24 23 22 21 20 19 18 17 16 15 14 13 Vcc WR RD CS A1 A0 CLK 2 OUT 2 GA TE 2 CLK 1 GATE 1 OUT A

8253 PINOUT
PIN NAMES D7 D0 CLK N GATE N OUT N RD WR CS A0 A1 Vcc GND Data Bus (8 Bit) Counter Clock Inputs Counter Gate Inputs Counter Outputs Read Counter Write Command or Data Chip Select Counter Select +5 Volts Ground

CLK 0 D7 D0 8 Data Bus Buffer Counter =0 GATE 0 OUT 0

RD WR A0 A1 CS Control Word Register Read Write Logic Counter =1

CLK 1 GATE 1 OUT 0

CLK 2 Counter =2 CLK 2 OUT 2

Internal Bus 8253 BLOCK DIAGRAM