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PD60046-S
Product Summary
VOFFSET IO+/VOUT ton/off (typ.) Deadtime (typ.) 600V max. 130 mA / 270 mA 10 - 20V 680 & 150 ns 520 ns
Packages
Description
The IR2104(S) are high voltage, high speed power 8 Lead SOIC MOSFET and IGBT drivers with dependent high and low 8 Lead PDIP IR2104S side referenced output channels. Proprietary HVIC and IR2104 latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates from 10 to 600 volts.
Typical Connection
up to 600V VCC
VCC
IN SD
VB HO VS LO
TO LOAD
IN SD COM
(Refer to Lead Assignment for correct pin configuration) This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
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Symbol
VB VS VHO VCC VLO VIN dVs/dt PD RthJA TJ TS TL
Definition
High side floating absolute voltage High side floating supply offset voltage High side floating output voltage Low side and logic fixed supply voltage Low side output voltage Logic input voltage (IN & SD ) Allowable offset supply voltage transient Package power dissipation @ TA +25C Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) (8 lead PDIP) (8 lead SOIC) (8 lead PDIP) (8 lead SOIC)
Min.
-0.3 VB - 25 VS - 0.3 -0.3 -0.3 -0.3 -55
Max.
625 VB + 0.3 VB + 0.3 25 VCC + 0.3 VCC + 0.3 50 1.0 0.625 125 200 150 150 300
Units
V/ns W C/W
Symbol
VB VS VHO VCC VLO VIN TA
Definition
High side floating supply absolute voltage High side floating supply offset voltage High side floating output voltage Low side and logic fixed supply voltage Low side output voltage Logic input voltage (IN & SD ) Ambient temperature
Min.
VS + 10 Note 1 VS 10 0 0 -40
Max.
VS + 20 600 VB 20 VCC VCC 125
Units
Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip DT97-3 for more details).
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Symbol
ton toff tsd tr tf DT MT
Definition
Turn-on propagation delay Turn-off propagation delay Shutdown propagation delay Turn-on rise time Turn-off fall time Deadtime, LS turn-off to HS turn-on & HS turn-on to LS turn-off Delay matching, HS & LS turn-on/off
Symbol
VIH VIL VSD,TH+ VSD,THVOH VOL ILK IQBS IQCC IIN+ IINVCCUV+ VCCUVIO+ IO-
Definition
Logic 1 (HO) & Logic 0 (LO) input voltage Logic 0 (HO) & Logic 1 (LO) input voltage SD input positive going threshold SD input negative going threshold High level output voltage, VBIAS - VO Low level output voltage, VO Offset supply leakage current Quiescent VBS supply current Quiescent VCC supply current Logic 1 input bias current Logic 0 input bias current VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold Output high short circuit pulsed current Output low short circuit pulsed current
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HV LEVEL SHIFT
Q PULSE FILTER R S VS HO
IN PULSE GEN
UV DETECT VCC
SD
LO
COM
Lead Definitions
Symbol Description
IN Logic input for high and low side gate driver outputs (HO and LO), in phase with HO Logic input for shutdown High side floating supply High side gate drive output High side floating supply return Low side and logic fixed supply Low side gate drive output Low side return
SD VB
HO VS VCC LO COM
Lead Assignments
1 2 3 4 VCC IN SD COM VB HO VS LO
8
7 6 5
1 2 3 4
VCC IN SD COM
VB HO VS LO
8
7 6 5
8 Lead PDIP
8 Lead SOIC
IR2104 4
IR2104S www.irf.com
IN
IN(LO)
50% 50%
SD
IN(HO)
ton tr 90% toff 90% tf
HO LO
LO HO
Figure 1. Input/Output Timing Diagram
10%
10%
50%
50%
SD
50%
IN
tsd
90%
HO LO
90%
HO
DT
10% DT
LO
Figure 3. Shutdown Waveform Definitions
90%
10%
IN (HO)
LO
HO
10%
MT 90%
MT
LO
HO
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1 20 0 1 00 0
M a x.
8 00 6 00 4 00 2 00 0 -50 -25 0 25 50 75 1 00 1 25
Temperature (C)
T yp .
5 00 4 00 3 00 2 00 1 00 T yp . 0 M ax .
-50
-25
25
50
75
1 00
1 25
Temperature (C)
500
1000 Turn-Off Delay Time (ns 800 600 400 200 Typ 0
10 12 14 16 18 20
Ma x .
10
12 14
16 18
20
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500
Shutdown Delay Time (ns)
T y p.
Temperature (C)
500
500
M ax.
Temperature (C)
200
15 0
50 Typ. 0 10 12 14 16 18 20
Temperature (C)
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Deadtime (ns)
Deadtime (ns)
Temperature (C)
Mi n.
Mi n.
Figure 12A. Logic "1" (HO) & Logic 0 (LO) & Inactive SD Input Voltage vs Temperature
4 3.2 2.4 1.6 Max . 0.8 0 -50
Figure 12B. Logic "1" (HO) & Logic 0 (LO) & Inactive SD Input Voltage vs Voltage
4 3 .2 I nputV ol ta g e (V ) 2 .4 1 .6 M ax. 0 .8 0
-25
25
50
75
100
125
10
12
14
16
18
20
Temperature (C)
Figure 13A. Logic "0" (HO) & Logic 1 (LO) & Active SD Input Voltage vs Temperature
Figure 13B. Logic "0" (HO) & Logic 1 (LO) & Active SD Input Voltage vs Voltage
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0 .8 0 .6 0 .4 0 .2 0 10 12 14 16 18 20 M ax.
Temperature (C)
0 .8 0 .6 0 .4 0 .2 0 -5 0 -2 5 0 25 50 75 100 125
0 .8 0 .6 0 .4 0 .2 M ax. 0 10 12 14 16 18 20
M ax.
Temperature (C)
500 400 300 200 100 0 0 100 200 300 400 500 600
Max.
Temperature (C)
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1 20 90 60 M ax . 30 T yp . 0 -50 -25 0 25 50 75 1 00 1 25
120 90 60 30 Ty p. 0 10 12 14 16 18 20
Max .
Temperature (C)
600 500 400 300 200 100 0 -5 0 -2 5 0 25 50 75 100 125 Typ. M ax.
Temperature (C)
30
25 20 15 10 5 0 10 12 14 16 18 20 M ax. Typ.
Temperature (C)
10
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5 4 3 2 Max. 1 0
4 3 2 Max. 1 0 -50
-25
25 50 75 Temperature (C)
100
125
10
12
20
Typ. Mi n.
Min.
0 -50
-25
25 50 75 Temperature (C)
100
125
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11
7 00
Output Sink Current (mA) Output Sink Current (mA)
70 0 60 0 50 0 40 0 30 0 20 0 Mi n. 10 0 0
-50 -25 0 25 50 75 1 00 1 25
6 00 5 00 4 00 3 00 Mi n. 2 00 1 00 0
Temperature (C)
T yp .
Ty p.
10
12
14
16
18
20
Case Outlines
8 Lead PDIP
12
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D A 5
B
FOOTPRINT 8X 0.72 [.028]
DIM A b c D
INCHES MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00
A1 .0040
6 E
5 H 0.25 [.010] A
E
6.46 [.255]
e e1 H K L
8X 1.78 [.070]
.050 BASIC .025 BASIC .2284 .0099 .016 0 .2440 .0196 .050 8
1.27 BASIC 0.635 BASIC 5.80 0.25 0.40 0 6.20 0.50 1.27 8
6X
e e1
3X 1.27 [.050]
A C 0.10 [.004] y
K x 45
8X b 0.25 [.010]
A1 C A B
8X L 7
8X c
NOTES: 1. DIMENSIONING & TOLERANC ING PER ASME Y14.5M-1994. 2. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INC HES]. 4. OUTLINE C ONFORMS TO JEDEC OUTLINE MS-012AA.
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006]. 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE.
8 Lead SOIC
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Date code
Pin 1 Identifier ? P MARKING CODE Lead Free Released Non-Lead Free Released
ORDER INFORMATION
Basic Part (Non-Lead Free) 8-Lead PDIP IR2104 order IR2104 8-Lead SOIC IR2104S order IR2104S
Leadfree Part 8-Lead PDIP IR2104 order IR2104PbF 8-Lead SOIC IR2104S order IR2104SPbF
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 This product has been qualified per industrial level Data and specifications subject to change without notice. 4/2/2004
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