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<XR_PAGE_TITLE>

CK
APPD

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.


2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

REV

ZONE

ECN

DESCRIPTION OF CHANGE

279015

ENGINEERING RELEASED

DATE

06/06/03 ?

Q59 MLB
CONFIG A,B,C

D
1
2,3
4,5
6,7
8
9
10-11
12
13
14-15
16
17
18
19
20-21
22-23
24-25
26-27
28
29
30
31
32
33
34
35
36
37
38
39
40-41
42-43
44
45-51
52-59
60-64
65-69

ENG
APPD

DATE
01

TABLE OF CONTENTS

PAGE

COVER PAGE
BLOCK DIAGRAM, SYSTEM, POWER & PCB INFO
MPC7450 MAXBUS
CPU SPEED & CONFIG OPTIONS
CPU LA CONNECTORS, ESP, CPU BYPASS
INTREPID MAX IF (SECTION 1)
INTREPID POWER & BYPASS (SECTION 8 & 9)
INTREPID DDR CONTROL
DDR MUXES
SO-DIMM, BIG DIMM
INTREPID AGP (SECTION 3)
NVIDIA AGP (SECTION 1)
NVIDIA FRAME BUFFER (SECTIONS 3 & 4)
NVIDIA FB SERIES TERMS, CLK DELAYS
GRAPHICS MEMORIES
NVIDIA DAC/DVI, CLOCKS & STRAPS (SECTIONS 2 & 5)
TMDS & EXTERNAL VGA CONNECTORS
NVIDIA POWER-ON RESET CONFIGURATION STRAPS
INTREPID GPIOS, INTERRUPTS & SERIAL PORTS (SECTION 6)
MODEM, BLUETOOTH, KITCHEN SINK & SERIAL DOWNLOAD
INTREPID PCI, ROM (SECTION 7)
WIRELESS PCI
USB2 CONTROLLER
USB POWER & CONNECTORS
INTREPID ETHERNET & FIREWIRE (SECTION 4)
ETHERNET PHY
FIREWIRE PHY
INTREPID UATA/IDE (SECTION 5)
ATA CD/HD CONNECTORS
AUDIO CODEC & VOLTAGE REGS
LINE IN/OUT BUFFERS
SPEAKER/MIC AMPS
POWER MANAGER UNIT
+5V/+12V, AUDIO, FW & TMDS POWER CONVERTERS
CONSTRAINT TABLES
NET TABLES
PART TABLES

LAST_MODIFIED=Mon Oct 27 12:25:21 2003

POWER RAIL DEFINITIONS


RUN SLEEP SHUTDOWN
+2_5V_MAIN
ON
OFF
ON
+3V_MAIN
ON
ON
OFF
+5V_MAIN
OFF
ON
ON
+5V_SLEEP
OFF
ON
OFF
+12V_MAIN
ON
ON
ON
+12V_SLEEP
OFF
ON
OFF
FW_PWR
ON
OFF
ON
+1.8V_SLEEP
OFF
ON
OFF
+MAXBUS_SLEEP
ON
OFF
OFF

SCHEMATIC AND PCB SUPPORT


PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

051-6569

SCHEM,MLB,Q59

SCH1

CRITICAL
CRITICAL

BOM OPTION

820-1599

PCB,MLB,IMACG4.A,B,C

PCB1

CRITICAL

825-2029

LBL,SER #,BARCODE

PCB1

056-1158

DESIGN GUIDE,MCO,IMACG4

PCB1

CRITICAL

057-0085

DFM,PNLZN DWG,MLB,Q59

PCB1

CRITICAL

630-XXXX

630-XXXX,PCBA,H,Q59,EEE XXX

HYNIX

OMIT

630-XXXX

630-XXXX,PCBA,S,Q59,EEE XXX

SAMSUNG

OMIT

PCB,UL RECOGNIZED, MIN.130 DEG. C TEMP. RATING AND V-0 FLAME RATING PER UL 796
& UL 94. PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURERS UL
FILE NUMBER, UL PCB MATERIAL DESIGNATION, TEMPERATURE RATING AND FLAME RATING.

DIMENSIONS ARE IN MILLIMETERS

Apple Computer Inc.

METRIC

XX

X.XX
DRAFTER

NOTICE OF PROPRIETARY PROPERTY

DESIGN CK

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

X.XXX
ENG APPD

MFG APPD

QA APPD

DESIGNER

RELEASE

SCALE

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

ANGLES

TITLE

DO NOT SCALE DRAWING

SCHEM,MLB,Q59,ABC
NONE
SIZE

THIRD ANGLE PROJECTION

MATERIAL/FINISH
NOTED AS
APPLICABLE

DRAWING NUMBER

051-6569
SHT

REV.

A
OF

69
DRAWING

<XR_PAGE_TITLE>

FW - B
Connector
P.36

Inverter
KITCHEN
P.29

LCD Panel
Connector
P.24

FireWire
PHY
P.36

RGB

GRAPHICS
MEMORY

NVIDIA
NV18B
64MB

Ethernet
PHY
P.35

VGA
Connector
P.25

EDID (I2C)

Ethernet
Connector
P.35

VGA/SVIDEO OUT

TMDS

FW - A
Connector
P.36

P.20
(EXTERNAL MEM)

GRAPHICS
MEMORY

P.21

P.17-27

(EXTERNAL MEM)

WIRELESS
P.31

AGP BUS
1394 OHCI

1.5V/3.3V
32BITS
66MHZ

3.3V

8BIT TX/RX
32BITS

USB
CONN(QTY3)
P.31
USB

USB2
CONTROL
P.32

P.28

MODEM
BLUETOOTH
P.29

FIREWIRE

ETHERNET

400 MB/S
P.34

10/100
P.34

4X AGP
PCI
P.16

PCI BUS

P.30

INTREPID
DDR MEMORY

I2C

MAXBUS

P.12

P.34

P.9

MEMORY BUS

I2C

BOOTROM
P.30

BOOT ROM
1M X 8
P.30

MAXBUS

2.5V

167MHZ
64BITS

167MHZ
32BIT ADDRESS
64BIT DATA

PMU
P.44

APOLLO

DDR MUXES
P.13

CPU

CPU PLL
Config
P.6

P.4-5

SYSTEM BLOCK

DDR SDRAM DIMM 0

P.15

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:25:22 2003

DDR SDRAM DIMM 1


SO-DIMM Connector

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

P.14

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
2
69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

THICKNESS

COPPER

TRACE WIDTH

(MILS)
(OZ)
---------------- ------------ --------

(MILS)
--------------

LAYER
DUAL
DC/DC

+12V

(LTC3707)

5.1V

TMDS
LDO
(EZ1582)

3.65V

3.3V

USB
5.1V
(SWITCH)
FW

12V
EXTERNAL
VIDEO

(SWITCH)

5.1V

(SWITCH)

C
GRAPHIC
DC/DC
(SC2602)

1.6V

HARD
DRIVE

1 - SIGNAL-TOP
PREPREG
2 - GROUND1
PREPREG
3 - SIGNAL
FILLER
4 - POWER
PREPREG

0.7
3
1.4
3
0.7
17.4
2.8
4

0.5
--1
--0.5
--2
---

5 - POWER

2.8

---

FILLER
6 - SIGNAL
PREPREG
7 - GROUND2
PREPREG

17.4
0.7
3
1.4
3

--0.5
--1
---

8 - SIGNAL-BOTTOM

0.7

0.5

OMIT

OMIT

ZT39

ZT46

HOLE-VIA-20R10

OPTICAL
DRIVE

OMIT

ZT40

5.1V

HOLE-VIA-20R10

OMIT

ZT47
1

4
---

=============
---

OMIT

OMIT

ZT59

HOLE-VIA-20R10

OMIT

ZT64

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

OMIT

ZT54

OMIT

ZT60

HOLE-VIA-20R10

ZT65

HOLE-VIA-20R10

HOLE-VIA-20R10

(SWITCH)
OMIT

ZT41

HOLE-VIA-20R10

OMIT

ZT48

HOLE-VIA-20R10

INTREPID
DC/DC

BACKLIGHT
600V RMS
INVERTER
(OZ960)

1.7V

OMIT

ZT42

HOLE-VIA-20R10

(SC2602)

OMIT

ZT49
1

OMIT

MAXBUS I/O
LDO

HOLE-VIA-20R10

OMIT

ZT66

HOLE-VIA-20R10

OMIT

OMIT

ZT56

OMIT
ZT67
HOLE-VIA-20R10

ZT62

HOLE-VIA-20R10

OMIT

OMIT

ZT57

OMIT

ZT63

HOLE-VIA-20R10

ZT68

HOLE-VIA-20R10

OMIT

ZT61

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

ZT50

HOLE-VIA-20R10

HOLE-VIA-20R10

1.8V
OMIT

(EZ1582)

2.5V

OMIT

ZT55

HOLE-VIA-20R10
1

HOLE-VIA-20R10

ZT43

---

ZT53
1

HOLE-VIA-20R10

DDR
DC/DC
(SC2602)

5.1V
HOLE-VIA-20R10

1.55V

---

================ ============ ========


62.0
TOTAL
---

(SWITCH)

CPU
DC/DC
(LTC3707)

ZT44

HOLE-VIA-20R10

OMIT

ZT51

HOLE-VIA-20R10

OMIT

ZT58

PWR BLOCK,PCB INFO

HOLE-VIA-20R10
1

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:29:21 2003

3.3V

POWER SYSTEM ARCHITECTURE

AGP
LDO
(EZ1582)

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

OMIT

ZT45

1.5V

HOLE-VIA-20R10

OMIT

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

ZT52

II NOT TO REPRODUCE OR COPY IT

HOLE-VIA-20R10

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
3
69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

CPU INTERNAL PLL FILTERING

CPU_VCORE_SLEEP
1

+MAXBUS_SLEEP
59D7> 59B5> 52C6> 45D2<> 8C1< 8B7< 4D3<

CPU_VCORE_SLEEP

6C5< 6D6< 7A3< 7B3< 7C3< 7C5< 7C7< 8A3<> 8D1< 8D4<
9B7< 9D8< 44B7< 44D1< 44D2< 45D2<> 46D4< 52C6> 59C7>

56D3> 9D3<> 8B7<> 7C7<


7C5< 4A3<

CPU_BR_L
CPU_BG_L

D2
M1

CPU_TS_L

L4

CPU_PULLDOWN

E11
H1
C11
G3

CPU_ADDR<0>
CPU_ADDR<1>
CPU_ADDR<2>
56D3> 9D3<> 8B8<> CPU_ADDR<3>
56D3> 9D3<> 8B5<> CPU_ADDR<4>
56D3> 9D3<> 8B7<> CPU_ADDR<5>
56D3> 9D3<> 8C4<> CPU_ADDR<6>
56D3> 9D3<> 8B7<> CPU_ADDR<7>
56D3> 9D3<> 8C5<> CPU_ADDR<8>
56D3> 9C3<> 8B8<> CPU_ADDR<9>
56D3> 9C3<> 8B8<> CPU_ADDR<10>
56D3> 9C3<> 8C4<> CPU_ADDR<11>
56D3> 9C3<> 8B7<> CPU_ADDR<12>
56D3> 9C3<> 8B8<> CPU_ADDR<13>
56D3> 9C3<> 8B7<> CPU_ADDR<14>
56D3> 9C3<> 8B7<> CPU_ADDR<15>
56D3> 9C3<> 8B8<> CPU_ADDR<16>
56D3> 9C3<> 8B8<> CPU_ADDR<17>
56D3> 9C3<> 8C8<> CPU_ADDR<18>
56D3> 9C3<> 8B7<> CPU_ADDR<19>
56D3> 9C3<> 8B8<> CPU_ADDR<20>
56D3> 9C3<> 8C7<> CPU_ADDR<21>
56D3> 9C3<> 8C7<> CPU_ADDR<22>
56D3> 9C3<> 8C8<> CPU_ADDR<23>
56D3> 9C3<> 8B7<> CPU_ADDR<24>
56D3> 9C3<> 8B8<> CPU_ADDR<25>
56D3> 9C3<> 8C8<> CPU_ADDR<26>
56D3> 9C3<> 8C8<> CPU_ADDR<27>
56D3> 9C3<> 8C7<> CPU_ADDR<28>
56D3> 9C3<> 8C8<> CPU_ADDR<29>
56D3> 9C3<> 8C7<> CPU_ADDR<30>
56D3> 9C3<> 8C7<> CPU_ADDR<31>

56D3> 9D3<> 8B4<>

F10

56D3> 9D3<> 8B5<>


56D3> 9D3<> 8B4<>

L2

NC_CPUAP<0>
NC_CPUAP<1>
NC_CPUAP<2>
NC_CPUAP<3>
NC_CPUAP<4>

CPU_TT<0>
56D3> 9B3<> 8B5<> 7A7< CPU_TT<1>
56D3> 9B3<> 8B4<> 7A7< CPU_TT<2>
56D3> 9B3<> 8B5<> 7A7< CPU_TT<3>
56D3> 9B3<> 8B4<> 7A7< CPU_TT<4>
56D3> 9B3<> 8B4<> 7B7< CPU_TBST_L
56D3> 9B3<> 8B5<> CPU_TSIZ<0>
56D3> 9B3<> 8B5<> CPU_TSIZ<1>
56D3> 9B3<> 8B7< CPU_TSIZ<2>
56D3> 9B3<> 8B4<> 7A7<

INT_V2

9C3<> 7B7< CPU_INT_GBL_L


56C3>

56C3> 8B5<>

R311
0 2
5%
1/16W
MF
402

CPU_GBL_L

D11
D1
C10
G2
D12
L3
G4
T2
F4
V1
J4
R2
K5
W2
J2
K4
N4
J3
M5
P5
N3
T1
V2
U1
N5
W1
B12
C4
G10
B11

NO_TEST

C1

NO_TEST

E3

NO_TEST

H6

NO_TEST

F5

NO_TEST

G7

E5
E6
F6
E9
C5
F11
G6
F7
E7
E2

56C3> 9B3<> 8B5<> 7A7< CPU_WT_L


INT_V1
56C3> 9C3<> 8C5<> 7A7< CPU_CI_L
1
R312
56C3> 9B3<> 8B5<> 7B7< CPU_AACK_L
100
1%
56C3> 9B3<> 8B8<> 7C7< CPU_ARTRY_L
1/16W
MF
7B5< CPU_SHD0_L
2 402
7B5< CPU_SHD1_L
56C3> 9B3< 8B8<> 7C7< CPU_HIT_L

D3
J1
R1
N2
E4
H5
B2

OVDD

AVDD

BR*
BG*

BVSEL
SYSCLK
CLKOUT
PLLCFG0
PLLCFG1
PLLCFG2
PLLCFG3
PLL_EXT
DBG*
DRDY*
DTI0
DTI1
DTI2
DTI3

TS*
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35

TDI
TDO
TMS
TCK
TRST*
LSSDMODE*
L1TSTCLK
L2TSTCLK

U34
800MHZ

APOLLO_MPC7445_360

TA*
TEA*

BGA
(1 OF 3)

C1036
0.1UF

20%
10V
2 CERM
402

A8

V14

V10

V7

V4

U16

U12

U2

T9

T6

R16

R13

R4

P11

P8

P2

N6

M3

L5

K2

J5

H3

G18

F2

E18

D5

C12

C2

B4

M12

M10

M8

L13

L11

L9

L7

K14

K12

K10

K8

J13

J11

J9

J7

H12

H10

H8

VDD
56D3> 9D3< 8B4<> 7C7<
56D3> 9D3<> 8B4<> 7B7<

1%
1/16W
MF
603

52C6> CPU_AVDD

5%
1/16W
MF
402 2

4D7< 8B7< 8C1< 45D2<> 52C6> 59B5> 59D7>

R901
10

R891
470

CPU_BUS_VSEL

B7

C1035
2.2UF

N20P80%
16V
2 CERM
805

7C4<

SYSCLK_CPU

A10
H2

NO_TEST

B8
C8
C7
D7
A7
M2
R3
G1
K1
P1
N1

NC_CPU_CLKOUT
CPU_PLL_CFG<0> 6C6< 8A8<>
CPU_PLL_CFG<1> 6C6< 8A8<>
CPU_PLL_CFG<2> 6C6< 8A8<>
CPU_PLL_CFG<3> 6C6< 8A8<>
CPU_PLL_CFGEXT 6C6< 8A8<>
CPU_DBG_L 7B7< 8B8<> 9B1<> 56C3>
CPU_DRDY_L_UF 56C3>
CPU_EDTI 7C5<
CPU_DTI<0> 8B7<> 9A1<> 56C3>
CPU_DTI<1> 8B4<> 9A1<> 56C3>
CPU_DTI<2> 8B4<> 9A1<> 56C3>

R895
47

5%
1/16W
MF
402 2

RC GLITCH FILTER
PLACE CLOSE TO PIN

R850
0 2
5%
1/16W
MF
402

A4
F1
C6
A5
E8
G8
B3

CPU_DRDY_L 7B7<

8B5<> 9B1< 56C3>

NOSTUFF
1

C954
10PF

5%
50V
2 CERM
402

JTAG_CPU_TDI 7A5< 8A3<> 59C7>


JTAG_CPU_TDO 8A3<> 59C7>
JTAG_CPU_TMS 7A5< 8A3<> 59C7>
JTAG_CPU_TCK 7D5< 8A3<> 59C7>
JTAG_CPU_TRST_L 7C5< 8A3<> 59C7>
CPU_LSSD_MODE 7B5<
CPU_L1TSTCLK 7B4<
CPU_L2TSTCLK 7C4<

B9

9A4< 56C3>

NOSTUFF
1

FILTERS A WAKE FROM SLEEP GLITCH


IF NECESSARY

CPU_TA_L 7C7< 8C4<> 9A1<> 56C3>


CPU_TEA_L 7B7< 8B5<> 9A1<> 56C3>

K6
L1

SEE_TABLE

TBEN
QREQ*
QACK*
CKSTP_IN*
CKSTP_OUT*

INT*
SMI*
MCP*
SRESET*
HRESET*

AP0
AP1
AP2
AP3
AP4

CPU_TBEN 7C5< 9A3<>


CPU_QREQ_L 7D5< 8B7<> 9B3< 56C3>
CPU_QACK_L 8B4<> 9B3<> 56C3>
CPU_CHKSTP_IN_L 7B5< 59C7>
CPU_CHKSTP_OUT_L 7B5< 8A3<> 8D5<>

E1
P4
G5
A3
B1

MPIC_CPU_INT_L 7A5< 8D7<> 28B5>


CPU_SMI_L 7A5< 44C4<>
CPU_MCP_L 7B5<
CPU_SRESET_L 7A5< 8A3<> 59C5>
CPU_HRESET_L 7A3< 7A5< 7B3< 8A3<>

D4
F9
C9
A2
D8

59C7>

44C2< 44D2< 59C7>

IBORG PULLS THIS UP, SPEC SAYS TO GROUND IT FOR SW CONTROL

TT0
TT1
TT2
TT3
TT4
TBST*
TSIZ0
TSIZ1
TSIZ2
GBL*
WT*
CI*
AACK*
ARTRY*
SHD0*
SHD1*
HIT*

PMON_IN*
PMON_OUT*

D9

BMODE0*
BMODE1*

G9

A9

F8

EXT_QUAL

A11

TEST0
TEST1
TEST2
TEST3
TEST4

A12

NO_TEST

CPU_EMODE0_L
CPU_EMODE1_L

7A4<
7A4<

D10

CPU_PULLUP 7A5<
CPU_PULLDOWN 4D7<>

C345
0.1UF

20%
10V
2 CERM
402

OMIT
ZH6
TH
SL-138X272-292
1 ZT10P1

B10

B
1

C352
0.1UF

20%
10V
2 CERM
402

B6

E10

OMIT
ZH5
TH
SL-138X272-292
1 ZT11P1

OMIT
ZH4
275R138
1
ZT9P1

CPU_PMONIN_L 7C5<
NC_PMON_OUT_L

OMIT
ZH7
275R138
1

ZT8P1

7C5<
1

C369
0.1UF

20%
10V
2 CERM
402

C370
0.1UF

20%
10V
2 CERM
402

V15

V11

V8

V5

U17

U13

U3

T10

T7

R17

R5

R14

P12

P9

P3

N7

M13

M9

M11

M7

M4

L12

L10

L8

L6

K13

K9

K3

K11

K7

J12

J8

J10

J6

H13

H11

H9

H7

H4

G17

F3

E17

D13

D6

C3

B5

GND

INTREPID VERSION 1 PULLS GBL


ALL THE TIME. NEED TO
CUT THE TRACE AND YANK
DOWN HARD FOR SNOOPING.
FIXED IN INTREPID VERSION 2.

MPC7450 MAXBUS

NOTICE OF PROPRIETARY PROPERTY

CPU MECHANICAL PARTS SUPPORT

LAST_MODIFIED=Mon Oct 27 12:29:22 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

875-1475

PAD,THERMAL,CPU,U34

U341

BOM OPTION

870-1113

HEAT SINK,CPU,Q26,U34

U342

DEV

870-1114

CLIP,HEAT SINK,CPU,Q26.U34

U343

DEV

SIZE

412-0042

SCREW,MACH,3MM W,8MM L,U34

U344

DEV

835-0251

NUT,3MM,U34

U345

DEV

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE COMPUTER INC.

SCALE

DRAWING NUMBER

REV.

051-6569 A
4
69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

APOLLO_MPC7445_360
NC_CPUCRUD<0>
NC_CPUCRUD<1>
NC_CPUCRUD<2>
NC_CPUCRUD<3>
NC_CPUCRUD<4>
NC_CPUCRUD<5>
NC_CPUCRUD<6>
NC_CPUCRUD<7>
NC_CPUCRUD<8>
NC_CPUCRUD<9>
NC_CPUCRUD<10>
NC_CPUCRUD<11>
NC_CPUCRUD<12>
NC_CPUCRUD<13>
NC_CPUCRUD<14>
NC_CPUCRUD<15>
NC_CPUCRUD<16>

NO_TEST

F18

NO_TEST

F17

NO_TEST

F19

NO_TEST

H19

NO_TEST

H18

NO_TEST

H17

NO_TEST

H16

NO_TEST

E19

NO_TEST

D18

NO_TEST

F16

NO_TEST

G16

NO_TEST

D19

NO_TEST

F15

NO_TEST

G19

NO_TEST

E16

NO_TEST

D17

NO_TEST

D16

NC_CPUCRUD<17>
NC_CPUCRUD<18>
NC_CPUCRUD<19>
NC_CPUCRUD<20>
NC_CPUCRUD<21>
NC_CPUCRUD<22>
NC_CPUCRUD<23>
NC_CPUCRUD<24>
NC_CPUCRUD<25>
NC_CPUCRUD<26>
NC_CPUCRUD<27>
NC_CPUCRUD<28>
NC_CPUCRUD<29>
NC_CPUCRUD<30>
NC_CPUCRUD<31>
NC_CPUCRUD<32>
NC_CPUCRUD<33>
NC_CPUCRUD<34>
NC_CPUCRUD<35>
NC_CPUCRUD<36>
NC_CPUCRUD<37>
NC_CPUCRUD<38>
NC_CPUCRUD<39>
NC_CPUCRUD<40>
NC_CPUCRUD<41>
NC_CPUCRUD<42>
NC_CPUCRUD<43>
NC_CPUCRUD<44>
NC_CPUCRUD<45>
NC_CPUCRUD<46>
NC_CPUCRUD<47>
NC_CPUCRUD<48>
NC_CPUCRUD<49>
NC_CPUCRUD<50>
NC_CPUCRUD<51>
NC_CPUCRUD<52>
NC_CPUCRUD<53>
NC_CPUCRUD<54>
NC_CPUCRUD<55>
NC_CPUCRUD<56>
NC_CPUCRUD<57>
NC_CPUCRUD<58>
NC_CPUCRUD<59>
NC_CPUCRUD<60>
NC_CPUCRUD<61>
NC_CPUCRUD<62>
NC_CPUCRUD<63>
NC_CPUCRUD<64>
NC_CPUCRUD<65>
NC_CPUCRUD<66>
NC_CPUCRUD<67>
NC_CPUCRUD<68>
NC_CPUCRUD<69>
NC_CPUCRUD<70>
NC_CPUCRUD<71>
NC_CPUCRUD<72>
NC_CPUCRUD<73>
NC_CPUCRUD<74>
NC_CPUCRUD<75>
NC_CPUCRUD<76>
NC_CPUCRUD<77>
NC_CPUCRUD<78>
NC_CPUCRUD<79>
NC_CPUCRUD<80>

NO_TEST

P15

NO_TEST

L15

NO_TEST

N15

NO_TEST

P18

NO_TEST

N14

NO_TEST

M14

NO_TEST

M17

NO_TEST

N13

NO_TEST

N16

NO_TEST

M19

NO_TEST

M16

NO_TEST

P19

NO_TEST

N17

NO_TEST

M15

NO_TEST

L17

NC_CPUCRUD<81>
NC_CPUCRUD<82>
NC_CPUCRUD<83>
NC_CPUCRUD<84>
NC_CPUCRUD<85>
NC_CPUCRUD<86>
NC_CPUCRUD<87>
NC_CPUCRUD<88>
NC_CPUCRUD<89>

NO_TEST

L14

NO_TEST

K15

NO_TEST

J14

NO_TEST

J18

NO_TEST

J19

NO_TEST

J15

NO_TEST

K19

NO_TEST

J16

NO_TEST

H15

NO_TEST

L16

NO_TEST

P16

NO_TEST

M18

NO_TEST

L19

NO_TEST

L18

NO_TEST

K18

NO_TEST

J17

NO_TEST

K16

NO_TEST

C19

NO_TEST

D15

NO_TEST

G15

NO_TEST

C18

NO_TEST

A16

NO_TEST

B19

NO_TEST

A19

NO_TEST

D14

NO_TEST

E15

NO_TEST

B15

NO_TEST

B17

NO_TEST

C17

NO_TEST

C16

NO_TEST

G13

NO_TEST

E14

NO_TEST

H14

NO_TEST

G14

NO_TEST

C15

NO_TEST

A17

NO_TEST

G12

NO_TEST

F14

NO_TEST

F13

NO_TEST

E13

NO_TEST

B16

NO_TEST

A15

NO_TEST

C14

NO_TEST

A18

NO_TEST

A13

NO_TEST

F12

NO_TEST

A14

NO_TEST

G11

NO_TEST

C13

NO_TEST

N12

NO_TEST

N18

NO_TEST

K17

NO_TEST

N19

NO_TEST

B18

NO_TEST

E12

NO_TEST

B13

NO_TEST

B14

NO_TEST

A6

NC_F18
NC_F17
NC_F19
NC_H19
NC_H18
NC_H17
NC_H16
NC_E19
NC_D18
NC_F16
NC_G16
NC_D19
NC_F15
NC_G19
NC_E16
NC_D17
NC_D16

U34
800MHZ

BGA

APOLLO_MPC7445_360

(3 OF 3)

CPU_DATA<0>
CPU_DATA<1>
56D3> 9D1<> 8C8<> CPU_DATA<2>
56D3> 9D1<> 8C5<> CPU_DATA<3>
56D3> 9D1<> 8C7<> CPU_DATA<4>
56D3> 9D1<> 8C8<> CPU_DATA<5>
56D3> 9D1<> 8C4<> CPU_DATA<6>
56D3> 9D1<> 8C8<> CPU_DATA<7>
56D3> 9D1<> 8C5<> CPU_DATA<8>
56D3> 9D1<> 8C4<> CPU_DATA<9>
56D3> 9D1<> 8C7<> CPU_DATA<10>
56D3> 9D1<> 8C5<> CPU_DATA<11>
56D3> 9D1<> 8C5<> CPU_DATA<12>
56D3> 9D1<> 8C7<> CPU_DATA<13>
56D3> 9D1<> 8C8<> CPU_DATA<14>
56D3> 9D1<> 8C5<> CPU_DATA<15>
56D3> 9C1<> 8C4<> CPU_DATA<16>
56D3> 9C1<> 8C7<> CPU_DATA<17>
56D3> 9C1<> 8C4<> CPU_DATA<18>
56D3> 9C1<> 8C4<> CPU_DATA<19>
56D3> 9C1<> 8C4<> CPU_DATA<20>
56D3> 9C1<> 8C8<> CPU_DATA<21>
56D3> 9C1<> 8C7<> CPU_DATA<22>
56D3> 9C1<> 8C8<> CPU_DATA<23>
56D3> 9C1<> 8D4<> CPU_DATA<24>
56D3> 9C1<> 8D7<> CPU_DATA<25>
56D3> 9C1<> 8C5<> CPU_DATA<26>
56D3> 9C1<> 8C7<> CPU_DATA<27>
56D3> 9C1<> 8D8<> CPU_DATA<28>
56D3> 9C1<> 8C8<> CPU_DATA<29>
56D3> 9C1<> 8C5<> CPU_DATA<30>
56D3> 9C1<> 8D7<> CPU_DATA<31>
56D3> 9C1<> 9B7< 8D7<> CPU_DATA<32>
56D3> 9C1<> 9B7< 8D8<> CPU_DATA<33>
56D3> 9C1<> 9B7< 8D8<> CPU_DATA<34>
56D3> 9C1<> 9B7< 8D7<> CPU_DATA<35>
56D3> 9C1<> 9A7< 8D4<> CPU_DATA<36>
56D3> 9C1<> 8D5<> CPU_DATA<37>
56D3> 9C1<> 8D5<> CPU_DATA<38>
56D3> 9C1<> 8D5<> CPU_DATA<39>
56D3> 9C1<> 8D7<> 6C4< CPU_DATA<40>
56D3> 9C1<> 8C4<> 6C4< CPU_DATA<41>
56D3> 9B1<> 8C5<> 6C4< CPU_DATA<42>
56D3> 9B1<> 8C4< 6C4< CPU_DATA<43>
56D3> 9B1<> 8C8<> 6C4< CPU_DATA<44>
56D3> 9B1<> 8C7<> 6C4< CPU_DATA<45>
56D3> 9B1<> 8C4<> 6C4< CPU_DATA<46>
56D3> 9B1<> 8C7< 6C4< CPU_DATA<47>
56D3> 9D8< 9B1<> 8C5<> CPU_DATA<48>
56D3> 9D8< 9B1<> 8C4<> CPU_DATA<49>
56D3> 9D8< 9B1<> 8C8<> CPU_DATA<50>
56D3> 9D8< 9B1<> 8C8<> CPU_DATA<51>
56D3> 9C8< 9B1<> 8C5<> CPU_DATA<52>
56D3> 9C8< 9B1<> 8C7<> CPU_DATA<53>
56D3> 9C8< 9B1<> 8D7<> CPU_DATA<54>
56D3> 9C8< 9B1<> 8C5<> CPU_DATA<55>
56D3> 9B1<> 8D8<> CPU_DATA<56>
56D3> 9D5< 9B1<> 8D5<> CPU_DATA<57>
56D3> 9D5< 9B1<> 8D4<> CPU_DATA<58>
56D3> 9D5< 9B1<> 8D8<> CPU_DATA<59>
56D3> 9D5< 9B1<> 8D8<> CPU_DATA<60>
56D3> 9C5< 9B1<> 8D4<> CPU_DATA<61>
56D3> 9C5< 9B1<> 8D4<> CPU_DATA<62>
56D3> 9C5< 9B1<> 8D5<> CPU_DATA<63>

NC_P15
NC_L15
NC_N15
NC_P18
NC_N14
NC_M14
NC_M17
NC_N13
NC_N16
NC_M19
NC_M16
NC_P19
NC_N17
NC_M15
NC_L17
NC_L14
NC_K15
NC_J14
NC_J18
NC_J19
NC_J15
NC_K19
NC_J16
NC_H15
NC_L16
NC_P16
NC_M18
NC_L19
NC_L18
NC_K18
NC_J17
NC_K16
NC_C19
NC_D15
NC_G15
NC_C18
NC_A16
NC_B19
NC_A19
NC_D14
NC_E15
NC_B15
NC_B17
NC_C17
NC_C16
NC_G13
NC_E14
NC_H14
NC_G14
NC_C15
NC_A17
NC_G12
NC_F14
NC_F13
NC_E13
NC_B16
NC_A15
NC_C14
NC_A18
NC_A13
NC_F12
NC_A14
NC_G11
NC_C13

56D3> 9D1<> 8C4<>

R15

56D3> 9D1<> 8C7<>

W15

NC_CPUDP<0>
NC_CPUDP<1>
NC_CPUDP<2>
NC_CPUDP<3>
NC_CPUDP<4>
NC_CPUDP<5>
NC_CPUDP<6>
NC_CPUDP<7>

T14
V16
W16
T15
U15
P14
V13
W13
T13
P13
U14
W14
R12
T12
W12
V12
N11
N10
R11
U11
W11
T11
R10
N9
P10
U10
R9
W10
U9
V9
W5
U6
T5
U5
W7
R6
P7
V6
P17
R19
V18
R18
V19
T19
U19
W19
U18
W17
W18
T16
T18
T17
W3
V17
U4
U8
U7
R7
P6
R8
W8
T8

NO_TEST

T3

NO_TEST

W4

NO_TEST

T4

NO_TEST

W9

NO_TEST

M6

NO_TEST

V3

NO_TEST

N8

NO_TEST

W6

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63

U34
800MHZ

BGA
(2 OF 3)

DP0
DP1
DP2
DP3
DP4
DP5
DP6
DP7

MPC7450 - 2

NC_N12
NC_N18
NC_K17
NC_N19
NC_B18
NC_E12
NC_B13
NC_B14
NC_A6

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:29:23 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
5
69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

BOMOPTIONS FOR UPPER-SET OF RESISTORS


1200@133&1500@167&1333@133&1667@167&1467@133&1833@167&1600@133&2000@167&1733@133&2167@167&1867@133&2333@167&2000@133&2500@167&2133@133&2667@167
667@133&833@167&733@133&917@167&800@133&1000@167&1067@133&1333@167&1333@133&1667@167&1467@133&1833@167&1600@133&2000@167&1867@133&2333@167&2133@133&2667@167
800@133&1000@167&867@133&1083@167&1067@133&1333@167&1200@133&1500@167&1733@133&2167@167&1867@133&2333@167&2133@133&2667@167
667@133&833@167&933@133&1167@167&1200@133&1500@167&1333@133&1667@167&1600@133&2000@167

D
667@133&833@167&733@133&917@167&800@133&1000@167&867@133&1083@167&1000@133&1250@167&1200@133&1500@167&1467@133&1833@167&1600@133&2000@167&1733@133&2167@167&2000@133&2500@167&2133@133&2667@167

+MAXBUS_SLEEP

4D5< 6C5< 7A3< 7B3< 7C3< 7C5< 7C7< 8A3<> 8D1< 8D4< 9B7< 9D8<
44B7< 44D1< 44D2< 45D2<> 46D4< 52C6> 59C7>

CPU FREQUENCY CONFIGURATION

NOSTUFF

59C7> 52C6>
8D1< 8A3<> 7C7< 7C5< 7C3< 7B3< 7A3< 6D6< 4D5<
46D4< 45D2<> 44D2< 44D1< 44B7< 9D8< 9B7< 8D4<

(SUPPORTED CPU & BUS SPEEDS)


667@133&733@133&800@133&867@133&933@133&1000@133&1067@133&1200@133&1333@133&1467@133&1600@133&1733@133&1867@133&2000@133&2133@133

+MAXBUS_SLEEP
NOSTUFF

CORE FREQUENCY
SPECIAL CONFIG
R382
10K

SPECIAL CONFIG SPECIAL CONFIG


1
R379
R378
10K
10K

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

SPECIAL CONFIG
R376
10K

SPECIAL CONFIG
R374
10K

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

4C3< 8A8<>

CPU_PLL_CFG<3>

4C3< 8A8<>

CPU_PLL_CFG<2>

4D3< 8A8<>

CPU_PLL_CFG<1>

4D3< 8A8<>

CPU_PLL_CFG<0>

4D3< 8A8<>

SPECIAL CONFIG SPECIAL CONFIG


1
1
R381
R380
1K
1K

SPECIAL CONFIG
1
R377
1K

SPECIAL CONFIG
1
R375
1K

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

NOSTUFF
1

1%
1/16W
MF
402 2

1%
1/16W
MF
402 2

R879
10K

CPU_PLL_CFGEXT

SPECIAL CONFIG
1
R383
1K

NOSTUFF
1

R878
10K

R8891
10K

R8661
10K

R8741
10K

1%
1/16W
MF
402 2

1%
1/16W
MF
402 2

1%
1/16W
MF
402 2

NOSTUFF
1

NOSTUFF
1

NOSTUFF
1

1%
1/16W
MF
402 2

1%
1/16W
MF
402 2

1%
1/16W
MF
402 2

R877
10K

R875
10K

167MHZ

R867
10K

R3641
4.7K

R8871
4.7K

R3571
4.7K

R3681
4.7K

R3651
4.7K

R3671
4.7K

R3561
4.7K

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

CPU_PLL_CFG
E

0123 HEX

5.0X

833

667

1011 0B

5.5X

917

733

1001 09

6.0X

1000

800

1101 0D

6.5X

1083

867

0101 05

7.0X

1167

933

0010 02

7.5X

1250

1000

0001 01

8.0X

1333

1067

1100 0C

9.0X

1500

1200

0111 17

10.0X

1667

1333

1010 1A

11.0X

1833

1467

1001 19

12.0X

2000

1600

1011 1B

13.0X

2167

1733

0101 15

14.0X

2333

1867

1100 1C

15.0X

2500

2000

0001 11

16.0X

2667

2133

1101 1D

5B4<> 8D7<> 9C1<> 56D3>


5B4<> 8C4<> 9C1<> 56D3>
5B4<> 8C5<> 9B1<> 56D3>
5B4<> 8C4< 9B1<> 56D3>
5B4<> 8C8<> 9B1<> 56D3>
5B4<> 8C7<> 9B1<> 56D3>
5B4<> 8C4<> 9B1<> 56D3>
5B4<> 8C7< 9B1<> 56D3>

INTREPID BOOT STRAPS


BITS 40 - 47

PCI0 SOURCE CLOCK


0: PLL4
1: PLL5 (NO SPREAD)

PCI1 SOURCE CLOCK


0: PLL4
1: PLL5 (NO SPREAD)

44B8<

INTERNALSPREADEN
0: INACTIVE
1: ACTIVE

SPARE

SPARE

CPU_PLL_STOP

PLL4MODESEL_NXT[2:0]
000: 166.4 MHZ
001: 149.76 MHZ
010: 133.12 MHZ
011: 99.84 MHZ
100: 83.20 MHZ

133MHZ
(MHZ)

(BUS-TO-CORE)
CPU_DATA<40>
CPU_DATA<41>
CPU_DATA<42>
CPU_DATA<43>
CPU_DATA<44>
CPU_DATA<45>
CPU_DATA<46>
CPU_DATA<47>

R3631
4.7K

(AT BUS FREQUENCY)

MULTIPLIER

(STUFF FOR 133 AND 167)

833@167&917@167&1000@167&1083@167&1167@167&1250@167&1333@167&1500@167&1667@167&1833@167&2000@167&2167@167&2333@167&2500@167&2667@167

(STUFF FOR 133 AND 167)

933@133&1167@167&1067@133&1333@167&1333@133&1667@167&1867@133&2333@167
733@133&917@167&800@133&1000@167&867@133&1083@167&1000@133&1250@167&1067@133&1333@167&1467@133&1833@167&1733@133&2167@167&1867@133&2333@167&2000@133&2500@167&2133@133&2667@167
667@133&833@167&733@133&917@167&933@133&1167@167&1000@133&1250@167&1333@133&1667@167&1467@133&1833@167&1600@133&2000@167&2000@133&2500@167
867@133&1083@167&933@133&1167@167&1000@133&1250@167&1200@133&1500@167&1733@133&2167@167&2000@133&2500@167
667@133&833@167&733@133&917@167&800@133&1000@167&867@133&1083@167&933@133&1167@167&1000@133&1250@167&1067@133&1333@167

CPU SPEED & BUS RATIO SUPPORT


THE CONFIGURATION RESISTORS BELOW ARE SELF CONFIGURING
WHEN THE ENGINEER SELECTS THE APPROPRIATE CPU AND
BUS SPEED BOM OPTION, THE APPROPRIATE RESISTORS ARE
ARE AUTOMATICALLY SELECTED

CPU BUS RATIO BITS


A

NOTICE OF PROPRIETARY PROPERTY

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

BOM OPTION

337S2799

IC,APOLLO6,SICOH,1.0GHZ,1.5V+30/-130MV,28W,85C

U34

CRITICAL

1000@167

337S2801

IC,APOLLO6,SICOH,1.25GHZ,1.57V+70/-70MV,35W,85C

U34

CRITICAL

1250@167

LAST_MODIFIED=Mon Oct 27 12:29:23 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
6
69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

BMODE | MSSCR0 | Sys | Vger | Addr


<0> <1> | <16:17> | Bus | ID | Drve
=========+=========+=====+======+======
L
L |
1 1 | ??? | 01 | yes unavail
L !hr |
1 0 | Max | 01 | yes unavail
L
hr |
1 1 | ??? | 00 | yes unavail
L
H |
1 0 | Max | 00 | yes unavail
---------+---------+-----+------+-----!hr L |
0 1 | MB+ | 01 | yes unavail
!hr !hr |
0 0 | 60x | 01 | yes unavail
!hr hr |
0 1 | MB+ | 00 | yes unavail
!hr H |
0 0 | 60x | 00 | yes unavail
---------+---------+-----+------+-----hr L |
1 1 | ??? | 01 | norm unavail
hr !hr |
1 0 | Max | 01 | norm
hr hr |
1 1 | ??? | 00 | norm unavail
HR H |
1 0 | MAX | 00 | NORM <- DEFAULT
---------+---------+-----+------+-----H
L |
0 1 | MB+ | 01 | norm unavail
H !hr |
0 0 | 60x | 01 | norm
H
hr |
0 1 | MB+ | 00 | norm unavail
H
H |
0 0 | 60x | 00 | norm

SIGNAL
CPU_EMODE0_L

59C7> 8A3<> 4C3<

JTAG_CPU_TCK

R924
10K 2

59C7> 8A3<> 4C3< JTAG_CPU_TRST_L

RP79
4B3<

59C7> 52C6>
8D1< 8A3<> 7C5< 7C3< 7B3< 7A3< 6D6< 6C5< 4D5<
46D4< 45D2<> 44D2< 44D1< 44B7< 9D8< 9B7< 8D4<

56D3> 9D3<> 8B7<> 4D7<>

CPU_TS_L

56C3> 9A1<> 8C4<> 4C3<

56C3> 9B3<> 8B8<> 4A7<>

4C3<

R348
10K 2
1

CPU_TA_L

CPU_ARTRY_L

R346
10K 2
1

56C3> 9B3< 8B8<> 4A7>

R840
10K 2

CPU_TEA_L

CPU_DBG_L

R845
10K 2
1

56D3> 9B3<> 8B4<> 4B7>

R847
10K 2
1

56D3> 9B3<> 8B4<> 4B7<>

RP78
10K
5%
1/16W
SM1

56D3> 9B3<> 8B5<> 4B7<>

CPU_TT<1>

59C7> 8D5<> 8A3<> 4B3>

CPU_TT<2>

RP78
10K
2

56D3> 9B3<> 8B4<> 4B7<>

CPU_TT<4>

4D3<

CPU_BUS_VSEL

1.8V INTERFACE
1.5V INTERFACE

VGER_INV_HRESET

7A3< 7B3< 44D1>

R914
200 2

R913
10K 2

+MAXBUS_SLEEP

5%
1/16W
MF
402

59C7>
4D5< 6C5< 6D6< 7A3< 7B3< 7C3< 7C5< 7C7< 8A3<> 8D1<
8D4< 9B7< 9D8< 44B7< 44D1< 44D2< 45D2<> 46D4< 52C6>

5%
1/16W
MF
402

CPU_PULLUP

59C7> 44D2< 44C2< 8A3<> 7B3< 7A3< 4B3<

R910
10K 2

1.8V BUS MODE


1.5V BUS MODE
2.5V BUS MODE

R909
1K 2

RP78
10K

NOSTUFF

R920
200 2
1

NOSTUFF

R906
0 2
1
5%
1/16W
MF
402

R882
1K 2
4C3<

CPU_L1TSTCLK

CPU_HRESET_L
R916
0 2

RP79
10K

CPU_EMODE0_L

CPUBUS_MAX

1
6

R905
200 2

R904
1K 2

RP79
10K
1

+MAXBUS_SLEEP

5%
1/16W
MF
402

CPU_HRESET_L

5%
1/16W
MF
402

4B3<

CPU_EMODE1_L

NOSTUFF

R902
200 2
1

59C7>
4D5< 6C5< 6D6< 7A3< 7B3< 7C3< 7C5< 7C7< 8A3<> 8D1<
8D4< 9B7< 9D8< 44B7< 44D1< 44D2< 45D2<> 46D4< 52C6>

4B3< 7A5< 7B3< 8A3<> 44C2< 44D2<


59C7>

CPU CONFIG OPTIONS


1%
1/16W
MF
402

+MAXBUS_SLEEP

7C5< 7C7< 8A3<> 8D1< 8D4< 9B7< 9D8<


NOTICE OF PROPRIETARY PROPERTY
4D5< 6C5< 6D6<
LAST_MODIFIED=Mon Oct 27 12:29:24 2003
7A3< 7B3< 7C3<
44B7< 44D1< 44D2< 45D2<> 46D4< 52C6> 59C7> THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

VGER_INV_HRESET

7B3< 7C3< 44D1>

II NOT TO REPRODUCE OR COPY IT

5%
1/16W
MF
402

R923
10K 2

7A3< 7B3< 7C3< 44D1>

CPUBUS_60X

5%
1/16W
SM1

4B3< 7A3< 7A5< 7B3< 8A3<> 44C2< 44D2< 59C7>

VGER_INV_HRESET

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

APPLE COMPUTER INC.

1%
1/16W
MF
402

4D5< 6C5< 6D6< 7A3< 7C3< 7C5< 7C7< 8A3<> 8D1< 8D4<
9B7< 9D8< 44B7< 44D1< 44D2< 45D2<> 46D4< 52C6> 59C7>

5%
1/16W
MF
402

1%
1/16W
MF
402

+MAXBUS_SLEEP

5%
1/16W
MF
402

R903
1K 2
1

JTAG_CPU_TDI

JTAG_CPU_TMS

R907
10K 2

R912
10K 2
1

5%
1/16W
SM1

7A3< 7B3< 7C3< 44D1>

R922
10K 2

4B3<

59C7> 8A3<> 4C3<

R917
200 2
1

59C7> 8A3<> 4C3<

VGER_INV_HRESET

5%
1/16W
MF
402

NOSTUFF

5%
1/16W
SM1

CPU_SMI_L

R919
0 2

NOSTUFF

1%
1/16W
MF
402

MPIC_CPU_INT_L

44C4<> 4B3<

4B3< 7A3< 7A5< 7B3< 8A3<> 44C2< 44D2< 59C7>

NOSTUFF

5%
1/16W
MF
402

RP79
10K
2

CPU_HRESET_L

59C7>
4D5< 6C5< 6D6< 7A3< 7B3< 7C3< 7C5< 7C7< 8A3<> 8D1<
8D4< 9B7< 9D8< 44B7< 44D1< 44D2< 45D2<> 46D4< 52C6>

5%
1/16W
MF
402

1%
1/16W
MF
402

5%
1/16W
SM1

28B5> 8D7<> 4B3<

5%
1/16W
MF
402

1%
1/16W
MF
402

R921
1K 2
1

RP78
10K
3

R926
0 2

+MAXBUS_SLEEP

1%
1/16W
MF
402

NOSTUFF

R918
10K 2

DO NOT USE UNLESS FIX INVERTER BUFFER

CPU_HRESET_L

CPU_SRESET_L

R856
10K 2

R911
10K 2
1

59C5> 8A3<> 4B3<

CPU_L2TSTCLK

1%
1/16W
MF
402

1%
1/16W
MF
402

1%
1/16W
MF
402

R858
10K 2

R860
10K 2
1

CPU_CHKSTP_IN_L

4A3<

5%
1/16W
SM1

R350
10K 2
1

NOSTUFF

CPU_LSSD_MODE

CPU_CHKSTP_OUT_L

1%
1/16W
MF
402

R843
10K 2
1

CPU_TT<3>

R857
10K 2
1

R842
10K 2
1

1%
1/16W
MF
402

56D3> 9B3<> 8B5<> 4B7<>

R915
0 2
5%
1/16W
MF
402

1%
1/16W
MF
402

1%
1/16W
MF
402

5%
1/16W
SM1

56D3> 9B3<> 8B4<> 4B7<>

NOSTUFF

59C7> 4B3<

R844
10K 2
1

4C3<

1%
1/16W
MF
402

1%
1/16W
MF
402

R349
10K 2
1

CPU_WT_L

CPU_TT<0>

CPU_MCP_L

R846
10K 2
1

1%
1/16W
MF
402

56C3> 9B3<> 8B5<> 4B7>

5%
1/16W
MF
402

+MAXBUS_SLEEP

CPU_SHD1_L

4B3<

4C3<

CPU_INT_GBL_L

56C3> 9C3<> 8C5<> 4A7> CPU_CI_L

NOSTUFF

BUS MODE
0V
INV_HRESET
OVDD

1%
1/16W
MF
402

1%
1/16W
MF
402

1%
1/16W
MF
402

56C3> 9C3<> 4B8<

2.5V INTERFACE

LOW

R925
200 2

1%
1/16W
MF
402

R859
470 2

CPU_TBEN

CPU_SHD0_L

R849
10K 2
1

CPU_BG_L

CPU_TBST_L

4A7<>

4A7<>

1%
1/16W
MF
402

56D3> 9D3<> 8B4<> 4D7<

59C7>
8D4< 8D1< 8A3<> 7C7< 7C3< 7B3< 7A3< 6D6< 6C5< 4D5<
52C6> 46D4< 45D2<> 44D2< 44D1< 44B7< 9D8< 9B7<

1%
1/16W
MF
402

CPU_AACK_L

56C3> 9B1<> 8B8<> 4C3<

1.5V INTERFACE

CPU_HRESET_H

5%
1/16W
MF
402

R851
10K 2
1

1%
1/16W
MF
402

56C3> 9B3<> 8B5<> 4A7<

4D7<>

1.8V INTERFACE

CPU_HRESET_L or L3_OVDD

4A3< CPU_PULLDOWN

9A3<> 4C3<

CPU_DRDY_L

56C3> 9A1<> 8B5<> 4C3<

LOW
CPU_HRESET_H

R848
10K 2

1%
1/16W
MF
402

1%
1/16W
MF
402

56C3> 9B1< 8B5<> 4C2<

MAX BUS MODE


2.5V INTERFACE

MPC7450 PULL-UPS
R841
10K 2
1

CPU_BR_L

CPU_HIT_L

10K

CPU_EDTI

1%
1/16W
MF
402

1%
1/16W
MF
402

56D3> 9D3< 8B4<> 4D7>

5%
1/16W
SM1

R347
10K 2
1%
1/16W
MF
402

CPU_PMONIN_L

+MAXBUS_SLEEP

60X BUS MODE

1%
1/16W
MF
402

1%
1/16W
MF
402

MAXBUS PULL-UPS

APPLICATION

HIGH
CPU_HRESET_L

CPU_L3_VSEL
CPU_QREQ_L

TIED
CPU_HRESET_L

CPU_BUS_VSEL

56C3> 9B3< 8B7<> 4C3>

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
7
69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

59C7>
8D1< 8A3<> 7C7< 7C5< 7C3< 7B3< 7A3< 6D6< 6C5< 4D5<
52C6> 46D4< 45D2<> 44D2< 44D1< 44B7< 9D8< 9B7<

C350
10UF

N20P80%
10V
2 Y5V
805

MAXBUS LOGIC ANALYZER SUPPORT


J20
SM

GND 38

C1_7 35
C1_6 34

7 C3_4

C1_5 33
C1_4 32

8 C3_3

C1_3 31

9 C3_2

C1_2 30
C1_1 29

10 C3_1

C1_0 28
C0_7 27

11 C3_0
12 C2_7

C0_6 26
C0_5 25

13 C2_6
14 C2_5

C0_4 24
C0_3 23

15 C2_4
16 C2_3
18 C2_1

C0_2 22
C0_1 21

19 C2_0

C0_0 20

17 C2_2

CPU_CHKSTP_OUT_L
56D3> 9C1<> 5B4<> CPU_DATA<37>
56D3> 9C1<> 5B4<> CPU_DATA<39>
56D3> 9C1<> 5B4<> CPU_DATA<38>
56D3> 9C5< 9B1<> 5A4<> CPU_DATA<63>
56D3> 9D5< 9B1<> 5B4<> CPU_DATA<57>
56D3> 9C1<> 5C4<> CPU_DATA<30>
56D3> 9C1<> 5C4<> CPU_DATA<26>
56D3> 9D1<> 5D4<> CPU_DATA<8>
56D3> 9D1<> 5C4<> CPU_DATA<15>
56D3> 9C8< 9B1<> 5B4<> CPU_DATA<55>
56D3> 9D1<> 5C4<> CPU_DATA<11>
56D3> 9D1<> 5D4<> CPU_DATA<3>
56D3> 9D1<> 5C4<> CPU_DATA<12>
56D3> 9C8< 9B1<> 5B4<> CPU_DATA<52>
56D3> 9B1<> 6C4< 5B4<> CPU_DATA<42>
56D3> 9D8< 9B1<> 5B4<> CPU_DATA<48>

45

10UF

C988
0.1UF

20%
10V
2 CERM
402

C353

2.2UF

C1041
0.1UF

N20P80%
16V
2 CERM
805

20%
10V
2 CERM
402

C1026
0.1UF

20%
10V
2 CERM
402

C1043

0.1UF

C1014

0.1UF

C987

0.1UF

C1013

0.1UF

C995

CPU_DATA<58> 5B4<> 9B1<> 9D5< 56D3>


CPU_DATA<36> 5C4<> 9A7< 9C1<> 56D3>
CPU_DATA<62> 5B4<> 9B1<> 9C5< 56D3>
CPU_DATA<61> 5B4<> 9B1<> 9C5< 56D3>
CPU_DATA<24> 5C4<> 9C1<> 56D3>
CPU_DATA<41> 5B4<> 6C4< 9C1<> 56D3>
CPU_DATA<9> 5D4<> 9D1<> 56D3>
CPU_DATA<19> 5C4<> 9C1<> 56D3>
CPU_DATA<20> 5C4<> 9C1<> 56D3>
CPU_DATA<16> 5C4<> 9C1<> 56D3>
CPU_DATA<18> 5C4<> 9C1<> 56D3>
CPU_DATA<49> 5B4<> 9B1<> 9D8< 56D3>
CPU_DATA<6> 5D4<> 9D1<> 56D3>
CPU_DATA<0> 5D4<> 9D1<> 56D3>
CPU_DATA<43> 5B4<> 6C4< 9B1<> 56D3>
CPU_DATA<46> 5B4<> 6C4< 9B1<> 56D3>

E1_5 33
E1_4 32

7 E3_4
8 E3_3
9 E3_2

E1_3 31
E1_2 30

10 E3_1
11 E3_0

E1_1 29
E1_0 28

12 E2_7
13 E2_6

E0_7 27
E0_6 26

14 E2_5
15 E2_4

E0_5 25
E0_4 24

16 E2_3
17 E2_2

E0_3 23
E0_2 22
E0_1 21

18 E2_1
19 E2_0

E0_0 20

C972
0.1UF

20%
10V
2 CERM
402

C994
0.1UF

20%
10V
2 CERM
402

C981

C980

CPU_ADDR<26>
CPU_ADDR<29>
56D3> 9C3<> 4B7<> CPU_ADDR<27>
56D3> 9C3<> 4C7<> CPU_ADDR<18>
56D3> 9C3<> 4C7<> CPU_ADDR<23>
56D3> 9C3<> 4B7<> CPU_ADDR<25>
56C3> 9B1<> 7B7< 4C3< CPU_DBG_L
56D3> 9C3<> 4C7<> CPU_ADDR<17>
56D3> 9C3<> 4C7<> CPU_ADDR<20>
56D3> 9C3<> 4C7<> CPU_ADDR<16>
56C3> 9B3<> 7C7< 4A7<> CPU_ARTRY_L
56D3> 9C3<> 4C7<> CPU_ADDR<10>
56D3> 9C3<> 4C7<> CPU_ADDR<13>
56C3> 9B3< 7C7< 4A7> CPU_HIT_L
56D3> 9D3<> 4C7<> CPU_ADDR<3>
56D3> 9C3<> 4C7<> CPU_ADDR<9>
56D3> 9C3<> 4B7<>
56D3> 9C3<> 4B7<>

6 A3_5

C1007
0.1UF

8 A3_3

A1_3 31
A1_2 30

9 A3_2
11 A3_0

A1_1 29
A1_0 28

12 A2_7

A0_7 27

13 A2_6

A0_6 26
A0_5 25

10 A3_1

14 A2_5

A0_4 24
A0_3 23

15 A2_4
16 A2_3

A0_2 22
A0_1 21

17 A2_2
18 A2_1

A0_0 20

19 A2_0

3 Q0

CPU_ADDR<8>
56C3> 9C3<> 7A7< 4A7> CPU_CI_L
56D3> 9B3<> 4B7> CPU_TSIZ<1>
56D3> 9D3<> 4C7<> CPU_ADDR<4>
56C3> 9A1<> 7B7< 4C3< CPU_TEA_L
56D3> 9B3<> 7A7< 4B7<> CPU_TT<1>
56D3> 9D3<> 4C7<> CPU_ADDR<1>
56D3> 9B3<> 4B7> CPU_TSIZ<0>
56C3> 9B3<> 7A7< 4B7> CPU_WT_L
56D3> 9B3<> 7A7< 4B7<> CPU_TT<3>
56C3> 9B1< 7B7< 4C2< CPU_DRDY_L
56C3> 4B8<> CPU_GBL_L
56C3> 9B3<> 7B7< 4A7< CPU_AACK_L
56D3> 9D3<> 4C7<>

5 D3_6

D1_6 34

6 D3_5

D1_5 33
D1_4 32

C961

0.1UF

0.1UF

C1020
0.1UF

20%
10V
2 CERM
402

C993
0.1UF

20%
10V
2 CERM
402

C1021
0.1UF

20%
10V
2 CERM
402

C990
0.1UF

20%
10V
2 CERM
402

C967
0.1UF

20%
10V
2 CERM
402

59D7> 59B5> 52C6> 45D2<> 8B7< 4D7< 4D3< CPU_VCORE_SLEEP

C1040

C976

10UF

C1037
10UF

N20P80%
10V
2 Y5V
805

9 D3_2
11 D3_0

CPU_ADDR<11> 4C7<> 9C3<> 56D3>


CPU_ADDR<6> 4C7<> 9D3<> 56D3>
CPU_TA_L 4C3< 7C7< 9A1<> 56C3>
CPU_TT<0> 4B7<> 7A7< 9B3<> 56D3>
CPU_ADDR<2> 4C7<> 9D3<> 56D3>
CPU_BR_L 4D7> 7C7< 9D3< 56D3>
CPU_TT<4> 4B7<> 7A7< 9B3<> 56D3>
CPU_ADDR<0> 4C7<> 9D3<> 56D3>
CPU_TBST_L 4B7> 7B7< 9B3<> 56D3>
CPU_DTI<1> 4C3< 9A1<> 56C3>
CPU_TT<2> 4B7<> 7A7< 9B3<> 56D3>
CPU_BG_L 4D7< 7B7< 9D3<> 56D3>
CPU_QACK_L 4C3< 9B3<> 56C3>
CPU_DTI<2> 4C3< 9A1<> 56C3>

D0_7 27
D0_6 26

12 D2_7
13 D2_6

D0_5 25
D0_4 24

14 D2_5
15 D2_4
17 D2_2

D0_3 23
D0_2 22

18 D2_1

D0_1 21

16 D2_3

19 D2_0

N20P80%
2 10V
Y5V
805

N20P80%
10V
2 Y5V
805

C1911

10UF

C598
10UF

N20P80%
2 10V
Y5V
805

10UF

N20P80%
2 10V
Y5V
805

10UF

N20P80%
2 10V
Y5V
805

C1912

N20P80%
10V
2 Y5V
805

C1054 1 C1055

C1016
10UF

N20P80%
10V
2 Y5V
805

10UF

N20P80%
10V
2 Y5V
805

C1042
10UF

N20P80%
10V
2 Y5V
805

D1_1 29
D1_0 28

10 D3_1

C1032
10UF

D1_3 31
D1_2 30

8 D3_3

45

44

43

42

41

40

4 D3_7

CLK2 36
D1_7 35

7 D3_4

GND
39

C973

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

GND 38
GND 37

SYM_VER1

2 GND

CPU_ADDR<30> 4B7<> 9C3<> 56D3>


CPU_ADDR<31> 4B7<> 9C3<> 56D3>
CPU_ADDR<28> 4B7<> 9C3<> 56D3>
CPU_ADDR<22> 4C7<> 9C3<> 56D3>
CPU_ADDR<21> 4C7<> 9C3<> 56D3>
CPU_ADDR<24> 4B7<> 9C3<> 56D3>
CPU_TS_L 4D7<> 7C7< 9D3<> 56D3>
CPU_ADDR<15> 4C7<> 9C3<> 56D3>
CPU_ADDR<19> 4C7<> 9C3<> 56D3>
CPU_ADDR<14> 4C7<> 9C3<> 56D3>
CPU_DTI<0> 4C3< 9A1<> 56C3>
CPU_ADDR<7> 4C7<> 9D3<> 56D3>
CPU_ADDR<12> 4C7<> 9C3<> 56D3>
CPU_QREQ_L 4C3> 7D5< 9B3< 56C3>
CPU_TSIZ<2> 4B7> 9B3<> 56D3>
CPU_ADDR<5> 4C7<> 9D3<> 56D3>

A1_5 33
A1_4 32

7 A3_4

C977

20%
10V
2 CERM
402

0.1UF

20%
10V
2 CERM
402

DPROBE

OMIT

A1_7 35
A1_6 34

5 A3_6

0.1UF

20%
10V
2 CERM
402

F-ST-SM

GND 37
CLK1 36

4 A3_7

0.1UF

C1033

10UF

N20P80%
2 10V
Y5V
805

CON_37SM_MICTOR

GND 38

3 CLK0

0.1UF

J19

SM
SYM_VER2

C991

C1003

20%
10V
2 CERM
402

GND

CON_38SM_MICTOR
APROBE

0.1UF

20%
10V
2 CERM
402

N20P80%
2 10V
Y5V
805

2 GND

C974

20%
10V
2 CERM
402

+MAXBUS_SLEEP

0.1UF

J31
1 GND

20%
10V
2 CERM
402

10UF

OMIT

20%
10V
2 CERM
402

0.1UF

20%
10V
2 CERM
402

C999
0.1UF

20%
10V
2 CERM
402

C998

0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C982
0.1UF

20%
10V
2 CERM
402

59C7>
8D4< 8A3<> 7C7< 7C5< 7C3< 7B3< 7A3< 6D6< 6C5< 4D5<
52C6> 46D4< 45D2<> 44D2< 44D1< 44B7< 9D8< 9B7<

E1_7 35
E1_6 34

5 E3_6
6 E3_5

39

44

43

42

41

40

C992

N20P80%
10V
2 Y5V
805

GND 37
Q2 36

3 Q3
4 E3_7

59C7> 8A3<> 7B5< 4B3>

GND
39

10UF

N20P80%
10V
2 Y5V
805

45

6 C3_5

C983

GND 38

SYM_VER5

44

5 C3_6

EPROBE

1 GND
2 GND

MPIC_CPU_INT_L 4B3< 7A5< 28B5>


CPU_DATA<35> 5C4<> 9B7< 9C1<> 56D3>
CPU_DATA<54> 5B4<> 9B1<> 9C8< 56D3>
CPU_DATA<32> 5C4<> 9B7< 9C1<> 56D3>
CPU_DATA<40> 5B4<> 6C4< 9C1<> 56D3>
CPU_DATA<31> 5C4<> 9C1<> 56D3>
CPU_DATA<25> 5C4<> 9C1<> 56D3>
CPU_DATA<27> 5C4<> 9C1<> 56D3>
CPU_DATA<22> 5C4<> 9C1<> 56D3>
CPU_DATA<17> 5C4<> 9C1<> 56D3>
CPU_DATA<10> 5D4<> 9D1<> 56D3>
CPU_DATA<13> 5C4<> 9D1<> 56D3>
CPU_DATA<1> 5D4<> 9D1<> 56D3>
CPU_DATA<4> 5D4<> 9D1<> 56D3>
CPU_DATA<53> 5B4<> 9B1<> 9C8< 56D3>
CPU_DATA<47> 5B4<> 6C4< 9B1<> 56D3>
CPU_DATA<45> 5B4<> 6C4< 9B1<> 56D3>

43

4 C3_7

10UF

SM

OMIT

GND 37
Q1 36

3 CLK3

42

SYM_VER3

2 GND

SYSCLK_LA
56D3> 9C1<> 9B7< 5C4<> CPU_DATA<34>
56D3> 9B1<> 5B4<> CPU_DATA<56>
56D3> 9D5< 9B1<> 5B4<> CPU_DATA<59>
56D3> 9C1<> 9B7< 5C4<> CPU_DATA<33>
56D3> 9D5< 9B1<> 5B4<> CPU_DATA<60>
56D3> 9C1<> 5C4<> CPU_DATA<28>
56D3> 9C1<> 5C4<> CPU_DATA<29>
56D3> 9C1<> 5C4<> CPU_DATA<23>
56D3> 9C1<> 5C4<> CPU_DATA<21>
56D3> 9D1<> 5C4<> CPU_DATA<14>
56D3> 9D8< 9B1<> 5B4<> CPU_DATA<50>
56D3> 9D1<> 5D4<> CPU_DATA<2>
56D3> 9D1<> 5D4<> CPU_DATA<5>
56D3> 9D8< 9B1<> 5B4<> CPU_DATA<51>
56D3> 9D1<> 5D4<> CPU_DATA<7>
56D3> 9B1<> 6C4< 5B4<> CPU_DATA<44>
56B3> 8A2<

C969

N20P80%
16V
2 CERM
805

J30

C958

CON_38SM_MICTOR

41

1 GND

CPROBE

N20P80%
10V
2 Y5V
805

2.2UF

40

OMIT

NOTE: INTREPID MAXBUS CONFIG STRAPS MUST DROP


TO 1K OR LOGIC ANALYZER MAY AFFECT STRAP VALUES

CON_38SM_MICTOR

+MAXBUS_SLEEP

C1913
10UF

N20P80%
10V
2 Y5V
805

C1056
10UF

C1057
10UF

N20P80%
2 10V
Y5V
805

N20P80%
2 10V
Y5V
805

C364

10UF

N20P80%
10V
2 Y5V
805

C1914

10UF

N20P80%
10V
2 Y5V
805

C1058
10UF

N20P80%
2 10V
Y5V
805

D0_0 20
GND

INTREPID CLOCK OUTPUT

39 40 41 42 43 44 45

NOSTUFF

J27

U.FL-R_SMT

(519-0698)

F-ST-SM
3

NOSTUFF

R314

CPU CORE DECOUPLING

CPU CORE DECOUPLING

59D7> 59B5> 52C6> 45D2<> 8C1< 4D7< 4D3< CPU_VCORE_SLEEP

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

132S0013

21

CAP,CER,.22UF,20%,6.3V,0402,X5R

SEE_TABLE

C1022
1UF

10%
6.3V
2 CERM
402

SEE_TABLE
1

C1027
1UF

10%
6.3V
2 CERM
402

SEE_TABLE
1

C1011
1UF

10%
6.3V
2 CERM
402

SEE_TABLE
1

C1008
1UF

10%
6.3V
2 CERM
402

SEE_TABLE
1

C1010
1UF

10%
6.3V
2 CERM
402

SEE_TABLE
1

C1025
1UF

BOM OPTION

10%
6.3V
2 CERM
402

1UF

SEE_TABLE

J32

SM12B-SRSS-TB

3
4
5

CPU_PLL_CFG<0> 4D3<
CPU_PLL_CFG<1> 4D3<
CPU_PLL_CFG<2> 4D3<
CPU_PLL_CFG<3> 4C3<
CPU_PLL_CFGEXT 4C3<
NO_TEST

NO_TEST

10
11
12

C1002

C1023
1UF

10%
2 6.3V
CERM
402

SEE_TABLE
1

C1017
1UF

10%
2 6.3V
CERM
402

SEE_TABLE
1

C1031
1UF

10%
2 6.3V
CERM
402

10%
2 6.3V
CERM
402

C997

+3V_MAIN

1UF

SEE_TABLE

6C6<
6C6<

C996

SEE_TABLE
1

1UF

C1012
1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

SEE_TABLE
1

C1024
1UF

10%
6.3V
2 CERM
402

SEE_TABLE
1

C1001
1UF

10%
6.3V
2 CERM
402

SEE_TABLE
1

C1028
1UF

10%
6.3V
2 CERM
402

SEE_TABLE
1

C1018
1UF

NC_TESTMODE
NC_LCENABLE

10%
6.3V
2 CERM
402

SEE_TABLE

C1096

10%
6.3V
2 CERM
402

SEE_TABLE
1

C1097 C1901 C1902


1

1UF

10%
6.3V
2 CERM
402

0.1UF

20%
10V
2 CERM
402

0.1UF

20%
10V
2 CERM
402

C1903
0.1UF

20%
10V
2 CERM
402

C1904
0.1UF

20%
10V
2 CERM
402

C1910

22

SYSCLK_LA 8D8<>

J22

52C6> 59C7>
6C5< 6D6< 7A3< 7B3< 7C3< 7C5< 7C7< 8D1<
8D4< 9B7< 9D8< 44B7< 44D1< 44D2< 45D2<> 46D4<

+MAXBUS_SLEEP 4D5<

SM-1
1

NO_TEST

NO_TEST

NO_TEST

JTAG_ASIC_TMS
JTAG_ASIC_TDI
59D7> 35B4<> JTAG_ASIC_TDO
59D7> 35C4< 34B7< JTAG_ASIC_TCK
59C7> 34B7< JTAG_ASIC_TRST_L

0.1UF

R939
10K

R940

10

11

12

13

14

15

16

17

18

19

20

CPU_CHKSTP_OUT_L 4B3> 7B5< 8D5<> 59C7>


CPU_HRESET_L 4B3< 7A3< 7A5< 7B3< 44C2< 44D2<
CPU_SRESET_L 4B3< 7A5< 59C5>
NO_TESTNC_JTAG10
JTAG_CPU_TMS 4C3< 7A5< 59C7>
JTAG_CPU_TDI 4C3< 7A5< 59C7>
JTAG_CPU_TDO 4C3> 59C7>
JTAG_CPU_TCK 4C3< 7D5< 59C7>
JTAG_CPU_TRST_L 4C3< 7C5< 59C7>

LA CONS & ESP


59C7>

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:29:27 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

1K

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

SIZE

(511S0018)
APPLE COMPUTER INC.

D
SCALE

(518S0105)

56B3>

NOSTUFF

1%
1/16W
MF
402 2

NC_JTAG7

20%
10V
2 CERM
402

INT_ANALYZER_CLK

5%
1/16W
MF
402

59D7> 35B4<> 35A2< 34B7<


59D7> 34B7< 28C6<

NOSTUFF

59A7> 56B3> 54A7< 16C7< 9B4<

10%
6.3V
2 CERM
402

10K

(518S0104)

R313

SEE_TABLE
1

5%
1/16W
MF
402 2

1_25GHZ_DECOUP

R9371

6C6<
6C6<

1UF

13

SEE_TABLE

6C6<

NC_FMAX7
NC_FMAX8
PWR_SWITCH* 44B1< 44C5<> 59D5>
PMU_RST* 29B3<> 44A5<> 44B5<> 59D5>
NO_TEST
NC_RESET_BUTTON_L

SEE_TABLE

1UF

10%
2 6.3V
CERM
402

C1009
1UF

F-RT-SM
14

CAP,CER,1UF,10%,6.3V,0402,X5R

PULLDOWN ON TRST* STRONGER TO OVERCOME POSSIBLE LEAKAGE

NOSTUFF

47

C1022,C1027,C1011,C1008,C1010,C1025,C1009,C1002,C1023,C1017,C1031,C997,C996,C1012,C1024,C1001,C1028,C1018,C1096,C1097,C1098

FMAX DEBUG CONNECTOR

21

R308

CLOSE TO INTREPID

TABLE_5_ITEM

138S0541

10%
6.3V
2 CERM
402

NOSTUFF
1

PLACE BOTH RESISTORS

C1022,C1027,C1011,C1008,C1010,C1025,C1009,C1002,C1023,C1017,C1031,C997,C996,C1012,C1024,C1001,C1028,C1018,C1096,C1097,C1098

C1098

56B3> INT_CLOCK_OUT

1GHZ_DECOUP

SEE_TABLE
1

5%
1/16W
MF
402

TABLE_5_ITEM

1
TABLE_5_HEAD

DRAWING NUMBER

REV.

051-6569 A
8
69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

7
INTREPID BOOT STRAPS

R720
4.7 2
1

+1_5V_INTREPID_PLL

52D3> 30D5< 28D6<> 16D6<

C854
0.1UF

5%
1/16W
MF
402

20%
10V
CERM 2
402

52C6> 46D4< 45D2<>


8D4< 8D1< 8A3<>
7A3< 6D6< 6C5< 4D5< +MAXBUS_SLEEP
7C7< 7C5< 7C3< 7B3<
44D2< 44D1< 44B7< 9B7<
59C7>

NOSTUFF
1
1%
1/16W
MF
2 402

R890
10K

NOSTUFF
1

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

R868
10K

NOSTUFF
1

56D3> 9B1<> 8C7<> 5B4<>


56D3> 9B1<> 8D7<> 5B4<>
56D3> 9B1<> 8C5<> 5B4<>

NOSTUFF
1

NOSTUFF
1

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

R832
10K

NOSTUFF
1

R876
10K

1%
1/16W
MF
402 2

56D3> 9B1<> 8C8<> 5B4<>


56D3> 9B1<> 8C5<> 5B4<>

R892
10K

NOSTUFF
1

NOSTUFF
1

R865
10K

1%
1/16W
MF
402 2

R863
10K

1%
1/16W
MF
402 2

R340
10K

1%
1/16W
MF
402 2

CPU_DATA<57>
CPU_DATA<58>
CPU_DATA<59>
CPU_DATA<60>
CPU_DATA<61>
CPU_DATA<62>
CPU_DATA<63>
NOSTUFF
1

R894
4.7K

R358
4.7K

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

NOSTUFF
1

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

R354
4.7K

8D5<> 9B1<>
8D4<> 9B1<>
8D8<> 9B1<>
8D8<> 9B1<>
8D4<> 9B1<>
8D4<> 9B1<>
8D5<> 9B1<>

R341
4.7K

5%
1/16W
MF
2 402
1

5B4<>
56D3>
5B4<>
56D3>
5B4<>
56D3>
5B4<>
56D3>
5B4<>
56D3>
5B4<>
56D3>
5A4<>
56D3>

R338
4.7K

5%
1/16W
MF
2 402

R886
4.7K

R352
4.7K

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402
1

R351
4.7K

R870
4.7K

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

PROCESSOR BUS MODE


0: MAX BUS (G4)
1: 60X BUS (G3)

FIREWIRE PHY INTERFACE


0: LEGACY INTERFACE
1: B-MODE INTERFACE

PCI1_REQ0_L / PCI1_GNT0_L
0: REQ/GNT
1: GPIOS

PCI1_REQ1_L / PCI1_GNT1_L
0: REQ/GNT
1: GPIOs

PCI1_REQ2_L / PCI1_GNT2_L
0: REQ/GNT
1: GPIOs

ROM_Ovrly_Rng
0: 0 IDE / 1 PCI1
1: 0-1 IDE / 2-3 PCI1

SPARE

SPARE

TI 1394B WORKAROUND
0: NORMAL 1394B
1: TI PHY WORKAROUND

EN_PCI_ROM_P
0: BOOTROM ON IDE/CARDSLOT
1: BOOTROM ON PCI1

SELPLL4EXTSRC
0: PLL5
1: EXTERNAL SOURCE

BUF_REF_CLK_OUTENABLE_H
0: INACTIVE
1: ACTIVE

MAXBUS OUTPUT
IMPEDANCE
111: 28.6 OHM
011: 33.3 OHM
101: 40 OHM
001: 50 OHM
110: 66.6 OHM
010: 100 OHM
100: 200 OHM
000: 200 OHM

R360
4.7K

5%
1/16W
MF
2 402
1

R366
4.7K

R343
4.7K

5%
1/16W
MF
2 402
1

5%
1/16W
MF
402 2

45D2<> 44D2< 44D1< 44B7<


7C3< 7B3< 7A3< 6D6< 6C5< 4D5< +MAXBUS_SLEEP
9D8< 8D4< 8D1< 8A3<> 7C7< 7C5<
59C7> 52C6> 46D4<

R893
4.7K

5%
1/16W
MF
2 402

R3591
4.7K

NOSTUFF
1

R355
4.7K

5%
1/16W
MF
2 402

NOSTUFF
1

NOSTUFF
1

NOSTUFF
1

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

R852
10K

INT_V1
1

56D3> 9C1<> 8D4<>

D25
A27
E24
G23
B26
A26
D23
A25
E23
J22
B25
H22
G22
D22
B24
B23
E22
J21
G21
E21
A24
D21
A23
H20
B22
H21
A22
E20
B21
D20
A21

56D3> 8B4<> 7B7< 4B7> CPU_TBST_L

A28

G26

G24

D26
E25
G25
B28
D27
J25
D28

QREQ

56C3> 8B4<> 4C3< CPU_QACK_L

G27

INT_SUSPEND_REQ_L
INT_SUSPEND_ACK_L

AK9

QACK
SUSPENDREQ
SUSPENDACK

44B8<>
44B5<>

R764
10 2
1

INT_ANALYZER_CLK

INT_V1

AM8

56C3> INT_CPU_FB_IN
56C3> INT_CPU_FB_OUT

5%
1/16W
MF
2 402

ADDS 2"
(0.35 NS)
56C3>

R3531
4.7K

R3441
4.7K

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

CPU_FB_PLUS3

56B3>

5%
1/16W
MF
2 402

INT_V2

ADDS 1"
(0.17 NS)

NOSTUFF
1

R772
0

CPU_FBI_PLUS1
NOSTUFF

SPARE

EXTPLL_SDWN_POL
0: ACTIVE HIGH
1: ACTIVE LOW

DDR_TPDEN_POL
0: ACTIVE HIGH
1: ACTIVE LOW

ANALYZERCLK_EN_H
0: INACTIVE
1: ACTIVE

DDR_TPDMODEENABLE_H
0: TDI INPUT (JTAG)
1: TDI OUTPUT

SYSCLK_CPU

R861
4.7K

56C3>

CPU_FB_PLUS2

5%
1/16W
MF
2 402

R713
0 2
1

CPU_FB_IN
H16
CPU_FB_OUT
G8
ANALYZER_CLK

CPU_CLK_EN

AH9

R321
0 2

5%
1/16W
MF
402 2
1

5%
1/16W
MF
402

R776
0

R319
0 2
1

CPU_FBO_PLUS1

5%
1/16W
MF
402

NOSTUFF
1

NOSTUFF

R310
0 2

CPU_FB_MINUS3

56C3>

5%
1/16W
MF
402

56C3>

R777
0 2

5%
1/16W
MF
402

ADDS 3"
(0.5 NS)

R757
0

5%
1/16W
MF
2 402

R765
0 2
1
5%
1/16W
MF
402

5%
1/16W
MF
2 402

H13

56C3> SYSCLK_CPU_UF

5%
1/16W
MF
402

7C5< 4C3<

AACK
ARTRY
HIT

J24

INT_ANALYZER_CLKA
44C4<>

MAXBUS
INTERFACE

CI
GBL
TBST
TSIZ_0
TSIZ_1
TSIZ_2
TT_0
TT_1
TT_2
TT_3
TT_4
WT

A32

R345
4.7K

(1 OF 9)

A_0
A_1
A_2
A_3
A_4
A_5
A_6
A_7
A_8
A_9
A_10
A_11
A_12
A_13
A_14
A_15
A_16
A_17
A_18
A_19
A_20
A_21
A_22
A_23
A_24
A_25
A_26
A_27
A_28
A_29
A_30
A_31

56C3> 8B7<> 7D5< 4C3> CPU_QREQ_L

H23

INTREPID_ACS_REF

R342
4.7K

TS

B31

5%
1/16W
MF
402

(ON PAGE 12)

CPU_HIT_L

1%
1/16W
MF
402 2

56C3> 4D2<

BR
BG

56C3> 8B5<> 7B7< 4A7< CPU_AACK_L


56C3> 8B8<> 7C7< 4A7<> CPU_ARTRY_L
56C3> 8B8<> 7C7< 4A7>

59A7> 56B3> 54A7< 16C7< 8A2<

H24

D_0
D_1
D_2
D_3
D_4
D_5
D_6
D_7
D_8
D_9
D_10
D_11
D_12
D_13
D_14
D_15
D_16
D_17
D_18
D_19
D_20
D_21
D_22
D_23
D_24
D_25
D_26
D_27
D_28
D_29
D_30
D_31
D_32
D_33
D_34
D_35
D_36
D_37
D_38
D_39
D_40
D_41
D_42
D_43
D_44
D_45
D_46
D_47
D_48
D_49
D_50
D_51
D_52
D_53
D_54
D_55
D_56
D_57
D_58
D_59
D_60
D_61
D_62
D_63

BGA
SEE_TABLE

B29

56D3> 9C1<> 8D7<> 5C4<>


56D3> 9C1<> 8D8<> 5C4<>
56D3> 9C1<> 8D8<>
56D3> 9C1<> 8D7<>

D24

CPU_TSIZ<0>
CPU_TSIZ<1>
56D3> 8B7< 4B7> CPU_TSIZ<2>
56D3> 8B4<> 7A7< 4B7<> CPU_TT<0>
56D3> 8B5<> 7A7< 4B7<> CPU_TT<1>
56D3> 8B4<> 7A7< 4B7<> CPU_TT<2>
56D3> 8B5<> 7A7< 4B7<> CPU_TT<3>
56D3> 8B4<> 7A7< 4B7<> CPU_TT<4>
56C3> 8B5<> 7A7< 4B7> CPU_WT_L

R862
10K

CPU_DATA<32>
CPU_DATA<33>
5C4<> CPU_DATA<34>
5C4<> CPU_DATA<35>
5C4<> CPU_DATA<36>

B27

A29

R853
10K

1%
1/16W
MF
402 2

CPU_TS_L

56C3> 8C5<> 7A7< 4A7> CPU_CI_L


56C3> 7B7< 4B8< CPU_INT_GBL_L

NOSTUFF
1

R854
10K

E26

56D3> 8B5<> 4B7>


56D3> 8B5<> 4B7>

BITS 32 - 39
R833
10K

H26

VDD15A_7
(PLL6)

E29

CPU_ADDR<0>
CPU_ADDR<1>
56D3> 8B4<> 4C7<> CPU_ADDR<2>
56D3> 8B8<> 4C7<> CPU_ADDR<3>
56D3> 8B5<> 4C7<> CPU_ADDR<4>
56D3> 8B7<> 4C7<> CPU_ADDR<5>
56D3> 8C4<> 4C7<> CPU_ADDR<6>
56D3> 8B7<> 4C7<> CPU_ADDR<7>
56D3> 8C5<> 4C7<> CPU_ADDR<8>
56D3> 8B8<> 4C7<> CPU_ADDR<9>
56D3> 8B8<> 4C7<> CPU_ADDR<10>
56D3> 8C4<> 4C7<> CPU_ADDR<11>
56D3> 8B7<> 4C7<> CPU_ADDR<12>
56D3> 8B8<> 4C7<> CPU_ADDR<13>
56D3> 8B7<> 4C7<> CPU_ADDR<14>
56D3> 8B7<> 4C7<> CPU_ADDR<15>
56D3> 8B8<> 4C7<> CPU_ADDR<16>
56D3> 8B8<> 4C7<> CPU_ADDR<17>
56D3> 8C8<> 4C7<> CPU_ADDR<18>
56D3> 8B7<> 4C7<> CPU_ADDR<19>
56D3> 8B8<> 4C7<> CPU_ADDR<20>
56D3> 8C7<> 4C7<> CPU_ADDR<21>
56D3> 8C7<> 4C7<> CPU_ADDR<22>
56D3> 8C8<> 4C7<> CPU_ADDR<23>
56D3> 8B7<> 4B7<> CPU_ADDR<24>
56D3> 8B8<> 4B7<> CPU_ADDR<25>
56D3> 8C8<> 4B7<> CPU_ADDR<26>
56D3> 8C8<> 4B7<> CPU_ADDR<27>
56D3> 8C7<> 4B7<> CPU_ADDR<28>
56D3> 8C8<> 4B7<> CPU_ADDR<29>
56D3> 8C7<> 4B7<> CPU_ADDR<30>
56D3> 8C7<> 4B7<> CPU_ADDR<31>

1%
1/16W
MF
402 2

INTREPID V1.1 IS 133MHZ ONLY

U25
INTREPID

56D3> 8B4<> 4C7<>


56D3> 8B5<> 4C7<>

R869
10K

CPU_DATA<48>
CPU_DATA<49>
CPU_DATA<50>
CPU_DATA<51>
CPU_DATA<52>
CPU_DATA<53>
CPU_DATA<54>
CPU_DATA<55>

20%
10V
CERM 2
402

INT_PLL6_GND
7C7< 4D7> CPU_BR_L
7B7< 4D7< CPU_BG_L

56D3> 8B7<> 7C7< 4D7<>

NOSTUFF
1

R8551
10K

R885
10K

1%
1/16W
MF
402 2

R339
10K

56D3> 8B4<>
56D3> 8B4<>

52D3>

J15

CPU_TBEN

A31

NOSTUFF
1

R766
0

R712
1K

1%
1/16W
MF
2 402

ACS_REF
CPU_CLK

G12
E11
H11
B9
B8
A9
A8
E12
D11
B10
J13
A10
D12
E13
G13
B11
D13
A11
G14
H14
E14
B12
G15
B13
H15
D14
B14
A12
G16
E15
J16
D15
A14
A13
D16
E16
G17
B15
H17
A15
B16
E17
A16
J18
H18
D17
G18
A17
B17
E18
B18
D18
A18
A19
H19
B19
J19
A20
D19
E19
G19
B20
G20

DBG

A30

CPU_DBG_L

DRDY

G28

CPU_DRDY_L

4C2< 7B7< 8B5<> 56C3>

DTI_0
DTI_1
DTI_2

K25

CPU_DTI<0>
CPU_DTI<1>
CPU_DTI<2>

4C3< 8B7<> 56C3>

TA
TEA

E27

H25

9D3<

4C3< 7B7< 8B8<> 56C3>

D29
B30

4C3< 8B4<> 56C3>


4C3< 8B4<> 56C3>

CPU_TA_L 4C3< 7C7< 8C4<> 56C3>


CPU_TEA_L 4C3< 7B7< 8B5<> 56C3>

E28

NO_TEST

XW47

INTREPID MAX

5%
1/16W
MF
2 402

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:29:28 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

MAIN LOOP IS 3" (0.5 NS)


SHORTER THAN MAXBUS CLOCK

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
9
69
1
SHT

OF

NONE

VIN = INTREPID VCORE (1.7V)


VOUT = MAXBUS RAIL (1.8V)

INT_PLL6_GND

ALLOWS ADJUSTING FB CLOCK FROM -3" (0.5 NS)


TO +2" (0.35 NS) IN 1" (0.17 NS) INCREMENTS
PLACE ALL SERPENTINES ON INTERNAL LAYER

VSSA_7
(PLL6)

TBEN

SM

R752
470

CPU_DATA<0> 5D4<> 8C4<> 56D3>


CPU_DATA<1> 5D4<> 8C7<> 56D3>
CPU_DATA<2> 5D4<> 8C8<> 56D3>
CPU_DATA<3> 5D4<> 8C5<> 56D3>
CPU_DATA<4> 5D4<> 8C7<> 56D3>
CPU_DATA<5> 5D4<> 8C8<> 56D3>
CPU_DATA<6> 5D4<> 8C4<> 56D3>
CPU_DATA<7> 5D4<> 8C8<> 56D3>
CPU_DATA<8> 5D4<> 8C5<> 56D3>
CPU_DATA<9> 5D4<> 8C4<> 56D3>
CPU_DATA<10> 5D4<> 8C7<> 56D3>
CPU_DATA<11> 5C4<> 8C5<> 56D3>
CPU_DATA<12> 5C4<> 8C5<> 56D3>
CPU_DATA<13> 5C4<> 8C7<> 56D3>
CPU_DATA<14> 5C4<> 8C8<> 56D3>
CPU_DATA<15> 5C4<> 8C5<> 56D3>
CPU_DATA<16> 5C4<> 8C4<> 56D3>
CPU_DATA<17> 5C4<> 8C7<> 56D3>
CPU_DATA<18> 5C4<> 8C4<> 56D3>
CPU_DATA<19> 5C4<> 8C4<> 56D3>
CPU_DATA<20> 5C4<> 8C4<> 56D3>
CPU_DATA<21> 5C4<> 8C8<> 56D3>
CPU_DATA<22> 5C4<> 8C7<> 56D3>
CPU_DATA<23> 5C4<> 8C8<> 56D3>
CPU_DATA<24> 5C4<> 8D4<> 56D3>
CPU_DATA<25> 5C4<> 8D7<> 56D3>
CPU_DATA<26> 5C4<> 8C5<> 56D3>
CPU_DATA<27> 5C4<> 8C7<> 56D3>
CPU_DATA<28> 5C4<> 8D8<> 56D3>
CPU_DATA<29> 5C4<> 8C8<> 56D3>
CPU_DATA<30> 5C4<> 8C5<> 56D3>
CPU_DATA<31> 5C4<> 8D7<> 56D3>
CPU_DATA<32> 5C4<> 8D7<> 9B7< 56D3>
CPU_DATA<33> 5C4<> 8D8<> 9B7< 56D3>
CPU_DATA<34> 5C4<> 8D8<> 9B7< 56D3>
CPU_DATA<35> 5C4<> 8D7<> 9B7< 56D3>
CPU_DATA<36> 5C4<> 8D4<> 9A7< 56D3>
CPU_DATA<37> 5B4<> 8D5<> 56D3>
CPU_DATA<38> 5B4<> 8D5<> 56D3>
CPU_DATA<39> 5B4<> 8D5<> 56D3>
CPU_DATA<40> 5B4<> 6C4< 8D7<> 56D3>
CPU_DATA<41> 5B4<> 6C4< 8C4<> 56D3>
CPU_DATA<42> 5B4<> 6C4< 8C5<> 56D3>
CPU_DATA<43> 5B4<> 6C4< 8C4< 56D3>
CPU_DATA<44> 5B4<> 6C4< 8C8<> 56D3>
CPU_DATA<45> 5B4<> 6C4< 8C7<> 56D3>
CPU_DATA<46> 5B4<> 6C4< 8C4<> 56D3>
CPU_DATA<47> 5B4<> 6C4< 8C7< 56D3>
CPU_DATA<48> 5B4<> 8C5<> 9D8< 56D3>
CPU_DATA<49> 5B4<> 8C4<> 9D8< 56D3>
CPU_DATA<50> 5B4<> 8C8<> 9D8< 56D3>
CPU_DATA<51> 5B4<> 8C8<> 9D8< 56D3>
CPU_DATA<52> 5B4<> 8C5<> 9C8< 56D3>
CPU_DATA<53> 5B4<> 8C7<> 9C8< 56D3>
CPU_DATA<54> 5B4<> 8D7<> 9C8< 56D3>
CPU_DATA<55> 5B4<> 8C5<> 9C8< 56D3>
CPU_DATA<56> 5B4<> 8D8<> 56D3>
CPU_DATA<57> 5B4<> 8D5<> 9D5< 56D3>
CPU_DATA<58> 5B4<> 8D4<> 9D5< 56D3>
CPU_DATA<59> 5B4<> 8D8<> 9D5< 56D3>
CPU_DATA<60> 5B4<> 8D8<> 9D5< 56D3>
CPU_DATA<61> 5B4<> 8D4<> 9C5< 56D3>
CPU_DATA<62> 5B4<> 8D4<> 9C5< 56D3>
CPU_DATA<63> 5A4<> 8D5<> 9C5< 56D3>

D10

STOPCPUCLK

5%
1/16W
MF
2 402

9A2<>

R864
10K

56D3> 9B1<> 8C4<> 5B4<>


56D3> 9B1<> 8C8<> 5B4<>

+1_5V_INTREPID_PLL7
C1101
0.1UF

BITS 48 - 63

NOSTUFF
1

56D3> 9B1<> 8C5<> 5B4<>

DRAWING

<XR_PAGE_TITLE>

INTREPID 1.1 SHOULD ALLOW MAXBUS


RAIL TO TURN OFF IN SLEEP
52C3> 46B4<> 17D5< 17A4< 17A3< 16D7< 16C2< 16A8< 11A6<
59C7>

+3V_MAIN

AA25
C12

AA29

C15

AB25

C18

AB27

AGP_IO_VDD

VDD3.3

SP2

SP3

SP4

CLIP-SM

CLIP-SM

CLIP-SM

CLIP-SM

EMI-SPRING

EMI-SPRING

EMI-SPRING

EMI-SPRING

SEE_TABLE

SEE_TABLE

SEE_TABLE

SEE_TABLE

AL10

AK6

AH6

AH3

AF25

AE6

AE3

AE17

AE15

AD21

AC14

G6

G3

F9

F7

F30

AC13

AC12

AB6

AB3

AA12

AA11

AR34

AR33

AP31

AP28

AP25

AP22

AP19

AN32

AL30

AL28

AL22

AL19

AJ23

AJ21

AH28

AH22

AH19

AF22

AE23

+2_5V_MAIN

AD20

+1_8V_MAIN

+INTREPID_CORE_MAIN

AE20

59C7> 47B2<> 46B3< 11D3<

SP1

+1_5V_AGP

CLIPS TO ATTACH INTREPID


HEATSINK TO GND AT THE
FOUR CORNERS

AL13

AL16
AL3

C24

AB31
AM4
AB34

BGA
(8 OF 9)
SEE_TABLE

C27
C30

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

870-1125

INTREPID EMI CLIP

SP1,SP2,SP3,SP4

BOM OPTION

AN5
AC25
AA21
AA24
AC28
AE31

AB13
AE34

F18

AF28

F21

AH30

F24

AH34

AB17

VDD1.8/CPUVIO

AP13
AP16

BGA
(9 OF 9)
SEE_TABLE

AB15
F15

AP10

U25
INTREPID

AC27

C9
F12

F27

INTREPID EMI CLIP SUPPORT

AL7

U25
INTREPID

C21

K3

AB19

K6
N24

AC17

N3

AC19

N6

AC23

P13

AK34

M15

AP35
AD13

M16

C35

M19

G31

P14

POWER

AD15

R22

AD22
M22

G34

M23

K31

T12

P15

T18

P18

T3

K34

N18

VDD3.3

P20
N21

VDD2.5

N28
P21
N31

N23
P16

N34

P19

N36

W12

R20

W13

T13

W3

U17

W6

U18

AP2

U24

AP7

V16

AR3

V19

B3

V20

C2

V22

C6

W16

D32

W24

D5

Y13

B34

Y18

E4

P25

T6
U12

VDD1.5

R17

P28

POWER/GROUND

R25
R27
T25
T28
T29
T31
T34
U25
U28
L24

V25

M14

V29

M17

W25

M18

W31

M20

W34

M21

Y27

M24

Y29

M28

E33

AD3

AD34

M31

AN33

M32

AN4

AD6

M34

AP1

AE14

M6

AP12

AE16

GROUND

M9

AP15

AE18

N15

AP18

AE19

N25

AP21

AE21

U19

P12

AP24

AE22

U22

P17

AP27

AE28

U27

P22

AP3

AG21

U29

P29

AP30

AG23

V10

P4

AP33

AG24

V12

R14

AP34

AG3

V17

R16

AP36

AG30

R18

AP6

AG34

VSS

V21

AP9

AG6

R21

AR2

AH20

V3

R23

AR35

AH21

V31

R24

AT3

AH23

V34

R26

AT34

AH27

V6

R29

B2

R19

VSS

V24

VSS

INTREPID VERSION SUPPORT


PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

343S0198

IC,ASIC,INTREPID,V1.X

U25

343S0211

IC,ASIC,INTREPID,V2.1

U25

AK3

W14

R31

C1

AK7

W23

R34

C10

AL12

W26

R6

C13

AL15

Y11

T11

C16

AL18

Y12

T14

C19

AL21

Y14

T23

C22

AL27

Y16

T24

C25

AL31

Y19

T27

C28

AL34

Y23

U10

C3

AL6

Y24

U16

C31

AL9

BOM OPTION
INT_V1

CRITICAL

INT_V2

INTREPID POWER

Y25

C34

CRITICAL

W11

B35

R3

V18

VSS

NOTICE OF PROPRIETARY PROPERTY

AD25

AD23

AD12

AC26

AC22

AC20

AC18

AC16

AC15

AC11

AB29

AB28

AB24

AB18

AB16

AB14

AB12

AB11

AA6

AA34

AA31

AA3

AA27

AA20

A34

C7

C36

D4

D33

F10

F13

F16

F19

F22

F25

F3

F28

F6

F31

F34

G7

J3

J31

J6

J34

AGP_IO_VSS
A3

AD28

AD31

M3

LAST_MODIFIED=Mon Oct 27 12:29:30 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
10 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

C289
10UF

C288
10UF

N20P80%
10V 2
Y5V
805

N20P80%
10V
Y5V 2
805

C291
10UF

C290
10UF

N20P80%
10V 2
Y5V
805

C890
0.1UF

20%
2 10V
CERM
402

N20P80%
10V
Y5V 2
805

C832
0.1UF

20%
2 10V
CERM
402

C901
0.1UF

20%
10V
2 CERM
402

C846
0.1UF

C885
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C902
0.1UF

20%
10V
2 CERM
402

C900
0.1UF

20%
2 10V
CERM
402

C888
0.1UF

20%
2 10V
CERM
402

C823
0.1UF

20%
10V
2 CERM
402

C887
0.1UF

20%
2 10V
CERM
402

C843
0.1UF

C891
0.1UF

20%
2 10V
CERM
402

C845
0.1UF

20%
10V
2 CERM
402

20%
2 10V
CERM
402

C277
10UF

C240
10UF

N20P80%
10V
Y5V 2
805

N20P80%
10V 2
Y5V
805

C271
10UF

C641
10UF

N20P80%
10V
Y5V 2
805

N20P80%
10V 2
Y5V
805

C700
0.1UF

20%
10V
2 CERM
402

C824
0.1UF

20%
2 10V
CERM
402

C871
0.1UF

C834
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C870
0.1UF

C897
0.1UF

C889
0.1UF

20%
2 10V
CERM
402

C874
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C884
0.1UF

C896
0.1UF

20%
10V
2 CERM
402

C898
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C842
0.1UF

C895
0.1UF

C869
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C278
0.1UF

C849
0.1UF

C281
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

59C7> 47B2<> 46B3< 10D6<

C872
0.1UF

20%
2 10V
CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C844
0.1UF

C280
0.1UF

20%
10V
2 CERM
402

20%
2 10V
CERM
402

C899
0.1UF

C878
0.1UF

C725
0.1UF

C836
0.1UF

C817
0.1UF

C839
0.1UF

C886
0.1UF

20%
10V
2 CERM
402

C837
0.1UF

20%
2 10V
CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C877
0.1UF

C688
0.1UF

C767
0.1UF

C793
0.1UF

C815
0.1UF

20%
2 10V
CERM
402

20%
10V
2 CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C856
0.1UF

C735
0.1UF

C722
0.1UF

C750
0.1UF

C753
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C801
0.1UF

C825
0.1UF

C838
0.1UF

C723
0.1UF

20%
10V
2 CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C699
0.1UF

C751
0.1UF

C826
0.1UF

C752
0.1UF

C292
10UF

C727
10UF

C841
10UF

N20P80%
10V 2
Y5V
805

N20P80%
10V
Y5V 2
805

N20P80%
10V
Y5V 2
805

C873
0.1UF

C279
0.1UF

C787
0.1UF

20%
2 10V
CERM
402

C789
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C764
0.1UF

20%
10V
2 CERM
402

C831
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C746
0.1UF

C730
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C655
10UF

C892
10UF

N20P80%
10V
Y5V 2
805

C794
0.1UF

20%
10V
2 CERM
402

C904
0.1UF

20%
2 10V
CERM
402

C687
0.1UF

20%
10V
2 CERM
402

C803
0.1UF

20%
10V
2 CERM
402

C768
0.1UF

20%
10V
2 CERM
402

C855
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C827
0.1UF

20%
10V
2 CERM
402

C876
0.1UF

20%
2 10V
CERM
402

20%
10V
2 CERM
402

C792
0.1UF

20%
10V
2 CERM
402

C714
0.1UF

20%
10V
2 CERM
402

C668
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C791
0.1UF

20%
10V
2 CERM
402

C802
0.1UF

20%
10V
2 CERM
402

C818
0.1UF

20%
2 10V
CERM
402

C755
0.1UF

20%
2 10V
CERM
402

20%
10V
2 CERM
402

C816
0.1UF

C814
0.1UF

C754
0.1UF

C724
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C880
0.1UF

N20P80%
10V 2
Y5V
805

C264
10UF

C637
10UF

N20P80%
10V
Y5V 2
805

N20P80%
10V 2
Y5V
805

C698
0.1UF

C745
0.1UF

20%
10V
2 CERM
402

C736
0.1UF

20%
10V
2 CERM
402

C796
0.1UF

C867
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C720
0.1UF

C728
0.1UF

C231
10UF

20%
10V
2 CERM
402

C813
0.1UF

C781
0.1UF

20%
10V
2 CERM
402

C232
10UF

N20P80%
10V
Y5V 2
805

C697
0.1UF

C693
0.1UF

C684
0.1UF

20%
2 10V
CERM
402

C765
0.1UF

20%
10V
CERM
402

C788
0.1UF

20%
2 10V
CERM
402

C800
0.1UF

20%
2 10V
CERM
402

C808
0.1UF

20%
10V
2 CERM
402

C734
0.1UF

20%
2 10V
CERM
402

C850
0.1UF

C810
0.1UF

20%
2 10V
CERM
402

C763
0.1UF

20%
10V
2 CERM
402

C748
0.1UF

20%
2 10V
CERM
402

C766
0.1UF

20%
2 10V
CERM
402

C780
0.1UF

20%
10V
2 CERM
402

C811
0.1UF

20%
2 10V
CERM
402

C731
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C798
0.1UF

20%
10V
2 CERM
402

C779
0.1UF

20%
10V
2 CERM
402

C747
0.1UF

20%
2 10V
CERM
402

C732
0.1UF

D
C790
0.1UF

20%
10V
2 CERM
402

C799
0.1UF

20%
2 10V
CERM
402

C775
0.1UF

C806
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C863
0.1UF

C868
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C680
0.1UF

C894
0.1UF

C717
0.1UF

20%
10V
2 CERM
402

C866
0.1UF

C829
0.1UF

20%
10V
2 CERM
402

C762
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C821
0.1UF

C822
0.1UF

C689
0.1UF

C691
0.1UF

C777
0.1UF

C812
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C643
0.1UF

C656
0.1UF

C774
0.1UF

C718
0.1UF

20%
10V
CERM
402

20%
2 10V
CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C743
0.1UF

C761
0.1UF

20%
2 10V
CERM
402

C776
0.1UF

20%
2 10V
CERM
402

C807
0.1UF

20%
2 10V
CERM
402

C883
0.1UF

20%
2 10V
CERM
402

C707
0.1UF

20%
10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
10V
2 CERM
402

C744
0.1UF

C828
0.1UF

20%
10V
2 CERM
402

C712
0.1UF

C835
0.1UF

C729
0.1UF

20%
10V
2 CERM
402

C865
0.1UF

20%
10V
2 CERM
402

C645
0.1UF

20%
10V
2 CERM
402

C644
0.1UF

20%
10V
2 CERM
402

C805
0.1UF

20%
10V
2 CERM
402

C716
0.1UF

20%
10V
2 CERM
402

C676
0.1UF

20%
10V
2 CERM
402

C881
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C679
0.1UF

C677
0.1UF

C708
0.1UF

C681
0.1UF

20%
2 10V
CERM
402

C673
0.1UF

20%
2 10V
CERM
402

C903
0.1UF

20%
2 10V
CERM
402

C879
0.1UF

20%
2 10V
CERM
402

C682
0.1UF

20%
2 10V
CERM
402

C678
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C657
0.1UF

C851
0.1UF

C875
0.1UF

C659
0.1UF

C690
0.1UF

C658
0.1UF

C852
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
2 10V
CERM
402

C893
0.1UF

C882
0.1UF

C660
0.1UF

20%
2 10V
CERM
402

C646
0.1UF

20%
10V
2 CERM
402

21 Balls
4 X 10UF (0805)
24 X 0.1UF (0402)

INTREPID AGP I/O DECOUPLING


1

C719
0.1UF

C809
0.1UF

20%
10V
2 CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

N20P80%
10V
Y5V 2
805

57 Balls
4 X 10UF (0805)
66 X 0.1UF (0402)

20%
10V
2 CERM
402

20%
10V
2 CERM
402

+1_5V_AGP

C721
0.1UF

20%
2 10V
CERM
402

C797
0.1UF

20%
2 10V
CERM
402

C833
0.1UF

C830
0.1UF

20%
10V
2 CERM
402

C782
0.1UF

52C3> 46B4<> 17D5< 17A4< 17A3< 16D7< 16C2< 16A8< 10D6<


59C7>

INTREPID 3.3V DECOUPLING

20%
10V
2 CERM
402

C749
0.1UF

+3V_MAIN

20%
2 10V
CERM
402

20%
2 10V
CERM
402

30 Balls
4 X 10UF (0805)
29 X 0.1UF (0402)

+INTREPID_CORE_MAIN

20%
2 10V
CERM
402

20%
10V
2 CERM
402

C857
0.1UF

C702
10UF

N20P80%
10V 2
Y5V
805

44 Balls
4 X 10UF (0805)
51 X 0.1UF (0402)

+2_5V_MAIN
INTREPID DDR DECOUPLING

INTREPID CORE DECOUPLING

24 Balls
4 X 10UF (0805)
36 X 0.1UF (0402)

+1_8V_MAIN
INTREPID MAXBUS DECOUPLING

C686
0.1UF

C709
0.1UF

C649
0.1UF

C667
0.1UF

C694
0.1UF

C695
0.1UF

C664
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

INTREPID BYPASS
A

C638
10UF

N20P80%
10V 2
Y5V
805

C628
10UF

N20P80%
10V 2
Y5V
805

C733
0.1UF

C650
0.1UF

C647
0.1UF

C710
0.1UF

C685
0.1UF

C683
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C665
0.1UF

20%
2 10V
CERM
402

C696
0.1UF

20%
2 10V
CERM
402

C666
0.1UF

20%
2 10V
CERM
402

C651
0.1UF

NOTICE OF PROPRIETARY PROPERTY

20%
2 10V
CERM
402

LAST_MODIFIED=Mon Oct 27 12:29:33 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

C662
0.1UF

20%
10V
2 CERM
402

C661
0.1UF

20%
10V
2 CERM
402

C648
0.1UF

20%
10V
2 CERM
402

C674
0.1UF

20%
10V
2 CERM
402

C711
0.1UF

20%
10V
2 CERM
402

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

C663
0.1UF

20%
10V
2 CERM
402

SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569
A
11 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

DDR MUX CONNECTIONS


0-ohm resistors to allow
rewiring if necessary
MUX_SEL_H
MEM_DATA<0>
MEM_DATA<1>
53D6< 13C8<> MEM_DATA<2>
MEM_DATA<3>
53D6< 13C8<>
53D6< 13C8<> MEM_DATA<4>
53D6< 13C8<> MEM_DATA<5>
53D6< 13C8<> MEM_DATA<6>
53D6< 13C8<> MEM_DATA<7>
53D6< 13C8<> MEM_DATA<8>
53D6< 13C8<> MEM_DATA<9>
53D6< 13C8<> MEM_DATA<10>
53D6< 13C8<> MEM_DATA<11>
53D6< 13C8<> MEM_DATA<12>
53D6< 13C8<> MEM_DATA<13>
53D6< 13C8<> MEM_DATA<14>
53D6< 13C8<> MEM_DATA<15>
53D6< 13B6<> MEM_DATA<16>
53D6< 13B6<> MEM_DATA<17>
53D6< 13B6<> MEM_DATA<18>
53D6< 13B6<> MEM_DATA<19>
53D6< 13B6<> MEM_DATA<20>
53D6< 13B6<> MEM_DATA<21>
53D6< 13B6<> MEM_DATA<22>
53D6< 13B6<> MEM_DATA<23>
53D6< 13A6<> MEM_DATA<24>
53D6< 13A6<> MEM_DATA<25>
53D6< 13A6<> MEM_DATA<26>
53D6< 13A6<> MEM_DATA<27>
53D6< 13A6<> MEM_DATA<28>
53D6< 13A6<> MEM_DATA<29>
53D6< 13A6<> MEM_DATA<30>
53D6< 13A6<> MEM_DATA<31>
53D6< 13C4<> MEM_DATA<32>
53D6< 13C4<> MEM_DATA<33>
53D6< 13C4<> MEM_DATA<34>
53D6< 13C4<> MEM_DATA<35>
53D6< 13C4<> MEM_DATA<36>
53D6< 13C4<> MEM_DATA<37>
53D6< 13C4<> MEM_DATA<38>
53D6< 13C4<> MEM_DATA<39>
53D6< 13C4<> MEM_DATA<40>
53D6< 13C4<> MEM_DATA<41>
53D6< 13C4<> MEM_DATA<42>
53D6< 13C4<> MEM_DATA<43>
53D6< 13C4<> MEM_DATA<44>
53D6< 13C4<> MEM_DATA<45>
53D6< 13C4<> MEM_DATA<46>
53D6< 13C4<> MEM_DATA<47>
53D6< 13B3<> MEM_DATA<48>
53D6< 13B3<> MEM_DATA<49>
53D6< 13B3<> MEM_DATA<50>
53D6< 13B3<> MEM_DATA<51>
53D6< 13B3<> MEM_DATA<52>
53D6< 13B3<> MEM_DATA<53>
53D6< 13B3<> MEM_DATA<54>
53D6< 13B3<> MEM_DATA<55>
53D6< 13B3<> MEM_DATA<56>
53D6< 13B3<> MEM_DATA<57>
53D6< 13B3<> MEM_DATA<58>
53D6< 13B3<> MEM_DATA<59>
53D6< 13B3<> MEM_DATA<60>
53D6< 13B3<> MEM_DATA<61>
53D6< 13B3<> MEM_DATA<62>
53D6< 13B3<> MEM_DATA<63>
53D6< 13C8<>
53D6< 13C8<>

AK32
AK33
AK31
AK35
AK36
AJ32
AJ35
AJ36
AG33
AG35
AH35
AG36
AH36
AH32
AG32
AG31
AE32
AF35
AF36
AE36
AE35
AE33
AD36
AD35
AA36
AA35
AA33
AB36
AB35
AC36
AA32
AB33
V36
U33
U32
V35
T30
U36
U35
T36
P33
R30
P35
P36
R36
R35
R33
R32
N35
M36
L35
M35
M33
L36
N33
M30
J32
J33
J35
K32
K33
J36
K36
K35

DDR_DATA_0
DDR_DATA_1
DDR_DATA_2
DDR_DATA_3
DDR_DATA_4
DDR_DATA_5
DDR_DATA_6
DDR_DATA_7
DDR_DATA_8
DDR_DATA_9
DDR_DATA_10
DDR_DATA_11
DDR_DATA_12
DDR_DATA_13
DDR_DATA_14
DDR_DATA_15
DDR_DATA_16
DDR_DATA_17
DDR_DATA_18
DDR_DATA_19
DDR_DATA_20
DDR_DATA_21
DDR_DATA_22
DDR_DATA_23
DDR_DATA_24
DDR_DATA_25
DDR_DATA_26
DDR_DATA_27
DDR_DATA_28
DDR_DATA_29
DDR_DATA_30
DDR_DATA_31
DDR_DATA_32
DDR_DATA_33
DDR_DATA_34
DDR_DATA_35
DDR_DATA_36
DDR_DATA_37
DDR_DATA_38
DDR_DATA_39
DDR_DATA_40
DDR_DATA_41
DDR_DATA_42
DDR_DATA_43
DDR_DATA_44
DDR_DATA_45
DDR_DATA_46
DDR_DATA_47
DDR_DATA_48
DDR_DATA_49
DDR_DATA_50
DDR_DATA_51
DDR_DATA_52
DDR_DATA_53
DDR_DATA_54
DDR_DATA_55
DDR_DATA_56
DDR_DATA_57
DDR_DATA_58
DDR_DATA_59
DDR_DATA_60
DDR_DATA_61
DDR_DATA_62
DDR_DATA_63

DDR_A_0
DDR_A_1
DDR_A_2
DDR_A_3
DDR_A_4
DDR_A_5
DDR_A_6
DDR_A_7
DDR_A_8
DDR_A_9
DDR_A_10
DDR_A_11
DDR_A_12
DDR_BA_0
DDR_BA_1

U25
INTREPID
BGA
(2 OF 9)
SEE_TABLE

(ON PAGE 12)

DDR
MEMORY
INTERFACE

H35
G35
G36
F36
F35
E35
E36
G32
D36
H36
G33
H33
D35
L30
M29

DDRCS_0
DDRCS_1
DDRCS_2
DDRCS_3

AN34

DDR_DQS_0
DDR_DQS_1
DDR_DQS_2
DDR_DQS_3
DDR_DQS_4
DDR_DQS_5
DDR_DQS_6
DDR_DQS_7

AJ31

DDR_DM_0
DDR_DM_1
DDR_DM_2
DDR_DM_3
DDR_DM_4
DDR_DM_5
DDR_DM_6
DDR_DM_7

AJ33

AN36
AL35
AL33

DDRRAS
DDRCAS
DDRWE
DDRCKE0
DDRCKE1
DDRCKE2
DDRCKE3

AH31
AD32
AB30
V30
P32
N29
L32

AH33
AD33
AC35
T35
T33
N32
L33
L29
H32
K30
AN35
AM35
AM36
AL36
AB32

DDR_SELHI_0
DDR_SELHI_1 AE29
DDR_SELLO_0 N30
DDR_SELLO_1 T32
DDR_MCLK_0_P
DDR_MCLK_0_N
DDR_MCLK_1_P
DDR_MCLK_1_N
DDR_MCLK_2_P
DDR_MCLK_2_N
DDR_MCLK_3_P
DDR_MCLK_3_N
DDR_MCLK_4_P
DDR_MCLK_4_N
DDR_MCLK_5_P
DDR_MCLK_5_N
DDR_REF

MEM_ADDR<0> 12C3< 53D6<


MEM_ADDR<1> 12C3< 53D6<
MEM_ADDR<2> 12C3< 53D6<
MEM_ADDR<3> 12D3< 53D6<
MEM_ADDR<4> 12D3< 53D6<
MEM_ADDR<5> 12C2< 53D6<
MEM_ADDR<6> 12D2< 53D6<
MEM_ADDR<7> 12D3< 53D6<
MEM_ADDR<8> 12D2< 53D6<
MEM_ADDR<9> 12C3< 53D6<
MEM_ADDR<10> 12C3< 53D6<
MEM_ADDR<11> 12B3< 53D6<
MEM_ADDR<12> 12D2< 53D6<
MEM_BA<0> 12B3< 53D6<
MEM_BA<1> 12B3< 53D6<
MEM_CS_L<0>
MEM_CS_L<1>
MEM_CS_L<2>
MEM_CS_L<3>

MEM_DQM<0>
MEM_DQM<1>
MEM_DQM<2>
MEM_DQM<3>
MEM_DQM<4>
MEM_DQM<5>
MEM_DQM<6>
MEM_DQM<7>

13C8<> 53D6<
13C8<> 53D6<

W30

5%
1/16W
MF
402

13B3<> 53D6<

NO_TEST

13C4<> 53D6<
13C4<> 53D6<
13B3<> 53D6<
13B3<> 53D6<

SYSCLK_DDRCLK_A0

MEM_ADDR<2>

SYSCLK_DDRCLK_A2_UF

53D6< 12D6<>

SYSCLK_DDRCLK_A0_L

MEM_ADDR<1>

14D6<> 53C6<

53D6< 12D6<>

SYSCLK_DDRCLK_A1

MEM_ADDR<0>

RP62
22

RP62
22

RP62
22
4

MEM_ADDR<9>

RP105
22

SYSCLK_DDRCLK_A2_L_UF

NO_TEST

NC_SYSCLK_DDRCLK_A2

MEM_BA<1>

RP116
22 8
1

RAM_ADDR<2>

NO_TEST

SYSCLK_DDRCLK_B0_UF

RP105
22 6

NC_SYSCLK_DDRCLK_A2_L MEM_BA<0>
53D6< 12D6<>

53C6< 12C6<>

RAM_ADDR<1>

MEM_ADDR<6>

RP105
22 5

RP109
22 5

MEM_WE_L

53D6< 12D6<>

MEM_ADDR<11>

SYSCLK_DDRCLK_B0_L

15B3> 53B6<

RP109
22 6

RAM_ADDR<0>

MEM_CKE<2>

SYSCLK_DDRCLK_B2_UF

RP109
22 8
1

SYSCLK_DDRCLK_B2_L_UF

RP109
22 7
2

MEM_CS_L<0>

RAM_ADDR<9>

RP116
22

14B6<> 15C6< 53D6<

53C6< 12C6<>

RP71
22

RP51
22

RP51
22

RP51
22

MEM_CS_L<1>

RP51
22

RAM_ADDR<6>

14B4<> 15C4> 53D6<

RAM_ADDR<5>

14B6<> 15C6< 53D6<

RAM_CKE<2>

RAM_CS_L<0>

RAM_CKE<0>

15B1< 15C6<
53C6<

14B6<>
53C6<

14B4<> 15C1<
53C6<

RAM_CS_L<1>

5%
1/16W
SM1

R1371

MEM_CS_L<3>

RP52
22

14B4<>
53C6<

R214

10K

10K

1%
1/16W
MF
402 2

1%
1/16W
MF
2 402

NOSTUFF

14B4<> 15B6< 53D6<

NOSTUFF

RAM_CS_L<3>

RAM_CKE<3>

RAM_CS_L<2>

RAM_CKE<1>

15B4> 53C6<

5%
1/16W
SM1

14B6<> 15B6< 53D6<


53C6< 12B6<>

RAM_WE_L 14B6<>

5%
1/16W
SM1

MEM_CKE<0>

MEM_CKE<3>

RP52
22
5%
1/16W
SM1

15B6< 53C6<
53C6< 12C6<>

MEM_CS_L<2>

RP52
22

15A1< 15C4>
53C6<

B
15B4> 53C6<

5%
1/16W
SM1
5

RAM_ADDR<11>

5%
1/16W
SM1

14B4<> 15C4> 53D6<


53C6< 12B6<>

MEM_CKE<1>

SYSCLK_DDRCLK_B1

RP52
22

R1721

14B6<> 15C1<
53C6<

53C6< 12C6<>

SYSCLK_DDRCLK_B1_L

MEM_RAS_L

R697
22 2
1

RAM_RAS_L

14B4<> 15B4> 53C6<

R235

15C6< 53B6<

MEM_CAS_L

R286
22 2

10K

1%
1/16W
MF
402 2

1%
1/16W
MF
2 402

NOSTUFF

5%
1/16W
MF
402

53C6< 12C6<>

SYSCLK_DDRCLK_B2

10K

15D6< 53B6<

RAM_CAS_L

NOSTUFF

14B4<> 15B6< 53C6<

5%
1/16W
MF
402

15A6< 53B6<

INTREPID DDR CNTRL


SYSCLK_DDRCLK_B2_L

NOTICE OF PROPRIETARY PROPERTY

15A6< 53B6<

LAST_MODIFIED=Mon Oct 27 12:29:35 2003

5%
1/16W
SM1

14D2<> 14D8<> 15D8< 52A6>

5%
1/16W
SM1

RAM_BA<0>

RP116
22 6
3

14B4<> 15B6< 53D6<

53C6< 12C6<>

53C6< 12C6<>

0.1UF

20%
10V
2 CERM
402

RP71
22

5%
1/16W
SM1

5%
1/16W
SM1

C30

14B4<> 15C4> 53D6<

5%
1/16W
SM1

5%
1/16W
SM1

SYSCLK_DDRCLK_B1_L_UF

RAM_ADDR<8>

5%
1/16W
SM1

MEM_ADDR<5>

5%
1/16W
SM1

1K

C14

14B6<> 15B6< 53D6<

53C6< 12C6<>

RAM_BA<1>

RP116
22 7
2

15B4> 53B6<

5%
1/16W
SM1

14B6<> 15C4> 53D6<

5%
1/16W
SM1

5%
1/16W
SM1

SYSCLK_DDRCLK_B0

RAM_ADDR<12>

5%
1/16W
SM1

14B4<> 15C6< 53D6<

53C6< 12B6<>

5%
1/16W
SM1

5%
1/16W
SM1

R625

LOCATE 2 DECOUPLING CAPS


DIRECTLY AT DDR_VREF_X BALLS
(U25-Y22 & T22)
DDR_VREF

5%
1/16W
SM1

14A4<> 53C6<

53D6< 12D6<>

SYSCLK_DDRCLK_B0_L_UF

RP71
22

14B6<> 15B4> 53D6<

53D6< 12D6<>

5%
1/16W
SM1

14A4<> 53C6<

SYSCLK_DDRCLK_A1_L

RP62
22

5%
1/16W
SM1

MIN_LINE_WIDTH=20

RAM_ADDR<10>

5%
1/16W
SM1

5%
1/16W
SM1

INT_MEM_REF

20%
10V
2 CERM
402

1%
1/16W
MF
2 402

5%
1/16W
SM1

14D6<> 53C6<

53D6< 12D6<>

RP105
22 8
1

0.1UF

100

R93

MEM_ADDR<10>

14B6<> 15C6< 53D6<

53D6< 12D6<>

5%
1/16W
SM1

MEM_ADDR<8>

5%
1/16W
SM1

R82

RP102
22

SYSCLK_DDRCLK_A1_L_UF

53D6< 12D6<>

5%
1/16W
SM1

53B6< SYSCLK_DDRCLK_B2_L_UF

MIN_LINE_WIDTH=25

+2_5V_MAIN

RP102
22 6
3

SYSCLK_DDRCLK_A1_UF

+2_5V_MAIN

RP68
22
4

5%
1/16W
SM1

SYSCLK_DDRCLK_B1_UF

INT_MEM_VREF

RP102
22 7
2

SYSCLK_DDRCLK_A0_L_UF

53B6< SYSCLK_DDRCLK_B1_L_UF
53B6< SYSCLK_DDRCLK_B2_UF

AA22

RAM_ADDR<7>

RP71
22

14B6<> 15C4> 53D6<

53D6< 12D6<>

5%
1/16W
SM1

5%
1/16W
SM1

1%
1/16W
MF
2 402

14A1<

RP102
22 8
1

SYSCLK_DDRCLK_A0_UF

53B6< SYSCLK_DDRCLK_B1_UF

DDR_VREF_0 Y22
DDR_VREF_1 T22

53D6< 12D6<>

13A6<> 53D6<
13C4<> 53D6<

13A6<> 53D6<
13A6<> 53D6<

MEM_ADDR<7>

MEM_ADDR<12>

SEL = 0; HOST=B PORT, A PORT = 100 OHMGND


SEL = 1; HOST=A PORT, B PORT = 100 OHMGND

53B6< SYSCLK_DDRCLK_B0_UF
53B6< SYSCLK_DDRCLK_B0_L_UF

W35

RAM_ADDR<3>

0S ARE SAME POLARITY (ACTIVE LO)


1S ARE SAME POLARITY (ACTIVE HI)

13C8<> 53D6<
13A6<> 53D6<

13C4<> 53D6<
13B3<> 53D6<

RP68
22
3

14B4<> 15C6< 53D6<

53D6< 12D6<>

5%
1/16W
SM1

V33
V32

MEM_ADDR<3>

R261
47 2
1

MEM_MUXSEL_L<1>

W33

W32

RAM_ADDR<4>

5%
1/16W
SM1

53C6< SYSCLK_DDRCLK_A2_UF
53B6< SYSCLK_DDRCLK_A2_L_UF

Y30

RP68
22
2

13A6<> 13C8<> 53C6<


53D6< 12D6<>

53C6< SYSCLK_DDRCLK_A1_UF
53C6< SYSCLK_DDRCLK_A1_L_UF

Y36

RP68
22

5%
1/16W
SM1

53C6< SYSCLK_DDRCLK_A0_UF
53C6< SYSCLK_DDRCLK_A0_L_UF

Y35

W36

53D6< 12D6<>

MUX_SEL_L

NC_MEM_MUXSEL_H<0>
53C6< MEM_MUXSEL_H<1>
NC_MEM_MUXSEL_L<0>
53C6< MEM_MUXSEL_L<1>

Y33

5%
1/16W
SM1

5%
1/16W
MF
402

MEM_RAS_L 12A3< 53C6<


MEM_CAS_L 12A3< 53C6<
MEM_WE_L 12B3< 53C6<
MEM_CKE<0> 12C2< 53C6<
MEM_CKE<1> 12B2< 53C6<
MEM_CKE<2> 12C2< 53C6<
MEM_CKE<3> 12B2< 53C6<

Y32

MEM_ADDR<4>

R288
47 2
1

MEM_MUXSEL_H<1>

12B2< 53C6<
12B2< 53C6<

13C8<> 53D6<

13A3<> 13C4<> 53C6<


53D6< 12D6<>

12C2< 53C6<
12C2< 53C6<

MEM_DQS<0>
MEM_DQS<1>
MEM_DQS<2>
MEM_DQS<3>
MEM_DQS<4>
MEM_DQS<5>
MEM_DQS<6>
MEM_DQS<7>

SERIES RESISTORS FOR CONTROL SIGNALS

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

LOCATE THESE RESISTORS NEAR INTREPID

II NOT TO REPRODUCE OR COPY IT

100

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

1%
1/16W
MF
2 402

SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
12 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

+2_5V_MAIN

+2_5V_MAIN
NOSTUFF

C613
0.1UF

20%
2 10V
CERM
402

20%
10V
2 CERM
402

DA17 A2
DA18 B1

H9 DH8
F9 DH9

DA19 D1

E9 DH10
C9 DH11

DB0* G1
DB1* J1

B9 DH12
B8 DH13

DB2* K2
DB3* J4

B6 DH14
B5 DH15

DB4* K5
DB5* K7

B3 DH16
B2 DH17

DB6* K8
DB7* K10
DB8* H10

C2 DH18
E2 DH19

DB9* F10
DB10* D10
DB11* B10
DB12* A9

E3 SEL

DB13* B7
DB14* A6
DB15* A4
DB16* A3
DB17* A1
DB18* C1

+2_5V_MAIN

53C6< 13A3<> 12D4<

20%
10V
2 CERM
402

E8

H6

H5

G9

G2

D9

D2

C6

C669
0.1UF

20%
10V
2 CERM
402

H9 DH8
F9 DH9

DA19 D1

E9 DH10
C9 DH11

DB0* G1

VDD

DA0 F1
DA1 H1

U22
CBTV4020

DA2 K1
DA3 K3

BGA

DA4 K4
DA5 K6

SYM_VER-3

DA6 J7
DA7 K9

DA8 J10
DA9 G10

MEM_DATA<16>
MEM_DATA<17>
53D6< 12C8<> MEM_DATA<18>
53D6< 12C8<> MEM_DATA<19>
53D6< 12C8<> MEM_DATA<20>
53D6< 12C8<> MEM_DATA<21>
53D6< 12C8<> MEM_DATA<22>
53D6< 12C8<> MEM_DATA<23>
53D6< 12C6<> MEM_DQS<2>
53D6< 12C6<> MEM_DQM<2>
53D6< 12C8<> MEM_DATA<24>
53D6< 12C8<> MEM_DATA<25>
53D6< 12C8<> MEM_DATA<26>
53D6< 12C8<> MEM_DATA<27>
53D6< 12C8<> MEM_DATA<28>
53D6< 12C8<> MEM_DATA<29>
53D6< 12C8<> MEM_DATA<30>
53D6< 12C8<> MEM_DATA<31>
53D6< 12C6<> MEM_DQS<3>
53D6< 12C6<> MEM_DQM<3>
53D6< 12C8<>
53D6< 12C8<>

53C6< 13C8<> 12D4<

DB1* J1
DB2* K2

B9 DH12
B8 DH13

DB3* J4
DB4* K5

B6 DH14
B5 DH15

DB5* K7
DB6* K8

B3 DH16
B2 DH17

DB7* K10
DB8* H10

C2 DH18
E2 DH19

DB9* F10
DB10* D10

E3 SEL

DB11* B10
DB12* A9
DB13* B7
DB14* A6

NOSTUFF
C671
0.1UF

DB15* A4
DB16* A3
DB17* A1

20%
10V
2 CERM
402

DB18* C1
DB19* E1

+2_5V_MAIN

RAM_DATA_B<32> 15B6< 53D6<


RAM_DATA_B<33> 15B6< 53D6<
RAM_DATA_B<34> 15B6< 53D6<
RAM_DATA_B<35> 15B6< 53D6<
RAM_DATA_B<36> 15B4> 53D6<
RAM_DATA_B<37> 15B4> 53D6<
RAM_DATA_B<38> 15B4> 53D6<
RAM_DATA_B<39> 15B4> 53D6<
RAM_DQS_B<4> 15B6< 15B8< 53D6<
RAM_DQM_B<4> 15B4> 53D6<
RAM_DATA_B<40> 15B6< 53D6<
RAM_DATA_B<41> 15B6< 53D6<
RAM_DATA_B<42> 15A6< 53D6<
RAM_DATA_B<43> 15A6< 53D6<
RAM_DATA_B<44> 15B4> 53D6<
RAM_DATA_B<45> 15B4> 53D6<
RAM_DATA_B<46> 15A4> 53D6<
RAM_DATA_B<47> 15A4> 53D6<
RAM_DQS_B<5> 15B6< 15B8< 53D6<
RAM_DQM_B<5> 15B4> 53D6<

MUX_SEL_L

DA10 E10
DA11 C10

F2 DH0
H2 DH1

DA12 A10

J2 DH2
J3 DH3

DA13 A8
DA14 A7

J5 DH4
J6 DH5

DA15 A5
DA16 B4

J8 DH6
J9 DH7

DA17 A2
DA18 B1

H9 DH8
F9 DH9

DA19 D1

E9 DH10
C9 DH11

DB0* G1
DB1* J1

B9 DH12
B8 DH13

DB2* K2
DB3* J4

B6 DH14
B5 DH15

DB4* K5
DB5* K7

B3 DH16
B2 DH17

DB6* K8
DB7* K10
DB8* H10

C2 DH18
E2 DH19

DB9* F10
DB10* D10
DB11* B10
DB12* A9

E3 SEL

DB13* B7
DB14* A6
DB15* A4
DB16* A3
DB17* A1
DB18* C1
DB19* E1

C908
0.1UF

20%
10V
2 CERM
402

VDD

DA0 F1
DA1 H1

U29
CBTV4020

DA2 K1
DA3 K3

BGA

DA4 K4
DA5 K6

SYM_VER-3

DA6 J7
DA7 K9
DA8 J10
DA9 G10

GND

GND
C5

C670
0.1UF

MUX_SEL_H

DA17 A2
DA18 B1

C5

DB19* E1

RAM_DATA_B<0> 15D6< 53D6<


RAM_DATA_B<1> 15D6< 53D6<
RAM_DATA_B<2> 15D6< 53D6<
RAM_DATA_B<3> 15D6< 53D6<
RAM_DATA_B<4> 15D4> 53D6<
RAM_DATA_B<5> 15D4> 53D6<
RAM_DATA_B<6> 15D4> 53D6<
RAM_DATA_B<7> 15D4> 53D6<
RAM_DQS_B<0> 15C8< 15D6< 53D6<
RAM_DQM_B<0> 15D4> 53D6<
RAM_DATA_B<8> 15D6< 53D6<
RAM_DATA_B<9> 15D6< 53D6<
RAM_DATA_B<10> 15C6< 53D6<
RAM_DATA_B<11> 15C6< 53D6<
RAM_DATA_B<12> 15D4> 53D6<
RAM_DATA_B<13> 15D4> 53D6<
RAM_DATA_B<14> 15C4> 53D6<
RAM_DATA_B<15> 15C4> 53D6<
RAM_DQS_B<1> 15C8< 15D6< 53D6<
RAM_DQM_B<1> 15D4> 53D6<

DA15 A5
DA16 B4

J8 DH6
J9 DH7

DA10 E10

RAM_DATA_A<16> 14D6<> 53D6<


RAM_DATA_A<17> 14C6<> 53D6<
RAM_DATA_A<18> 14C6<> 53D6<
RAM_DATA_A<19> 14C6<> 53D6<
RAM_DATA_A<20> 14D4<> 53D6<
RAM_DATA_A<21> 14C4<> 53D6<
RAM_DATA_A<22> 14C4<> 53D6<
RAM_DATA_A<23> 14C4<> 53D6<
RAM_DQS_A<2> 14C6<> 14C8< 53D6<
RAM_DQM_A<2> 14C4<> 53D6<
RAM_DATA_A<24> 14C6<> 53D6<
RAM_DATA_A<25> 14C6<> 53D6<
RAM_DATA_A<26> 14C6<> 53D6<
RAM_DATA_A<27> 14C6<> 53D6<
RAM_DATA_A<28> 14C4<> 53D6<
RAM_DATA_A<29> 14C4<> 53D6<
RAM_DATA_A<30> 14C4<> 53D6<
RAM_DATA_A<31> 14C4<> 53D6<
RAM_DQS_A<3> 14C6<> 14C8< 53D6<
RAM_DQM_A<3> 14C4<> 53D6<

MEM_DATA<48>
MEM_DATA<49>
53D6< 12B8<> MEM_DATA<50>
53D6< 12B8<> MEM_DATA<51>
53D6< 12B8<> MEM_DATA<52>
53D6< 12B8<> MEM_DATA<53>
53D6< 12B8<> MEM_DATA<54>
53D6< 12B8<> MEM_DATA<55>
53D6< 12C6<> MEM_DQS<6>
53D6< 12C6<> MEM_DQM<6>
53D6< 12B8<> MEM_DATA<56>
53D6< 12B8<> MEM_DATA<57>
53D6< 12B8<> MEM_DATA<58>
53D6< 12B8<> MEM_DATA<59>
53D6< 12B8<> MEM_DATA<60>
53D6< 12B8<> MEM_DATA<61>
53D6< 12B8<> MEM_DATA<62>
53D6< 12B8<> MEM_DATA<63>
53D6< 12C6<> MEM_DQS<7>
53D6< 12C6<> MEM_DQM<7>
53D6< 12B8<>
53D6< 12B8<>

53C6< 13C4<> 12D4<

RAM_DATA_B<16> 15C6< 53D6<


RAM_DATA_B<17> 15C6< 53D6<
RAM_DATA_B<18> 15C6< 53D6<
RAM_DATA_B<19> 15C6< 53D6<
RAM_DATA_B<20> 15C4> 53D6<
RAM_DATA_B<21> 15C4> 53D6<
RAM_DATA_B<22> 15C4> 53D6<
RAM_DATA_B<23> 15C4> 53D6<
RAM_DQS_B<2> 15C6< 15C8< 53D6<
RAM_DQM_B<2> 15C4> 53D6<
RAM_DATA_B<24> 15C6< 53D6<
RAM_DATA_B<25> 15C6< 53D6<
RAM_DATA_B<26> 15C6< 53D6<
RAM_DATA_B<27> 15C6< 53D6<
RAM_DATA_B<28> 15C4> 53D6<
RAM_DATA_B<29> 15C4> 53D6<
RAM_DATA_B<30> 15C4> 53D6<
RAM_DATA_B<31> 15C4> 53D6<
RAM_DQS_B<3> 15B8< 15C6< 53D6<
RAM_DQM_B<3> 15C4> 53D6<

MUX_SEL_H

C909
0.1UF

20%
10V
2 CERM
402

NOSTUFF
C910
0.1UF

20%
10V
2 CERM
402

F2 DH0
H2 DH1

DA11 C10
DA12 A10

J2 DH2
J3 DH3

DA13 A8
DA14 A7

J5 DH4
J6 DH5

DA15 A5
DA16 B4

J8 DH6
J9 DH7

DA17 A2
DA18 B1

H9 DH8
F9 DH9

DA19 D1

E9 DH10
C9 DH11

DB0* G1
DB1* J1

B9 DH12
B8 DH13

DB2* K2
DB3* J4

B6 DH14
B5 DH15

DB4* K5
DB5* K7
DB6* K8

B3 DH16
B2 DH17

DB7* K10
DB8* H10

C2 DH18
E2 DH19

DB9* F10
DB10* D10
DB11* B10
DB12* A9

E3 SEL

DB13* B7
DB14* A6
DB15* A4
DB16* A3
DB17* A1
DB18* C1
DB19* E1

RAM_DATA_A<48> 14A6<> 53D6<


RAM_DATA_A<49> 14A6<> 53D6<
RAM_DATA_A<50> 14A6<> 53D6<
RAM_DATA_A<51> 14A6<> 53D6<
RAM_DATA_A<52> 14A4<> 53D6<
RAM_DATA_A<53> 14A4<> 53D6<
RAM_DATA_A<54> 14A4<> 53D6<
RAM_DATA_A<55> 14A4<> 53D6<
RAM_DQS_A<6> 14A6<> 14B8< 53D6<
RAM_DQM_A<6> 14A4<> 53D6<
RAM_DATA_A<56> 14A6<> 53D6<
RAM_DATA_A<57> 14A6<> 53D6<
RAM_DATA_A<58> 14A6<> 53D6<
RAM_DATA_A<59> 14A6<> 53D6<
RAM_DATA_A<60> 14A4<> 53D6<
RAM_DATA_A<61> 14A4<> 53D6<
RAM_DATA_A<62> 14A4<> 53D6<
RAM_DATA_A<63> 14A4<> 53D6<
RAM_DQS_A<7> 14A6<> 14A8< 53D6<
RAM_DQM_A<7> 14A4<> 53D6<

RAM_DATA_B<48> 15A6< 53D6<


RAM_DATA_B<49> 15A6< 53D6<
RAM_DATA_B<50> 15A6< 53D6<
RAM_DATA_B<51> 15A6< 53D6<
RAM_DATA_B<52> 15A4> 53D6<
RAM_DATA_B<53> 15A4> 53D6<
RAM_DATA_B<54> 15A4> 53D6<
RAM_DATA_B<55> 15A4> 53D6<
RAM_DQS_B<6> 15A6< 15B8< 53D6<
RAM_DQM_B<6> 15A4> 53D6<
RAM_DATA_B<56> 15A6< 53D6<
RAM_DATA_B<57> 15A6< 53D6<
RAM_DATA_B<58> 15A6< 53D6<
RAM_DATA_B<59> 15A6< 53D6<
RAM_DATA_B<60> 15A4> 53D6<
RAM_DATA_B<61> 15A4> 53D6<
RAM_DATA_B<62> 15A4> 53D6<
RAM_DATA_B<63> 15A4> 53D6<
RAM_DQS_B<7> 15A6< 15A8< 53D6<
RAM_DQM_B<7> 15A4> 53D6<

GND
H6

J8 DH6
J9 DH7

J5 DH4
J6 DH5

F8

DA15 A5
DA16 B4

DA13 A8
DA14 A7

F3

J5 DH4
J6 DH5

DA11 C10
DA12 A10

J2 DH2
J3 DH3

H5

MUX_SEL_L

DA13 A8
DA14 A7

F2 DH0
H2 DH1

RAM_DATA_A<32> 14B6<> 53D6<


RAM_DATA_A<33> 14B6<> 53D6<
RAM_DATA_A<34> 14B6<> 53D6<
RAM_DATA_A<35> 14B6<> 53D6<
RAM_DATA_A<36> 14B4<> 53D6<
RAM_DATA_A<37> 14B4<> 53D6<
RAM_DATA_A<38> 14B4<> 53D6<
RAM_DATA_A<39> 14B4<> 53D6<
RAM_DQS_A<4> 14B6<> 14B8< 53D6<
RAM_DQM_A<4> 14B4<> 53D6<
RAM_DATA_A<40> 14B6<> 53D6<
RAM_DATA_A<41> 14B6<> 53D6<
RAM_DATA_A<42> 14A6<> 53D6<
RAM_DATA_A<43> 14A6<> 53D6<
RAM_DATA_A<44> 14B4<> 53D6<
RAM_DATA_A<45> 14B4<> 53D6<
RAM_DATA_A<46> 14A4<> 53D6<
RAM_DATA_A<47> 14A4<> 53D6<
RAM_DQS_A<5> 14A6<> 14B8< 53D6<
RAM_DQM_A<5> 14A4<> 53D6<

G9

53C6< 13A6<> 12D4<

DA12 A10

J2 DH2
J3 DH3

DA9 G10
DA10 E10

MEM_DATA<32>
53D6< 12C8<> MEM_DATA<33>
53D6< 12C8<> MEM_DATA<34>
53D6< 12C8<> MEM_DATA<35>
53D6< 12C8<> MEM_DATA<36>
53D6< 12C8<> MEM_DATA<37>
53D6< 12C8<> MEM_DATA<38>
53D6< 12C8<> MEM_DATA<39>
53D6< 12C6<> MEM_DQS<4>
53D6< 12C6<> MEM_DQM<4>
53D6< 12B8<> MEM_DATA<40>
53D6< 12B8<> MEM_DATA<41>
53D6< 12B8<> MEM_DATA<42>
53D6< 12B8<> MEM_DATA<43>
53D6< 12B8<> MEM_DATA<44>
53D6< 12B8<> MEM_DATA<45>
53D6< 12B8<> MEM_DATA<46>
53D6< 12B8<> MEM_DATA<47>
53D6< 12C6<> MEM_DQS<5>
53D6< 12C6<> MEM_DQM<5>

F8

DA10 E10
DA11 C10

F2 DH0
H2 DH1

DA7 K9
DA8 J10

F3

MEM_DATA<0>
MEM_DATA<1>
53D6< 12D8<> MEM_DATA<2>
53D6< 12D8<> MEM_DATA<3>
53D6< 12D8<> MEM_DATA<4>
53D6< 12D8<> MEM_DATA<5>
53D6< 12D8<> MEM_DATA<6>
53D6< 12D8<> MEM_DATA<7>
53D6< 12C6<> MEM_DQS<0>
53D6< 12C6<> MEM_DQM<0>
53D6< 12D8<> MEM_DATA<8>
53D6< 12D8<> MEM_DATA<9>
53D6< 12D8<> MEM_DATA<10>
53D6< 12D8<> MEM_DATA<11>
53D6< 12D8<> MEM_DATA<12>
53D6< 12D8<> MEM_DATA<13>
53D6< 12C8<> MEM_DATA<14>
53D6< 12C8<> MEM_DATA<15>
53D6< 12C6<> MEM_DQS<1>
53D6< 12C6<> MEM_DQM<1>
53D6< 12D8<>
53D6< 12D8<>

DA6 J7

53D6< 12C8<>

20%
10V
2 CERM
402

C859
0.1UF

G2

DA8 J10
DA9 G10

20%
2 10V
CERM
402

C5

DA6 J7
DA7 K9

DA4 K4
DA5 K6

H5

DA4 K4
DA5 K6

DA2 K1
DA3 K3

BGA
SYM_VER-3

G9

BGA
SYM_VER-3

DA0 F1
DA1 H1

U27
CBTV4020

G2

DA2 K1
DA3 K3

D9

U18
CBTV4020

RAM_DATA_A<0> 14D6<> 53D6<


RAM_DATA_A<1> 14D6<> 53D6<
RAM_DATA_A<2> 14D6<> 53D6<
RAM_DATA_A<3> 14D6<> 53D6<
RAM_DATA_A<4> 14D4<> 53D6<
RAM_DATA_A<5> 14D4<> 53D6<
RAM_DATA_A<6> 14D4<> 53D6<
RAM_DATA_A<7> 14D4<> 53D6<
RAM_DQS_A<0> 14C8< 14D6<> 53D6<
RAM_DQM_A<0> 14D4<> 53D6<
RAM_DATA_A<8> 14D6<> 53D6<
RAM_DATA_A<9> 14D6<> 53D6<
RAM_DATA_A<10> 14D6<> 53D6<
RAM_DATA_A<11> 14D6<> 53D6<
RAM_DATA_A<12> 14D4<> 53D6<
RAM_DATA_A<13> 14D4<> 53D6<
RAM_DATA_A<14> 14D4<> 53D6<
RAM_DATA_A<15> 14D4<> 53D6<
RAM_DQS_A<1> 14C8< 14D6<> 53D6<
RAM_DQM_A<1> 14D4<> 53D6<

D2

DA0 F1
DA1 H1

C6

VDD

NOSTUFF
C860
0.1UF

E8

VDD

F8

F3

E8

C858
0.1UF

D9

20%
2 10V
CERM
402

D2

C612
0.1UF

C6

20%
2 10V
CERM
402

H6

C611
0.1UF

E8

N20P80%
2 10V
Y5V
805

F8

C230
10UF

F3

DDR MUXES
A

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:29:36 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

H6

H5

G9

G2

D9

D2

C6

C5

GND
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
13 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

+2_5V_MAIN

+2_5V_MAIN

NC_SODIMM201

DISTRIBUTE THESE TWO CAPS


ALONG VREF TRACE

C46

0.1UF

20%
10V
2 CERM
402

NOSTUFF

1
3

RAM_DATA_A<0>
RAM_DATA_A<1>

53D6< 13D7<>
53D6< 13D7<>

5
7
9

53D6< 13D7<>

RAM_DQS_A<0>
RAM_DATA_A<2>

53D6< 13D7<>
53D6< 13C7<>

RAM_DATA_A<3>
RAM_DATA_A<8>

11

53D6< 14C8< 13D7<>

LOCATE C1601 AND C1401


DIRECTLY ON PIN AT J26-1

15D8<
12A7< DDR_VREF
14D2<>
52A6>

C1401
0.1UF

20%
2 10V
CERM
402

C47

0.1UF

13
15

C1601
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

17
19
21

RAM_DATA_A<9>
13C7<> RAM_DQS_A<1>

23

53D6< 13C7<>
53D6< 14C8<

25
27

NOSTUFF

53D6< 13C7<>
53D6< 13C7<>

RAM_DATA_A<10>
RAM_DATA_A<11>

29
31
33

+2_5V_MAIN

53C6< 12C4< SYSCLK_DDRCLK_A0


53C6< 12C4< SYSCLK_DDRCLK_A0_L

NOSTUFF

35
37
39

R1403
1

53D6< 14D6<> 13D7<>

470

RAM_DQS_A<0>

NOSTUFF

R1405

53D6< 14D6<> 13C7<>

470

470

47

53D6< 13B5<>

RAM_DQS_A<2>
RAM_DATA_A<18>

49
51

5%
1/16W
MF
402

5%
1/16W
MF
402

RAM_DQS_A<1>

53D6< 14C8< 13B5<>

53D6< 13B5<>
53D6< 13B5<>

R1407

C
53D6< 14C6<> 13B5<>

53D6< 14C8<

RAM_DATA_A<25>
13B5<> RAM_DQS_A<3>

470

53D6< 13B5<>

53D6< 13B5<>

470

R1411

53D6< 14B6<> 13D4<>

470

470

53D6< 15C4> 12D3<


53D6< 15B6< 12C3<

R1415

53D6< 14A6<> 13B2<>

470

R1417

53D6< 14A6<> 13B2<>

RAM_DQS_A<7>

5%
1/16W
MF
402

95
97

NO_TEST

99
101

470

RAM_ADDR<7>
RAM_ADDR<5>
RAM_ADDR<3>
RAM_ADDR<1>

105
107
109
111

RAM_ADDR<10>

115
117

53C6< 12C1<

RAM_CS_L<0>
NC_SODIMM123

119
121
NO_TEST

53D6< 13D4<>
53D6< 13D4<>

RAM_DATA_A<32>
RAM_DATA_A<33>

470

129
131

53D6< 14B8< 13D4<>

RAM_DQS_A<4>
RAM_DATA_A<34>

133

53D6< 13D4<>

135

53D6< 13D4<>
53D6< 13D4<>

RAM_DATA_A<35>
RAM_DATA_A<40>

137
139
141
143

5%
1/16W
MF
402

123

127

NOSTUFF

NOSTUFF
470

91

125

R1416
1

89

NO_TEST

53D6< 15B6< 12B3< RAM_BA<0>


53C6< 15B6< 12B3< RAM_WE_L

53D6< 15B4> 12C3<

5%
1/16W
MF
402

5%
1/16W
MF
402

RAM_DQS_A<6>

NO_TEST

113

NOSTUFF

NOSTUFF
1

85

NC_SODIMM97
RAM_ADDR<12>
12C3< RAM_ADDR<9>

R1414

NO_TEST

79

NO_TEST

93

53D6< 15C6< 12D3<


53D6< 15C6< 12C1<

5%
1/16W
MF
402

5%
1/16W
MF
402

RAM_DQS_A<5>

83

NC_SODIMM89
NC_SODIMM91

53D6< 15C6<

NOSTUFF

R1413

53D6< 14A6<> 13C4<>

NC_SODIMM83
NC_SODIMM85

NO_TEST

77

103

NOSTUFF
470

NO_TEST

53D6< 15C4> 12D1<

R1412

NC_SODIMM77
NC_SODIMM79

53C6< 15C1< 12B1< RAM_CKE<1>

5%
1/16W
MF
402

5%
1/16W
MF
402

RAM_DQS_A<4>

73

NO_TEST

87

NOSTUFF

NOSTUFF
1

71

NO_TEST

81

R1410
470

67

5%
1/16W
MF
402

5%
1/16W
MF
402

RAM_DQS_A<3>

65

69

NC_SODIMM71
NC_SODIMM73

NOSTUFF

R1409

53D6< 14C6<> 13B5<>

61

RAM_DATA_A<26>
RAM_DATA_A<27>

R1408
470

59

75

NOSTUFF
1

55

63

5%
1/16W
MF
402

5%
1/16W
MF
402

RAM_DQS_A<2>

53

57

NOSTUFF

NOSTUFF
470

RAM_DATA_A<19>
RAM_DATA_A<24>

53D6< 13B5<>

R1406
1

43
45

NOSTUFF

R1404
1

RAM_DATA_A<16>
RAM_DATA_A<17>

41

53D6< 13B5<>
53D6< 13B5<>

5%
1/16W
MF
402

RAM_DATA_A<41>
13C4<> RAM_DQS_A<5>

145

53D6< 13C4<>
53D6< 14B8<

147
149

53D6< 13C4<>

NOSTUFF

R1418
1

470

53D6< 13C4<>

RAM_DATA_A<42>
RAM_DATA_A<43>

151
153
155

157

5%
1/16W
MF
402

159
161

53D6< 13C2<>
53D6< 13C2<>

+3V_MAIN

RAM_DATA_A<48>
RAM_DATA_A<49>

163
165
167

53D6< 14B8< 13B2<> RAM_DQS_A<6>


53D6< 13C2<> RAM_DATA_A<50>

169
171
173

C319
10UF

N20P80%
10V
2 Y5V
805

53D6< 13C2<>
53D6< 13B2<>

RAM_DATA_A<51>
RAM_DATA_A<56>

175
177
179

53D6< 13B2<>

RAM_DATA_A<57>
RAM_DQS_A<7>

181
183

53D6< 14A8< 13B2<>


1

C929
0.1UF

20%
2 10V
CERM
402

185

53D6< 13B2<>
53D6< 13B2<>

RAM_DATA_A<58>
RAM_DATA_A<59>

187
189
191

INT_I2C_DATA0
INT_I2C_CLK0

34B3< 15A6<

193
195

34B3< 15A6<

197

NC_SODIMM199
NC_SODIMM202

+2_5V_MAIN

201

NO_TEST

199

VREF0

VREF1

VSS0
DQ0

VSS1
DQ4

J26
AS0A42-D2R

DQ1
VDD0

F-RT-SM

DQ5
VDD1

DQS0
DQ2

DM0
DQ6

VSS2

VSS3
DQ7

DQ3
DQ8

DQ12
VDD3

VDD2
DQ9

DQ13

DQS1
VSS4

DM1
VSS5

DQ10
DQ11

DQ14
DQ15

VDD4
CK0

VDD5
VDD6

CK0*
VSS7

VSS6
VSS8
KEY

DQ16

DQ20

DQ17
VDD7

DQ21
VDD8

DQS2
DQ18

DM2
DQ22

VSS9
DQ19

VSS10
DQ23

DQ24
VDD9
DQ25
DQS3
VSS11
DQ26
DQ27

RFU2
VSS13

RFU3
VSS14
RFU5
RFU7

VDD13
RFU8

VDD14
RFU9

RFU10

RFU11
VSS16

VSS15
RFU12

VSS17
VDD15

RFU13
VDD16

VDD17

CKE1
RFU14

CKE0
RFU15

A12
A9

A11
A8

VSS18
A7

VSS19
A6

A5
A3

A4
A2

A1

A0
VDD19

VDD18
A10_AP

BA1
RAS*

BA0
WE*

CAS*

S0*
RFU16

S1*
RFU17

VSS20
DQ32

VSS21
DQ36

DQ33
VDD20

DQ37
VDD21

DQS4
DQ34

DM4
DQ38

VSS22
DQ35

VSS23
DQ39

DQ40

DQ44
VDD23

VDD22
DQ41

DQ45
DM5

DQS5
VSS24

VSS25

DQ42
DQ43

DQ46
DQ47

VDD24
VDD26

VDD25
CK1*

VSS26
VSS27

CK1
VSS28

DQ48
DQ49

DQ52
DQ53

VDD27
DQS6
DQ50
VSS29
DQ51

DQ57
DQS7

VSS32
DQ62

DQ59
VDD31

DQ63
VDD32
SA0
SA1

VDDSPD

SA2
RFU19

RFU18

C1402
0.1UF

20%
10V
2 CERM
402

20%
10V
CERM 2
402

DDR_VREF

RAM_DATA_A<7> 13D7<> 53D6<


RAM_DATA_A<12> 13C7<> 53D6<

18
20

12A7< 14D8<> 15D8< 52A6>

22
24

LOCATE C1602 AND C1402


DIRECTLY ON PIN AT J26-2

RAM_DATA_A<13> 13C7<> 53D6<


RAM_DQM_A<1> 13C7<> 53D6<

26
28
30

RAM_DATA_A<14> 13C7<>
RAM_DATA_A<15> 13C7<>

32

53D6<
53D6<

34

DDR DECOUPLING

36

+2_5V_MAIN

38

SLOT "A"

40
42

RAM_DATA_A<20>
RAM_DATA_A<21>

44

1 - 10UF
24 - 0.1UF

13B5<> 53D6<
13B5<> 53D6<

46
48

RAM_DQM_A<2> 13B5<> 53D6<


RAM_DATA_A<22> 13B5<> 53D6<

50
52

RAM_DATA_A<23>
RAM_DATA_A<28>

54
56

60

13B5<> 53D6<
13B5<> 53D6<

RAM_DATA_A<29> 13B5<> 53D6<


RAM_DQM_A<3> 13A5<> 53D6<

64
66

RAM_DATA_A<30>
RAM_DATA_A<31>

68

13B5<> 53D6<

C244
0.1UF

C263
0.1UF

C320
0.1UF

C243
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C275
0.1UF

C276
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C1407
0.1UF

C1408
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C1416
0.1UF

C1417
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
10V
2 CERM
402

C313
0.1UF

C242
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C1406
0.1UF

20%
10V
2 CERM
402

C1415
0.1UF

C255
0.1UF

C256
0.1UF

20%
10V
2 CERM
402

C304
0.1UF

20%
10V
2 CERM
402

C1409
0.1UF

20%
10V
2 CERM
402

C1418
0.1UF

C1403
0.1UF

20%
10V
2 CERM
402

C261
0.1UF

20%
10V
2 CERM
402

C1410
0.1UF

20%
10V
2 CERM
402

C1411
0.1UF

20%
10V
2 CERM
402

C1419
0.1UF

C1404
0.1UF

20%
10V
2 CERM
402

C311
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C1412
0.1UF

C1405
0.1UF

13B5<> 53D6<

70
72

NO_TEST

74

NO_TEST

NC_SODIMM72
NC_SODIMM74

76
78

NO_TEST

80

NO_TEST

NC_SODIMM78
NC_SODIMM80

82
84

NO_TEST

86

NO_TEST

20%
10V
2 CERM
402

C1413
0.1UF

20%
10V
2 CERM
402

NC_SODIMM84
NC_SODIMM86

88
90
92
94
96
98

NO_TEST

100
102

RAM_CKE<0> 12C1< 15C1< 53C6<


NC_SODIMM98
RAM_ADDR<11> 12B3< 15C4> 53D6<
RAM_ADDR<8> 12D1< 15C4> 53D6<

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C1420
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

RAM_ADDR<6>
RAM_ADDR<4>
RAM_ADDR<2>
RAM_ADDR<0>

108
110
112

C1421
0.1UF

20%
10V
2 CERM
402

+2_5V_MAIN

104
106

12D1< 15C4> 53D6<


12D3< 15C6< 53D6<

12C3< 15C6< 53D6<


12C3< 15B6< 53D6<

116
118
120
122
124

NO_TEST

C1414
10UF

N20P80%
10V
2 Y5V
805

114

RAM_BA<1> 12B3< 15B6< 53D6<


RAM_RAS_L 12A2< 15B4> 53C6<
RAM_CAS_L 12A2< 15B6< 53C6<
RAM_CS_L<1> 12C1< 53C6<
NC_SODIMM124

126
128

RAM_DATA_A<36> 13D4<> 53D6<


RAM_DATA_A<37> 13D4<> 53D6<

130
132

+2_5V_MAIN

RAM_DQM_A<4> 13D4<> 53D6<


RAM_DATA_A<38> 13D4<> 53D6<

134
136
138
140

RAM_DATA_A<39> 13D4<>
RAM_DATA_A<44> 13C4<>

142

R1401

53D6<
53D6<

100
1%
1/16W
MF
2 402

144
146

RAM_DATA_A<45> 13C4<> 53D6<


RAM_DQM_A<5> 13C4<> 53D6<

148

MIN_LINE_WIDTH=25

INT_MEM_VREF

150
152

RAM_DATA_A<46> 13C4<> 53D6<


RAM_DATA_A<47> 13C4<> 53D6<

154
156

12A8<>

LOCATE THESE RESISTORS BETWEEN DIMMS


1

R1402
100

158

SYSCLK_DDRCLK_A1_L 12B4< 53C6<


SYSCLK_DDRCLK_A1 12C4< 53C6<

160

1%
1/16W
MF
2 402

162
164

RAM_DATA_A<52>
RAM_DATA_A<53>

166

13C2<> 53D6<
13C2<> 53D6<

168

RAM_DQM_A<6> 13B2<> 53D6<


RAM_DATA_A<54> 13B2<> 53D6<

172

176

RAM_DATA_A<55>
RAM_DATA_A<60>

178

SO-DIMM SLOT A

13B2<> 53D6<
13B2<> 53D6<

180
182

NOTICE OF PROPRIETARY PROPERTY

RAM_DATA_A<61> 13B2<> 53D6<


RAM_DQM_A<7> 13B2<> 53D6<

184

LAST_MODIFIED=Mon Oct 27 12:29:39 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

186
188

RAM_DATA_A<62>
RAM_DATA_A<63>

190

13B2<> 53D6<
13B2<> 53D6<

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

192

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

194
196

SIZE

ADDR=0 (0xA0)

198
200

NO_TEST

APPLE COMPUTER INC.

NC_SODIMM200

D
SCALE

(516S0029)

202

NO_TEST

16

174

VSS31
DQ58

C1602
0.1UF

RAM_DQM_A<0> 13D7<> 53D6<


RAM_DATA_A<6> 13D7<> 53D6<

14

DQ54
VSS30

DQ61
DM7

SDA
SCL

12

170

DQ60
VDD30

13D7<> 53D6<
13D7<> 53D6<

10

VDD28
DM6

DQ55

DQ56
VDD29

62

VDD12
RFU1

RAM_DATA_A<4>
RAM_DATA_A<5>

58

VDD11
RFU0

RFU4
RFU6

DQ29
DM3
DQ30
DQ31

MIN_LINE_WIDTH=20

DQ28
VDD10

VSS12

+2_5V_MAIN

NO_TEST

MIN_LINE_WIDTH=20

DRAWING NUMBER

REV.

051-6569 A
14 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

DDR DECOUPLING

+2_5V_MAIN

+2_5V_MAIN

+2_5V_MAIN
1

53D6< 13C7<>

C48

0.1UF

20%
2 10V
CERM
402

NOSTUFF

C49

0.1UF

C50
0.1UF

20%
2 10V
CERM
402

C1702
0.1UF

20%
10V
2 CERM
402

20%
2 10V
CERM
402

NOSTUFF

RAM_DATA_B<0>

53D6< 13C7<> RAM_DATA_B<1>


53D6< 15C8< 13C7<> RAM_DQS_B<0>

RAM_DATA_B<2>

53D6< 13C7<>
1

DDR_VREF
12A7<
14D2<>
14D8<>
52A6>

+2_5V_MAIN

C1501
0.1UF MIN_LINE_WIDTH=20

20%
10V
2 CERM
402

DISTRIBUTE THESE THREE CAPS


ALONG VREF TRACE

SLOT "B"

53D6< 13C7<>

NOSTUFF

RAM_DATA_B<3>
NC_BIGDIMM9
NC_BIGDIMM10

8
NO_TEST

NO_TEST

10
11

RAM_DATA_B<8>
53D6< 13C7<> RAM_DATA_B<9>
53D6< 15C8< 13B7<> RAM_DQS_B<1>

12

53D6< 13C7<>

+2_5V_MAIN

13
14
15

NOSTUFF

SYSCLK_DDRCLK_B1
53B6< 12A4< SYSCLK_DDRCLK_B1_L

R1503
1

53D6< 15D6< 13C7<>

470

18

53D6< 13C7<>

NOSTUFF

R1504
NOSTUFF

R1505
1

53D6< 15D6< 13B7<>

470

470

5%
1/16W
MF
402

NOSTUFF

NOSTUFF

R1507
1

53D6< 15C6< 13A5<>

470

470

NOSTUFF
1

R1509

53D6< 15C6< 13A5<>

470

470

RAM_DATA_B<19>

31
32

R1513

53D6< 15B6< 13B4<>

35

RAM_ADDR<4>

37

53D6< 14B4<> 12D3<

38

RAM_DATA_B<26>
RAM_DATA_B<27>
12C3< RAM_ADDR<2>

53D6< 14B6<> 12C3<

470

R1515

53D6< 15A6< 13B2<>

40
41

470

43
NO_TEST

44

NO_TEST

45

NC_BIGDIMM47
RAM_ADDR<0>
NC_BIGDIMM49

NO_TEST

48
NO_TEST

53D6< 14B4<> 12B3<

NC_BIGDIMM51
RAM_BA<1>

NO_TEST

R1517
1

53D6< 15A6< 13A2<>

470

5%
1/16W
MF
402

RAM_DATA_B<32>

53

53D6< 13C4<> RAM_DATA_B<33>


53D6< 15B8< 13C4<> RAM_DQS_B<4>

55

RAM_DATA_B<34>

57

53D6< 13C4<>

56

58

53D6< 14B6<> 12B3< RAM_BA<0>


53D6< 13C4<> RAM_DATA_B<35>

59

RAM_DATA_B<40>

61

53D6< 13C4<>

60

62

RAM_DQS_B<7>

+2_5V_MAIN

5%
1/16W
MF
402

53C6< 14B6<> 12B3< RAM_WE_L


53D6< 13C4<> RAM_DATA_B<41>

63

RAM_CAS_L

65

53C6< 14B4<> 12A2<

64

R1518
1

5%
1/16W
MF
402

53D6< 13B2<>
53D6< 13B2<>

67
68
69

NC_BIGDIMM71
RAM_DATA_B<48>
RAM_DATA_B<49>

NO_TEST

71
72
73
74

SYSCLK_DDRCLK_B2_L
12A4< SYSCLK_DDRCLK_B2

53B6< 12A4<
53B6<

75
76
77

R809
1K

1%
1/16W
MF
2 402

66

53D6< 15B8< 13B4<> RAM_DQS_B<5>


53D6< 13C4<> RAM_DATA_B<42>
53D6< 13C4<> RAM_DATA_B<43>

70

NOSTUFF
470

51
52

R1516
NOSTUFF

49

54

NOSTUFF
470

47

50

53D6< 13C4<>

5%
1/16W
MF
402

5%
1/16W
MF
402

RAM_DQS_B<6>

39

R1514
470

RAM_ADDR<1>
NC_BIGDIMM44
NC_BIGDIMM45

53D6< 14B4<> 12C3<

NOSTUFF

NOSTUFF
1

36

46

5%
1/16W
MF
402

5%
1/16W
MF
402

RAM_DQS_B<5>

33

53D6< 13A5<> RAM_DATA_B<25>


53D6< 15B8< 13A5<> RAM_DQS_B<3>

NOSTUFF

NOSTUFF
470

29

53D6< 14B6<> 12C1< RAM_ADDR<5>


53D6< 13A5<> RAM_DATA_B<24>

5%
1/16W
MF
402

R1512
1

28

53D6< 13A5<>
53D6< 13A5<>

NOSTUFF

5%
1/16W
MF
402

RAM_DQS_B<4>

27

42

R1511

53D6< 15B6< 13C4<>

25

30

R1510
470

24

RAM_ADDR<9>
53D6< 13A5<> RAM_DATA_B<18>
53D6< 14B6<> 12D3< RAM_ADDR<7>

53D6< 14B4<>

NOSTUFF
1

23

5%
1/16W
MF
402

5%
1/16W
MF
402

RAM_DQS_B<3>

RAM_DATA_B<16>
53D6< 13A5<> RAM_DATA_B<17>
53D6< 15C8< 13A5<> RAM_DQS_B<2>
53D6< 13A5<>

34

NOSTUFF
1

21
22

53D6< 13A5<>

R1508
470

20

5%
1/16W
MF
402

5%
1/16W
MF
402

RAM_DQS_B<2>

19

53D6< 14B6<> 12C3<

R1506

53D6< 13C7<>
53C6< 15B1<

RAM_DATA_B<10>
RAM_DATA_B<11>
12C1< RAM_CKE<2>

26

5%
1/16W
MF
402

RAM_DQS_B<1>

17

5%
1/16W
MF
402

RAM_DQS_B<0>

16

53B6< 12A4<

53D6< 15B8< 13B2<> RAM_DQS_B<6>


53D6< 13B2<> RAM_DATA_B<50>

78

RAM_DATA_B<51>

80

53D6< 13B2<>

79

81

M_VDDID

82

53D6< 13B2<>
53D6< 13A2<>

RAM_DATA_B<56>
RAM_DATA_B<57>

83
84
85

R796
1K

1%
1/16W
MF
2 402

RAM_DQS_B<7>
RAM_DATA_B<58>
RAM_DATA_B<59>

53D6< 15A8< 13A2<>

86

53D6< 13A2<>
53D6< 13A2<>

87
88
89

M_SPD_WP

90

34B3< 14A6<> INT_I2C_DATA0


34B3< 14A6<> INT_I2C_CLK0

91
92

J11
TH-DDR-DIMM-71243
FRONT SIDE

SYM_VER3

REAR SIDE

VREF SX64 DIMM


DQ0
VSS
DQ1
DQS0

VSS
DQ4
DQ5

VDDQ
DM0/DQS9

DQ2
VDD

DQ6
DQ7

DQ3
NC

VSS
NC

NC
VSS

NC
A13

DQ8
DQ9

VDDQ
DQ12

DQS1

DQ13

VDDQ
CK1

DM1/DQS10
VDD

CK1*
VSS

DQ14
DQ15

DQ10
DQ11

CKE1
VDDQ

CKE0
VDDQ

BA2
DQ20

DQ16
DQ17

A12
VSS

DQS2
VSS

DQ21
A11

A9

DM2/DQS11

DQ18
A7

VDD
DQ22

VDDQ
DQ19

A8
DQ23

A5
DQ24

VSS
A6

VSS
DQ25

DQ28
DQ29

DQS3
A4

VDDQ
DM3/DQS12

VDD
DQ26

A3
DQ30

DQ27
A2
VSS

VSS
DQ31
NC

A1
NC

NC
VDDQ

NC
VDD

CK0
CKO*

NC
A0

VSS
NC

NC
VSS

A10
NC

NC
BA1

VDDQ
NC

DQ32

VSS

VDDQ
DQ33

DQ36
DQ37

DQS4
DQ34
VSS
BA0

VDD
DM4/DQS13
DQ38
DQ39

DQ35
DQ40

VSS
DQ44

VDDQ

RAS*

WE*
DQ41

DQ45
VDDQ

CAS*
VSS

S0*
S1*

DQS5
DQ42

DM5/DQS14
VSS

DQ43
VDD

DQ46
DQ47

NC,S2*
DQ48
DQ49
VSS

NC,S3*
VDDQ
DQ52
DQ53

CK2*
CK2

NC,FETEN
VDD

VDDQ

DM6/DQS15

DQS6
DQ50

DQ54
DQ55

DQ51
VSS

VDDQ
NC

VDDID
DQ56

DQ60
DQ61

DQ57
VDD

VSS
DM7/DQS16

DQS7
DQ58

DQ62
DQ63

DQ59
VSS

VDDQ
SA0

WP
SDA

SA1
SA2

SCL

VVDDSPD

+2_5V_MAIN

93

RAM_DATA_B<4>
RAM_DATA_B<5>

94
95

13C7<> 53D6<
13C7<> 53D6<

96

98
99
100
101

NO_TEST

102

NO_TEST

103

NO_TEST

C726
0.1UF

C936
0.1UF

C864
0.1UF

C922
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C819
0.1UF

20%
2 10V
CERM
402

C914
0.1UF

20%
2 10V
CERM
402

C741
0.1UF

20%
2 10V
CERM
402

C925
0.1UF

20%
2 10V
CERM
402

C1504
0.1UF

C1505
0.1UF

C1506
0.1UF

C1507
0.1UF

NC_BIGDIMM101
NC_BIGDIMM102
NC_BIGDIMM103

C624
0.1UF

20%
2 10V
CERM
402

C1502
0.1UF

N20P80%
10V
2 Y5V
805

C1513
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C602
0.1UF

C672
0.1UF

C1509
0.1UF

C1510
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C1508
0.1UF

C1503
0.1UF

104

RAM_DATA_B<12> 13C7<> 53D6<


RAM_DATA_B<13> 13B7<> 53D6<
RAM_DQM_B<1> 13B7<> 53D6<

105
106
107
108

RAM_DATA_B<14> 13B7<> 53D6<


RAM_DATA_B<15> 13B7<> 53D6<
RAM_CKE<3> 12B1< 15A1< 53C6<

109
110
111

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C1511
0.1UF

20%
2 10V
CERM
402

112
113

NO_TEST

114
115

NC_BIGDIMM113
RAM_DATA_B<20> 13A5<> 53D6<
RAM_ADDR<12> 12D1< 14B6<> 53D6<

C1514
0.1UF

116

C1515
0.1UF

20%
10V
2 CERM
402

20%
2 10V
CERM
402

RAM_DATA_B<21> 13A5<> 53D6<


RAM_ADDR<11> 12B3< 14B4<> 53D6<
RAM_DQM_B<2> 13A5<> 53D6<

117
118
119

+2_5V_MAIN

120

122
123

R497
10K

RAM_ADDR<6> 12D1< 14B4<> 53D6<


RAM_DATA_B<28> 13A5<> 53D6<
RAM_DATA_B<29> 13A5<> 53D6<

126
127

+2_5V_MAIN

RAM_DQM_B<3> 13A5<> 53D6<


RAM_ADDR<3> 12D3< 14B6<> 53D6<
RAM_DATA_B<30> 13A5<> 53D6<

130
131

3
CKE_HYNIX

NO_TEST

135

NO_TEST

RAM_DATA_B<31>
NC_BIGDIMM134
NC_BIGDIMM135

R5121

13A5<> 53D6<

C51

4.7K

138

141
142

NO_TEST

143
144

2N7002

INT_PU_RESET_L

NC_BIGDIMM144

15_I286

5%
1/16W
MF
402

151

SM

+2_5V_MAIN

CKE_HYNIX

13C4<> 53D6<

NOSTUFF

NOSTUFF

13C4<> 53D6<

RAM_DQM_B<4> 13C4<> 53D6<


RAM_DATA_B<38> 13C4<> 53D6<
RAM_DATA_B<39> 13C4<> 53D6<

150

2N7002

148
149

SM

Q41

R508

RAM_DATA_B<36>
RAM_DATA_B<37>

147

CKE_HYNIX

14B6<> 53D6<

145
146

CKE_HYNIX

Q54

44C2<> 34C3<
NO_TEST

14B6<>

53C6<

NC_BIGDIMM140
RAM_ADDR<10> 12C3<
NC_BIGDIMM142

1%
1/16W
MF
2 402

RAM_CKE<1> 12B1<
3

139
NO_TEST

TO SO-DIMM

10K

SYSCLK_DDRCLK_B0 12B4< 53B6<


SYSCLK_DDRCLK_B0_L 12B4< 53B6<

137

140

SM

5%
1/16W
MF
2 402

20%
10V
2 CERM
402

1%
1/16W
MF
402 2

136

R405

R471

2N7002

0.1UF

1K

12C1< 14B4<>
53C6<

Q42

CKE_HYNIX

CKE_HYNIX

NOSTUFF

134

NOSTUFF
D

132
133

0.1UF

RAM_CKE<0>

128
129

C55

20%
10V
2 CERM
402

1%
1/16W
MF
2 402

124
125

NOSTUFF

NOSTUFF

RAM_DATA_B<22> 13A5<> 53D6<


RAM_ADDR<8> 12D1< 14B4<> 53D6<
RAM_DATA_B<23> 13A5<> 53D6<

121

C58

0.1UF

R507

20%
10V
2 CERM
402

10K

1%
1/16W
MF
2 402

152

RAM_CKE<2>

RAM_DATA_B<44> 13C4<> 53D6<


RAM_RAS_L 12A2< 14B4<> 53C6<
RAM_DATA_B<45> 13C4<> 53D6<

153
154
155

Q52

156

2N7002

RAM_CS_L<2> 12B1< 53C6<


RAM_CS_L<3> 12B1< 53C6<
RAM_DQM_B<5> 13B4<> 53D6<

157
158
159

SM

R495
10K

TO BIG DIMM

1%
1/16W
MF
2 402

12C1< 15C6<
53C6<

NOSTUFF

CKE_HYNIX

160

13B4<> 53D6<

NO_TEST

RAM_DATA_B<46>
RAM_DATA_B<47>
NC_BIGDIMM163

13B2<> 53D6<

NO_TEST

RAM_DATA_B<52>
RAM_DATA_B<53>
NC_BIGDIMM167

161
162
163

RAM_CKE<3> 12B1<
3

164

166
167

2N7002

13B2<> 53D6<

RAM_DQM_B<6> 13B2<> 53D6<


RAM_DATA_B<54> 13B2<> 53D6<
RAM_DATA_B<55> 13B2<>

169
170
171

175

SM

+3V_MAIN

53D6<

172

174

168

173

CKE_HYNIX

Q53

165

15C4>

53C6<

13B4<> 53D6<

NO_TEST

NC_BIGDIMM173
RAM_DATA_B<60>
RAM_DATA_B<61>

BIG DIMM SLOT B

13A2<> 53D6<
13A2<> 53D6<

176
177
178
179

RAM_DQM_B<7> 13A2<> 53D6<


RAM_DATA_B<62> 13A2<> 53D6<
RAM_DATA_B<63> 13A2<> 53D6<

180
181

1%
1/16W
MF
2 402

20%
10V
2 CERM
402

R825
1K

C943
0.1UF

NOTICE OF PROPRIETARY PROPERTY

C945
10UF

LAST_MODIFIED=Mon Oct 27 12:29:41 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

N20P80%
10V
2 Y5V
805

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

RAM_SA0

II NOT TO REPRODUCE OR COPY IT

182
183

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

ADDR = 1 (0XA2)

SIZE

184

APPLE COMPUTER INC.

(516-1001)

C593
0.1UF

D
SCALE

DDR SDRAM SLOT B

C1512
10UF

RAM_DQM_B<0> 13C7<> 53D6<


RAM_DATA_B<6> 13C7<> 53D6<
RAM_DATA_B<7> 13C7<> 53D6<

97

C562
0.1UF

15_I282

LOCATE C1702 AND C1501


DIRECTLY ON PIN J11-1

1 - 10UF
24 - 0.1UF

DRAWING NUMBER

REV.

051-6569 A
15 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

54C7< 17B8< 16A4<>

AGP_AD_STB_L<0>

INTREPID AGP CLK IS 1.5V OUT


NEED 3.3V SWING FOR VIDEO CHIPS

+1_5V_INTREPID_PLL

52D3> 30D5< 28D6<> 9D4<

R667
4.7 2
1

VERSION 1 WORKAROUND IS LA CLOCK


VERSION 2 WORKAROUND IS UNUSED PIN

C760
0.1UF

52C3> 46B4<> 17D5< 17A4< 17A3< 16C2< 16A8< 11A6< 10D6<


59C7>

5%
1/16W
MF
402

C1801
0.1UF

20%
10V
CERM 2
402

+1_5V_AGP

54A7< 30C5<> 30A7<

INT_ROM_OVERLAY_PU

54A7< 17C6<

R225
22 2
54B7< 17A8< 16D3<

5%
1/16W
MF
402

THESE RESISTORS
SHARE THE SAME PAD

INT_V1

+3V_MAIN

R224
22 2

52C3> 16A7<

R226
0 2

INT_ANALYZER_CLK

5%
1/16W
MF
402

AN19

STP_AGP
AGPPVT
AGPVREF0
AB21 AGPVREF1
AJ24
AB20

8A2< 9B4< 54A7< 56B3>


59A7>

54B7< 17A8< 16C6<>

U25
INTREPID

AGPREQ
AGPGNT

BGA
(3 OF 9)

AGPAD0
AGPAD1
AGPAD2
AGPAD3
AGPAD4
AGPAD5
AGPAD6
AGPAD7
AGPAD8
AGPAD9
AGPAD10
AGPAD11
AGPAD12
AGPAD13
AGPAD14
AGPAD15
AGPAD16
AGPAD17
AGPAD18
AGPAD19
AGPAD20
AGPAD21
AGPAD22
AGPAD23
AGPAD24
AGPAD25
AGPAD26
AGPAD27
AGPAD28
AGPAD29
AGPAD30
AGPAD31

SEE_TABLE

(ON PAGE 12)

AT19

AGP_BUSY
AGP_CLK
AK27
AGP_FB_IN
AK25
AGP_FB_OUT
AK28

INT_AGP_FB_IN
INT_AGP_FB_OUT

54A7<
54A7<

NOSTUFF

2" LONGER

AGP

(0.5NS SLOWER)

2" SHORTER

(ZERO DELAY)

(0.5NS FASTER)

AGP_FBI_EQUAL

54A7<

AGP_FB_PLUS2

NOSTUFF

54A7<

AGP
INTERFACES

NOSTUFF

R203
0 2
1

R215
0 2
1

5%
1/16W
MF
402

5%
1/16W
MF
402
NOSTUFF
1

R220
0

R211
0

5%
1/16W
MF
2 402

NOSTUFF

R204
0 2

5%
1/16W
MF
2 402

NOSTUFF

5%
1/16W
MF
402

VOUT = AGPIO (1.5V)


VIN = VCORE (1.5V)

NOSTUFF
1

R622
0

5%
1/16W
MF
2 402

R216
0 2
5%
1/16W
MF
402

AGP_FBO_EQUAL

54A7<

PLACE ALL SERPENTINES ON INTERNAL LAYER

AGPCBE_0
AGPCBE_1
AGPCBE_2
AGPCBE_3

AGP_REQ_L
AGP_GNT_L

AT33
AM29

AM19
AT20
AR20
AT21
AN20
AR21
AN21
AM21
AT22
AR22
AN22
AM22
AN23
AR23
AT24
AM23
AR24
AT25
AR25
AM24
AN25
AL24
AR26
AT26
AM25
AN26
AM26
AR27
AT27
AR28
AN27

AT23
AN24
AL25
AT29

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

AT32

C603
470PF
1

R5491
4.99K

50V
CERM

1%
1/16W
MF 2
402

GPU_AGP_VREF_H

2
10%

54B7< 17B8< 16B1<

R545
82.5

AGP_WBF_L

AK30

AGP_WBF

1%
1/16W

AR29
AT28
AM28
AM27

AR32
AM31
AN31
AR31
AT31
AM30
AN30

MF
2 402

R2051
4.99K

VSSA_5
(PLL5)

1%
1/16W
MF
2 402

20%
2 10V
CERM
402

R197
82.5

C222
470PF
1

54B7< 17A8< 16A4<>

1%
1/16W
MF
402

R217
10K 2

54B7< 17A8> 16D3< 16C6<>

1%
1/16W
MF
402

R221
10K 2

NOSTUFF

AGP_BUSY_L

R161
10K 2

1%
1/16W
MF
402

52C3> 46B4<> 17D5< 17A4< 17A3< 16D7< 16A8< 11A6< 10D6<


59C7>

54B7< 17B6<> 16C4<>

AGP_REQ_L

+1_5V_AGP

RP37
10K

5%
1/16W
SM1

54B7< 17B6< 16C4<>

54C7< 17B8< 16B4<>

AGP_GNT_L

AGP_DEVSEL_L

54C7< 17B8< 16B4<>

RP98
10K
3

AGP_IRDY_L

54C7< 17B8< 16B4<>

17C8< 54C7<
17C8< 54C7<

AGP_STOP_L

NC_RP1PIN4

NO_TEST

54B7< 17A8< 16B4<

AGP_SBA<3>

54B7< 17A8< 16A4<>

54B7< 17B6< 16A4<>

1%
1/16W
MF
402
1

R587
10K 2

RP50
10K

AGP_WBF_L

54B7< 17B6< 16A4<>

AGP_ST<0>

RP50
10K

RP50
10K

5%
1/16W
SM1

5%
1/16W
SM1
4

1%
1/16W
MF
402

AGP_SBA<6>

54B7< 17B8< 16A6<>

RP49
10K
5%
1/16W
SM1

5%
1/16W
SM1

54B7< 17A8< 16A4<>

AGP_SBA<2>

5%
1/16W
SM1

AGP_ST<2>

5%
1/16W
SM1

RP49
10K

5%
1/16W
SM1

RP48
10K
2

AGP_ST<1>

RP99
10K

AGP_SBA<7>
RP49
10K
3

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

R580
10K 2
1

R233
10K 2

RP49
10K
1

AGP_SBA<0>

54B7< 17B6< 16A4<>

RP37
10K
1

5%
1/16W
SM1

AGP_SBA<4>

RP99
10K
5%
1/16W
SM1

5%
1/16W
SM1

54B7< 17A8< 16B4<>

17C8< 54C7<
17C8< 54C7<

RP99
10K
3

AGP_RBF_L
RP48
10K

54B7< 17A8< 16B4<>

5%
1/16W
SM1

54B7< 17A8< 16B4<>

RP98
10K
4

5%
1/16W
SM1

54B7< 17B8< 16A4<>

RP98
10K

RP99
10K

AGP_SBA<1>

AGP_TRDY_L
RP98
10K

5%
1/16W
SM1

54B7< 17A8< 16B4<>

5%
1/16W
SM1

5%
1/16W
SM1

54C7< 17B8< 16B4<>

AGP_SBA<5>

5%
1/16W
SM1

54C7< 17B8< 16B4<>

54B7< 17A8< 16B4<>


7

5%
1/16W
SM1

RP37
10K
3

AGP_FRAME_L

RP37
10K

RP50
10K

5%
1/16W
SM1

1%
1/16W
MF
402

AGP_ST<0>
AGP_ST<1>
AGP_ST<2>

16B1< 17B6< 54B7<


16B1< 17B6< 54B7<
16B1< 17B6< 54B7<

AGP_AD_STB<0> 16B3< 17B8< 54C7<


AGP_AD_STB_L<0> 16D1< 17B8< 54C7<
AGP_AD_STB<1> 16B3< 17B8< 54C7<
AGP_AD_STB_L<1> 16D1< 17B8< 54C7<

AK20
AK19
AK21
AK22

AGP_PIPE_L 16B3< 17B8< 54B7<


AGP_RBF_L 16B3< 17B8< 54B7<

INTREPID AGP
A

NOTICE OF PROPRIETARY PROPERTY

INT_PLL5_GND

LAST_MODIFIED=Mon Oct 27 12:29:42 2003

16D5<

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

XW48
SM

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

1
SIZE

10%

APPLE COMPUTER INC.

50V
CERM
402

R234
10K 2

1%
1/16W
MF
402

OMIT
2

GPU_AGP_VREF_L

1%
1/16W
MF
402

16C6<> 52C3>

C1802
0.1UF

AGP_SB_STB_L

R222
10K 2

V13

NO_TEST

1%
1/16W

AGP_SB_STB 16B3< 17B8< 54B7<


AGP_SB_STB_L 16D1< 17A8< 54B7<

AGPPIPE AJ29
AGPRBF AK24

402

INT_AGP_VREF

MF 2
402

AGP_AD_STB0_P
AGP_AD_STB0_N
AGP_AD_STB1_P
AGP_AD_STB1_N

54B7< 17B8< 16A4<> AGP_PIPE_L


AGP_PAR 17B8< 54B7<
AGP_FRAME_L 16C3< 17B8< 54C7<
AGP_TRDY_L 16B3< 17B8< 54C7<
AGP_IRDY_L 16C3< 17B8< 54C7< 54C7< 17B8< 16A4<> AGP_AD_STB<0>
AGP_STOP_L 16B3< 17B8< 54C7<
AGP_DEVSEL_L 16C3< 17B8< 54C7<
AGP_SBA<0> 16C1< 17A8< 54B7< 54C7< 17B8< 16A4<> AGP_AD_STB<1>
AGP_SBA<1> 16C1< 17A8< 54B7<
AGP_SBA<2> 16B1< 17A8< 54B7<
AGP_SBA<3> 16C1< 17A8< 54B7<
54B7< 17B8< 16A4<> AGP_SB_STB
AGP_SBA<4> 16C1< 17A8< 54B7<
AGP_SBA<5> 16C1< 17A8< 54B7<
AGP_SBA<6> 16B1< 17A8< 54B7<
AGP_SBA<7> 16B1< 17A8< 54B7<

AN28

AGP_ST0 AN29
AGP_ST1 AT30
AGP_ST2 AR30

(PLACE CLOSE TO GPU AGP BALLS)

STOP_AGP_L

16C3< 17B6< 54B7<

AGP_CBE<0>
AGP_CBE<1>
AGP_CBE<2>
AGP_CBE<3>

AM20

AGPPAR
AGPFRAME
AGPTRDY
AGPIRDY
AGPSTOP
AGPDEVSEL

GPU AGP I/O REFERENCE


+1_5V_AGP

16C3< 17B6<> 54B7<

AGP_AD<0> 17D8< 54C7<


AGP_AD<1> 17D8< 54C7<
AGP_AD<2> 17D8< 54C7<
AGP_AD<3> 17D8< 54C7<
AGP_AD<4> 17D8< 54C7<
AGP_AD<5> 17D8< 54C7<
AGP_AD<6> 17D8< 54C7<
AGP_AD<7> 17D8< 54C7<
AGP_AD<8> 17D8< 54C7<
AGP_AD<9> 17D8< 54C7<
AGP_AD<10> 17D8< 54C7<
AGP_AD<11> 17D8< 54C7<
AGP_AD<12> 17D8< 54C7<
AGP_AD<13> 17D8< 54C7<
AGP_AD<14> 17D8< 54C7<
AGP_AD<15> 17C8< 54C7<
AGP_AD<16> 17C8< 54C7<
AGP_AD<17> 17C8< 54C7<
AGP_AD<18> 17C8< 54C7<
AGP_AD<19> 17C8< 54C7<
AGP_AD<20> 17C8< 54C7<
AGP_AD<21> 17C8< 54C7<
AGP_AD<22> 17C8< 54C7<
AGP_AD<23> 17C8< 54C7<
AGP_AD<24> 17C8< 54C7<
AGP_AD<25> 17C8< 54C7<
AGP_AD<26> 17C8< 54C7<
AGP_AD<27> 17C8< 54C7<
AGP_AD<28> 17C8< 54C7<
AGP_AD<29> 17C8< 54C7<
AGP_AD<30> 17C8< 54C7<
AGP_AD<31> 17C8< 54C7<

AR19

AGP_SB_STB_P AH25
AGP_SB_STB_N AG25

59C7> 52C3> 46B4<>


16D7< 16C2< 11A6< 10D6<
17D5< 17A4< 17A3<

AGP_BUSY_L

VDD15A_5
(PLL5)

54B7< 17A8> 16D3< 16D1< AGP_BUSY_L


54A7< CLK66M_GPU_UF

5%
1/16W
MF
402

54B7< 17A8> 16D1< 16C6<>

16A5<>

V14

STOP_AGP_L
INT_AGPPVT
INT_AGP_VREF

AGP_AD_STB_L<1>

INT_PLL5_GND

1%
1/16W
MF
2 402

INT_V2

CLK66M_GPU_AGP

54C7< 17B8< 16A4<>

20%
10V
CERM 2
402

R619
60.4

1%
1/16W
MF
402

AGP PULL-UPS/PULL DOWNS


+1_5V_INTREPID_PLL5 52D3>

R223
10K 2

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
16
69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

52C3> 46B4<> 17A4< 17A3< 16D7< 16C2< 16A8< 11A6< 10D6<


59C7>

44D3< 27C5<

AGP_RESET_L

2
3
4

RP30
22

NO_TEST

5%
1/16W
SM1

NO_TEST

NO_TEST

1
2
3
4

RP32
22
5%
1/16W
SM1

3
4

RP42
22
5%
1/16W
SM1

3
4

RP31
22
5%
1/16W
SM1

1
2
3
4

3
4

3
4

2
3
4

1
402

01

5%
1/16W
SM1

5%
1/16W
SM1

54C7< 16C3< 16B4<>

54B7< 16B4<> AGP_PAR


54C7< 16B4<> 16B3< AGP_STOP_L

AGP_DEVSEL_L

54C7< 16C3< 16B4<>

NO_TEST

NO_TEST

NO_TEST

NO_TEST

NO_TEST

NO_TEST

NO_TEST

NO_TEST

NO_TEST

NO_TEST

5%
1/16W
SM1

NO_TEST

NO_TEST

54B7<

RP43
22

5%
1/16W
SM1

NO_TEST

54B7<
54B7<

NO_TEST

54B7<

AGP_WBF_L
54B7< 16B3< 16A4<> AGP_PIPE_L
54B7< 16B3< 16A4<> AGP_RBF_L

5%
1/16W
SM1

NO_TEST

NO_TEST

AGP_GNT_L
AGP_REQ_L

GPU_AGP_FRAME_L
GPU_AGP_IRDY_L
GPU_AGP_TRDY_L
NO_TEST 54B7< GPU_AGP_DEVSEL_L
NO_TEST
54B7< GPU_AGP_STOP_L
54B7< GPU_AGP_PAR

RP35

5%
1/16W
SM1

RP46
22

7
6
5

54B7<
54B7<

54B7< 16B3< 16A4<> AGP_SB_STB


54B7< 16D1< 16A4<> AGP_SB_STB_L
54B7< 16C1< 16B4<>
54B7< 16B4<> 16B1<
54B7< 16C1< 16B4<>
54B7< 16C1< 16B4<
54B7< 16B1< 16A4<>
54B7< 16B1< 16A4<>
54B7< 16C1< 16B4<>
54B7< 16C1< 16B4<>

3
4

R210
1

AGP_SBA<3>
AGP_SBA<2>
AGP_SBA<1>
AGP_SBA<0>
AGP_SBA<7>
AGP_SBA<6>
AGP_SBA<4>
AGP_SBA<5>

RP33
22
5%
1/16W
SM1

3
4

54B7<

54B7<
54B7<

54B7< 16D3< 16C6<>


52A6> 17A2<

AK21
AH20
AJ20
AG26
AE24
AG25
AG24
AF24
AG23
AE22
AF22
AE21
AG20
AG19
AF19
AE19
AF18
AG18
AE18

AG12
AF15

AE15
AF13

AK16
AG16
AJ17
AJ16
AH17
AK18

AG15

RP47
22
5%
1/16W
SM1

RP36
22
5%
1/16W
SM1

AGP_AD_STB_L_GPUUF<1> AF21

54A7< GPU_AGP_SB_STB AK13


54A7< GPU_AGP_SB_STB_L AJ13

22 NO_TEST

54A7<

NO_TEST 54A7<
NO_TEST 54A7<

7
6
5

54A7<

8
7

NO_TEST 54A7<
NO_TEST 54A7<

NO_TEST 54A7<

54A7<

GPU_AGP_SBA<0>
GPU_AGP_SBA<1>
GPU_AGP_SBA<2>
GPU_AGP_SBA<3>
GPU_AGP_SBA<4>
GPU_AGP_SBA<5>
GPU_AGP_SBA<6>
GPU_AGP_SBA<7>

GPU_MBDET_L
54B7< 16D3< 16D1< 16C6<>

AJ21

NO_TEST 54B7<

1
2

AJ22

AH22

54B7< AGP_AD_STB_GPUUF<0> AK24


NO_TEST 54B7< AGP_AD_STB_L_GPUUF<0> AJ25
NO_TEST
54B7< AGP_AD_STB_GPUUF<1> AG21

R558

22

AJ23

:
:
:
:
:

PCICLK
PCIRST*

: CLK
: RST*

PCIGNT*
PCIREQ*

: GNT
: REQ

PCIFRAME*
PCIIRDY*
PCITRDY*
PCIDEVSEL*
PCISTOP*
PCIPAR

:
:
:
:
:
:

FRAME
IRDY
TRDY
DEVSEL
STOP
PAR

PCIINTA*
:
NC_PCIINTB*:
AGPRBF*
:
AGPWBF*
:
AGPPIPE*
:
<RESRVD>
:
AGPST0
:
AGPST1
:
AGPST2
:

INTA
INTB
RBF
WBF
DBI_HI
DBI_LO
ST0
ST1
ST2

AGP_BUSY_L
STOP_AGP_L

AJ11
AH11
AJ12
AH12
AJ14
AH14
AJ15
AH15
AF16
AF12
AG11

GPU_AGP_VREF

C202
0.1UF

20%
10V
2 CERM
402

C180
0.1UF

20%
10V
2 CERM
402

C185
0.1UF

20%
10V
2 CERM
402

C203
0.1UF

20%
10V
2 CERM
402

C183
0.1UF

20%
10V
2 CERM
402

C176
0.1UF

20%
10V
2 CERM
402

AE23
AD11

52A6> 48C2<> 23C7<>

GRAPH_CORE

CORE BYPASS

AD14

MIN_LINE_WIDTH=20

AD23
AD20
AD17

C104
0.01UF

10%
16V
2 CERM
402

AA17
AA18

C134
0.01UF

C117
0.1UF

20%
10V
2 CERM
402

10%
16V
2 CERM
402

C109
0.1UF

20%
10V
2 CERM
402

C100
0.1UF

20%
10V
2 CERM
402

C101
0.1UF

20%
10V
2 CERM
402

C103
0.1UF

C110
0.1UF

20%
10V
2 CERM
402

C139
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C99
0.1UF

20%
10V
2 CERM
402

C146
0.1UF

20%
10V
2 CERM
402

L20
Y20

MIN_LINE_WIDTH=20

L13
Y13
N20

P20

V20

VDD

C148
0.01UF

10%
16V
2 CERM
402

U20

L11

C149
0.01UF

10%
16V
2 CERM
402

C150
0.1UF

20%
10V
2 CERM
402

C147
0.1UF

20%
10V
2 CERM
402

C118
0.1UF

20%
10V
2 CERM
402

C135
0.1UF

20%
10V
2 CERM
402

C169
0.1UF

C140
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

N11
P11

MIN_LINE_WIDTH=20

U11
V11
2

Y11

C161
10UF

N20P80%
1 10V
Y5V
805

L14
Y14
L17

C93
10UF

N20P80%
1 10V
Y5V
805

C168
10UF

N20P80%
1 10V
Y5V
805

C94
10UF

C120
0.1UF

20%
10V
2 CERM
402

N20P80%
1 10V
Y5V
805

C102
0.1UF

20%
10V
2 CERM
402

C151
0.1UF

+3V_MAIN

20%
10V
2 CERM
402

Y17

AGP 8X
C0*/BE0
C1*/BE1
C2*/BE2
C3*/BE3

AGP_PLLVDD

Y18

R198
10 2

1%
1/16W
MF
402

L18

+3V_MAIN

C223
4.7UF

N20P80%
10V
CERM
805

20%
2 10V
CERM
402

C219
0.1UF

C217
0.001UF

10%
2 50V
CERM
402

I/O BYPASS

AC6
U7

VDD33

C177
0.01UF

U6

AD15

10%
16V
2 CERM
402

H7
AD16

C111
0.01UF

10%
16V
2 CERM
402

C129
0.1UF

20%
10V
2 CERM
402

C136
0.1UF

20%
10V
2 CERM
402

C116
0.1UF

20%
10V
2 CERM
402

C87
0.1UF

20%
10V
2 CERM
402

C184
0.1UF

20%
10V
2 CERM
402

AD19
AD22

AK29

AGPSBSTBF
AGPSBSTBS*

P24
2

+5V_MAIN

:
:
:
:
:
:
:
:

<RESRVD>
AGPBUSY*
AGPSTOP*

: MBDET*
: BUSY*
: STOP*

AGPVREF

1%
1/16W
MF 2
402

AGP_PLLVDD

AE12

: AGPVREF

ALL ARE NO_TEST

C137
10UF

C193
0.1UF

20%
10V
2 CERM
402

AA13

50 OHM
TO GND

C91
0.01UF

10%
16V
2 CERM
402

C97
0.01UF

10%
16V
2 CERM
402

C187
0.1UF

C179
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C105
0.1UF

20%
10V
2 CERM
402

C112
0.1UF

20%
10V
2 CERM
402

C181
0.1UF

20%
10V
2 CERM
402

C182
0.1UF

20%
10V
2 CERM
402

C188
0.1UF

20%
10V
2 CERM
402

GPU_50PULLUP
GPU_50PULLDWN 52A8>

GPU AGP I/O REFERENCE

AA14

46B4<> 17D5< 17A4< 16D7< 16C2<

(PLACE CLOSE TO INTREPID AGP BALLS)


C214
470PF
1
2
16A8< 11A6< 10D6< +1_5V_AGP
R195
4.99K

10K OHM
TO GND
AE5

52A8>

R177
10K

1%
1/16W
2 MF
402

R160
49.9

1%
1/16W
2 MF
402

10D6<
+1_5V_AGP 59C7>
1

R169
49.9

10K

402

NC_NVAGP_TDO
NVAGP_TDI
NVAGP_TMS

GPU_AGP_VREF

1%
1/16W
MF
402 2

10K

R1025

17A8< 52A6>

R196
4.99K

NV34

R192
82.5

1%
1/16W
MF
2 402

1%
1/16W
2 MF
402

R10241

R72

11A6< 16A8< 16C2< 16D7< 17A3< 17D5< 46B4<> 52C3>

+3V_MAIN
NVAGP_TRST_L

10%
50V
CERM
402

1%
1/16W
MF
402 2

GPU_TMODE
1

GPU_AGP_VREF_X

59C7> 52C3>
1

TESTMODE

20%
10V
2 CERM
402

C186
0.1UF

52A8>

AGPCALPU

N20P80%
1 10V
Y5V
805

AE9

50 OHM
TO VDDQ

AGPCALPD

SBA0*
SBA1*
SBA2*
SBA3*
SBA4*
SBA5*
SBA6*
SBA7*

NC

VD50CLAMP0
VD50CLAMP1

N4

: SBSTBF
: SBSTBS

AGPSBA0
AGPSBA1
AGPSBA2
AGPSBA3
AGPSBA4
AGPSBA5
AGPSBA6
AGPSBA7

+3V_MAIN
R168
10K

AD12

AGPADSTBF0 : ADSTBF0
AGPADSTBS0* : ADSTBS0
AGPADSTBF1 : ADSTBF1
AGPADSTBS1* : ADSTBS1

AGP VERSION SELECT


(LOW = AGP V3.X)
(HIGH = AGP V2.X)

20%
10V
2 CERM
402

AC7

AH23

AGP_INT_L
AE10
NC_GPU_INTB_L
NO_TEST
54A7< GPU_AGP_RBF_L AG14
GPU_AGP_WBF_L AG17
NO_TEST
54A7< GPU_AGP_PIPE_L AJ18
AJ19
NC_GPU_DBI_LO
AG13
16B1< 16A4<> AGP_ST<0>
AE16
16B1< 16A4<> AGP_ST<1>
AE13
16B1< 16A4<> AGP_ST<2>

1
2

AH25

C201
0.1UF

20%
10V
2 CERM
402

MIN_LINE_WIDTH=20

AE20

AGPVDDQ

22

54B7<

AGP_AD_STB<0>
54C7< 16D1< 16A4<> AGP_AD_STB_L<0>
54C7< 16D1< 16A4<> AGP_AD_STB_L<1>
54C7< 16B3< 16A4<> AGP_AD_STB<1>

AJ26

C178
0.1UF

G14

22

3
5%
41/16W
SM1

54C7< 16B3< 16A4<>

AH26

AE17

RP45

54B7< 16B1< 16A6<>

AJ27

10%
16V
2 CERM
402

H6

54B7< 16C4<> 16C3<


54B7< 16C4<> 16C3<

28B8< 28B5<>

AK27

GPU_AGP_CBE<0> AJ24
GPU_AGP_CBE<1> AH19
GPU_AGP_CBE<2> AF25
GPU_AGP_CBE<3> AG22

54A7< 16D8< CLK66M_GPU_AGP


NV_PCI_RST_L

5%

R1027
2
1

NO_TEST

RP34
22

TMDS_XMIT_SI_P

AGP_IRDY_L

NO_TEST

5%

54C7< 16B4<> 16B3< AGP_TRDY_L


54C7< 16C3< 16B4<> AGP_FRAME_L

RP44
22

R1026
2

402

NO_TEST

1
2

RP41
22

1
2

NO_TEST

1
2

NO_TEST

1
2

AH27

TCLK
TMS
TDI
E2 TDO
D2 TRST*

MAIN_RESET_L

AK28

C200
0.01UF

R193
82.5

C215
470PF
1

1%
1/16W
MF
2 402

GPU_AGP_VREF_Y

10%
50V
CERM
402

D1

59A5>
31D4< 30B2<
44C4<> 32A8<

NO_TEST

C192
0.01UF

10%
16V
2 CERM
402

AE14

C1

54C7< 16B4<>

NO_TEST

C2

54C7< 16B4<>
54C7< 16B4<>

NO_TEST

AE11

T7

5%
1/16W
SM1

PCIAD0
PCIAD1
PCIAD2
PCIAD3
PCIAD4
PCIAD5
PCIAD6
PCIAD7
PCIAD8
PCIAD9
PCIAD10
PCIAD11
PCIAD12
PCIAD13
PCIAD14
PCIAD15
PCIAD16
PCIAD17
PCIAD18
PCIAD19
PCIAD20
PCIAD21
PCIAD22
PCIAD23
PCIAD24
PCIAD25
PCIAD26
PCIAD27
PCIAD28
PCIAD29
PCIAD30
PCIAD31
AGP 2X,4X
PCIC0/BE0*
PCIC1/BE1*
PCIC2/BE2*
PCIC3/BE3*

R7

AGP_CBE<0>
AGP_CBE<3>
AGP_CBE<2>
AGP_CBE<1>

54C7< 16B4<>

AJ28

A1

54B7<

NC_GPU<0>
NC_GPU<1>
NC_GPU<2>
NC_GPU<3>
NC_GPU<4>

GPU_AGP_AD<0>
54B7< GPU_AGP_AD<1>
54B7< GPU_AGP_AD<2>
54B7< GPU_AGP_AD<3>
54B7< GPU_AGP_AD<4>
54B7< GPU_AGP_AD<5>
54B7< GPU_AGP_AD<6>
54B7< GPU_AGP_AD<7>
54B7< GPU_AGP_AD<8>
54B7< GPU_AGP_AD<9>
54B7< GPU_AGP_AD<10>
54B7< GPU_AGP_AD<11>
54B7< GPU_AGP_AD<12>
54B7< GPU_AGP_AD<13>
54B7< GPU_AGP_AD<14>
54B7< GPU_AGP_AD<15>
54B7< GPU_AGP_AD<16>
54B7< GPU_AGP_AD<17>
54B7< GPU_AGP_AD<18>
54B7< GPU_AGP_AD<19>
54B7< GPU_AGP_AD<20>
54B7< GPU_AGP_AD<21>
54B7< GPU_AGP_AD<22>
54B7< GPU_AGP_AD<23>
54B7< GPU_AGP_AD<24>
54B7< GPU_AGP_AD<25>
54B7< GPU_AGP_AD<26>
54B7< GPU_AGP_AD<27>
54B7< GPU_AGP_AD<28>
54B7< GPU_AGP_AD<29>
54B7< GPU_AGP_AD<30>
54B7< GPU_AGP_AD<31>

RP40
22

G6

AK30

AGP_AD<0>
54C7< 16C4<> AGP_AD<1>
54C7< 16C4<> AGP_AD<2>
54C7< 16C4<> AGP_AD<3>
54C7< 16C4<> AGP_AD<7>
54C7< 16C4<> AGP_AD<5>
54C7< 16C4<> AGP_AD<6>
54C7< 16C4<> AGP_AD<4>
54C7< 16C4<> AGP_AD<8>
54C7< 16C4<> AGP_AD<9>
54C7< 16C4<> AGP_AD<10>
54C7< 16C4<> AGP_AD<11>
54C7< 16C4<> AGP_AD<12>
54C7< 16C4<> AGP_AD<13>
54C7< 16C4<> AGP_AD<14>
54C7< 16C4<> AGP_AD<15>
54C7< 16C4<> AGP_AD<16>
54C7< 16C4<> AGP_AD<18>
54C7< 16C4<> AGP_AD<17>
54C7< 16C4<> AGP_AD<19>
54C7< 16C4<> AGP_AD<20>
54C7< 16C4<> AGP_AD<21>
54C7< 16C4<> AGP_AD<22>
54C7< 16C4<> AGP_AD<23>
54C7< 16B4<> AGP_AD<24>
54C7< 16B4<> AGP_AD<25>
54C7< 16B4<> AGP_AD<26>
54C7< 16B4<> AGP_AD<27>
54C7< 16B4<> AGP_AD<28>
54C7< 16B4<> AGP_AD<29>
54C7< 16B4<> AGP_AD<30>
54C7< 16B4<> AGP_AD<31>
54C7< 16C4<>

OUTPUT DRIVER BYPASS

+1_5V_AGP

U39
NV18B
BGA
(1 OF 5)

NV34

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

1%
1/16W
MF
402 2

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

NVAGP_TCLK

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:29:45 2003

10K

1%
1/16W
MF
402 2

NVIDIA AGP

R80
1
402

10K

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
17 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

+2_5V_MAIN
2

C86
0.01UF

C84
0.1UF

10V
CERM

10%
1

EVENLY DISTRIBUTE 0.01UF & 0.1 UF CAPS

C73
0.1UF

10V
CERM

20%

16V
CERM
402

C81
0.1UF

10V
CERM

20%

402

20%

402

C90
0.01UF

C72
0.1UF

10V
CERM

10%
1

402

20%

16V
CERM
402

C78
0.01UF

C98
0.1UF

10V
CERM

10%
1

402

C133
0.1UF

20%

16V
CERM
402

C167
0.1UF

10V
CERM

20%
1

402

20%

10V
CERM
402

C159
0.1UF

20%
1

402

C95
10UF

402

C75
0.1UF

10V
CERM

C82
0.1UF

10V
CERM

20%

N20P80%
10V
2 Y5V
805

10V
CERM

402

20%

C79
0.1UF

C115
0.01UF

16V
CERM

20%
1

402

10V
CERM
402

10%

C175
0.1UF

20%
1

402

C199
0.1UF

C83
0.01UF

16V
CERM

20%

10V
CERM

402

10%

10V
CERM

AMONGST FBVDDQ PINS ON NV ASIC

402

C80
0.1UF

C89
0.01UF

16V
CERM

20%
1

402

C96
0.1UF

10V
CERM

10%

10V
CERM
402

C145
0.1UF

10V
CERM

20%

402

20%

402

402

C124
10UF

20%
6.3V
2 CERM
805

+2_5V_MAIN
FBD<0>
55D3> 19D8< FBD<1>
55D3> 19D8< FBD<2>
55D3> 19D8< FBD<3>
55D3> 19D8< FBD<4>
55D3> 19D8< FBD<5>
55D3> 19D8< FBD<6>
55D3> 19D8< FBD<7>
55D3> 19D8< FBD<8>
55D3> 19D8< FBD<9>
55D3> 19D8< FBD<10>
55D3> 19D8< FBD<11>
55D3> 19D8< FBD<12>
55D3> 19D8< FBD<13>
55D3> 19D8< FBD<14>
55D3> 19D8< FBD<15>
55D3> 19D8< FBD<16>
55D3> 19D8< FBD<17>
55D3> 19D8< FBD<18>
55D3> 19C8< FBD<19>
55D3> 19C8< FBD<20>
55D3> 19C8< FBD<21>
55D3> 19C8< FBD<22>
55D3> 19C8< FBD<23>
55D3> 19C8< FBD<24>
55D3> 19C8< FBD<25>
55D3> 19C8< FBD<26>
55D3> 19C8< FBD<27>
55D3> 19C8< FBD<28>
55D3> 19C8< FBD<29>
55D3> 19C8< FBD<30>
55D3> 19C8< FBD<31>
55D3> 19D5< FBD<32>
55D3> 19D5< FBD<33>
55D3> 19D5< FBD<34>
55D3> 19D5< FBD<35>
55D3> 19D5< FBD<36>
55D3> 19D5< FBD<37>
55D3> 19D5< FBD<38>
55D3> 19D5< FBD<39>
55D3> 19D5< FBD<40>
55D3> 19D5< FBD<41>
55D3> 19D5< FBD<42>
55D3> 19D5< FBD<43>
55D3> 19D5< FBD<44>
55D3> 19D5< FBD<45>
55D3> 19D5< FBD<46>
55D3> 19D5< FBD<47>
55D3> 19D5< FBD<48>
55D3> 19D5< FBD<49>
55D3> 19D5< FBD<50>
55D3> 19C5< FBD<51>
55D3> 19C5< FBD<52>
55D3> 19C5< FBD<53>
55D3> 19C5< FBD<54>
55D3> 19C5< FBD<55>
55D3> 19C5< FBD<56>
55D3> 19C5< FBD<57>
55D3> 19C5< FBD<58>
55D3> 19C5< FBD<59>
55D3> 19C5< FBD<60>
55D3> 19C5< FBD<61>
55D3> 19C5< FBD<62>
55D3> 19C5< FBD<63>

N25

55D3> 19D8<

55D3> 18G3<
55D3> 18G3<
55D3> 18G3<
55D3> 18G3<
55D3> 18G3<
55D3> 18G3<
55D3> 18G3<
55D3> 18G3<

N27
N26
M25
K26
K27
J27
H27
N29
M29
M28
L29
J29
J28
H29
G30
K25
J26
J25
G26
F28
F26
E27
D27
H28
G29
F29
E29
C30
C29
B30
A30
AJ29
AJ30
AH29
AH30
AF29
AE29
AD29
AC28
AG28
AF27
AE26
AE28
AD25
AB25
AB26
AA25
AD30
AC29
AB28
AB29
Y29
W28
W29
V29
AC27
AB27
AA27
AA26
W25
V26
V27
V25

FBDQM<0>
FBDQM<1>
FBDQM<2>
FBDQM<3>
FBDQM<4>
FBDQM<5>
FBDQM<6>
FBDQM<7>

L27
K29
G25
E28
AF28
AD27
AA30
Y27

FBA<0>
FBA<1>
55D3> 18F3< FBA<2>
55D3> 18F3< FBA<3>
55D3> 18F3< FBA<4>
55D3> 18F3< FBA<5>
55D3> 18E3< FBA<6>
55D3> 18E3< FBA<7>
55D3> 18E3< FBA<8>
55D3> 18E3< FBA<9>
55D3> 18E3< FBA<10>
55D3> 18E3< FBA<11>
55D3> 18E3< FBA<12>

V30

FBABA<0>
FBABA<1>

R26

55D3> 18F3<
55D3> 18F3<

55D3> 18E3<
55D3> 18E3<

55D3> 18G3< FBARAS_L


55D3> 18G3< FBACAS_L
55D3> 18F3< FBAWE_L
55D3> 18F3< FBACS0_L
NC_FBACS1_L

U28
U29
T28
T29
T27
T30
T26
T25
R27
R25
R30
U24

R29

P28
P29
R28
U27
TESTPOINT

P27

52A6> GPU_FB_VREF

ROMA14
26D8< ROMA15
NC_ROMCS_L
26D8<

R2

TESTPOINT

R1

TESTPOINT

G11

FBAD0
FBAD1 (3 OF 5)
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBVDDQ
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
NC_VTT
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
GND
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7
FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBAA12

L25
Y25
F11
F14
F20
F23
Y24
L24
G20
G23
H24
AC24
H25
P25
U25

NO_TEST

AC25

NO_TEST
NO_TEST

G9
G12
G15
G16
G19
G22
J24
M24
R24
T24
W24
AB24
A25
AK25
AA5
AF20
AH16
AK15
AF11
AH21
U26
AD28
AH18
F25
C18
E14
AF8
Y8
K3
G3
F6
AF17
AF23
AH24
AH28
AG27
AF26
AF14
AH13
L8
P26
G28
K28
N28
V28
AA28
F30
J30
M30
W30
AB30
AE30
H26
L26
Y26
AC26
E17
D28
C7
E8
A9
C10
E11
C13
E20
C21
E23
C24
A6
A12
AH10
AK12
C3
D4
E5
AG4
AH3
AK6
AH7
AF5
AE6
AK9
N3
H11
AC11
H20
AC20
L23
Y23
F1
J1
M1
T1
W1
AB1
AE1
A19
AK19
A22
AK22
K5
J7
AE25

FBCAL_TERM_GND D3
FBCAL_CLK_GND E3

FBVREF
ROMA14
ROMA15
ROMCS*

FB_DLLVDD C27
FBACKE N30
FBACLK0 U21
FBACLK0* V21
FBACLK1 N21
FBACLK1* P21
M27

FBADQS0
K30
FBADQS1
G27
FBADQS2
D30
FBADQS3
AG30
FBADQS4
AD26
FBADQS5
AA29
FBADQS6
W27
FBADQS7
NC_FBADQS0*
NC_FBADQS1*
NC_FBADQS2*
NC_FBADQS3*
NC_FBADQS4*
NC_FBADQS5*
NC_FBADQS6*
NC_FBADQS7*

FBD<64>
55C3> 19C8< FBD<65>
55C3> 19C8< FBD<66>
55C3> 19C8< FBD<67>
55C3> 19C8< FBD<68>
55C3> 19C8< FBD<69>
55C3> 19C8< FBD<70>
55C3> 19C8< FBD<71>
55C3> 19C8< FBD<72>
55C3> 19C8< FBD<73>
55C3> 19B8< FBD<74>
55C3> 19B8< FBD<75>
55C3> 19B8< FBD<76>
55C3> 19B8< FBD<77>
55C3> 19B8< FBD<78>
55C3> 19B8< FBD<79>
55C3> 19B8< FBD<80>
55C3> 19B8< FBD<81>
55C3> 19B8< FBD<82>
55C3> 19B8< FBD<83>
55C3> 19B8< FBD<84>
55C3> 19B8< FBD<85>
55C3> 19B8< FBD<86>
55C3> 19B8< FBD<87>
55C3> 19B8< FBD<88>
55C3> 19B8< FBD<89>
55C3> 19B8< FBD<90>
55C3> 19B8< FBD<91>
55C3> 19B8< FBD<92>
55C3> 19B8< FBD<93>
55C3> 19B8< FBD<94>
55C3> 19B8< FBD<95>
55C3> 19C5< FBD<96>
55C3> 19C5< FBD<97>
55C3> 19C5< FBD<98>
55C3> 19C5< FBD<99>
55C3> 19C5< FBD<100>
55C3> 19C5< FBD<101>
55C3> 19C5< FBD<102>
55C3> 19C5< FBD<103>
55C3> 19C5< FBD<104>
55C3> 19C5< FBD<105>
55C3> 19B5< FBD<106>
55C3> 19B5< FBD<107>
55C3> 19B5< FBD<108>
55C3> 19B5< FBD<109>
55C3> 19B5< FBD<110>
55C3> 19B5< FBD<111>
55C3> 19B5< FBD<112>
55C3> 19B5< FBD<113>
55C3> 19B5< FBD<114>
55C3> 19B5< FBD<115>
55C3> 19B5< FBD<116>
55C3> 19B5< FBD<117>
55C3> 19B5< FBD<118>
55C3> 19B5< FBD<119>
55C3> 19B5< FBD<120>
55C3> 19B5< FBD<121>
55C3> 19B5< FBD<122>
55C3> 19B5< FBD<123>
55C3> 19B5< FBD<124>
55C3> 19B5< FBD<125>
55C3> 19B5< FBD<126>
55C3> 19B5< FBD<127>

M26
L28
F27
D29
AG29
AE27
Y28
W26

F13

55C3> 19C8<

F8

FBCAL_PU_GND E4

FBARAS*
FBACAS*
FBAWE*
FBACS0*
FBACS1*

AF2

G8

FBCAL_PD_VDDQ F5

FBABA0
FBABA1

C28
TESTPOINT

F17

U39
NV18B
BGA

NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST

NC_VTT<0>
NC_VTT<1>
NC_VTT<2>
NC_VTT<3>
NC_VTT<4>
NC_VTT<5>
NC_VTT<6>
NC_VTT<7>
NC_VTT<8>
NC_VTT<9>
NC_VTT<10>
NC_VTT<11>

+2_5V_MAIN

D13
E13
F12
E10
D10
D9
D8
B13
B12
C12
B11
B9
C9
B8
A7
F10
E9
F9
F7
C6
E6
D5
C4
C8
B7
B6
B5
A3
B3
A2
B2
B29
A29
B28
A28
B26
B25
B24
C23
E26
D26
E25
C25
E24
F22
E22
F21
A24
B23
C22
B22
B20
C19
B19
B18
D23
D22
D21
E21
F19
E18
D18
F18

FBDQM<8>
55C3> 18D3< FBDQM<9>
55C3> 18D3< FBDQM<10>
FBDQM<11>
18D3<
55C3>
55C3> 18D3< FBDQM<12>
55C3> 18D3< FBDQM<13>
55C3> 18C3< FBDQM<14>
55C3> 18C3< FBDQM<15>

D11

FBBA<0>
FBBA<1>
55C3> 18B3< FBBA<2>
55C3> 18B3< FBBA<3>
55C3> 18B3< FBBA<4>
55C3> 18B3< FBBA<5>
55C3> 18B3< FBBA<6>
55C3> 18B3< FBBA<7>
55C3> 18B3< FBBA<8>
55C3> 18B3< FBBA<9>
55C3> 18B3< FBBA<10>
55C3> 18B3< FBBA<11>
55C3> 18A3< FBBA<12>

A18

FBBBA<0>
FBBBA<1>

E15

FBBCLK0
55B3> 19B3< FBBCLK0_L
55B3> 19C3< FBBCLK1
55B3> 19B3< FBBCLK1_L

K18

55C3> 18D3<

R71
49.9

1%
1/16W
MF
2 402

FBCAL_PD_VDDQ
FBCAL_PU_GND 18A5<

2 C62

FBCAL_TERM_GND 18A5<

20%
CERM
1 10V
402

FBCAL_CLK_GND

18C6< FB_DLLVDD

FBACKE 18D3<

55D3>

FBACLK0 19C3< 55C3>


FBACLK0_L 19C3< 55C3>
FBACLK1 19D3< 55C3>
FBACLK1_L 19D3< 55C3>
FBDQS<0>
FBDQS<1>
FBDQS<2>
FBDQS<3>
FBDQS<4>
FBDQS<5>
FBDQS<6>
FBDQS<7>

D7
C5
C26
F24
B21
D20

55C3> 18C3<
55C3> 18B3<

0.1UF

18A5<

B10

19A8< 55C3>
19A8< 55C3>

55C3> 18A3<
55C3> 18A3<

19A8< 55C3>
19A8< 55C3>
19A8< 55C3>

C17
B17
C16
B16
D16
A16
E16
F16
D15
F15
A15
G17

B15

55B3> 19B3<

19A8< 55C3>
19A8< 55C3>
19A8< 55C3>

K17
K13
K14

NC_FBDQS_L<0>
NC_FBDQS_L<1>
NC_FBDQS_L<2>
NC_FBDQS_L<3>
NC_FBDQS_L<4>
NC_FBDQS_L<5>
NC_FBDQS_L<6>
NC_FBDQS_L<7>

U39
NV18B
FBCD0 (4 BGA
OF 5)
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
THERMAL GND
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63
FBCDQS0
FBCDQS1
FBCDQS2
FBCDQS3
FBCDQS4
FBCDQS5
FBCDQS6
FBCDQS7

FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7
FBCA0
FBCA1
FBCA2
FBCA3
FBCA4
FBCA5
FBCA6
FBCA7
FBCA8
FBCA9
FBCA10
FBCA11
FBCA12

NC_FBCDQS0*
NC_FBCDQS1*
NC_FBCDQS2*
NC_FBCDQS3*
NC_FBCDQS4*
NC_FBCDQS5*
NC_FBCDQS6*
NC_FBCDQS7*
FBCRAS*
FBCCAS*
FBCWE*
FBCCS0*
FBCCS1*
FBCCKE

FBCBA0
FBCBA1

DQM RS CLOSE TO GPU


OTHER RS BETWEEN GPU & MEMORY

N13
P13
U13
V13

R14

55D3> 18D8>

55D3> 18D8>
55D3> 18D8>

FBDQM<4>

55D3> 18D8>

FBDQM<5>

55D3> 18D8>

FBDQM<6>

55D3> 18D8>

FBDQM<7>

R164 0
1

U7
TLV431A
SOT

1%
1/16W
MF
2 402

C54
0.1UF

NOSTUFF

C510
100PF

5%
50V
2 CERM
402

R463
1K

1%
1/16W
MF
2 402

C509
0.1UF

R50
0

1/16W

55D3>

RFBDQM<3> 20C6<

55D3>

RFBDQM<4> 20C2<

55D3>

RFBDQM<5> 20C2<

55D3>

RFBDQM<6> 20C2<

55D3>

RFBDQM<7> 20C2<

55D3>

RFBACAS_L 20B2<

20B6< 55D3>

5% MF 402

W15
M16

22

RP22

N16

55D3> 18C8>

FBACAS_L

55D3> 18C8>

FBARAS_L

P16

1/16W

R16

5%

22

RP22

U16

55D3> 18C8>

FBACS0_L

V16

55D3> 18C8>

1/16W

5%

SM1

1/16W

W16

RP22 22

SM1

T16

5%

RP22 22

SM1

FBAWE_L

M17

1/16W

5%

ZT29

ZT20

ZT30

ZT31

NO_TEST

RFBARAS_L 20B2<

20B6< 55D3>

NO_TEST

RFBACS0_L 20B2<

20B6< 55C3>

NO_TEST

RFBAWE_L

20B2< 20B6< 55D3>

SM1

N17
P17
R17
T17

RP94 22

U17

55D3> 18D8>

FBA<0>

55D3> 18D8>

FBA<1>

V17

1/16W 5%

W17

RP94 22

N18

55D3> 18D8>

FBA<2>

55D3> 18D8>

FBA<3>

55D3> 18D8>

FBA<4>

55D3> 18D8>

FBA<5>

P18

1/16W 5%

RP95 22
3

V18

1/16W 5%

RP95 22
55D3> 18D8>

FBA<6>

NO_TEST

P19

55D3> 18D8>

FBA<7>

55D3> 18D8>

FBA<8>

55D3> 18D8>

FBA<9>

1/16W 5%

1/16W 5%

RP23 22
55D3> 18D8>

FBA<10>

55D3> 18C8>

FBA<11>

55D3> 18C8>

FBA<12>

V12

T12

FBABA<0>
FBABA<1>

NO_TEST

RP93 22

SM1

M13

RP93 22
3

T13

1/16W 5% SM1

1/16W 5%

ZT22

ZT23

ZT34

ZT24

ZT25

ZT37

ZT26

ZT27

ZT38

ZT36

ZT33

ZT35

RFBA<0>

20D2< 20D6< 55D3>

RFBA<1>

20C2< 20C6< 55D3>

RFBA<2>

20C2< 20C6< 55D3>

RFBA<3>

20C2< 20C6< 55D3>

RFBA<4>

20C2< 20C6< 55D3>

RFBA<5>

20C2< 20C6< 55D3>

RFBA<6>

20C2< 20C6< 55D3>

RFBA<7>

20C2< 20C6< 55D3>

RFBA<8>

20C2< 20C6< 55D3>

RFBA<9>

20C2< 20C6< 55D3>

RFBA<10>

20C2< 20C6< 55D3>

RFBA<11>

20C2< 20C6< 55D3>

1/16W 5% SM1

1/16W 5%

55D3> 18C8<>
55D3> 18C8<>

RP93 22

SM1

RP93 22

R13

SM1

1/16W 5%

W12

1/16W 5%

NO_TEST

M12
R12

SM1

RP23 22

SM1

P12

U12

1/16W 5%

N12

RP23 22

SM1

RP23 22

V19
W19

SM1

T19
U19

1/16W 5%

R19

SM1

RP95 22

SM1

M19
N19

1/16W 5%

W18

SM1

RP95 22

SM1

NO_TEST

T18
U18

1/16W 5%

R18

RP94 22

SM1

NO_TEST

M18

NC_RFBA<12>
ZT21

ZT32

RFBABA<0> 20C2<

20C6< 55D3>

RFBABA<1> 20C2<

20C6< 55D3>

SM1

W13

WEAK PULL-DOWN
RECOMMENDED BY NVIDIA

FBDQS<8> 19A5< 55B3>


FBDQS<9> 19A5< 55B3>
FBDQS<10> 19A5< 55B3>
FBDQS<11> 19A5< 55B3>
FBDQS<12> 19A5< 55B3>
FBDQS<13> 19A5< 55B3>
FBDQS<14> 19A5< 55B3>
FBDQS<15> 19A5< 55B3>

D12
A10
E7
A4
A27
D24
A21
D19
E12
C11
D6
B4
B27

NO_TEST

D25
C20
E19

NC_FBDQS_L<8>
NC_FBDQS_L<9>
NC_FBDQS_L<10>
NC_FBDQS_L<11>
NC_FBDQS_L<12>
NC_FBDQS_L<13>
NC_FBDQS_L<14>
NC_FBDQS_L<15>

55D3> 18D7<>

1%
1/16W
MF
2 402

55C3> 18D5>

FBDQM<8>
FBDQM<9>

B14
C15
D17
D14
A13

TESTPOINT

NV34 1R64
1/16W

55C3> 18D5>

FBDQM<10>

55C3> 18D5>

FBDQM<11>

FBBRAS_L 18C3< 55C3>


FBBCAS_L 18C3< 55C3>
FBBWE_L 18C3< 55C3>
FBBCS0_L 18C3< 55C3>
NC_FBBCS1_L
FBBCKE 18A3< 55B3>

FBDQM<12>

R70 0
5% MF 402

55C3> 18D5>

FBDQM<14>

R58 0

R59 0

FBDQM<15>

1/16W

FBBCLK0
FBBCLK0*
FBBCLK1
FBBCLK1*

55C3> 18C4<>

FBBCS0_L

55C3> 18D4<>

FBBCAS_L
FBBRAS_L

RP9 22

SM1

FBBWE_L

55C3> 18D4<>

NV34

1/16W 5%

55C3> 18D4<>

RP9 22
3

NV34

1/16W

5% SM1

RP9 22

SM1

RFBDQM<11>

21C6< 55C3>

RFBDQM<12>

21C2< 55C3>

RFBDQM<13>

21C2< 55C3>

RFBDQM<14>

21C2< 55C3>

RFBDQM<15>

21C2< 55C3>

5% MF 402

22

RP9

NV34

21C6< 55C3>

5% MF 402

MF 402

55C3>

RFBDQM<10>

NV34
2

1/16W

1/16W 5%

55C3> 18D5>

NV34

55C3>

RFBDQM<9> 21C6<

5% MF 402

R56 0

FBDQM<13>

RFBDQM<8> 21C6<

NV34

R67 0
1
1/16W

1/16W 5% MF 402

55C3> 18D5>

2
5% MF 402

R54 0

20C2< 20C6< 55C3>

NV34

R66 0
1/16W

1/16W

NV34

RFBACKE

5% MF 402

NV34

1/16W
402
5%
MF

R131
10K

55C3> 18D5>
C14

22

55C3> 18D5>

ZT28

R130

FBACKE
1

NV34

ZT2

ZT5

ZT1

ZT3

RFBBCS0_L 21B2<
RFBBWE_L

21B6< 55B3>

21B2< 21B6< 55B3>

RFBBCAS_L 21B2<
RFBBRAS_L

21B6< 55B3>

21B2< 21B6< 55B3>

NO_TEST

5% SM1

+3V_MAIN
1

C61
4.7UF

C70
0.1UF

20%
10V
2 CERM
402

C69
0.001UF

R52
10

NV34
2

1%
1/16W
MF
402

55C3> 18D5<>

FBBA<0>

55C3> 18D5<>

FBBA<1>

55C3> 18D5<>

FBBA<2>

NO_TEST

RP85 22
2

FBBA<3>

55C3> 18D5<>

FBBA<4>

55C3> 18D5<>

FBBA<5>

55C3> 18D5<>

FBBA<6>

55C3> 18D5<>

FBBA<7>
FBBA<8>

5%
1/16W
MF
402

FBBA<10>

55C3> 18C5<>

FBBA<11>

18D7<

FBBBA<0>
FBBBA<1>

RP83 22
1/16W 5%

NV34

5
SM1

6
SM1

RP83 22

ZT11

ZT10

ZT12

ZT17

ZT14

ZT16

ZT18

RP83 22

NV34

ZT15

1/16W 5%

ZT9

ZT13

SM1

8
5%

SM1

RP8 22
1

RP8 22
2

SM1

NO_TEST

1/16W

21D2< 21D6< 55C3>

RFBBA<1>

21C2< 21C6< 55C3>

RFBBA<2>

21C2< 21C6< 55C3>

RFBBA<3>

21C2< 21C6< 55C3>

RFBBA<4>

21C2< 21C6< 55C3>

RFBBA<5>

21C2< 21C6< 55C3>

RFBBA<6>

21C2< 21C6< 55C3>

RFBBA<7>

21C2< 21C6< 55C3>

RFBBA<8>

21C2< 21C6< 55C3>

RFBBA<9>

21C2< 21C6< 55C3>

RFBBA<10> 21C2<

21C6< 55C3>

RFBBA<11> 21C2<

21C6< 55C3>

NC_RFBBA<12>

NV34

6
5%

RFBBA<0>

SM1

RP8 22
3

RP8 22

NV34

1/16W 5%

SM1

1/16W 5%

FBCAL_PU_GND

NV34

1/16W 5% SM1

NV34

ZT4

ZT7

RFBBBA<0> 21C2<

21C6< 55C3>

RFBBBA<1> 21C2<

21C6< 55C3>

NVIDIA FRAME BUFFER

SM1

NOTICE OF PROPRIETARY PROPERTY

1%
1/16W
MF
2 402

5%
1/16W
MF
2 402

1%
1/16W
MF
2 402

R95
49.9

55C3> 18C5<>

SM1

RP84 22

1/16W 5% SM1

FBBA<12>

55C3> 18C5<>

8
5%

RP83 22

1/16W 5%

18D7< FBCAL_CLK_GND
18D7< FBCAL_TERM_GND

1/16W

NV34

1/16W

55C3> 18C5<>

SM1

RP84 22

NV34

20%
10V
2 CERM
402

SM1

6
5%

FBBA<9>

55C3> 18D5<>

5%

RP84 22

NV34
2

1/16W

NO_TEST

NV34

RP84 22
3

NV34
55C3> 18D5<>

RP85 22

1/16W 5% SM1

55C3> 18D5<>

ZT8

5
SM1

NV34

10%
50V
2 CERM
402

ZT6

RP85 22
1/16W 5%

55C3> 18D5<>

MEMREFN2

55D3>

RFBDQM<2> 20C6<

5% MF 402

R143 0
1

1/16W 5%

20%
10V
2 CERM
402

1/16W

MF 402

V15

5%
1/16W
MF
402

R49
0

R155 0

1/16W 5%

U15

NV34

R41
1K

R154 0

T15

55D3>

RFBDQM<1> 20C6<

5% MF 402

P15
R15

1/16W

1/16W 5% MF 402

N15

NOSTUFF

R84 0
1

M15

RFBDQM<0> 20C6<

5% MF 402

FBDQM<3>

V14
W14

1/16W

5% MF 402

1/16W

MEMREFN1

FBDQM<2>

1/16W

U14

R111 0
1

T14

NVIDIA VREF

NOSTUFF

2
5% MF 402

R90 0

NV34

5%
1/16W
MF
2 402

P14

+2_5V_MAIN

R117 0

1/16W

N20P80%
10V
2 CERM
805

FBDQM<1>

1/16W 5%

R36
0

FBDQM<0>

55D3> 18D8>

1/16W

N14

NV34

18D7< FB_DLLVDD

55D3> 18D8>

M14

R83
0

WEAK PULL-DOWN
RECOMMENDED BY NVIDIA

R88
549
55B3> 18C4<>

FBBCKE
1 NV34

R61
10K

LAST_MODIFIED=Mon Oct 27 12:29:50 2003

NV34

R62 ZT19
2
22
1

RFBBCKE

21C2< 21C6< 55B3>

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

1%
1/16W
MF
2 402

SIZE DRAWING NUMBER

APPLE COMPUTER INC.

NONE

REV.

051-6569

E
SCALE

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

1/16W
402
5%
MF

SHT

18

OF

69
DRAWING

<XR_PAGE_TITLE>

PLACE RS BETWEEN GPU & MEMORY


FBD<0>
FBD<1>
FBD<2>
55D3> 18G8<> FBD<3>
55D3> 18G8<> FBD<4>
55D3> 18G8<> FBD<5>
55D3> 18G8<> FBD<6>
55D3> 18G8<> FBD<7>
55D3> 18G8<> FBD<8>
55D3> 18G8<> FBD<9>
55D3> 18G8<> FBD<10>
55D3> 18G8<> FBD<11>
55D3> 18G8<> FBD<12>
55D3> 18G8<> FBD<13>
55D3> 18G8<> FBD<14>
55D3> 18G8<> FBD<15>
55D3> 18G8<> FBD<16>
55D3> 18G8<> FBD<17>
55D3> 18G8<> FBD<18>
55D3> 18G8<> FBD<19>
55D3> 18G8<> FBD<20>
55D3> 18G8<> FBD<21>
55D3> 18G8<> FBD<22>
55D3> 18G8<> FBD<23>
55D3> 18G8<> FBD<24>
55D3> 18F8<> FBD<25>
55D3> 18F8<> FBD<26>
55D3> 18F8<> FBD<27>
55D3> 18F8<> FBD<28>
55D3> 18F8<> FBD<29>
55D3> 18F8<> FBD<30>
55D3> 18F8<> FBD<31>
55D3> 18G8<>

55D3> 18G8<>
55D3> 18G8<>

NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST

NO_TEST

NO_TEST

RP20
RP20
RP20
RP20
RP19
RP19
RP19
RP19
RP21
RP21
RP21
RP21
RP18
RP18
RP18
RP18
RP91
RP91
RP91
RP91
RP90
RP90
RP90
RP90
RP92
RP92
RP92
RP92
RP17
RP17
RP17
RP17

RFBD<0> 20C5<> 55D3>


RFBD<1> 20C5<> 55D3>
RFBD<2> 20C5<> 55D3>
RFBD<3> 20C5<> 55D3>
RFBD<4> 20C5<> 55D3>
RFBD<5> 20C5<> 55D3>
RFBD<6> 20C5<> 55D3>
RFBD<7> 20C5<> 55D3>
RFBD<8> 20C5<> 55D3>
RFBD<9> 20C5<> 55D3>
RFBD<10> 20C5<> 55D3>
RFBD<11> 20C5<> 55D3>
RFBD<12> 20C5<> 55D3>
RFBD<13> 20C5<> 55D3>
RFBD<14> 20C5<> 55D3>
RFBD<15> 20C5<> 55D3>
RFBD<16> 20C5<> 55D3>
RFBD<17> 20C5<> 55D3>
RFBD<18> 20C5<> 55D3>
RFBD<19> 20C5<> 55D3>
RFBD<20> 20C5<> 55D3>
RFBD<21> 20C5<> 55D3>
RFBD<22> 20C5<> 55D3>
RFBD<23> 20C5<> 55D3>
RFBD<24> 20C5<> 55D3>
RFBD<25> 20C5<> 55D3>
RFBD<26> 20B5<> 55D3>
RFBD<27> 20B5<> 55D3>
RFBD<28> 20B5<> 55D3>
RFBD<29> 20B5<> 55D3>
RFBD<30> 20B5<> 55D3>
RFBD<31> 20B5<> 55D3>

FBD<64>
FBD<65>
18G5<> FBD<66>
18G5<> FBD<67>
18G5<> FBD<68>
18G5<> FBD<69>
18G5<> FBD<70>
18G5<> FBD<71>
18G5<> FBD<72>
18G5<> FBD<73>
18G5<> FBD<74>
18G5<> FBD<75>
18G5<> FBD<76>
18G5<> FBD<77>
18G5<> FBD<78>
18G5<> FBD<79>
18G5<> FBD<80>
18G5<> FBD<81>
18G5<> FBD<82>
18G5<> FBD<83>
18G5<> FBD<84>
18G5<> FBD<85>
18G5<> FBD<86>
18G5<> FBD<87>
18G5<> FBD<88>
18F5<> FBD<89>
18F5<> FBD<90>
18F5<> FBD<91>
18F5<> FBD<92>
18F5<> FBD<93>
18F5<> FBD<94>
18F5<> FBD<95>

55C3> 18G5<>
55C3> 18G5<>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>
55C3>

NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

RP10
RP10
RP10
RP10
RP14
RP14
RP14
RP14
RP82
RP82
RP82
RP82
RP12
RP12
RP12
RP12
RP11
RP11
RP11
RP11
RP80
RP80
RP80
RP80
RP81
RP81
RP81
RP81
RP13
RP13
RP13
RP13

NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34
NV34

RFBD<64>
RFBD<65>
RFBD<66>
RFBD<67>
RFBD<68>
RFBD<69>
RFBD<70>
RFBD<71>
RFBD<72>
RFBD<73>
RFBD<74>
RFBD<75>
RFBD<76>
RFBD<77>
RFBD<78>
RFBD<79>
RFBD<80>
RFBD<81>
RFBD<82>
RFBD<83>
RFBD<84>
RFBD<85>
RFBD<86>
RFBD<87>
RFBD<88>
RFBD<89>
RFBD<90>
RFBD<91>
RFBD<92>
RFBD<93>
RFBD<94>
RFBD<95>

PLACE THESE R CLOSE TO GPU


55C3> 18C7<>

55C3> 18C7<>

55C3> 18C7<>

55C3> 18C7<>

55C3> 18C7<>

FBD<32>
FBD<33>
FBD<34>
18F8<> FBD<35>
18F8<> FBD<36>
18F8<> FBD<37>
18F8<> FBD<38>
18F8<> FBD<39>
18F8<> FBD<40>
18F8<> FBD<41>
18F8<> FBD<42>
18F8<> FBD<43>
18F8<> FBD<44>
18E8<> FBD<45>
18E8<> FBD<46>
18E8<> FBD<47>
18E8<> FBD<48>
18E8<> FBD<49>
18E8<> FBD<50>
18E8<> FBD<51>
18E8<> FBD<52>
18E8<> FBD<53>
18E8<> FBD<54>
18E8<> FBD<55>
18E8<> FBD<56>
18E8<> FBD<57>
18E8<> FBD<58>
18E8<> FBD<59>
18E8<> FBD<60>
18E8<> FBD<61>
18E8<> FBD<62>
18E8<> FBD<63>

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

55D3> 18F8<>
55D3> 18F8<>
55D3> 18F8<>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>
55D3>

NO_TEST
NO_TEST
NO_TEST

NO_TEST

NO_TEST
NO_TEST

NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST

RP29
RP29
RP29
RP29
RP27
RP27
RP27
RP27
RP28
RP28
RP28
RP28
RP97
RP97
RP97
RP97
RP25
RP25
RP25
RP25
RP96
RP96
RP96
RP96
RP26
RP26
RP26
RP26
RP24
RP24
RP24
RP24

RFBD<32>
RFBD<33>
RFBD<34>
RFBD<35>
RFBD<36>
RFBD<37>
RFBD<38>
RFBD<39>
RFBD<40>
RFBD<41>
RFBD<42>
RFBD<43>
RFBD<44>
RFBD<45>
RFBD<46>
RFBD<47>
RFBD<48>
RFBD<49>
NO_TESTRFBD<50>
RFBD<51>
RFBD<52>
RFBD<53>
RFBD<54>
RFBD<55>
RFBD<56>
RFBD<57>
RFBD<58>
RFBD<59>
RFBD<60>
RFBD<61>
RFBD<62>
RFBD<63>

20C1<> 55D3>
20C1<> 55D3>
20C1<> 55D3>
20C1<> 55D3>
20C1<> 55D3>
20C1<> 55D3>
20C1<> 55D3>

PLACE RS CLOSE TO GPU

20C1<> 55D3>
20C1<> 55D3>
20C1<> 55D3>

R123
15 1
2

55C3> 18D7> FBACLK1

20C1<> 55D3>
20C1<> 55D3>

1%
1/16W
MF
402

20C1<> 55D3>
20C1<> 55D3>
20C1<> 55D3>
20C1<> 55D3>
20C1<> 55D3>
20C1<> 55D3>

55C3> 18D7>

FBACLK1_L

R132
15 1

RFBACLK1
R1581
100
1%
1/16W
MF
402 2

20C2< 55C3>

PLACE 100OHM TERM AT RAM

RFBACLK1_L

20C2< 55C3>

1%
1/16W
MF
402

20C1<> 55D3>
20C1<> 55D3>
20C1<> 55D3>
20C1<> 55D3>
20C1<> 55D3>
20C1<> 55D3>

55C3> 18D7> FBACLK0

20C1<> 55D3>

R148
15 1
1%
1/16W
MF
402

20C1<> 55D3>
20B1<> 55D3>
20B1<> 55D3>
20B1<> 55D3>
20B1<> 55D3>
20B1<> 55D3>
55C3> 18D7>

20B1<> 55D3>

FBACLK0_L

R156
15 1

RFBACLK0
R5001
100
1%
1/16W
MF
402 2

20C6< 55C3>

PLACE 100OHM TERM AT RAM

RFBACLK0_L

20C6< 55C3>

1%
1/16W
MF
402

NO_TEST

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

55C3> 18C7<>

55C3> 18C7<>

55C3> 18C7<>

R122
0 1
2

FBDQS<0>
FBDQS<1>

R101
0 1
2
5%
1/16W
MF
402

FBDQS<2>
FBDQS<3>
FBDQS<4>
FBDQS<5>
FBDQS<6>
FBDQS<7>

R81
0

5%
1/16W
MF
402

R159
0 1
2
5%
1/16W
MF
402

R140
0 1
2

R97
0

FBDQSTERM<0>

FBDQSTERM<2>

5%
1/16W
NO_TEST
MF
402 55C3> FBDQSTERM<3>

R167
0 1
2

21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21C5<> 55C3>
21B5<> 55C3>
21B5<> 55C3>
21B5<> 55C3>
21B5<> 55C3>
21B5<> 55C3>
21B5<> 55C3>

R483
15 2
1

55C3>

R509
15 2
1

55C3>

55C3>

5%
1/16W
MF
402

1%
1/16W
MF
402

R146
15 2
1

NO_TEST

FBDQSTERM<6>

5%
1/16W
NO_TEST
MF
402 55C3> FBDQSTERM<7>

1%
1/16W
MF
402

R506
15 2
1

NO_TEST

FBDQSTERM<4>

5%
1/16W
NO_TEST
MF
402 55C3> FBDQSTERM<5>

R147
0 1
2

21C5<> 55C3>
21C5<> 55C3>

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

NO_TEST
NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST
NO_TEST

NO_TEST
NO_TEST

PLACE THESE R CLOSE TO SGRAM

NO_TEST

21C5<> 55C3>

NO_TEST

5%
1/16W
NO_TEST
MF
402 55C3> FBDQSTERM<1>

FBD<96>
FBD<97>
55C3> 18F5<> FBD<98>
55C3> 18F5<> FBD<99>
55C3> 18F5<> FBD<100>
55C3> 18F5<> FBD<101>
55C3> 18F5<> FBD<102>
55C3> 18F5<> FBD<103>
55C3> 18F5<> FBD<104>
55C3> 18F5<> FBD<105>
55C3> 18F5<> FBD<106>
55C3> 18F5<> FBD<107>
55C3> 18F5<> FBD<108>
55C3> 18E5<> FBD<109>
55C3> 18E5<> FBD<110>
55C3> 18E5<> FBD<111>
55C3> 18E5<> FBD<112>
55C3> 18E5<> FBD<113>
55C3> 18E5<> FBD<114>
55C3> 18E5<> FBD<115>
55C3> 18E5<> FBD<116>
55C3> 18E5<> FBD<117>
55C3> 18E5<> FBD<118>
55C3> 18E5<> FBD<119>
55C3> 18E5<> FBD<120>
55C3> 18E5<> FBD<121>
55C3> 18E5<> FBD<122>
55C3> 18E5<> FBD<123>
55C3> 18E5<> FBD<124>
55C3> 18E5<> FBD<125>
55C3> 18E5<> FBD<126>
55C3> 18E5<> FBD<127>
55C3> 18F5<>
55C3> 18F5<>

21C5<> 55C3>
21C5<> 55C3>

55C3>

1%
1/16W
MF
402

R153
15 2
1

1%
1/16W
MF
402

R479
15 2
1
1%
1/16W
MF
402

R187
15 2
1
1%
1/16W
MF
402

R186
15 2
1
1%
1/16W
MF
402

RFBDQS<0> 20C6<>

55C3>

RP88 NV34
RP88 NV34
RP88 NV34
RP88 NV34
RP89 NV34
RP89 NV34
RP89 NV34
RP89 NV34
RP4 NV34
RP4 NV34
RP4 NV34
RP4 NV34
RP86 NV34
RP86 NV34
RP86 NV34
RP86 NV34
RP5 NV34
RP5 NV34
RP5 NV34
RP5 NV34
RP6 NV34
RP6 NV34
RP6 NV34
RP6 NV34
RP7 NV34
RP7 NV34
RP7 NV34
RP7 NV34
RP87 NV34
RP87 NV34
RP87 NV34
RP87 NV34

PLACE THESE R CLOSE TO GPU


55B3> 18D4<>

FBDQS<8>

NV34

RFBDQS<1> 20C6<>
RFBDQS<2> 20C6<>

55C3>

55C3>

55B3> 18D4<>

55B3> 18D4<>

FBDQS<9>

RFBDQS<4> 20C2<>

55C3>

55C3>

55B3> 18D4<>

55B3> 18D4<>

FBDQS<10>
FBDQS<11>

RFBDQS<6> 20C2<>

55C3>

55C3>

55B3> 18D4<>

55B3> 18D4<>

FBDQS<12>
FBDQS<13>

55C3>

55B3> 18D4<>

FBDQS<14>

1%
1/16W
MF
402

FBDQS<15>

R55
0

R60
0

NV34
55B3> 18C5<>

NV34
55B3> 18C5<>

R105
15 1

FBBCLK0

R201
100
1%
1/16W
MF
402 2

21C2< 55B3>

PLACE 100OHM TERM AT RAM

RFBBCLK1_L

R103
15 1
1%
1/16W
MF
402

NV34
55B3> 18C5<>

21C2< 55B3>

FBBCLK0_L

R104
15 1

RFBBCLK0

21C6< 55B3>

NV34

R4031
100
1%
1/16W
MF
402 2

PLACE 100OHM TERM AT RAM

RFBBCLK0_L

21C6< 55B3>

1%
1/16W
MF
402

PLACE THESE R CLOSE TO SGRAM


55B3>

NV34

R415
15 2
1

NO_TEST

55B3> FBDQSTERM<9>

1%
1/16W
MF
402

55B3> FBDQSTERM<11>

55B3>

55B3>

RFBDQS<9> 21C6<>

55B3>

1%
1/16W
MF
402

1%
1/16W
MF
402

R31
15

55B3>

NO_TEST

R25
15

55B3>

NV34
1

R32
15

NV34

R24
15
1%
1/16W
MF
402

RFBDQS<10>

21C6<> 55B3>

RFBDQS<11>

21C6<> 55B3>

RFBDQS<12>

21C2<> 55B3>

RFBDQS<13>

21C2<> 55B3>

NV34
2

1%
1/16W
MF
402

1%
1/16W
MF
402

NO_TEST

55B3> FBDQSTERM<15>

RFBDQS<8> 21C6<>

1%
1/16W
MF
402

R429
15 2
1

NV34
55B3> FBDQSTERM<13>

R428 NV34
15 2

R416
15 2
1

NV34
NO_TEST

5%
1/16W
MF
402

FBBCLK1_L

RFBBCLK1
NV34

1%
1/16W
MF
402

R57 NV34
NO_TEST
0 1
FBDQSTERM<14>
5%
1/16W
MF
402

FBBCLK1

R106
15 1
2
1%
1/16W
MF
402

R53 NV34
NO_TEST
0 1
FBDQSTERM<12>
5%
1/16W
MF
402

55B3> 18C5<>

R69 NV34
NO_TEST
0 1
FBDQSTERM<10>
5%
1/16W
MF
402

5%
1/16W
MF
402

NV34

RFBDQS<7> 20C2<>

R68
0

NV34

R63 NV34
NO_TEST
0 1
FBDQSTERM<8>
5%
1/16W
MF
402

5%
1/16W
MF
402

NV34

RFBDQS<5> 20C2<>

R65
0
5%
1/16W
MF
402

NV34

RFBDQS<3> 20C6<>

RFBD<96> 21C1<> 55C3>


RFBD<97> 21C1<> 55C3>
RFBD<98> 21C1<> 55C3>
RFBD<99> 21C1<> 55C3>
RFBD<100> 21C1<> 55C3>
RFBD<101> 21C1<> 55C3>
RFBD<102> 21C1<> 55C3>
RFBD<103> 21C1<> 55C3>
RFBD<104> 21C1<> 55C3>
RFBD<105> 21C1<> 55C3>
RFBD<106> 21C1<> 55C3>
RFBD<107> 21C1<> 55C3>
RFBD<108> 21C1<> 55C3>
RFBD<109> 21C1<> 55C3>
RFBD<110> 21C1<> 55C3>
RFBD<111> 21C1<> 55C3>
RFBD<112> 21C1<> 55C3>
RFBD<113> 21C1<> 55C3>
RFBD<114> 21C1<> 55C3>
RFBD<115> 21C1<> 55C3>
RFBD<116> 21C1<> 55C3>
RFBD<117> 21C1<> 55C3>
RFBD<118> 21C1<> 55C3>
RFBD<119> 21C1<> 55C3>
RFBD<120> 21C1<> 55C3>
RFBD<121> 21C1<> 55C3>
RFBD<122> 21B1<> 55C3>
RFBD<123> 21B1<> 55C3>
RFBD<124> 21B1<> 55C3>
RFBD<125> 21B1<> 55C3>
RFBD<126> 21B1<> 55C3>
RFBD<127> 21B1<> 55C3>

FB TERMINATION

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:29:53 2003

NV34

RFBDQS<14>

21C2<> 55B3>

RFBDQS<15>

21C2<> 55B3>

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

1%
1/16W
MF
402

SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
19 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

+2_5V_MAIN

+2_5V_MAIN
PLACE NEAR VDD PINS

C540
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

+2_5V_MAIN

PLACE NEAR VDD PINS

C544
0.1UF

C532
0.1UF

C533
0.001UF

10%
50V
2 CERM
402

20%
10V
2 CERM
402

C158
0.1UF

20%
10V
2 CERM
402

C142
0.1UF

20%
10V
2 CERM
402

C144
0.1UF

C143
0.001UF

10%
50V
2 CERM
402

20%
10V
2 CERM
402

C521
1
10UF
N20P80%
10V
2
Y5V
805

C520
10UF
N20P80%
10V
Y5V
805

C216
1
10UF
N20P80%
10V
2
Y5V
805

C205
10UF
N20P80%
10V
Y5V
805

+2_5V_MAIN

+2_5V_MAIN

SEE_TABLE
SEE_TABLE

U41
SDRAM_DDR_4MX32

U12
SDRAM_DDR_4MX32

BGA

BGA
E5

D8

SEE_TABLE

E8

E11

E10

VDD

VSS

L7

RFBA<0>
RFBA<1>
55D3> 20C2< 18F2<> RFBA<2>
55D3> 20C2< 18F2<> RFBA<3>
55D3> 20C2< 18F2<> RFBA<4>
55D3> 20C2< 18F2<> RFBA<5>
55D3> 20C2< 18E2<> RFBA<6>
55D3> 20C2< 18E2<> RFBA<7>
55D3> 20C2< 18E2<> RFBA<8>
55D3> 20C2< 18E2<> RFBA<9>
55D3> 20C2< 18E2<> RFBA<10>
55D3> 20C2< 18E2<> RFBA<11>

K7

L8

K8
K9
L5

C3
L10
C5
C7

F6

C8

F7

C10

F8

C12

F9

E3

G6

E12

G7

VDDQ

G4

55C3> 19A6<
55C3> 19A6<

G9
H6

G11

H7

J4

H8

J11

20C4< 20A3<
52A6>

55C3> 19A6<

G8

VSS_THERM

F11

55C3> 19A6<
55D3> 18G2<
55D3> 18G2<

H9

K4

J6

K11

J7

55D3> 18G2<
55D3> 18G2<

J8

SGRAVREF

N13

VREF

B4

D4
D5
D6
D9
D10
D11

N8
M9
N9
N10
N11
M8
L6
M7

RFBDQS<0>
RFBDQS<1>
RFBDQS<2>
RFBDQS<3>

B2
H13
H2
B13

RFBDQM<0>
RFBDQM<1>
RFBDQM<2>
RFBDQM<3>

B3
H12
H3
B12

RFBACLK0
55C3> 19C1< RFBACLK0_L
55C3> 20C2< 18D2<> RFBACKE
55C3> 20B2< 18F2<> RFBACS0_L
55D3> 20B2< 18G2<> RFBARAS_L
55D3> 20B2< 18G2<> RFBACAS_L
55D3> 20B2< 18F2<> RFBAWE_L

M11

NC_FB1<0>
NC_FB1<1>
NC_FB1<2>
NC_FB1<3>
NC_FB1<4>
NC_FB1<5>
NC_FB1<6>
NC_FB1<7>
NC_FB1<8>

E6

VSSQ

N7

M5

55C3> 19C1<

B11

20%
2 10V
CERM
402

M6

N4

55D3> 20C2< 18E2<>

J9

C2201
0.1UF

N6

RFBABA<0>
RFBABA<1>

55D3> 20C2< 18E2<>


1

N5

55D3> 20D2< 18F2<>


55D3> 20C2< 18F2<>

K6

L11

F4

E5

D8

E7

E4

E8

SEE_TABLE

E7

E4

L4

(2 OF 2)

D7

(2 OF 2)

D7

E9
F5
F10
G5
G10
H5
H10
J5

M12
N12
N2
M2
L2
L3
NO_TEST

C4

NO_TEST

C11

NO_TEST

H4

NO_TEST

H11

NO_TEST

L12

NO_TEST

L13

U12
SDRAM_DDR_4MX32
BGA
A0
(1 OF 2)
DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQS0
DQ12
DQS1
DQ13
DQS2
DQ14
DQS3
DQ15
DQ16
DM0
DQ17
DM1
DQ18
DM2
DQ19
DM3
DQ20
BA0
DQ21
BA1
DQ22
DQ23
CK
DQ24
CK
DQ25
CKE
DQ26
CS
DQ27
RAS
DQ28
CAS
DQ29
WE
DQ30
DQ31

NC

E11
L4

RFBD<0> 19D7< 55D3>


RFBD<1> 19D7< 55D3>
RFBD<2> 19D7< 55D3>
RFBD<3> 19D7< 55D3>
RFBD<4> 19D7< 55D3>
RFBD<5> 19D7< 55D3>
RFBD<6> 19D7< 55D3>
RFBD<7> 19D7< 55D3>
RFBD<8> 19D7< 55D3>
RFBD<9> 19D7< 55D3>
RFBD<10> 19D7< 55D3>
RFBD<11> 19D7< 55D3>
RFBD<12> 19D7< 55D3>
RFBD<13> 19D7< 55D3>
RFBD<14> 19D7< 55D3>
RFBD<15> 19D7< 55D3>
RFBD<16> 19D7< 55D3>
RFBD<17> 19D7< 55D3>
RFBD<18> 19D7< 55D3>
RFBD<19> 19C7< 55D3>
RFBD<20> 19C7< 55D3>
RFBD<21> 19C7< 55D3>
RFBD<22> 19C7< 55D3>
RFBD<23> 19C7< 55D3>
RFBD<24> 19C7< 55D3>
RFBD<25> 19C7< 55D3>
RFBD<26> 19C7< 55D3>
RFBD<27> 19C7< 55D3>
RFBD<28> 19C7< 55D3>
RFBD<29> 19C7< 55D3>
RFBD<30> 19C7< 55D3>
RFBD<31> 19C7< 55D3>

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

VDD

VSS

L7

K6
K7

L8

K8

L11

K9
L5

C3
L10
C5
C7

F6

C8

F7

C10

F8

C12

F9

E3

G6

E12

G7

F4

VDDQ

F11

SGRAVREF

VSS_THERM

55C3> 19A6<
55C3> 19A6<

G9

G4

H6

G11

H7

55C3> 19A6<
55C3> 19A6<

J4

H8

J11

H9

K4

J6

55D3> 18G2<
55D3> 18G2<

J7

55D3> 18G2<

J8

55D3> 18G2<

N13

RFBA<0>
RFBA<1>
55D3> 20C6< 18F2<> RFBA<2>
55D3> 20C6< 18F2<> RFBA<3>
55D3> 20C6< 18F2<> RFBA<4>
55D3> 20C6< 18F2<> RFBA<5>
55D3> 20C6< 18E2<> RFBA<6>
55D3> 20C6< 18E2<> RFBA<7>
55D3> 20C6< 18E2<> RFBA<8>
55D3> 20C6< 18E2<> RFBA<9>
55D3> 20C6< 18E2<> RFBA<10>
55D3> 20C6< 18E2<> RFBA<11>

VREF

J9
B4
B11

20%
10V
2 CERM
402

D4
D5
D6
D9
D10
D11
E6

VSSQ

M13

RFU1
RFU2

L9

NO_TEST

M10

NO_TEST

M3

NO_TEST

M4

NO_TEST

N3

N8
M9
N9
N10
N11
M8
L6
M7

RFBDQS<4>
RFBDQS<5>
RFBDQS<6>
RFBDQS<7>

B2
H13
H2
B13

RFBDQM<4>
RFBDQM<5>
RFBDQM<6>
RFBDQM<7>

B3
H12
H3
B12

M11

NC_FB2<0>
NC_FB2<1>
NC_FB2<2>
NC_FB2<3>
NC_FB2<4>
NC_FB2<5>
NC_FB2<6>
NC_FB2<7>
NC_FB2<8>

E9

G5
G10
H5

NO_TEST

N7

55C3> 19D1< RFBACLK1


55C3> 19D1< RFBACLK1_L
55C3> 20C6< 18D2<> RFBACKE
55C3> 20B6< 18F2<> RFBACS0_L
55D3> 20B6< 18G2<> RFBARAS_L
55D3> 20B6< 18G2<> RFBACAS_L
55D3> 20B6< 18F2<> RFBAWE_L

F10

NC_FB1<9>
NC_FB1<10>

M6

N4

55D3> 20C6< 18E2<>

F5

MCL

N6

RFBABA<0>
RFBABA<1>

55D3> 20C6< 18E2<>

C2202
0.1UF

N5

55D3> 20D6< 18F2<>


55D3> 20C6< 18F2<>

G8

K11

52A6> 20C8< 20A3<

U41
SDRAM_DDR_4MX32
BGA
A0
(1 OF 2)
DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQS0
DQ12
DQS1
DQ13
DQS2
DQ14
DQS3
DQ15
DQ16
DM0
DQ17
DM1
DQ18
DM2
DQ19
DM3
DQ20
BA0
DQ21
BA1
DQ22
DQ23
CK
DQ24
CK
DQ25
CKE
DQ26
CS
DQ27
RAS
DQ28
CAS
DQ29
WE
DQ30
DQ31

E10

H10
J5
J10

J10

M5

M12
N12
N2
M2
L2
L3
NO_TEST

C4

NO_TEST

C11

NO_TEST

H4

NO_TEST

H11

NO_TEST

L12

NO_TEST

L13

NO_TEST

M3

NO_TEST

M4

NO_TEST

N3

NC

RFBD<32>
RFBD<33>
RFBD<34>
RFBD<35>
RFBD<36>
RFBD<37>
RFBD<38>
RFBD<39>
RFBD<40>
RFBD<41>
RFBD<42>
RFBD<43>
RFBD<44>
RFBD<45>
RFBD<46>
RFBD<47>
RFBD<48>
RFBD<49>
RFBD<50>
RFBD<51>
RFBD<52>
RFBD<53>
RFBD<54>
RFBD<55>
RFBD<56>
RFBD<57>
RFBD<58>
RFBD<59>
RFBD<60>
RFBD<61>
RFBD<62>
RFBD<63>

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

MCL

M13

RFU1
RFU2

L9

NO_TEST

M10

NO_TEST

19D4< 55D3>
19D4< 55D3>
19D4< 55D3>
19D4< 55D3>
19D4< 55D3>
19D4< 55D3>
19D4< 55D3>
19D4< 55D3>
19D4< 55D3>
19D4< 55D3>
19D4< 55D3>
19D4< 55D3>
19D4< 55D3>
19D4< 55D3>
19D4< 55D3>
19D4< 55D3>

19D4< 55D3>
19D4< 55D3>
19D4< 55D3>
19C4< 55D3>
19C4< 55D3>
19C4< 55D3>
19C4< 55D3>
19C4< 55D3>
19C4< 55D3>
19C4< 55D3>
19C4< 55D3>
19C4< 55D3>
19C4< 55D3>
19C4< 55D3>
19C4< 55D3>
19C4< 55D3>

NC_FB2<9>
NC_FB2<10>

K5
K5

K10

K10

+2_5V_MAIN

C569
0.001UF

10%
2 50V
CERM
402

+2_5V_MAIN

C568
0.1UF

20%
2 10V
CERM
402

C567
0.1UF

20%
2 10V
CERM
402

C566
0.001UF

10%
2 50V
CERM
402

C554
0.1UF

20%
2 10V
CERM
402

C545
0.1UF

C535
0.001UF

10%
2 50V
CERM
402

20%
2 10V
CERM
402

C534
0.1UF

20%
2 10V
CERM
402

C553
0.1UF

20%
2 10V
CERM
402

C565
0.001UF

C194
0.001UF

10%
2 50V
CERM
402

10%
2 50V
CERM
402

C198
0.1UF

20%
2 10V
CERM
402

C174
0.1UF

20%
2 10V
CERM
402

C166
0.001UF

10%
50V
2 CERM
402

C141
0.1UF

20%
2 10V
CERM
402

C165
0.1UF

20%
2 10V
CERM
402

C173
0.001UF

10%
2 50V
CERM
402

C197
0.1UF

20%
2 10V
CERM
402

C196
0.1UF

20%
2 10V
CERM
402

C195
0.001UF

10%
2 50V
CERM
402

+2_5V_MAIN
SEE_TABLE
1

SGRAM0 & SGRAM1 VREF

R152
1K

SGRAM0 & SGRAM1 MEMORY SUPPORT


PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

333S0249

SDRAM,4MX32,DDR,275MHZ

U12,U41

CRITICAL

SAMSUNG_275_32M

333S0250

SDRAM,4MX32,DDR,275MHZ

U12,U41

CRITICAL

HYNIX_275_32M

5%
1/16W
MF
2 402

BOM OPTION

MEMREFG_ACT

MEMREFG1

1
1

333S0251

SDRAM,4MX32,DDR,300MHZ

U12,U41

CRITICAL

SAMSUNG_300_32M

333S0252

SDRAM,4MX32,DDR,300MHZ

U12,U41

CRITICAL

HYNIX_300_32M

MEMREFG_ACT

U16
TLV431A
3 SOT

R163
1K

1%
1/16W
MF
2 402

4
5

100PF

SGRAM0 & SGRAM1 DDR MEMORY REFERENCE SUPPORT


CRITICAL

MEMREFG_ACT
1 C191

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

116S1103

RES,1K-OHM,5%,1/16W,0402

R152

MEMREFG_ACT

116S1000

RES,0-OHM,5%,1/16W,0402

R152

MEMREFG_PAS

5%
2 50V
CERM
402

BOM OPTION

R176
1K

1%
1/16W
MF
2 402

C157
0.1UF

20%
2 10V
CERM
402

SGRAVREF

20C4< 20C8< 52A6>

5%
1/16W
MF
402

MEMREFG_PAS
1

R151
0 2

MEMREFG_PAS

MEMREFG2
MEMREFG_PAS
1 C172

0.1UF

SGRAM0 & SGRAM1

R166
0 2

NOTICE OF PROPRIETARY PROPERTY

5%
1/16W
MF
402

LAST_MODIFIED=Mon Oct 27 12:29:55 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

20%
2 10V
CERM
402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
20 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

5
+2_5V_MAIN

+2_5V_MAIN
PLACE NEAR VDD PINS

+2_5V_MAIN

PLACE NEAR VDD PINS


64M_GRAM_DECOUP

64M_GRAM_DECOUP

64M_GRAM_DECOUP

C467
0.1UF

20%
10V
2 CERM
402

64M_GRAM_DECOUP

C487
0.1UF

20%
10V
2 CERM
402

C493
0.1UF

20%
10V
2 CERM
402

64M_GRAM_DECOUP

64M_GRAM_DECOUP

C494
0.001UF

10%
50V
2 CERM
402

64M_GRAM_DECOUP

C17
0.1UF

20%
10V
2 CERM
402

C39
0.1UF

20%
10V
2 CERM
402

64M_GRAM_DECOUP

64M_GRAM_DECOUP

C21
0.1UF

20%
10V
2 CERM
402

C32
0.001UF

10%
50V
2 CERM
402

C460
10UF
N20P80%
10V
Y5V
805

64M_GRAM_DECOUP

C38
10UF
N20P80%
10V
Y5V
805

64M_GRAM_DECOUP

C15
10UF
N20P80%
10V
Y5V
805

64M_GRAM_DECOUP

C492
10UF
N20P80%
10V
Y5V
805

+2_5V_MAIN

+2_5V_MAIN
SEE_TABLE

U5
SDRAM_DDR_4MX32

U36
SDRAM_DDR_4MX32

BGA

BGA

(2 OF 2)

D7

D7

D8

E7

D8

E7

E4

E8

E4

E8

E11
L4

E10

VDD

VSS

L7

K6
K7

L8

K8

L11

K9
L5

C3
L10
C5
C7

F6

C8

F7

C10

F8

C12

F9

E3

G6

E12
F4

VDDQ
VSS_THERM

H6

G11

H7

J4

H8

K4

J6
J7

N13

VREF

J9

55C3>
55C3>

55C3> 21C2< 18A2<>


55C3> 21C2< 18A2<>

B4

64M_GRAM_DECOUP

B11

C2301
0.1UF

D4

20%
10V
2 CERM
402

D5
D6
D9
D10
D11

M9
N9
N10
N11
M8
L6
M7
B2
H13
H2
B13
B3
H12
H3
B12

RFBBBA<0>
RFBBBA<1>

N4
M5

RFBBCLK0
55B3> 19B1< RFBBCLK0_L
55B3> 21C2< 18A2<> RFBBCKE
55B3> 21B2< 18C2<> RFBBCS0_L
55B3> 21B2< 18C2<> RFBBRAS_L
55B3> 21B2< 18C2<> RFBBCAS_L
55B3> 21B2< 18C2<> RFBBWE_L
NC_FB3<0>
NC_FB3<1>
NC_FB3<2>
NC_FB3<3>
NC_FB3<4>
NC_FB3<5>
NC_FB3<6>
NC_FB3<7>
NC_FB3<8>

E9
F5
F10
G5
G10
H5
H10
J5

N8

M11

55B3> 19B1<

E6

VSSQ

N7

RFBDQM<8>
RFBDQM<9>
18D2< RFBDQM<10>
18D2< RFBDQM<11>

J8

SGRBVREF

M6

55C3> 18D2<
55C3> 18D2<

H9

K11

N6

RFBDQS<8>
55B3> 19A3< RFBDQS<9>
RFBDQS<10>
55B3> 19A3<
55B3> 19A3< RFBDQS<11>

G9

G4

N5

55B3> 19A3<

G8

J11

21C4< 21A3<
52A6>

RFBBA<0>
RFBBA<1>
55C3> 21C2< 18B2<> RFBBA<2>
55C3> 21C2< 18B2<> RFBBA<3>
55C3> 21C2< 18B2<> RFBBA<4>
55C3> 21C2< 18B2<> RFBBA<5>
55C3> 21C2< 18B2<> RFBBA<6>
55C3> 21C2< 18B2<> RFBBA<7>
55C3> 21C2< 18B2<> RFBBA<8>
55C3> 21C2< 18B2<> RFBBA<9>
55C3> 21C2< 18B2<> RFBBA<10>
55C3> 21C2< 18B2<> RFBBA<11>
55C3> 21D2< 18C2<>
55C3> 21C2< 18B2<>

G7

F11

(2 OF 2)

E5

M12
N12
N2
M2
L2
L3
NO_TEST

C4

NO_TEST

C11

NO_TEST

H4

NO_TEST

H11

NO_TEST

L12

NO_TEST

U5
SDRAM_DDR_4MX32
BGA
A0
(1 OF 2)
DQ0
A1
SEE_TABLE
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQS0
DQ12
DQS1
DQ13
DQS2
DQ14
DQS3
DQ15
DQ16
DM0
DQ17
DM1
DQ18
DM2
DQ19
DM3
DQ20
BA0
DQ21
BA1
DQ22
DQ23
CK
DQ24
CK
DQ25
CKE
DQ26
CS
DQ27
RAS
DQ28
CAS
DQ29
WE
DQ30
DQ31
MCL
RFU1
RFU2

NC

L13

E5

SEE_TABLE

E11

RFBD<64>
RFBD<65>
RFBD<66>
RFBD<67>
RFBD<68>
RFBD<69>
RFBD<70>
RFBD<71>
RFBD<72>
RFBD<73>
RFBD<74>
RFBD<75>
RFBD<76>
RFBD<77>
RFBD<78>
RFBD<79>
RFBD<80>
RFBD<81>
RFBD<82>
RFBD<83>
RFBD<84>
RFBD<85>
RFBD<86>
RFBD<87>
RFBD<88>
RFBD<89>
RFBD<90>
RFBD<91>
RFBD<92>
RFBD<93>
RFBD<94>
RFBD<95>

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

VSS

L7

19C7< 55C3>
19C7< 55C3>

K8
K9
L5

C3
L10

19C7< 55C3>
19C7< 55C3>

C5

19C7< 55C3>
19C7< 55C3>

C8

C7

F6
F7

C10

F8

19C7< 55C3>
19B7< 55C3>

C12

F9

19B7< 55C3>

E12

19B7< 55C3>
19B7< 55C3>

F4

E3

G6
G7

VDDQ
VSS_THERM

19B7< 55C3>
19B7< 55C3>

H6

G11

H7

J4

H8

19B7< 55C3>
19B7< 55C3>

J11

19B7< 55C3>
19B7< 55C3>

K4

J6

K11

J7

19B7< 55C3>
52A6> 21C8< 21A3<
19B7< 55C3>

VREF

N13

19B7< 55C3>
19B7< 55C3>

J9

64M_GRAM_DECOUP

19B7< 55C3>
19B7< 55C3>
19B7< 55C3>

D6

19B7< 55C3>
19B7< 55C3>

D11

D10

VSSQ

L9

NO_TEST
NO_TEST

M3

H5

M4

H10

N3

J5

J10

J10

K5

K5

C470
0.001UF

10%
2 50V
CERM
402

H2
B13
B3
H12

N12

55B3> 21B6< 18C2<> RFBBRAS_L


55B3> 21B6< 18C2<> RFBBCAS_L
55B3> 21B6< 18C2<> RFBBWE_L

M2

NC_FB4<0>
NC_FB4<1>
NC_FB4<2>
NC_FB4<3>
NC_FB4<4>
NC_FB4<5>
NC_FB4<6>
NC_FB4<7>
NC_FB4<8>

G10

NO_TEST

H13

55B3> 21C6< 18A2<> RFBBCKE


55B3> 21B6< 18C2<> RFBBCS0_L

G5

NO_TEST

B2

55B3> 19C1< RFBBCLK1


55B3> 19B1< RFBBCLK1_L

E9

NO_TEST

M7

M11

F10

NC_FB3<9>
NC_FB3<10>

L6

N4

F5

M10

M8

RFBBBA<0>
RFBBBA<1>

E6

19B7< 55C3>

N11

H3

55C3> 21C6< 18A2<>

D5

D9

N9
N10

B12

D4

19B7< 55C3>
19B7< 55C3>

M9

55C3> 18C2< RFBDQM<15>

B11

20%
2 10V
CERM
402

N8

55C3> 18C2< RFBDQM<14>

55C3> 21C6< 18A2<>

B4

C2302
0.1UF

N7

55C3> 18D2< RFBDQM<12>


55C3> 18D2< RFBDQM<13>

J8

SGRBVREF

M6

55B3> 19A3< RFBDQS<14>


55B3> 19A3< RFBDQS<15>

H9

K10

64M_GRAM_DECOUP

G9

G4

N6

55B3> 19A3< RFBDQS<12>


55B3> 19A3< RFBDQS<13>

G8

F11

N5

55C3> 21D6< 18C2<>


55C3> 21C6< 18B2<>

K7

L8

M13

M5

M12

N2

L2
L3
NO_TEST

C4

NO_TEST

C11

NO_TEST

H4

NO_TEST

H11

NO_TEST

L12

NO_TEST

L13

NO_TEST

M3

NO_TEST

M4

NO_TEST

N3

MCL
RFU1
RFU2

NC

RFBD<96> 19C4< 55C3>


RFBD<97> 19C4< 55C3>
RFBD<98> 19C4< 55C3>
RFBD<99> 19C4< 55C3>
RFBD<100> 19C4< 55C3>
RFBD<101> 19C4< 55C3>
RFBD<102> 19C4< 55C3>
RFBD<103> 19C4< 55C3>
RFBD<104> 19C4< 55C3>
RFBD<105> 19C4< 55C3>
RFBD<106> 19B4< 55C3>
RFBD<107> 19B4< 55C3>
RFBD<108> 19B4< 55C3>
RFBD<109> 19B4< 55C3>
RFBD<110> 19B4< 55C3>
RFBD<111> 19B4< 55C3>
RFBD<112> 19B4< 55C3>
RFBD<113> 19B4< 55C3>
RFBD<114> 19B4< 55C3>
RFBD<115> 19B4< 55C3>
RFBD<116> 19B4< 55C3>
RFBD<117> 19B4< 55C3>
RFBD<118> 19B4< 55C3>
RFBD<119> 19B4< 55C3>
RFBD<120> 19B4< 55C3>
RFBD<121> 19B4< 55C3>
RFBD<122> 19B4< 55C3>
RFBD<123> 19B4< 55C3>
RFBD<124> 19B4< 55C3>
RFBD<125> 19B4< 55C3>
RFBD<126> 19B4< 55C3>
RFBD<127> 19B4< 55C3>

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

M13
L9

NO_TEST

M10

NO_TEST

NC_FB4<9>
NC_FB4<10>

K10

+2_5V_MAIN

RFBBA<0>
RFBBA<1>
55C3> 21C6< 18B2<> RFBBA<2>
55C3> 21C6< 18B2<> RFBBA<3>
55C3> 21C6< 18B2<> RFBBA<4>
55C3> 21C6< 18B2<> RFBBA<5>
55C3> 21C6< 18B2<> RFBBA<6>
55C3> 21C6< 18B2<> RFBBA<7>
55C3> 21C6< 18B2<> RFBBA<8>
55C3> 21C6< 18B2<> RFBBA<9>
55C3> 21C6< 18B2<> RFBBA<10>
55C3> 21C6< 18B2<> RFBBA<11>

K6

L11

19C7< 55C3>
19C7< 55C3>

U36
SDRAM_DDR_4MX32
BGA
A0
(1 OF 2)
DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQS0
DQ12
DQS1
DQ13
DQS2
DQ14
DQS3
DQ15
DQ16
DM0
DQ17
DM1
DQ18
DM2
DQ19
DM3
DQ20
BA0
DQ21
BA1
DQ22
DQ23
CK
DQ24
CK
DQ25
CKE
DQ26
CS
DQ27
RAS
DQ28
CAS
DQ29
WE
DQ30
DQ31

E10

VDD

L4

19C7< 55C3>

SEE_TABLE

+2_5V_MAIN

64M_GRAM_DECOUP

C462
0.1UF

64M_GRAM_DECOUP

64M_GRAM_DECOUP

C488
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C466
0.001UF

10%
2 50V
CERM
402

64M_GRAM_DECOUP

64M_GRAM_DECOUP

C461
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

64M_GRAM_DECOUP

C469
0.1UF

C475
0.001UF

64M_GRAM_DECOUP

C486
0.1UF

20%
2 10V
CERM
402

10%
2 50V
CERM
402

64M_GRAM_DECOUP

C476
0.1UF

20%
2 10V
CERM
402

64M_GRAM_DECOUP

64M_GRAM_DECOUP

C489
0.001UF

10%
2 50V
CERM
402

10%
2 50V
CERM
402

QTY

DESCRIPTION

REFERENCE DES

333S0249

SDRAM,4MX32,DDR,275MHZ

U5,U36

CRITICAL

SAMSUNG_275_64M

333S0250

SDRAM,4MX32,DDR,275MHZ

U5,U36

CRITICAL

HYNIX_275_64M

333S0251

SDRAM,4MX32,DDR,300MHZ

U5,U36

CRITICAL

SAMSUNG_300_64M

SDRAM,4MX32,DDR,300MHZ

U5,U36

64M_GRAM_DECOUP

64M_GRAM_DECOUP

C22
0.1UF

20%
2 10V
CERM
402

C23
0.1UF

20%
2 10V
CERM
402

64M_GRAM_DECOUP

10%
2 50V
CERM
402

CRITICAL

BOM OPTION

SEE_TABLE
1
5%
1/16W
MF
2 402

HYNIX_300_64M

CRITICAL

MEMREFG_ACT_64M

U2
TLV431A
3 SOT

SGRAM2 & SGRAM3 DDR MEMORY REFERENCE SUPPORT


DESCRIPTION

C29
0.1UF

20%
2 10V
CERM
402

64M_GRAM_DECOUP

C34
0.1UF

20%
2 10V
CERM
402

64M_GRAM_DECOUP

C33
0.001UF

10%
2 50V
CERM
402

64M_GRAM_DECOUP

C20
0.1UF

20%
2 10V
CERM
402

64M_GRAM_DECOUP

C31
0.1UF

20%
2 10V
CERM
402

64M_GRAM_DECOUP

C28
0.001UF

10%
2 50V
CERM
402

MEMREFG_ACT_64M

MEMREFG3

A
QTY

64M_GRAM_DECOUP

SGRAM2 & SGRAM3 VREF

R18
1K

REFERENCE DES

CRITICAL

MEMREFG_PAS_64M
1 C8

1%
1/16W
MF
2 402

20%
10V
2 CERM
402

R6
1K

0.1UF

BOM OPTION

116S1103

RES,1K-OHM,5%,1/16W,0402

R18

MEMREFG_ACT_64M

116S1000

RES,0-OHM,5%,1/16W,0402

R18

MEMREFG_PAS_64M

MEMREFG_ACT_64M 164M_GRAM_DECOUP
1

C11
100PF

5%
2 50V
CERM
402

R4
1K

1%
1/16W
MF
2 402

MEMREFG4

MEMREFG_PAS_64M
1 C9

0.1UF

R17
0

SGRBVREF

SGRAM2 & SGRAM3

21C4< 21C8< 52A6>

5%
1/16W
MF
402

64M_GRAM_DECOUP

PART NUMBER

C40
0.001UF

+2_5V_MAIN

SGRAM0 & SGRAM1 MEMORY SUPPORT


PART NUMBER

333S0252

C16
0.001UF

NOTICE OF PROPRIETARY PROPERTY

MEMREFG_PAS_64M

R5
0

LAST_MODIFIED=Mon Oct 27 12:29:58 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

5%
1/16W
MF
402

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

20%
2 10V
CERM
402

SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
21 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

24A7<
24A7<

+3V_MAIN

C226
4.7UF

N20P80%
2 10V
CERM
805

C212
0.1UF

20%
2 10V
CERM
402

ANALOG_VSYNC*

R200

ANALOG_HSYNC*

10%
2 50V
CERM
402

TESTPOINT M5
TESTPOINT M4

26B7< VIPHAD0
26B7< VIPHAD1

TESTPOINT P3

52A6>

L2401
1000-OHM-EMI
1

NVPLLVDD

L4

VIPD0
VIPD1
VIPD2
VIPD3
VIPD4
VIPD5
VIPD6
VIPD7

J3

TESTPOINT

J2

TESTPOINT

VIPVDDQ0
VIPVDDQ1
VIPVDDQ2

L6

VIPCAL_PD_VDDQ
VIPCAL_PU_GND

P6

SEE_TABLE

VIPHCLK
VIPHCTL
VIPHAD0
VIPHAD1

PLLVDD

52A8> VIPCLK

VIPPCLK

K2
K1
L3
L2
N2
N1

VIPD0
VIPD1
VIPD2
VIPD3
VIPD4
VIPD5
VIPD6
VIPD7

0.1UF
20%
10V
2 CERM
402

VSYNC*
HSYNC*

AE3

C163
0.001UF

DAC2VDD

AB4

57D5>

10%
50V
2 CERM
402

52B6>

AF3

(GND)

AC4

AE2

R178
75

NOSTUFF

C207
27PF

1%
1/16W
MF
2 402

C190
27PF

57D5> DAC2RSET
57D5> DAC2VREF

R179
75

1%
1/16W
MF
2 402

5%
50V
CERM 2
402

NOSTUFF

+3V_MAIN

26B8<
26D7<

1%
1/16W
MF
2 402

26D7<
26D7<
26B8<
26C5<

R133
49.9

1C128

0.1UF

1%
1/16W
MF
2 402

L7

20%
2 10V
CERM
402

M7

VIP_PU
VIP_PD

P7

DACA_VSYNC
DACA_HSYNC

DACB_VSYNC
DACB_HSYNC
DACB_VDD
DACB_IDUMP

DACA_VDD
DACA_IDUMP

AJ8
AH9

TESTPOINT
TESTPOINT

NV11_VSYNC
NV11_HSYNC

1%
1/16W
MF
402 2

26D3<

1
1 NOSTUFF
C227

26D3<

SEE_TABLE
1

R173
75

DVOVREF
27B5< DVODE
27B5< DVOCLKOUT
27B6< DVOCLKOUT*
DVOCLKIN
27B5< 26D7< DVOHSYNC
27B5< DVOVSYNC

C162
0.01UF

5%
50V
2 CERM
603

1%
1/16W
MF
2 402

R174
1K

SEE_TABLE

AD3
AB5

AF4
TESTPOINT AE4
TESTPOINT AJ2
TESTPOINTAK2

AG1
AD5
TESTPOINT AD6

10UF

(GND)

AJ9

NV_BLUE2
NV_GREEN2
NV_RED2

1%
1/16W
MF
402 2

R5621
121

CVBS_D

1%
1/16W
MF
402 2

3
D

CVBS_CNT

Q10
2N7002

+3V_MAIN

SM

DACB_BLUE
DACB_GREEN
DACB_RED

DACA_BLUE
DACA_GREEN
DACA_RED

AJ10
AK10

AJ1

57C2> 27C5< 27A8< DVOD4


57C2> 27C5< 27A8< DVOD5

AH2

57C2> 27C5< 27A8< DVOD6


57C2> 27C5< 27A8< DVOD7

AJ3

57C2> 27C5< 26B1< DVOD8


57C2> 27C5< 27A8< DVOD9

AH4

DVOD10
DVOD11

AJ4

W7

NO_TEST

Y7

NO_TEST

AA6

NO_TEST

NC_DACC_BLU
NC_DACC_GRN
NC_DACC_RED

NC_DACC_RSET AC5

NO_TEST

NC_DACC_RSET

NC_DACC_BLUE
NC_DACC_GREEN
NC_DACC_RED

DVOVREF
DVODE
DVOCLKOUT
DVOCLKOUT*
DVOCLKIN
DVOHSYNC
DVOVSYNC

NOSTUFF
1

R191
10K

10K

22A8< 22A6< +3V_GPU_SS

AG3

AK1

AK3

AK4

AH5

B1

1%
1/16W
MF
2 402

1%
1/16W
MF
402 2

R183
121

C228
0.01UF

1%
1/16W
MF
2 402

10%
2 16V
CERM
402

NOSTUFF
1

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

5%
2 50V
CERM
402

R555
75

DVOD0
DVOD1
DVOD2
DVOD3
DVOD4
DVOD5
DVOD6
DVOD7
DVOD8
DVOD9
DVOD10
DVOD11

XTALSSIN

S1=M (NC) FOR -1.5% DOWN SPREAD


(NVIDIA RECOMMENDATION)

FOR +/-1.2% CENTER SPREAD

C368
0.1UF
20%
10V
CERM
402

C778
4.7UF

AJ6

57D5> NV11_XTALIN

XTALOUT

AH6

57D5> NV11_XTALOUT

DVOVDD

XTALOUTBUFF

AJ5

GPU_XTALOUTBUFF

G1

GPU_STRAP<0>
GPU_STRAP<1>
GPU_STRAP<2>
GPU_STRAP<3>

BUFRST*

STRAP0
STRAP1
NC_STRAP2
NC_STRAP3

G2
F2
F3

22B7< 22A6<

NC

+3V_GPU_SS
NOSTUFF

R599
0 2 CY811_S1
23D5<> NV_GPIOD7 1
5%
402
1/16W
MF

GPU_SS

R952
0

NC

5%
1/16W
MF
402
2

FRSEL

S1
S0

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

RES 95.3 OHM,1%,1/16W,0402

R554

NV18B

26D3<
26D3<

114S1332

RES 133 OHM,1%,1/16W,0402

R554

NV34

114S1212

RES 121 OHM,1%,1/16W,0402

R562

NV18B

114S1212

RES 121 OHM,1%,1/16W,0402

R562

NV34

TABLE_5_ITEM

TABLE_5_ITEM

5%
1/16W
MF
402
2

CY811_S0

NC_BUF_RST

NOTE: GPU_STRAP<3..2> ARE


TRUELY NC PINS. BUT
WERE CONNECTING TO THEM
AS A PRECAUTION

R170
49.9

R569
5.1M 2

TABLE_5_HEAD

PART#

5%
1/16W
MF
603

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

132S1045

CAP 0.01UF,50V,10%,0603

C162

NV18B

138S0518

CAP 1UF,10V,10%,0603

C162

NV34

TABLE_5_ITEM

Y2
SM-3
1

ADD DUAL LAYOUT SUPPORT


FOR ALTERNATE CRYSTAL

27.000M
CRITICAL
1

C617
22PF

5%
50V
2 CERM
402

GPU_SS

C616
22PF

5%
50V
2 CERM
402

22B2< 52A8>

DAC & CLOCKS

22B7<

NOSTUFF

R955
0

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:30:00 2003


NOSTUFF

1
1

R956
0 2

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

NVIDIA ASIC SUPPORT


NV_GPIOD8

23D5<>

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

338S0119

IC,NV18B,GRPHCS CTLR

U39

CRITICAL

5%
402
1/16W
MF

BOM OPTION

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

NV18B

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

338S0113

5%
1/16W
MF
402

IC,NV34,GRPHCS CTLR

U39

CRITICAL

NV34

SIZE

APPLE COMPUTER INC.

D
SCALE

155S0143

TABLE_5_ITEM

R954
0 NOSTUFF

BOM OPTION

TESTPOINT

1%
1/16W
MF
2 402

R957
0 2 GPU_XTALSSIN
1

+3V_GPU_SS 22A8<
1

NOSTUFF

5%
1/16W
MF
402
2

22A5< 52A8>

5%
402
1/16W
MF

VSS

R953
0

114S9531

5%
2 50V
CERM
402

TABLE_5_HEAD

22A8<

GPU_SS

GPU_SS_XIN

C607
27PF

26A4<
26B3<

0.1UF

1%
1/16W
MF
2 402

VDD
U9
CRITICAL
CY25811
SOI
1
XIN/CLKIN
8 XOUT
SSCLK 5 CLK27M_MEM_SS

5%
2 50V
CERM
402

NOSTUFF
1

1%
1/16W
MF
2 402

XTALIN

GPU_SS

C606
27PF

GPU_XTALSSIN

R171
49.9

S0=0

NOSTUFF
1

C605
27PF

R188
10K GPU_SS_NO

20%
6.3V
CERM
805

NOSTUFF

GPU_SS

R557
75

AJ7

C1103

+3V_MAIN

GPU_SS

NOSTUFF

R556
75

NOTE: KEEP STUB SHORT ->

5%
1/16W
MF
402

10%
50V
2 CERM
402

PLACE CLOSE TO GPU

DVO_PU AB6 DVOCAL_PD_VDDQ


DVO_PD AB7 DVOCAL_PU_GND

1R185

MIN_LINE_WIDTH=25

SM

R942
22 2

2
SM

C206
0.001UF

AE8

20%
10V
2 CERM
402

L33
FERR-EMI-100-OHM

20%
10V
2 CERM
402

NV_BLUE2 22C1<> 22C1<>


NV_GREEN2 22C1<> 22C1<>
NV_RED2 22C1<> 22C1<>

DACRSET
DACVREF

DACA_RSET AG8
DACA_VREF AH8

DACB_RSET
DACB_VREF

AD9

20%
10V
CERM 2
402

THIS IS A HUGE 3A BEAD


HOW MUCH CURRENT DO WE NEED HERE?
GPU_SS

57C2> 27C5< 26D1< DVOD3

AD8

AH1

+3V_MAIN

1%
1/16W
MF
402 2

C209
0.1UF

57C2> 27C5< 27A8< DVOD1


57C2> 27C5< 26D1< DVOD2

57C2> 27B5< 27A8<


57C2> 27B5< 27A8<

R1941
10K

22B4<> GPU_XTALOUTBUFF

C224
0.1UF

PLACE CLOSE TO GPU


STRAPS
AG2

57C2> 27C5< 27A8< DVOD0

1%
1/16W
MF
2 402

SEE_TABLE

R5541
95.3

S1=0

N20P80%
10V
2 Y5V
805

AG10

+3V_MAIN

SEE_TABLE

L68
100-OHM-EMI

52B6> DACVDD

AG9

1NV18B

S0=1

1
1

5%
50V
CERM 2
402

+3V_MAIN

26B7<

R1451
49.9

AD2

23D7<>

R118
10K

26B7<

AD1

1
1

1C164

C153
10UF

N20P80%
10V
2 Y5V
805

5%
50V
CERM 2
402

AK7

I2CA_SCL
I2CA_SDA

SM

L2401 SHOULD BE 155S0141 IF STUFFED


57D5> 25C6< ANALOG_BLU
57D5> 25C6< ANALOG_GRN
57D5> 25B6< ANALOG_RED
NOSTUFF

TESTPOINT P2

I2CC_SCL
I2CC_SDA

1% 402
1/16W

10

NC_VIPHCLK

57D5>

SEE_TABLE

C170
27PF

C213
0.001UF

AF7

26D5< VIPHCTL

2
SM

ROUTE THE RGB LINES


AS 75 OHM TRACES.

AG5

AG7

U39
NV18B
BGA
(2 OF 5)

MF 1/16W 1% 402

SEE_TABLE
L13
100-OHM-EMI
1

R199
10 2

MF

+3V_MAIN

MON_I2C_SCL
MON_I2C_SDA

25B6<

1%
1/16W
MF
603

59B7> 57D5> 26B5< 25D6<>

AG6

25B6<

R206
10 2
1

59B7> 57D5> 26B5< 25C6<>

GRAPH_DDC_SCL
GRAPH_DDC_SDA

2 FLTR,EMI,1000 OHMS,.2A,0805

L13,L68

DRAWING NUMBER

REV.

051-6569 A
22 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

+3V_MAIN
+3V_MAIN

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

R91
10K

LAMP_STS

[IN]

MON_DETECT

[IN]

29A3<

59D5> 25C6<

LCD_PWM

[OUT]

FPD_PWR_ON

[OUT]

29A8<
51B3<

22B7<
29B8<

47

1
402

47

1
402

R98
10K

R85

R86

INV_CUR_HI

51B1<>

TMDS_EN

47

[IN]

1
402

R112

R92
10K

1%
1/16W
MF
2 402

+3V_MAIN

GPIOD0

F4

GPIOD1

NV_GPIOD2
FPD_PWR_ON

G4

GPIOD2

H5

GPIOD3

GPIOD6

R107

J6

GPIOD7

22A6<

NV_GPIOD8

402

10K 1

R113

K4

GPIOD8

402

10K 1

R115

K6

GPIOD9

NC_GPU_THERMC

H3

THERMD-

NC_GPU_THERMA

H2

THERMD+

M3

FPBCLKOUT
FPBCLKOUT*

10K

1%
1/16W
MF
402

402

1K
1K

1K
1K

NV_GPIOD9

R124
R119

GPU_FPBCLK
GPU_FPBCLK_L

M2

U39
NV18B
BGA
(5 OF 5)

402

R1020NV34
1

10K

402

R237 NV18B
R213 NV18B

GPU_SWAP_A
GPU_SWAP_B

2
402

1%
1/16W
MF
402

402

1K
47

R564
R102

10K 1

R114

C160
0.1UF

20%
10V
2 CERM
402

GPU_STEREO
GPU_TESTMECLK

AF9
AD4
Y5
G24

I2CB_SDA
I2CB_SCL

STEREO
TESTMEMCLK

GPU_FW_PME_L AF10 NC_FRWR_PME*


N6 NC_FRWR_VAUXC
M6 NC_FRWR_VAUXP
(+3V_MAIN)
L5 NC_FRWRLNKON
GPULNKON
NC_GPULPS NO_TEST N5 NC_FRWRLPS

MAKE TP AS SHORT AS POSSIBLE

AE7

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

IFPATXD0
IFPATXD0*

U4

IFPATXD1
IFPATXD1*

Y2

IFPATXD2
IFPATXD2*

V3

Y3

IFPBTXD4
IFPBTXD4*

W4

IFPBTXD5
IFPBTXD5*

AB3

IFPBTXD6
IFPBTXD6*

Y6

IFPBTXD7
IFPBTXD7*

AC3

V5

AB2

W6

AC2

IFPCTXC
IFPCTXC*

P5

IFPCTXD0
IFPCTXD0*

R3

IFPCTXD1
IFPCTXD1*

U2

IFPCTXD2
IFPCTXD2*

U3

P4

T2

T3

V2

R990

SI_SCL 27C5<

NOSTUFF

TMDS_XMIT_GPU

01

R961

TMDS_CKP
TMDS_CKM

R881TMDS_XMIT_GPU
01
2 R962
01
2 R946TMDS_XMIT_GPU
TMDS_XMIT_GPU 01
2 R963
01
2 R947TMDS_XMIT_GPU
TMDS_XMIT_GPU 01
2 R964
01
2 R960TMDS_XMIT_GPU

01

57D2> 23C2< GPU_TMDS_D0P

TMDS_D0P
TMDS_D0M

TMDS_XMIT_GPU

57D2> 23C2< GPU_TMDS_D2P


W3 57D2> 23C2< GPU_TMDS_D2M

AA2

SI_SCA 27C5<

NOSTUFF

01

57D2> 23C2< GPU_TMDS_D1P


AA1 57D2> 23C2< GPU_TMDS_D1M

V4

R9912

01

T4 57D2> 23C2< GPU_TMDS_D0M

U5

R207
2K

GRAPH_IIC_SDA2
GRAPH_IIC_SCL2

57D2> 23C2< GPU_TMDS_CKP


V1 57D2> 23C2< GPU_TMDS_CKM

W2

IFPBTXC
IFPBTXC*

SWAPRDY_A
SWAPRDY_B

AF6

IFPATXC
IFPATXC*

IFPATXD3
IFPATXD3*

402

20%
10V
2 CERM
402

J5
2

GRAPH_CORE

C189
0.1UF

GPIOD5

10K 1

1%
1/16W
MF
2 402

J4

402

R1019 NV34
R184
10K

GPIOD4

NV_GPIOD7

402

H4

22A8<

52A6> 48C2<> 17D4<

G5

NV_GPIOD5

NV_GPIOD0
MON_DETECT

CVBS_CNT
[OUT]

R208
2K

TMDS_D1P
TMDS_D1M
TMDS_D2P
TMDS_D2M

5%
1/16W
MF
402

NC_TMDS_TXD3P
NC_TMDS_TXD3M

IFP0VREF

AA4

IFP0RSET

V6

IFP0PLLVDD

U10

IFPABPLLVDD

V10

IFPABPLLGND

IFP0AVCC
1

C125
0.1UF

20%
10V
2 CERM
402

SEE_TABLE
1

NOSTUFF
1

C130
0.1UF

20%
2 10V
CERM
402

R149
1K

C152
0.1UF

IFPABRSET

NC_EXT_TMDS_D1M
NC_EXT_TMDS_D2P
NC_EXT_TMDS_D2M

52A6> 23A6<

57D2> 23D3<>

GPU_TMDS_CKP

NC_TMDS_TXD7P
NC_TMDS_TXD7M

57D2> 23D3<>

GPU_TMDS_CKM

NC_DFPCLK
NC_DFPCLK*

57D2> 23D3<>

GPU_TMDS_D0P

57D2> 23D3<>

GPU_TMDS_D0M

NC_DFPD0
NC_DFPD1
NC_DFPD2
NC_DFPD3
NC_DFPD5
NC_DFPD6

57D2> 23D3<>

GPU_TMDS_D1P

57D2> 23D3<>

GPU_TMDS_D1M

57D2> 23D3<>

GPU_TMDS_D2P

57D2> 23D3<>

NC_IFP1VREF
NC_IFP1RSET

IFPCPLLVDD

P10

GPU_IFB1IOVDD

IFPCPLLGND

N10

T5

IFPAIOVDD

IFPCIOVDD

R5

T6

IFPAIOGND

IFPCIOGND

R6

5%
1/16W
MF
2 402

Y4

IFPBIOVDD

W5

27C2< 57D2>
27C2< 57D2>
27C2< 57D2>
27C2< 57D2>

TMDS_GPU_PU

49.9

TMDS_GPU_PU

TMDS_GPU_PU

TMDS_GPU_PU

2
1

49.9 1

49.9

TMDS_GPU_PU

GPU_TMDS_D2M

49.9

TMDS_GPU_PU

TMDS_GPU_PU

49.9

49.9

TMDS_GPU_PU

IFP0AVCC

49.9
1

49.9

R992
2 R996
R993
2 R997

R994
2 R998
R995
2 R999
1%
1/16W
MF
402

GPU_IFP1PLLVDD
1

R141
0

27C2< 57D2>

NO_TEST NC_EXT_TMDS_D1P

R4

IFPCRSET

27C2< 57D2>

NC_EXT_TMDS_D0P
NC_EXT_TMDS_D0M

AA3

IFPCVPROBE

1%
1/16W
MF
2 402

20%
2 10V
CERM
402

IFPABVPROVE

27C2< 57D2>
27C2< 57D2>

PLACE TMDS RESISTORS ON OPPOSITE SIDE TO TMDS


RESISTORS ON PAGE 29

NC_EXT_TMDS_CKP
NC_EXT_TMDS_CKM

MAKE TP AS SHORT AS POSSIBLE


52A6>

24B7<>
59A7>
24A7<>
59A7>
24B7<>
59B7>
24B7<>
59A7>
24C7<>
59B7>
24C7<>
59B7>
24D7<>
59B7>
24D7<>
59B7>

IFPBIOGND
2

R157
10K
1%
1/16W
MF
402

R144
10K
1%
1/16W
MF
402

VOUT = 2.8V
1

+3V_MAIN

C119
0.1UF

20%
10V
2 CERM
402

C131
0.1UF

20%
10V
2 CERM
402

1
TMDS_PLL_ACT

+5V_MAIN

D10
MBR0530
SM
2

R246
0

5%
1/10W
FF
2 805

VALUES CONTROL GPU TMDS SWING


TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION

TMDS_PLL_ACT

TMDS_PLL_ACT

TABLE_5_ITEM

U20
LM1117
SOT-223-4
IN
OUT 2
1

NV18B

114S1503

RES,1.5K,1%,1/16W,0402

R149

NV34

R602
100

L2501
FERR-EMI-100-OHM

IFP_VADJ

1
1

20%
6.3V
TANT
SMA

R149

1 TMDS_PLL_ACT

(SYM_VER1)

1%
1/16W
MF
2 402

C2501
10UF

RES,1K,1%,1/16W,0402

TABLE_5_ITEM

20%
2 10V
TANT
SMB

IFP_AVCC

ADJ/GND
C636
22UF

114S1003

R592
124

1%
1/16W
MF
402

10%
2 10V
CERM
805

C635

IFP0AVCC

DVI AND STRAPS

23C1< 52A6>

SM
1

1UF

C626
0.1UF

20%
2 16V
CERM
603

C618
0.001UF

NOTICE OF PROPRIETARY PROPERTY

10%
2 50V
CERM
402

LAST_MODIFIED=Mon Oct 27 12:30:02 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

TMDS_PLL_ACT

TMDS_PLL_ACT

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
23 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

L82
FERR-250-OHM
52B6> 51C1<>

+3.3VFPD

INT_TMDS_3V

2
SM

XMIT_RES

59B7> 57D2> 27C2< 23D1<

TMDS_D2P

R603
0 2

TD2P

R600
301

L76

1%
1/16W
MF
2 402
SEE_TABLE

59B7> 57D2> 27C2< 23D1<

SYM_VER-2

TMDS_D2M

90-OHM
SM
XMIT_CHOKE

R594
0 2

TD2M

XMIT_RES

XMIT_RES

59B7> 57D2> 27C2< 23D1<

TMDS_D1P

1%
1/16W
MF
2 402

L74
90-OHM
SM
XMIT_CHOKE

SYM_VER-2

SEE_TABLE

59B7> 57D2> 27C2< 23D1<

TD1P

R591
301

R593
0 2

R582
0 2
1

TMDS_D1M

(518S0039)

J12
FI-TWE21P-VF

TD1M

F-ST-SM
22

XMIT_RES

INT_TMDS_3V

1
2

59C7> 52A6> INT_TMDS_3V

3
4

57C5>

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION

57C5>

TD2M
TD1P

6
7
8

TABLE_5_ITEM

114S3012

RES,301 OHMS,1%,1/16W,0402

R559,R570,R591,R600

FPD_3V3

116S1202

RES,200 OHMS,5%,1/16W,0402

R559,R570,R591,R600

FPD_12VM

57C5> TD1M

11

57C5> TD0P

10

57C5>

TABLE_5_ITEM

57C5>

TD0M
TCKP

12
13
14
15
16
17
18

59C5>

TMDS_DDC_DAT

XMIT_RES

59B7> 57D2> 27C2< 23D1<

57C5> TD2P

TMDS_D0P

TD0P

59C5> TMDS_DDC_CLK

20

INT_TMDS_3V

21

23

R581
0 2

57C5> TCKM
59B7> 52B6> DDC_VCC_3

19

43B7<
29A3<
43A7<
52C4

C652
0.01UF

10%
2 16V
CERM
402

C107
10UF

10%
2 16V
CERM
1210

R570
301

L71

1%
1/16W
MF
2 402

SYM_VER-2

INTERNAL TMDS CONNECTOR

90-OHM
SM
XMIT_CHOKE

SEE_TABLE

59A7> 57D2> 27C2< 23D1<

TMDS_D0M

R568
0 2

TD0M

XMIT_RES

XMIT_RES

59A7> 57D2> 27C2< 23D1<

TMDS_CKP

R567
0 2

TCKP

L67

R559
301

1%
1/16W
MF
2 402

90-OHM
SM

XMIT_CHOKE
SYM_VER-1

SEE_TABLE

59A7> 57D2> 27C2< 23D1<

R550 0
1

TMDS_CKM

TCKM

XMIT_RES

22D5<>

GRAPH_DDC_SDA

R540
2K
5%

1/16W
MF
1 402

TMDS_DDC_DAT

5%
1/16W
MF
402

+3V_MAIN

R546
33 2

TMDS/LVDS

L64
FERR-250-OHM
1

NOTICE OF PROPRIETARY PROPERTY

SM
1

5%
1/16W
MF
2 402

10%
16V
2 CERM
402

R547
2K

22D5<>

R551
33 2
1

GRAPH_DDC_SCL

DDC_VCC_3

LAST_MODIFIED=Mon Oct 27 12:30:03 2003

C610
0.01UF

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

TMDS_DDC_CLK

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

5%
1/16W
MF
402

SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569
A
24 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

52A3> 33A6<> 25C2< 25B5<>

USB_PWR

D6
BAV99DW
SOT-363
5

59B7> 57D5> 26B5< 22D7<

ANALOG_HSYNC*

NOSTUFF
4

5%
50V
2 CERM
402

PLACE 75 OHM TERMINATIONS


NEAR GRAPHICS CHIP RGB PINS

59B7> 57D5> 26B5< 22D7<

ANALOG_VSYNC*

C421
22PF
D7
BAV99DW
SOT-363
5

THE RGB TRACES MUST BE GUARDBANDED


BY DACGND FROM THE GRAPHICS CHIP

NOSTUFF
4

59D5> 23D7<>

C422
22PF

5%
2 50V
CERM
402

MON_DETECT

ALT
CHASSIS

J9
F-RT-TCX3160-110200

FL3
LCFILTER

TH-4MT

SM-220MHZ

57D5> 22C7<>

ANALOG_BLU

17
1

2
15
3

4
1

C
MON_DETECT

13

59B7>
57D5>

FILT_ANALOG_BLU

SM-220MHZ

57D5> 22C7<>

ANALOG_GRN

59B7> 52A6> DDC_VCC_5

ANALOG_VSYNC*

14

FL2
LCFILTER

59B7> 57D5>

FILT_ANALOG_GRN

10

ANALOG_HSYNC*

59B7> 57D5>

FILT_ANALOG_RED

12

USB_PWR 25B5<>

25D3<> 33A6<> 52A3>

SM

C423
0.01UF

10%
16V
2 CERM
402

(GRN_RTN)

59B5> VGA_IIC_DAT

4
3

1
1

(BLU_RTN)

3
6

L9
FERR-250-OHM

59B5> VGA_IIC_CLK

11

(RED_RTN)

ALT
CHASSIS

16

FL4
LCFILTER

18

C414
0.01UF

SM-220MHZ

57D5> 22C7<>

ANALOG_RED

2
3

(514-0021)

C432
0.01UF

10%
16V
2 CERM
402

C409
0.01UF

10%
16V
2 CERM
402

USB_PWR

ROUTE THE ANALOG RGB TRACES AT 75 OHMS.


SEE THE EXTERNAL DESIGN GUIDE FOR LAYOUT DETAILS.

D28
BAV99DW

R7
2K

22D5<>

ALT
CHASSIS

52A3> 33A6<> 25D3<> 25C2<

10%
16V
CERM 2
402

R19
2K

5%
1/16W
MF
402 2

SOT-363
5

5%
1/16W
MF
2 402

MON_I2C_SDA

R3
33

NOSTUFF
4
2

5%
1/16W
MF
402

22D5<>

MON_I2C_SCL

R2
33

D27
BAV99DW
SOT-363
5

5%
1/16W
MF
402

NOSTUFF
4

EXTERNAL VGA CONNECTOR


C415
47PF

5%
50V
CERM 2
402

C416
47PF

5%
50V
2 CERM
402

ALT
CHASSIS

EXTERNAL VGA

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:30:03 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
25 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

+3V_MAIN
+3V_MAIN

+3V_MAIN

R596

SEE_TABLE
2

R533

10K

10K

1%
1/16W
MF
1 402

22D5<>

VIPHCTL

10K
1%

1/16W
MF
1 402

1/16W
MF
1 402

NOSTUFF
2

R125

10K
1%

10K

22C4<>

1%
1/16W
MF
1402

1/16W
MF
1402

SEE_TABLE
2

R583

1/16W
MF
1 402

R561

(5) HOST MODE


[0] = [VIPHCTL]

22D4<> VIPD5

0 = PCI MODE

22D4<> VIPD4

* 1 = AGP MODE

10K
1%

10K
1%

1/16W
MF
1402

1/16W
MF
1402

22B4<>

SEE_TABLE
2

R588
1K

R116

10K

1K
1%

1/16W
MF
1 402

1%
1/16W
MF
1 402

R142

1K
1%

=
=
=
=
=

R1023

R79

1K

1K
1%

1%
1/16W
MF
2 402

1/16W
MF
1 402

1K
1%
1/16W
MF
1 402

0X112 GEFORCE2 GO
0X113 QUADRO2 GO
0X114 NV17M
0X110 GEFORCE2GO MX (NV11B)
NV18B,NV31,NV34

1111 = 222MHZ
1101 = 275MHZ SAMSUNG
1100 = 275MHZ HYNIX

R136

(3) PCI DEVICE ID


[3..0] = [DVOHSYNC,VIPD3,VIPD5,VIPD4]
0010
0011
0100
0000
1001

SEE_TABLE
2

(8) FRAME BUFFER MEMORY TYPE


[3..0] = [NV11_HSYNC,NV11_VSYNC,GPU_STRAP<3>,GPU_STRAP<2>]
2

PARALLEL
SERIAL AT25F
SERIAL SST45VF
SERIAL FUTURE

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

1/16W
MF
1 402

22D4<> VIPD7

=
=
=
=

1K

1/16W
MF
1 402
SEE_TABLE
2

NOSTUFF
1

R560

R1022

1K
1%

SEE_TABLE

+3V_MAIN

1/16W
MF
1 402
NOSTUFF
2

R73

1/16W
MF
1 402

1K
1%

22B5<> 27C5< 57C2>


22C5<> 27C5< 57C2>

SEE_TABLE
SEE_TABLE
2

R126

1/16W
MF
1 402

1%
1/16W
MF
1 402

DVOD3
DVOD2

1K
1%

10K

GPU_STRAP<2>

1K
1%

R552

R535

NV11_HSYNC

R597

NOSTUFF
2

R77

22C4<> NV11_VSYNC
22B4<> GPU_STRAP<3>

27B5< 22C5> DVOHSYNC


22D4<> VIPD3

00
01
10
* 11

10K

1%
1/16W
1 MF
402

SEE_TABLE
2

R595

(1) ROM TYPE (OVERRIDDEN IF STRAP1 = 0)


[1..0] = [ROMA15,ROMA14]

R236

SEE_TABLE

1%
1/16W
MF
1 402

ROMA15
ROMA14

2 SEE_TABLE

R74

10K
1%

1K
1%

18C8<
18C8>

SEE_TABLE
2

R598

1/16W
MF
1 402

R553

+3V_MAIN

10K
1%
2

PART NUMBER

QTY

DESCRIPTION

114S1004

RES,10KOHM,1%,0402

114S1003

RES,1KOHM,1%,0402

114S1004

RES,10KOHM,1%,0402

114S1003

RES,1KOHM,1%,0402

114S1004

RES,10KOHM,1%,0402

114S1003

RES,1KOHM,1%,0402

114S1004

RES,10KOHM,1%,0402

114S1003

RES,1KOHM,1%,0402

(6) AGP SIDEBAND


[0] = [VIPD7]
* 0 = ENABLE AGP SIDEBAND

REFERENCE DES

CRITICAL

R598,R583,R77,R236,R535

BOM OPTION
SAMSUNG_NV18B_270

R73

SAMSUNG_NV18B_270

R598,R583,R236,R535

HYNIX_NV18B_270

R73,R79

HYNIX_NV18B_270

1 = DISABLE AGP SIDEBAND

+3V_MAIN

+3V_MAIN

+3V_MAIN

NOSTUFF
2

R134

NOSTUFF
2

R399

10K

1%
1/16W
MF
1 402

10K
5%

1/16W
MF
1 402

1/16W
MF
1 402

TMDS_XMIT_SI

R401
10K
5%

10K
5%

1/16W
MF
1402

1/16W
MF
1402

1/16W
MF
1402

59B7> 57D5> 25D6<> 22D7<


59B7> 57D5> 25C6<> 22D7<

22B4<>

ANALOG_HSYNC*
ANALOG_VSYNC*

R543

GPU_STRAP<1>

10K
5%

R87
1K
1%

NOSTUFF
2

R397

R449

57C2> 27C5< 22B5<> DVOD8

1K
1%

1K
1%

1/16W
MF
1 402

R1021
1K

NV34
1%
1/16W
MF
402
2

1K
1%

1/16W
MF
1 402

1/16W
MF
1 402

(9) SUB-VENDOR
[0] = [GPU_STRAP<1>]

TMDS_XMIT_GPU
2

NOSTUFF
2

R541

R408

1K
1%

(2) CRYSTAL FREQUENCY SELECT


[1..0] = [VIPD6,VIPD2]

R426

R443

1K

0 = SYSTEM BIOS (VENDOR & SUBSYSTEM ID=0X0000)


1 = ADAPTER CARD VGA BIOS (VENDOR & SUBSYSTEM ID=0X54-0X57)
FASTWR
0 = ENABLE
1 = DISABLE

1K
1%

1%
1/16W
MF
1 402

1/16W
MF
1 402

1/16W
MF
1 402

+3V_MAIN

00 = 13.5MHZ
01 = 14.38MHZ

NVIDIA STRAPS 1

* 10 = 27MHZ

11 = {UNDEFINED}

(4) USER DEFINED STRAPS


[3..0] = [VIPHAD1,VIPHAD0,VIPD1,VIPD0]
THESE BITS ARE UNDEFINED BUT THEY
MUST BE KEPT LOW DURING RESET

R94

(7) TV MODE
[1..0] = [ANALOG_HSYNC*,ANALOG_VSYNC*]
00
01
10
* 11

=
=
=
=

SECAM
NTSC
PAL
DISABLED

NV18B

1/16W
MF
1402

+3V_MAIN

R439

10K
5%

1/16W
MF
1 402

1/16W
MF
1 402

HYNIX_NV34_270

NOSTUFF
2

VIPHAD1
22D5<> VIPHAD0
22D4<> VIPD1
22D4<> VIPD0

1K
1%

HYNIX_NV34_270

R597,R1022

10K

22D5<>

R100

R583,R74,R77,R535

5%
1/16W
MF
1 402

R542

22D4<> VIPD2

SAMSUNG_NV34_270

R427

NOSTUFF
2

22D4<> VIPD6

SAMSUNG_NV34_270

R1022

NOSTUFF
2

R445

10K
1%

R598,R583,R535,R74,R77

10K
1%

22B4<>

NOTICE OF PROPRIETARY PROPERTY

1/16W
MF
1 402

LAST_MODIFIED=Mon Oct 27 12:30:05 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

GPU_STRAP<0>

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

(10) PCI ADDRESS BUS


[0] = [GPU_STRAP<0>]

(THESE RESISTORS ARE ALL NOSTUFF)

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

0 = REVERSED

* 1 = NORMAL
APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569
A
26 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

+3V_MAIN

+3V_MAIN

TMDS_XMIT_SI_P

TMDS_XMIT_SI_P

L4

L88

FERR-EMI-100-OHM
1

FERR-EMI-100-OHM

SM

3V_SI_AVCC

SM

C325 1

C366

10UF

C557

100PF

20%
6.3V 2
CERM
805

100PF

5%
50V
CERM 2
402
TMDS_XMIT_SI_P TMDS_XMIT_SI_P

27B2< 3V_SI_VCC

C583

100PF

5%
50V
CERM 2
402
TMDS_XMIT_SI_P

5%
2 50V
CERM
402
TMDS_XMIT_SI_P

C786

100PF

5%
2 50V
2
CERM
402
TMDS_XMIT_SI_P

C984
10UF

20%
6.3V
CERM
805
TMDS_XMIT_SI_P

L87

FERR-EMI-100-OHM
TMDS_XMIT_SI_P

3V_SI_PLLVCC

NOTE:
330OHM HI SWING
RESISTOR MAY NEED TO BE
HIGHER

SM

C272 1

C113 1

10UF

10UF

20%
6.3V 2
CERM
805
TMDS_XMIT_SI_P

20%
6.3V 2
CERM
805
TMDS_XMIT_SI_P

C360 1

C449

100PF

100PF

5%
50V
CERM 2
402
TMDS_XMIT_SI_P

5%
50V
CERM 2
402
TMDS_XMIT_SI_P

PLL NOISE SHOULD BE LESS THAN 100MV PEAK-TO-PEAK

R972
330

NOSTUFF

R967

R969

4.7K

5%
1/16W
MF
402 2

4.7K

4.7K

5%
1/16W
MF
402 2

5%
1/16W
MF

5%
1/16W
MF
402 2

2 402

23D2< SI_SCL
23D2< SI_SCA

27

NC

25
47
44

57C2> 27A8< 22C5<> DVOD0


57C2> 27A8< 22C5<> DVOD1
57C2> 26D1< 22C5<> DVOD2
57C2> 26D1< 22B5<> DVOD3
57C2> 27A8< 22B5<> DVOD4
57C2> 27A8< 22B5<> DVOD5
57C2> 27A8< 22B5<> DVOD6
57C2> 27A8< 22B5<> DVOD7
57C2> 26B1< 22B5<> DVOD8
57C2> 27A8< 22B5<> DVOD9
57C2> 27A8< 22B5<> DVOD10
57C2> 27A8< 22B5<> DVOD11
22C5<> DVODE
26D7< 22C5> DVOHSYNC
22C5> DVOVSYNC
R1000
22C5> DVOCLKOUT
SI_SWING_LO 0
1
2
DVOCLKOUT*
SI_IDCK_M

18
17
16
15
14
13
10
9
8
7
6
5
19
20
21
12
11

MSEN 48

IPD
IPD
IPD

PD*
EDGE/HTPLG

NC

57C2> SI_TMDS_CKP
57C2> SI_TMDS_CKM

TXC+ 33
TXC- 32

U1
D0
SIL1162
D1
TX0+ 36
TSSOP
D2
TX0- 35
D3
TX1+ 39
TMDS_XMIT_SI_P
D4
TX1- 38
D5
CRITICAL
D6
TX2+ 42
D7
TX2- 41
D8
D9
D10
D11
DE
HSYNC
EXT_SWING 30
VSYNC
VREF 2
IDCK+
IDCK-

57C2> SI_TMDS_D0P
57C2> SI_TMDS_D0M
57C2> SI_TMDS_D1P
57C2> SI_TMDS_D1M

TMDS_XMIT_SI

22 1

57C2> SI_TMDS_D2M

22 1

22 1

TMDS_CKM

24B7<> 57D2> 59A7>


23D1< 24A7<> 57D2> 59A7>

R978 TMDS_D0P

23D1< 24B7<> 57D2> 59B7>

TMDS_D0M

23D1< 24B7<> 57D2> 59A7>

R979 TMDS_D1P

23D1< 24C7<> 57D2> 59B7>

TMDS_D1M

23D1< 24C7<> 57D2> 59B7>

TMDS_XMIT_SI

22 1

R975

TMDS_XMIT_SI

R977TMDS_CKP23D1<

TMDS_XMIT_SI

22 1

R974

TMDS_XMIT_SI

22 1

22 1

R973

TMDS_XMIT_SI

57C2> SI_TMDS_D2P

TMDS_XMIT_SI

22 1

R980 TMDS_D2P

R976 TMDS_XMIT_SI

23D1< 24D7<> 57D2> 59B7>


24D7<> 57D2> 59B7>

TMDS_D2M 23D1<

5%
1/16W
MF
402

PLACE TMDS RESISTORS ON OPPOSITE SIDE TO TMDS


RESISTORS ON PAGE 25

SI_EXT_SWING_SET

3V_SI_VCC

27D3<

SEE_TABLE

R10031

49

29
45

23

5%
MF
402

1/16W

37
1

22C5<>

SI_I2C_OFF
AGP_RESET_L
SI_EDGE

SCL/DK1
SDA/DK0
CTL3/A2
ISEL/RST*

TMDS_XMIT_SI_P

PGND
PGND
AGND
AGND
AGND
GND
GND
GND
THRML
PAD

26
24

31
43

44D3< 17B8<

MF

R971

R1001

4.7K

5%

1/16W
2 402

28

PVCC1
46
PVCC2 40
AVCC
34
AVCC 22
VCC
3
VCC

NOSTUFF

TMDS_XMIT_SI_P

NOSTUFF

1K

1%
1/16W
MF
402 2
TABLE_5_HEAD

TMDS_XMIT_SI_P

NOSTUFF

R9651
4.7K

5%
1/16W
MF
402 2

NOSTUFF

R9661
4.7K

5%
1/16W
MF
402 2

SI_VREF

TMDS_XMIT_SI_P

R9681
4.7K

5%
1/16W
MF
402 2

SI_SWING_HI

R9701 R10021
4.7K

5%
1/16W
MF
402 2

SI_SWING_LO
1

R1004

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

114S1003

RES,1K,1%,1/16W,0402

R1003

SI_SWING_LO

116S1000

RES,0 OHM,1%,1/16W,0402

R1003

SI_SWING_HI

TABLE_5_ITEM

1K

5%
1/16W
MF
402 2

1%
1/16W
MF
402 2

SILICON IMAGE 1162 TMDS


+3V_MAIN
2

R250
MF

R548
10K
1%

MF

1/16W

MF
1 402
57C2> 27B5< 22B5<>
57C2> 27B5< 22B5<>

R248
10K
1%

1/16W

MF
1 402

10K
1%

1/16W

1/16W

MF

1 402

R537

10K
1%

1/16W

1402

R563

10K
1%

1/16W

R238

10K
1%

MF

1 402

R243
10K
1%

1/16W

MF
1402

1402

R241

R244

10K
1%

10K
1%

1/16W

1/16W

MF
1402

MF

1 402

DVOD11
DVOD10
DVOD9

NVIDIA STRAPS 2

57C2> 27C5< 22B5<>


57C2> 27C5< 22B5<>
57C2> 27C5< 22B5<>
57C2> 27C5< 22B5<>
57C2> 27C5< 22B5<>

NOTICE OF PROPRIETARY PROPERTY

DVOD7
DVOD6
DVOD5
DVOD4

LAST_MODIFIED=Mon Oct 27 12:30:06 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

57C2> 27C5< 22C5<>


57C2> 27C5< 22C5<>

DVOD1
DVOD0

SIZE

APPLE COMPUTER INC.

D
SCALE

UNDEFINED RESET CONFIGURATION STRAPS

DRAWING NUMBER

REV.

051-6569 A
27 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

+2_5V_MAIN

1%
1/16W
MF
402 2

0.1UF

20%
10V
CERM 2
402

20%
10V
CERM 2
402

PLL TEST FUNCTION

C229

NOSTUFF
1

NOSTUFF
1

R292
1K

R291

NOSTUFF
1

R274

1K

1%
1/16W
MF
402 2

R228

1K

1K

1%
1/16W
MF
402 2

1%
1/16W
MF
402 2

NOSTUFF
1

NOSTUFF
1

1K

1%
1/16W
MF
402 2

R276

R708

R735

R727

R661

R577

R573

1K

1K

1K

1K

1K

1K

1K

1%
1/16W
MF
402 2

1%
1/16W
MF
402 2

1%
1/16W
MF
402 2

1%
1/16W
MF
402 2

C3001 1

JTAG TDO)

1%
1/16W
MF
402 2

1%
1/16W
MF
402 2

G5

28A8< INT_GPIO1_PD
59D5> 29D7<> 28D1< COMM_SHUTDOWN

E1
J7

COMM_RESET_L
36C8< FWPHYRST
SND_HP_MUTE_L
41A7<
43C8< SND_AMP_MUTE_L
28B8< INT_GPIO9_PU
39B4< 28A8< SND_HW_RESET_L
28A8< INT_GPIO12_PU
59A5> 28C1< UNUSED_GPIO15
35B8< 28D1< INT_ENET_RST_L

F2

CONFIGURED FOR INTREPID VERSION 1


VIEW AGP CLOCK OUT LA CLOCK PIN

GPIO & INTERRUPT PULL-UPS


R746
1

AGP_INT_L 17B6<>

1%
1/16W
MF
402

10K

1%
1/16W
MF
402

R750
1

10K

1%
1/16W
MF
402

B
1

3
4

10K

10K

5%
1/16W
SM1

3
4

SPARE

10K

5%
1/16W
SM1

7
6

NO_TEST

33SLOTB_INT_L

2
3
4

10K
5%
1/16W
SM1

NO_TEST

7
6
5

2
3
4

10K

5%
1/16W
SM1

NO_TEST

7
6
5

COMM_RING_DET_L 28B5<>
INT_EXTINT13_PU 44C5<>
28B5<>
NC_RPT77P6
PMU_INT_L 28B5<> 44B5<>

29C5<>
59D5>

10K

NC_CBUS_INT_L
PMU_INT_NMI 28B5<> 44C4<>
PMU_REQ_L 28C3> 44C2<
EXTINT14 28B5<>

J23
U.FL-R_SMT

NC_RP2848
INT_GPIO12_PU 28B5<>
INT_GPIO1_PD 28C5<>
SND_HW_RESET_L 28B5<>

E31

D30

PMU_PME_L

AJ7

44B4<> INT_PROC_SLEEP_REQ_L
44B4<> INT_PEND_PROC_INT

AT6

R666
1

10K

1
NOSTUFF
1

R611

D34

G30

5%
1/16W
MF
402

NOSTUFF

R672
1

5%
1/16W
MF
2 402

10M

5%
1/16W
MF
402

Y5

18.432M
1

32A8<

CLK18M_INT_XO

C32
B32
E30
J9
F4
D1
E2
H7
G4

AN8

44C5<>

SEE_TABLE

(ON PAGE 12)

VIA
MISO
REQ*
MOSI
ACK*
SCK

7
6
5

R756
10K

INT_ENET_RST_L

35B8< 28B5<>

USB

35B4> 28B5<>

ENET_ENERGY_DET

AUDIO/I2S

CLOCKS

AT7

WATCHDOG

NC_BRCLKO

U15

BUF_REF_CLK_OUT
SS_REF_CLK_IN

R1005
USB PULL-UPS

USB_PWR_FLT*

10K

1%
1/16W
MF
402

+3V_MAIN

RP60
28B3< USB_OC_EF_L
28B3<> USB_PWREN_CD_L
28B3<>
28B3<>

USB_PWREN_AB_L
USB_PWREN_EF_L

2
3
4

+3V_MAIN

10K

5%
1/16W
SM1

6
5

10K
1%
1/16W
MF
2 402

59A5> 28B5<>

402
402

58B5> 28A3< USB_DBN

402

24
24

24
24

R724USB1 USB_DAP_F 33B7<


R718USB1 USB_DAN_F 33B7<
R736USB1 USB_DBP_F 33C7<
R742USB1 USB_DBN_F 33C7<

UNUSED_GPIO15

58B5>
NOSTUFF
1

58B5>

R267
10K

58B5>

1%
1/16W
MF
2 402

58B5>

33A7>

58B5> 28A3< USB_DCP

402

58B5> 28A3< USB_DCN

402

24
24

R723USB1 USB_DCP_F 33D7<


R728USB1 USB_DCN_F 33D7<

R694
R691

58B5>
58B5>

USB_DDP_F_TERM
USB_DDN_F_TERM

J1

USB_VD5_P
USB_VD5_N N8

XTAL_IN
V15 XTAL_OUT
AN7
STOPXTAL

5%
1/16W
SM1

USB_PWREN_CD_L 28C2<

J2

P8

USB_PRTPWR2
USB_PWRFLT2

10K

R294

58B5> 28A3< USB_DBP

24
24

58B5> 28A3< USB_DAN

402

N20P80%
2 10V
CERM
805

402

402

10K

RP117
NC_RP3324_2 NO_TEST

4.7UF

20%
2 10V
CERM
402

58B5> 28A3< USB_DAP

USB_DDP
USB_DDN

USB_VD4_P K5
USB_VD4_N L5

U4

0.1UF

USB_PWREN_AB_L 28C2<
USB_PWR_FLT* 28C1< 32B1<

USB_VD3_P M7
USB_VD3_N M8

5%
1/16W
SM1

C820

PMU_FROM_INT 44C4<>
PMU_REQ_L 28A8< 44C2<
PMU_TO_INT 44C4<>
PMU_ACK_L 44C4<>
PMU_CLK 44C4<>

USB_PRTPWR1
USB_PWRFLT1

PCIPME
PROCSLEEPREQ
PENDPROCINT

SCCTXDB AR4
SCCRTSB AL5
SCCRXDB AG10
SCCGPIOB AP4
SCCTRXCB AM5

USB_VD2_P H2
USB_VD2_N H1

INTERRUPTS

C795

COMM_TXD_L 29C7<> 59C5>


COMM_RTS_L 29D5<> 59C5>
COMM_DTR_L 29C7<> 59C5>
COMM_RXD 29C5<> 59C5>
COMM_GPIO_L 28D3< 29C5<> 59C5>
COMM_TRXC 28D3< 29C7<> 59C5>

K4

10K

5%
1/16W
SM1

SCCTXDA AF9
SCCRTSA AN3
SCCDTRA AF10
SCCRXDA AG11
SCCGPIOA AG9
SCCTRXCA AT4

USB_PRTPWR0
USB_PWRFLT0

RP117

33A7> 32B1< 28B3<

USB_VD1_P G2
USB_VD1_N G1

EXTINT0
EXTINT1
EXTINT2
EXTINT3
EXTINT4
EXTINT5
EXTINT6
EXTINT7
EXTINT8
EXTINT9
EXTINT10
EXTINT11
EXTINT12
EXTINT13
EXTINT14
EXTINT15
EXTINT16
EXTINT17
CPU_INT

C785

10%
2 16V
CERM
402

J4

10K

N7

R4

MOD_DTO
MOD_DTI
MOD_SYNC
MOD_BITCLK
MOD_CLKOUT

R2

R7
T5
P2
R5

402

58B5> USB_DEN

402

58A5> USB_DFP
58A5> USB_DFN

402
402

22
22

22
22

R762
R763
R271
R272

BT_USB_DP 29D3<>
BT_USB_DM 29D3<>
MODEM_USB_DP
MODEM_USB_DM

58B5> 59B5>

58A5> 59B5>

29C5<> 58A5> 59B5>


29C5<> 58A5> 59B5>

USB_PWREN_EF_L 28C2<
USB_OC_EF_L 28C2<

M5

AUD_DTO
AUD_DTI
AUD_SYNC
AUD_BITCLK
AUD_CLKOUT

58B5> USB_DEP

INT_SND_TO_AUDIO
AUDIO_TO_SND
INT_SND_SYNC
INT_SND_SCLK
INT_SND_CLKOUT

T4
R1
V8
P1

RP108

47

47
47
47

3
1

SND_TO_AUDIO 39C4<
AUDIO_TO_SND 39C1<
SND_SYNC 39C1<>
SND_SCLK 39B1<>
SND_CLKOUT 39B4<

RP108
6RP108
8RP108

INT_MOD_DTO 28A8< 28C6<


R30011
INT_MOD_DTI 28A8< 28C6<
15K
INT_MOD_SYNC 28A8< 28C6<
5%
1/16W
INT_MOD_BITCLK 28A8< 28C6<
MF
402 2
INT_MOD_CLKOUT 28A8< 28C6<

R3002

15K
5%
1/16W
MF
402
2

R6501

R651 R6601

R683

15K

15K

10K

10K

5%
1/16W
MF
402 2

5%
1/16W
MF
2 402

1%
1/16W
MF
402 2

1%
1/16W
MF
2 402

R711
0

5%
1/16W
MF
2 402

K9

R710

IIC

10K

1%
1/16W
MF
2 402

C840
27pF

5%
50V
2 CERM
402

IICCLK_2 AL4
IICDATA_2 AH8

28A3< 28C6<

INT_I2C_CLK2 28D1< 29C7<> 34B5< 39B1<> 59A7>


INT_I2C_DATA2 28D1< 29C7<> 34B5< 39B1<> 59A7>
58B5> 28B3<> USB_DAP
58B5> 28B3<> USB_DAN
58B5> 28B3<> USB_DBP
58B5> 28B3<> USB_DBN
58B5> 28B3<> USB_DCP
58B5> 28B3<> USB_DCN

INT_REF_CLK_IN_PD
INT_MOD_CLKOUT 28A3> 28C6<
INT_MOD_DTO 28A3> 28C6<
INT_MOD_BITCLK 28A3<> 28C6<
INT_MOD_SYNC 28A3<> 28C6<

COMM_SHUTDOWN

5%
1/16W
SM1

+3V_MAIN

0.01UF

USB_VD0_P L8
USB_VD0_N L7

5%
50V
CERM 2
402

59D5> 29D7<> 28C5<>

SM

GENERAL
PURPOSE
I/OS

INT_WATCHDOG_L

8X4.5MM-SM

27pF

INT_MOD_DTI

D31

CLK18M_INT_XIN
CLK18M_INT_XOUT
44C4<> SYSTEM_CLK_EN

5%
1/16W
SM1

RP117

RP117

28A5<>

53A6<
8

5%
1/16W
SM1

59A5> 44B2<> 32A8< 31C2<

NOSTUFF

C784 1
2

E34

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO9
GPIO11
GPIO12
GPIO15
GPIO16

AA15

10K

33SLOTB_INT_L
UNUSED_EXTINT7
UNUSED_EXTINT8
44C4<> 28A8< PMU_INT_NMI
28D3< VCORE_VGATE
32A8< 28A8< USB2_CRUN_L_INT
28B8< INT_EXTINT12_PU
28B8< INT_EXTINT13_PU
28A8< EXTINT14
59B7> 41A5< SND_HP_SENSE_L
42B8< SND_SPKR_ID
32B6> 28B8< INT_EXTINT17_PU
8D7<> 7A5< 4B3< MPIC_CPU_INT_L

CRITICAL

USB2_CRUN_L_INT 28B5<>

NOSTUFF

A33

39B4<

1%
1/16W
MF
402

35B4> 28C1< ENET_ENERGY_DET

CLK18M_INT_EXT

F-ST-SM
3

NOSTUFF

R680
1

B33

28B7<> 31C2<>
59A5>

51

1%
1/16W
MF
402

K7

59B5> 40D4< SND_LIN_SENSE_L

(518S0104)

RP110
R589
1

F1

28B8< 17B6<> AGP_INT_L


28B8< INT_EXTINT3_PU

32B6>

RP100
1

K8

C33

(USB2.0 IRQ)

RP74
1

J5

28B8<>
28B8<>

INT_GPIO9_PU 28B5<>
INT_EXTINT12_PU 28B5<>
INT_EXTINT17_PU 28B5<>
INT_EXTINT3_PU 28B5<>

H4

F33

5%
1/16W
MF
402

2 28B5<> UNUSED_EXTINT8 SPARE

L9

59D5> 44C5<> 29C5<> 28B8< COMM_RING_DET_L


44B5<> 28B8< PMU_INT_L

R747
1

1%
1/16W
MF
402
7

H5

NOSTUFF

FW_C_LKON

33SLOTB_INT_L

28B5<> UNUSED_EXTINT7

1
2

36B5<> 34C5<>

R306
1

RP113
2

28B5<>

R749

J8

FERR-EMI-100-OHM

U25

4.7K 1
5%
1/16W
MF
402

52D3>

L16

INTREPID

28D3< SNF_FSEL

28A5<>

20%
10V
CERM 2
402

BGA
(6 OF 9)

TOO MANY MODS TO LIST, SEE INTREPID ERS

10K

INT_PLL1_GND

0.1UF

59A7> 29D5<>

+3V_MAIN

INT_PLL2_GND

INT_I2C_DATA2

1%
1/16W
MF
402

VCORE_VGATE

52A3> +3V_INTREPID_USB

INT_MOD_BITCLK 28A3<> 28A8<


INT_MOD_CLKOUT 28A3> 28A8<
INT_MOD_DTO 28A3> 28A8<
INT_MOD_SYNC 28A3<> 28A8< (INTREPID
INT_MOD_DTI 28A3< 28A8<
JTAG_INTRP_TDO 34B7> 35B3<
JTAG_ASIC_TDI 8A4<> 34B7< 59D7>
INT_TST_PLLEN_PD 34B7<

1K

10K

1%
1/16W
MF
402

+1_5V_INTREPID_PLL1

NOSTUFF
1

1K

1%
1/16W
MF
402 2

20%
10V
CERM 2
402

R232

1%
1/16W
MF
402 2

NOSTUFF
1

0.1UF

R574

1%
1/16W
MF
402 2

20%
10V
CERM 2
402

VDDU33_2 U8

1K

1%
1/16W
MF
402 2

R641
39B1<> 34B5< 29C7<> 28A3<>
59A7>

RP39

0.1UF

VDDU33_1 T8

R289

1K

1%
1/16W
MF
402 2

28B5<>

VSSU_2

R678

1K

1%
1/16W
MF
402 2

5%
1/16W
MF
402

SNF_FSEL

4.7K 1
5%
1/16W
MF
402

5%
1/16W
SM1

COMM_TRXC

52D3>

R8

R231

4.7

INT_PLL3_GND 28A4<>
+1_5V_INTREPID_PLL2

28C5<>

R755

R9

C3002

R565
1

59C5> 29C7<> 28C3<>

0.1UF

HWPLL_TESTMUXSEL[0:5]
NOSTUFF
1

4.7

10K

5%
1/16W
SM1

52D3>

20%
10V
CERM 2
402

5%
1/16W
MF
402

C692 1

INT_PLL7_GND 28A4<>
+1_5V_INTREPID_PLL3

0.1UF

R620
1

+3V_MAIN

C3003

10K

NO_TEST

INT_I2C_CLK2

RP39

RP39

5%
1/16W
MF
402

C703 1

INTREPID DEBUG HOOKS

4.7

R264

COMM_GPIO_L

59C5> 29C5<> 28C3<>

NC_RP3319

VSSU_1

10%
10V 2
X5R
603

52D3>

20%
10V
CERM 2
402

R628

10K

5%
1/16W
SM1

0.1UF

VDD15A_8 AG29
(PLL9)

1UF

LT1962_INT_BYP
R590
56.2K

BYP 3
GND 4

SHDN

20%
10V
CERM 2
402

C3004

VSSA_8
(PLL9)

0.1UF

59A7> 39B1<> 34B5< 29C7<> 28A3<>

AH29

C234 1

5%
1/16W
MF
402

C704 1

AK18

5%
1/16W
MF
603

20%
2 6.3V
CERM
805

LT1962_INT_ADJ

ADJ 2

PCI_
VDD15A_4 AJ18
(PLL7)

NC

NC_RPT48P1 NO_TEST
INT_PLL9_GND 28A4<>
+1_5V_INTREPID_PLL4

VSSA4
(PLL7)

NC

10UF

4.7

+3V_MAIN

I2C 2 PULL-UPS

RP39

20%
10V
CERM 2
402

PCI_
VDD15A_3 AJ17
(PLL3)

NC_UT6P6 NO_TEST

C233

+3V_MAIN

52D3>

0.1UF

R629

VSSA3
(PLL3)

NC_UT6P7 NO_TEST

20%
10V
CERM 2
402

C3005

AJ16

+1_5V_INTREPID_PLL8

PCI_
VDD15A_2 AJ12
(PLL2)

R572

0.1UF

1%
1/16W
MF
402 2

10%
16V
CERM 2
402

AJ13

LT1962_INT_VIN

15.8K

0.01uF

U19

LT1962-ADJ
MSOP
8 IN
OUT 1

C713

4.7

5%
1/16W
MF
402

PCI_
VDD15A_1 AA16
(PLL1)

+1_8V_MAIN
NOSTUFF

R586

C623 1

5%
1/16W
MF
603

VSSA1
(PLL1)

VSSA2
(PLL2)

R571

R630
52D3> 30D5< 16D6< 9D4< +1_5V_INTREPID_PLL

15K
402 15K
402 15K
402 15K
402 15K
402 15K
402

R305
R396
R247
R398
R333
R493

INTREPID GPIO/
SCC/USB/I2S

USB2

USB2

NOTICE OF PROPRIETARY PROPERTY

USB2

LAST_MODIFIED=Mon Oct 27 12:30:09 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

USB2
USB2

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

USB2

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

NO_TEST

28C4<
28D4<

RP66

INT_PLL1_GND
INT_PLL2_GND

2
NO_TEST

2
NO_TEST

XW42
XW43
XW44
XW45
XW46
SM
SM
SM
SM
SM

NO_TEST

NO_TEST

INT_PLL9_GND
INT_PLL7_GND
INT_PLL3_GND

28D4<

SIZE

28D4<

28D4<

APPLE COMPUTER INC.

SCALE
1

DRAWING NUMBER

REV.

051-6569 A
28 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

MODEM BOARD CONNECTOR

BLUETOOTH CONNECTOR

(DASH II)

+3V_MAIN

+3V_MAIN

BS3

NOSTUFF
1

NOSTUFF

C622

10UF

C621

R584

0.1uF

N20P80%
10V
2 Y5V
805

R585

4.7K

20%
10V
2 CERM
402

1%
1/16W
MF
2 402

J13
SM-2MT-6MM-HT

COMM_SHUTDOWN
NC_MODEM_DETECT_L
59C5> 28C3> COMM_DTR_L

59D5> 28D1< 28C5<>

NO_TEST

59C5> 28C3<> COMM_TXD_L


59C5> 28D3< 28C3<> COMM_TRXC

NC_DAA_CLKOUT
NC_DAA_LOADOUT
NC_-10VUNREG

N20P80%
10V
2 Y5V
805

10

11

12

13

14

15

16

COMM_RXD 28C3<> 59C5>


COMM_GPIO_L 28C3<> 28D3<

NO_TEST

21

22

+12V NEEDS TO BE 25 MIL TRACE

NO_TEST

23

24

25

26

MODEM_USB_DP
MODEM_USB_DM

27

28

29

30

NO_TEST

31

32

NO_TEST

33

34

NO_TEST

35

36

NO_TEST

37

38

39

40

IIC_ADD

NO_TEST

0.1uF

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

NO_TEST

F-ST-SM

NO_TEST

NO_TEST

NO_TEST

NO_TEST

10

NO_TEST

NC_BT3
NC_BT4
NC_BT5
NC_BT6
NC_BT1

BS4
STDOFF-197OD-236H-TH
NC_BS4
1
NO_TEST

15K

BS4 SHORTEST STANDOFF


FURTHEST FROM J28

(516S0093)

BLUETOOTH CARD MOUNTING HARDWARE SUPPORT


52C1> 59D7>

28B2< 58A5> 59B5>


28B2< 58A5> 59B5>

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

860-0170

STDOFF,BLUETOOTH,SHORT

BS4

860-0171

STDOFF,BLUETOOTH,LONG

BS3

CRITICAL

BOM OPTION

NC_AUD_MODEM_RTN
NC_AUD_MODEM
NC_AUDIO2MODEM
NC_AUDIO2MODEMRTN

C
SERIAL DOWNLOAD INTERFACE

PIN 35 IIC ADDRESS


WE ARE SET TO ADDR= AC

C620

53307-1090

59C5>

COMM_RING_DET_L 28B5<> 28B8< 44C5<> 59D5>


NC_-12VREG
+12V_SLEEP 29A3< 29A8< 50D5< 51A5< 51C2< 51D6<>

20

J28

20%
10V
2 CERM
402

R3281

COMM_RESET_L 28C5<> 59A7>


COMM_RTS_L 28C3> 59C5>

18

C
10UF

19

59A7>

C619

17

+5V_MAIN

0.1uF

R3291
15K

NO_TEST

59A7> 39B1<> 34B5< 28D1< 28A3<> INT_I2C_CLK2


59A7> 39B1<> 34B5< 28D1< 28A3<> INT_I2C_DATA2

NOSTUFF

STDOFF-197OD-236H-TH
NC_BS3
1

C314

BT_USB_DM
BT_USB_DP

59B5> 58A5> 28B2<


59B5> 58B5> 28B2<

44

20%
6.3V
2 CERM
805

10K

5%
1/16W
MF
2 402

C312
10UF

43

20%
10V
2 CERM
402

52B3> 44D5<> 44C2< 44B1< 44A5<>

PMU_POWER

(515S0120)

NC_BS1

BS2

BS1

STDOFF-197OD-236H-TH

STDOFF-197OD-236H-TH

NO_TEST

NC_BS2

NO_TEST

R7061

R6681

1%
1/16W
MF
402 2

1%
1/16W
MF
402 2

10K

10K

J24

R670
10K

1%
1/16W
MF
2 402

R669
10K

1%
1/16W
MF
2 402

SM

PMU_CNVSS
44D4<> PMU_AP

44B5<

MODEM STANDOFF SUPPORT


PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

860-1034

STDOFF-19709-236H-TH

BS1,BS2

(CE*)

CRITICAL

BOM OPTION

59D5> 44B5<> 44A5<> 8A8<>


44C4<>

PMU_RST*
PMU_EPM*

1%
1/16W
MF
402 2

KITCHEN SINK CONNECTOR


DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

CONN,HDR,STR,2MMPITCH,18P,PEG

J14

CRITICAL

KITCH_SINK_18P

516-0031

CONN,HDR,STR,2MMPITCH,16P,PEG

J14

CRITICAL

KITCH_SINK_16P

18P_GND

TABLE_5_ITEM

L77

L75

R6131

KS_INT_SPKR+_FILT

59A7> 58A5> 43B8< MICHIGH


59A7> 58A5> 43A8< MICLOW
59A7> INV_CUR_HI_FILT
59A7> 52B3> KS5VSD

KS_INT_SPKR-_FILT

10

11

12

LCD_PWM_FILT

13

14

59A7> 52B3> LED_5V_FILT


59C7> 52B3> FAN_12V_FILT

15

16

17

18

59A7>

L72

51C2<
29A3<
50D5<
52C1>

+12V_SLEEP

(518-0098)
1

N20P80%
10V
2 Y5V
805

C604
0.1UF

20%
10V
2 CERM
402

MODEM, BLUETOOTH,
KITCHEN SINK
& SERIAL DOWNLOAD

52B3>

SM

FERR-250-OHM
1

NOSTUFF
10UF

29A8< 29C5<> 50D5< 51A5< 51C2<


51D6<> 52C1> 59D7>

L69

20%
2 35V
TANT
SMD

C625

LED_RET 51B6<

C629
10UF

42B4< 43D7< 58A5> 59B7>

1000-OHM-EMI
1

SM

KS_INT_SPKR-

L73 FW_12V
FERR-250-OHM
1
2
+12V_SLEEP

LED_RET_FILT

43D7< 58A5> 59B7>

SM

59A7> LAMP_STS_FILT
52A3>
59A7>

SM

KS_INT_SPKR+

L78

L66

FERR-250-OHM
51D6<>
29C5<>
51A5<
59D7>

SM

L65

36D6< 50C6<> 51D4<> 52B6>

SM

L70
SM

52B3> +12VSD_FILT

FERR-250-OHM
52B3> LED_5V

OMIT

SERIAL DOWNLOAD CONNECTOR

FERR-250-OHM

NC_PMU_DL_10
NC_PMU_DL_12

L80

FERR-250-OHM
23D7< LCD_PWM

12 NO_TEST

FERR-250-OHM

59A7> 58A5> 43A8< MICSHLD

SM

82.5

(TXD)

10 NO_TEST

LAMP_STS

NOTICE OF PROPRIETARY PROPERTY

23D7<

LAST_MODIFIED=Mon Oct 27 12:30:11 2003

SM
1

C630
220PF

5%
25V
2 CERM
402

C627

0.01UF

10%
16V
2 CERM
402

C614
220PF

5%
25V
2 CERM
402

PMU_P64 44C2<>
LID_SWITCH 44C4<>
RESET_BUTTON* 44C4<> 59D5>
NMI_BUTTON* 44C4<> 59D5>

SM

+5V_SLEEP

9
11

L103 FW_24V
FERR-250-OHM
1
2
FW_PWR

M-ST-TH

FERR-250-OHM

1%
1/4W
FF
1210 2

HL55091

SM

+5V_MAIN

J14

FERR-250-OHM
INV_CUR_HI

(RXD)

5%
1/16W
MF
603

SEE_TABLE
CRITICAL

23D7<

R1015

TABLE_5_ITEM

518-0098

(SCLK)

(MICROPHONE,INTERNAL SPEAKER CONNECTIONS


INVERTER,LCD,LED & FAN POWER)
FW_24V

TABLE_5_HEAD

QTY

(BUSY)

515S1392

10K

PART#

LOW FOR LOADING CODE

R7051

C608

0.01UF

10%
16V
2 CERM
402

C601

0.01UF

C609

0.01UF

10%
16V
2 CERM
402

10%
16V
2 CERM
402

C615
220PF

5%
25V
2 CERM
402

C639
100PF

5%
50V
2 CERM
402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

C640
100PF

5%
50V
2 CERM
402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

52C4 43B7< 43A7< 24B3<

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
29 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

7
R218
22 2
1

CLK33M_PCI_SLOTB

C848
0.1UF

5%
1/16W
MF
402

R719
2.2 2

+1_5V_INTREPID_PLL6 52D3>

5%
1/16W
MF
402

C3201
0.1UF

20%
10V
CERM 2
402

20%
10V
CERM 2
402

NOSTUFF

NC_CLK33M_PCI_SLOTC

NO_TEST

5%
1/16W
MF
402

MAIN LOOP MATCHES


LONGEST PCI CLOCK

USB2

Vout = PCI I/O (3.3V)


Vin = Vcore (1.5V)

R566
22 2
1

54C7<

NOSTUFF

R616
0 2
1

R617
22 2
1

5%
1/16W
MF
402

5%
1/16W
MF
402
NOSTUFF
1

R253
0

5%
1/16W
MF
2 402 NOSTUFF

NOSTUFF

R256
0 2
1

R262
0 2
1

5%
1/16W
MF
402

5%
1/16W
MF
402

32B6<

R252
22

R621
39

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402
NOSTUFF

R618
0 2
54C7< PCI_FBI_EQUAL 1

Adds 2"

PCI_FBI_PLUS2

5%
1/16W
MF
402

R259
0

5%
1/16W
MF
2 402

Adds 2"

5%
1/16W
MF
2 402

59C7> 31B2<> 30B2<

RP63
10K
8

59B7> 31B4<> 30B2<

PCI_IRDY_L

5%
1/16W
SM1
7

RP63
10K

RP69
4.7K

AJ19

AN16
AT15
AH16
AR15
AM17

AM16

53A6< 32B6<>

INT_ROM_OVERLAY_PU
INT_ROM_CS_L
INT_ROM_OE_L
INT_ROM_RW_L

ROM_CS_L

R227
22 1

ROM_RW_L

AJ15
AK17
AM9
AR7
AN9

R230
22 1
2

R578
22 1

NO_TEST

5%
1/16W
MF
402

AK12
AJ8
AN10
AT8
AN11
AH13
AK13
AR9
AR10
AT9
AR11
AM12
AN12
AK11
AT11
AT10
AN13
AM13
AR12
AJ11
AT12
AM11
AR13
AK15
AH15
AN14
AT13
AK14
AN15
AM15

INT_PLL4_GND

PCI_TRDY_L

RP63
10K
5

59C7> 31B4<> 30C6<

PCI_DEVSEL_L

PCI_STOP_L
RP69
4.7K
8

30C5<> 31B7< 32B6<> 54D7< 59A5>

PCI_SLOTB_REQ_L

PCI_SLOTC_REQ_L

7
INT_V1

RP69
4.7K

RP38
10K

RP38
10K
6

PCI_SLOTD_REQ_L

30D5<> 32B6>

ROM_ONBOARD_CS_L
ROM_OE_L
59B7> 31B4<> 30B6< ROM_RW_L
59A7> ROM_WP_L
32A8< 31D4< 17C8< MAIN_RESET_L

59D5> 31B4<>

59C7> 31B2<> 30C6<

21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37
38

22
24
9
12
10

PCI_SLOTB_GNT_L

U42
FEPR-1MX8
110
TSOP
DQ0
A0
A1 SEE_TABLEDQ1
DQ2
A2
DQ3
A3
DQ4
A4
DQ5
A5
DQ6
A6
DQ7
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20

NC_RP1399

52C4 49B2<>
59D7>

PCI_SLOTD_GNT_L

25
26
27
28
32
33
34
35

PCI_AD<24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>

30C4<>
59B3>
30C4<>
30C4<>
59B3>
30C4<>
30C4<>

31B6< 32C6<> 53A6<


31B7< 32C6<> 53A6<
31B6< 32B6<> 53A6<

R510
0 2
1

30D5<> 32B6<

31B7< 32B7<> 53A6<


31B6< 32B6<> 53A6<

30C4<> 31B7< 32B6<> 53A6<


30C4<> 31B6< 32B6<> 53A6<
59B3>
30C4<> 31B7< 32B6<> 53A6<

CE
OE
WE
WP
PWD

B
39

+2_5V_MAIN

1MB BOOT ROM

DEV
5

LED_ROMCS_L

U38
SN74AUC1G04
4
LED_ROMCS

04

5%
1/16W
MF
402

SC70-5
DEV

R5111
681

16D7< 30C5<> 54A7<

1%
1/16W
MF
402

1%
1/16W
MF
402 2

FLASH BOOT ROM SUPPORT

ROM PULL-UP

A
RFA STRUCTURE AT PVT
REPORTING TO 341T1292

PART NUMBER

QTY

341S1291

DESCRIPTION

REFERENCE DES

IC,FLASH,ROM,Q59 PVT,VER TBD

U42

CRITICAL
CRITICAL

BOM OPTION

LED_ROMCS_LIGHT

ROM_PVT

DEV

341S1289

IC,FLASH,ROM,Q59 EVT,VER TBD

U42

CRITICAL

ROM_EVT

DS4
GREEN

341S1290

IC,FLASH,ROM,Q59 DVT,4.7.4B0

U42

CRITICAL

ROM_DVT

SM

341T1292

IC,FLASH,ROM,Q59 PROD,VER TBD

U42

CRITICAL

ROM_PROD_T

341S1280

IC,FLASH,ROM,Q59 DEV,VER TBD

U42

CRITICAL

ROM CHIP SELECT

INTREPID PCI
& BOOT ROM

009-6525

IC,FEPR,FLASH ROM,DEV

U42

OMIT

335S0350

IC,FLASH ROM,1MB,BLANK

U42

OMIT

NOTICE OF PROPRIETARY PROPERTY

ROM_DEV

LAST_MODIFIED=Mon Oct 27 12:30:13 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

RFA STRUCTURE ONCE ROM IS FINAL


REPORTING TO 341T1292

341S1372

IC,FLASH,ROM,Q59 PROD,VER TBD

U42

CRITICAL

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

ROM_PROD

009-6588

IC,FEPR,FLASH ROM,PROD

U42

OMIT

335S0350

IC,FLASH ROM,1MB,BLANK

U42

OMIT

SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
30 69
1
SHT

OF

NONE

OVERRIDE ROM MODULE


INTERCEPTS ROM CHIP SELECT

30D5<> 31C2<> 59A5>

DEV
2

31

VCC

GND

5%
1/16W
SM1

INT_ROM_OVERLAY_PU

30

23

NO_TEST

RP38
10K

11

30D5<>

5%
1/16W
SM1

5%
1/16W
SM1

R579
10K 1
2

RP38
10K
8

5%
1/16W
SM1
2

1%
1/16W
MF
402 2

59A5> 44C4<>

30D5<> 31C3<> 59A5>

30D5<>

R212
10K

1%
1/16W
MF
402

INTREPID PCI INTERFACE


PCI_SLOTC_GNT_L

5%
1/16W
SM1

5%
1/16W
SM1

5%
1/16W
SM1

ROM_CS_L

30C5<> 31B7< 32B6<> 54D7< 59A5>

5%
1/16W
SM1
4

PCI_AD<0>
53A6< 32C6<> 31C7< 30D4<> PCI_AD<1>
53A6< 32C6<> 31C7< 30D4<> PCI_AD<2>
53A6< 32C6<> 31C7< 30D4<> PCI_AD<3>
59C3> 53A6< 32C6<> 31C7< 30D4<> PCI_AD<4>
53A6< 32C6<> 31C7< 30D4<> PCI_AD<5>
59C3> 53A6< 32C6<> 31C7< 30D4<> PCI_AD<6>
53A6< 32C6<> 31C7< 30D4<> PCI_AD<7>
53A6< 32C6<> 31C7< 30D4<> PCI_AD<8>
59C3> 53A6< 32C6<> 31C7< 30D4<> PCI_AD<9>
53A6< 32C6<> 31C7< 30C4<> PCI_AD<10>
59C3> 53A6< 32C6<> 31C7< 30C4<> PCI_AD<11>
53A6< 32C6<> 31C7< 30C4<> PCI_AD<12>
59C3> 53A6< 32C6<> 31C7< 30C4<> PCI_AD<13>
53A6< 32C6<> 31C7< 30C4<> PCI_AD<14>
59B3> 53A6< 32C6<> 31C7< 30C4<> PCI_AD<15>
59B3> 53A6< 32C6<> 31C7< 30C4<> PCI_AD<16>
53A6< 32C6<> 31C6< 30C4<> PCI_AD<17>
59B3> 53A6< 32C6<> 31C7< 30C4<> PCI_AD<18>
53A6< 32C6<> 31C6< 30C4<> PCI_AD<19>
59B3> 53A6< 32C6<> 31C6< 30C4<> PCI_AD<20>

R138
1K 2
1

30C5<> 31B7< 32B6<> 53A6< 59A5>

10%
50V
CERM 2
402

59C3> 53A6< 32C6<> 31C7< 30D4<>

1%
1/16W
MF
402 2

C225
0.001UF

VPP

R139
10K

20%
10V
CERM 2
402

SM

+3V_MAIN
4

C123
0.1UF

+3V_MAIN

XW49

30C5<> 31B7< 32B6<> 54D7< 59A5>

PCI_FRAME_L

+3V_MAIN

30D4<

5%
1/16W
MF
402

30C5<> 31B7< 32B6<> 54D7<

AR8

J10

5%
1/16W
MF
402

ROM_OE_L

AK16

PCI_AD<0> 30C2< 31C7< 32C6<> 53A6< 59C3>


PCI_AD<1> 30C2< 31C7< 32C6<> 53A6<
PCI_AD<2> 30C2< 31C7< 32C6<> 53A6<
PCI_AD<3> 30C2< 31C7< 32C6<> 53A6<
PCI_AD<4> 30C2< 31C7< 32C6<> 53A6< 59C3>
PCI_AD<5> 30C2< 31C7< 32C6<> 53A6<
PCI_AD<6> 30C2< 31C7< 32C6<> 53A6< 59C3>
PCI_AD<7> 30C2< 31C7< 32C6<> 53A6<
PCI_AD<8> 30C2< 31C7< 32C6<> 53A6<
PCI_AD<9> 30C2< 31C7< 32C6<> 53A6< 59C3>
PCI_AD<10> 30C2< 31C7< 32C6<> 53A6<
PCI_AD<11> 30B2< 31C7< 32C6<> 53A6< 59C3>
PCI_AD<12> 30B2< 31C7< 32C6<> 53A6<
PCI_AD<13> 30B2< 31C7< 32C6<> 53A6< 59C3>
PCI_AD<14> 30B2< 31C7< 32C6<> 53A6<
PCI_AD<15> 30B2< 31C7< 32C6<> 53A6< 59B3>
PCI_AD<16> 30B2< 31C7< 32C6<> 53A6< 59B3>
PCI_AD<17> 30B2< 31C6< 32C6<> 53A6<
PCI_AD<18> 30B2< 31C7< 32C6<> 53A6< 59B3>
PCI_AD<19> 30B2< 31C6< 32C6<> 53A6<
PCI_AD<20> 30B2< 31C6< 32C6<> 53A6< 59B3>
PCI_AD<21> 31C7< 32C6<> 53A6<
PCI_AD<22> 31C6< 32C6<> 53A6< 59B3>
PCI_AD<23> 31C7< 32C6<> 53A6<
PCI_AD<24> 30C1<> 31B6< 32C6<> 53A6< 59B3>
PCI_AD<25> 30C1<> 31B7< 32C6<> 53A6<
PCI_AD<26> 30C1<> 31B6< 32B6<> 53A6< 59B3>
PCI_AD<27> 30C1<> 31B7< 32B7<> 53A6<
PCI_AD<28> 30C1<> 31B6< 32B6<> 53A6<
PCI_AD<29> 30C1<> 31B7< 32B6<> 53A6<
PCI_AD<30> 30C1<> 31B6< 32B6<> 53A6< 59B3>
PCI_AD<31> 30C1<> 31B7< 32B6<> 53A6<

AM10

5%
1/16W
SM1

RP69
4.7K
6

VDD15A_6
(PLL4)

PCIAD_0
PCIAD_1
PCIAD_2
PCIAD_3
PCI_GNT_0
U25
PCIAD_4
PCI_GNT_1 INTREPID
PCIAD_5
BGA
PCI_GNT_2
(7 OF 9)
PCIAD_6
PCI_CLK0
PCIAD_7
PCI_CLK1
PCIAD_8
PCI/ROM
PCI_CLK2
PCIAD_9
INTERFACE
PCIAD_10
PCI_CLK_OUT
PCI_CLK_IN
PCIAD_11
PCIAD_12
SEE_TABLE
PCI_PAR
(ON PAGE 12) PCIAD_13
PCI_FRAME
PCIAD_14
PCI_TRDY
PCIAD_15
PCI_IRDY
PCIAD_16
PCI_STOP
PCIAD_17
PCI_DEVSEL
PCIAD_18
PCI_CBE_0
PCIAD_19
PCI_CBE_1
PCIAD_20
PCI_CBE_2
PCIAD_21
PCI_CBE_3
PCIAD_22
PCIAD_23
ROM_OVRLY_EN
PCIAD_24
ROM_CS
PCIAD_25
ROM_OE
PCIAD_26
ROM_WE
PCIAD_27
PCIAD_28
PCIAD_29
PCIAD_30
PCIAD_31
(PLL4)
VSSA_6
PCI_REQ_0
PCI_REQ_1
PCI_REQ_2

5%
1/16W
SM1

5%
1/16W
SM1

RP63
10K

AM18

53A6< 32B6<>

PCI PULL-UPS

+3V_MAIN

AT18

59A5> 53A6< 32B6<> 31B7<


53A6< 32B6<> 31B7<

NO_TEST

59C7> 31B4<> 30B4<

PCI_CBE<0>
PCI_CBE<1>
31B7< PCI_CBE<2>
31B7< PCI_CBE<3>

AH18

AR14

54A7< 30A7< 16D7<

PLACE ALL SERPENTINES ON INTERNAL LAYER


ALLOWS ADJUSTING FEEDBACK CLOCK FROM MATCHED (0 NS)
TO +10" (1.7 NS) IN 2" (0.35 NS) INCREMENTS

AN17

AT14

54C7< PCI_FB_PLUS6

(0.7 ns)

AN18

PCI_PAR
59A5> 53A6< 32B6<> 31B7< 30B7< PCI_FRAME_L
59A5> 54D7< 32B6<> 31B7< 30B7< PCI_TRDY_L
54D7< 32B6<> 31B7< 30B7< PCI_IRDY_L
59A5> 54D7< 32B6<> 31B7< 30B7< PCI_STOP_L
59A5> 54D7< 32B6<> 31B7< 30B7< PCI_DEVSEL_L
59A5> 54D7< 32B6<> 31B7<

R255
0

(1 ns)

AT16

AT17

AR18

Adds 6"

PCI_SLOTB_GNT_L
PCI_SLOTC_GNT_L
30B5< PCI_SLOTD_GNT_L

AR16

CLK33M_PCI_SLOTB_UF
CLK33M_PCI_SLOTC_UF
CLK33M_PCI_SLOTD_UF
54D7< INT_PCI_FB_OUT
54C7< INT_PCI_FB_IN

54D7<
54D7<
54D7<

AR17

59A5> 31C2<> 30B5<


30B5<

TEST WITH 220-OHM

(0.35 ns)

32B6>

TEST WITH 220-OHM

30C4<>

J11

PCI_SLOTB_REQ_L
PCI_SLOTC_REQ_L
30B7< PCI_SLOTD_REQ_L

59A5> 31C3<> 30B7<


30B7<

5%
1/16W
MF
402

NOSTUFF

NO_TEST

54C7<

CLK33M_PCI_SLOTD

PCI_FBO_PLUS2

PCI_FB_PLUS4

54D7<

INT_PLL4_GND

R219
22 2
1

D
54A7< 32A6<

+1_5V_INTREPID_PLL
1

59A5> 54D7< 31C2<>

52D3> 28D6<> 16D6< 9D4<

DRAWING

<XR_PAGE_TITLE>

+3V_MAIN
+3V_MAIN
1

NOSTUFF
1

N20P80%
10V
2 Y5V
805

NOSTUFF
1

R949
10K

NOSTUFF
C260
10UF

C250
10UF

N20P80%
10V
2 Y5V
805

10%
16V
2 CERM
402

C259
0.01UF

C249
0.1UF

20%
10V
2 CERM
402

R950
10K

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

+3V_MAIN
59A5> 44C4<> 32A8< 30B2< 17C8<

R948
0 2
1

MAIN_RESET_L

PCI_AD<0>
53A6< 32C6<> 30D4<> 30C2< PCI_AD<1>
53A6< 32C6<> 30D4<> 30C2< PCI_AD<2>
53A6< 32C6<> 30D4<> 30C2< PCI_AD<3>
59C3> 53A6< 32C6<> 30D4<> 30C2< PCI_AD<4>
53A6< 32C6<> 30D4<> 30C2< PCI_AD<5>
59C3> 53A6< 32C6<> 30D4<> 30C2< PCI_AD<6>
53A6< 32C6<> 30D4<> 30C2< PCI_AD<7>
53A6< 32C6<> 30D4<> 30C2< PCI_AD<8>
59C3> 53A6< 32C6<> 30D4<> 30C2< PCI_AD<9>
53A6< 32C6<> 30C4<> 30C2< PCI_AD<10>
59C3> 53A6< 32C6<> 30C4<> 30B2< PCI_AD<11>
53A6< 32C6<> 30C4<> 30B2< PCI_AD<12>
59C3> 53A6< 32C6<> 30C4<> 30B2< PCI_AD<13>
53A6< 32C6<> 30C4<> 30B2< PCI_AD<14>
59B3> 53A6< 32C6<> 30C4<> 30B2< PCI_AD<15>
59B3> 53A6< 32C6<> 30C4<> 30B2< PCI_AD<16>
59B3> 54C7< 31C3<> PCIT_AD<17>
59B3> 53A6< 32C6<> 30C4<> 30B2< PCI_AD<18>
59B3> 54C7< 31C3<> PCIT_AD<19>
53A6< 32C6<> 30C4<> PCI_AD<23>
53A6< 32C6<> 30C4<> PCI_AD<21>
54C7< 31C2<> PCIT_AD<22>
54C7< 31C2<> PCIT_AD<20>
53A6< 32B7<> 30C4<> 30C1<> PCI_AD<27>
53A6< 32C6<> 30C4<> 30C1<> PCI_AD<25>
54C7< 31C2<> PCIT_AD<26>
54C7< 31C2<> PCIT_AD<24>
59B3> 54C7< 31C2<> PCIT_AD<28>
54C7< 31C2<> PCIT_AD<30>
53A6< 32B6<> 30C4<> 30C1<> PCI_AD<31>
53A6< 32B6<> 30C4<> 30C1<> PCI_AD<29>
59A5> 54D7< 32B6<> 30C5<> PCI_PAR
59A5> 53A6< 32B6<> 30C5<> 30B7< PCI_FRAME_L
59A5> 54D7< 32B6<> 30C5<> 30B7< PCI_TRDY_L
54D7< 32B6<> 30C5<> 30B7< PCI_IRDY_L
59A5> 54D7< 32B6<> 30C5<> 30B7< PCI_STOP_L
59A5> 54D7< 32B6<> 30C5<> 30B7< PCI_DEVSEL_L
53A6< 32B6<> 30C5<> PCI_CBE<1>
59A5> 53A6< 32B6<> 30C5<> PCI_CBE<0>
53A6< 32B6<> 30C5<> PCI_CBE<2>
53A6< 32B6<> 30C5<> PCI_CBE<3>
NC_PCIR0
NC_PCIR1

59C3> 53A6< 32C6<> 30D4<> 30C2<

2
3
4

RP77
33
5%
1/16W
SM1

1
2
3
4

7
6
5
8

RP75
33
5%
1/16W
SM1

7
6
5
8

RP73
33

5%
1/16W
SM1

4
1
2
3
4

RP72
33

5%
1/16W
SM1

3
4

RP59
33
5%
1/16W
SM1

3
4

RP58
33
5%
1/16W
SM1

3
4

RP56
33
5%
1/16W
SM1

1
2
3
4

3
4

5%
1/16W
SM1

3
4

5%
1/16W
SM1

NO_TEST

NO_TEST

6
5

7
6
5

7
6
5

7
6
5
8

RP67
33
5%
1/16W
SM1

7
6
5
8

1
2

RP61
33

1
2

RP54
33

1
2

1
2

1
2

5
8

1
2

RP64
33

5%
1/16W
SM1

6
5

J25
EDGE-SOCKET-UP

MAIN_RESET_L_PU

F-RT-SM-4MM

5%
1/16W
MF
402

PLACE RPS NEAR WIRELESS CONNECTOR


PCIT_AD<0> 31B2<> 54C7<
NO_TEST PCIT_AD<1>
31B3<> 54C7< 59C3>
NO_TEST PCIT_AD<2>
31B2<> 54C7< 59C3>
NO_TEST PCIT_AD<3>
31B3<> 54C7< 59C3>
PCIT_AD<4> 31B2<> 54C7<
NO_TEST PCIT_AD<5>
31B3<> 54C7< 59C3>
NO_TEST PCIT_AD<6>
31B2<> 54C7<
PCIT_AD<7> 31B3<> 54C7< 59C3>
PCIT_AD<8> 31B3<> 54C7< 59C3>
NO_TEST PCIT_AD<9>
31B2<> 54C7<
NO_TEST PCIT_AD<10>
31B3<> 54C7< 59C3>
NO_TEST PCIT_AD<11>
31B2<> 54C7<
PCIT_AD<12> 31B3<> 54C7< 59C3>
NO_TEST PCIT_AD<13>
31B2<> 54C7<
NO_TEST PCIT_AD<14>
31C3<> 54C7< 59B3>
NO_TEST PCIT_AD<15>
31C2<> 54C7<
PCIT_AD<16> 31C2<> 54C7<
PCI_AD<17> 30B2< 30C4<> 32C6<> 53A6<
PCIT_AD<18> 31C2<> 54C7<
PCI_AD<19> 30B2< 30C4<> 32C6<> 53A6<
PCIT_AD<23> 31C3<> 54C7< 59B3>
PCIT_AD<21> 31C3<> 54C7< 59B3>
PCI_AD<22> 30C4<> 32C6<> 53A6< 59B3>
PCI_AD<20> 30B2< 30C4<> 32C6<> 53A6< 59B3>
PCIT_AD<27> 31C3<> 54C7< 59B3>
PCIT_AD<25> 31C3<> 54C7< 59B3>
PCI_AD<26> 30C1<> 30C4<> 32B6<> 53A6< 59B3>
PCI_AD<24> 30C1<> 30C4<> 32C6<> 53A6< 59B3>
PCI_AD<28> 30C1<> 30C4<> 32B6<> 53A6<
PCI_AD<30> 30C1<> 30C4<> 32B6<> 53A6< 59B3>
NO_TEST PCIT_AD<31>
31C3<> 54C7< 59B3>
NO_TEST PCIT_AD<29>
31C3<> 54C7< 59B3>
PCIT_PAR 31C2<> 54C7<
NO_TEST PCIT_FRAME_L 31C2<> 54C7<
NO_TEST PCIT_TRDY_L 31C2<> 54C7<
NO_TEST PCIT_IRDY_L 31C3<> 54C7< 59B5>
PCIT_STOP_L 31C2<> 54C7<
NO_TEST PCIT_DEVSEL_L 31C2<> 54C7<
NO_TEST PCIT_CBE<1> 31C3<> 54C7< 59A5>
NO_TEST PCIT_CBE<0> 31B2<> 54C7<
PCIT_CBE<2> 31C3<> 54C7< 59A5>
NO_TEST PCIT_CBE<3> 31C3<> 54C7< 59A5>
NO_TEST
NC_PCITR0
NO_TEST
NC_PCITR1

59A5> 30D5<>

TOP_CONTACTS

RF_DISABLE_L
30B7< PCI_SLOTB_REQ_L

59B3> 54C7< 31B6<


59B3> 54C7< 31B6<
59B3> 54C7< 31B6<
59B3> 54C7< 31B6<

PCIT_AD<31>
PCIT_AD<29>
PCIT_AD<27>
PCIT_AD<25>

59A5> 54C7< 31B6<

PCIT_CBE<3>

59B3> 54C7< 31C6<

PCIT_AD<23>
PCIT_AD<21>
PCIT_AD<19>

59B3> 54C7< 31C6<


59B3> 54C7< 31C7<
59B3> 54C7< 31C7<

PCIT_AD<17>

59A5> 54C7< 31B6<

PCIT_CBE<2>
PCIT_IRDY_L

59B5> 54C7< 31B6<

59B5>

R2931
10K

59A5> 54C7< 31B6<


59B3> 54C7< 31C6<

1%
1/16W
MF
402 2

59C3> 54C7< 31C6<


59C3> 54C7< 31C6<
59B7> 30B6< 30B2<

PCIT_CBE<1>
PCIT_AD<14>
PCIT_AD<12>
PCIT_AD<10>

ROM_RW_L
59C3> 54C7< 31C6<

PCIT_AD<8>
PCIT_AD<7>

59C3> 54C7< 31C6<

PCIT_AD<5>

59C3> 54C7< 31C6<

59D5> 30B2<

ROM_ONBOARD_CS_L

59C3> 54C7< 31C6<

59C7> 30C6< 30B4<

ROM_CS_L

59C3> 54C7< 31C6<

10

11

12

13

14

15

RF_CLKRUN_L

CLK33M_PCI_SLOTB 30D7< 54D7<


PCI_SLOTB_GNT_L 30B5< 30D5<>
PMU_PME_LL 5%

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

PMU_PME_L 28B5<>

402

PCIT_AD<22> 31C7< 54C7<


PCIT_AD<20> 31C7< 54C7<
PCIT_PAR 31B6< 54C7<
PCIT_AD<18> 31C6< 54C7<
PCIT_AD<16> 31C6< 54C7<

32A8< 44B2<> 59A5>

R285
22

5%
1/16W
MF
402

PCIT_FRAME_L 31B6< 54C7<


PCIT_TRDY_L 31B6< 54C7<
PCIT_STOP_L 31B6< 54C7<
PCIT_DEVSEL_L 31B6< 54C7<
PCIT_AD<15>
PCIT_AD<13>
PCIT_AD<11>

31C6< 54C7<
31C6< 54C7<
31C6< 54C7<

PCIT_AD<9> 31C6< 54C7<


PCIT_CBE<0> 31B6< 54C7<
ROM_OE_L 30B2< 30C6< 59C7>
PCIT_AD<6> 31C6< 54C7<

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

NO_TEST

NO_TEST

77

78

NO_TEST

NO_TEST

79

80

NO_TEST

81

82

NO_TEST

NO_TEST

83

84

NO_TEST

NO_TEST

85

86

NO_TEST

NO_TEST

87

88

NO_TEST

NO_TEST

89

90

NO_TEST

NO_TEST

91

92

NO_TEST

NO_TEST

93

94

NO_TEST

NO_TEST

95

96

NO_TEST

NO_TEST

97

98

NO_TEST

NO_TEST

99

100

NO_TEST

PCIT_AD<1>

59A5>
59A5>

33SLOTB_INT_L 28B7<> 59A5>


PCIT_AD<30> 31B7< 54C7<
PCIT_AD<28> 31B7< 54C7< 59B3>
PCIT_AD<26> 31B7< 54C7<
PCIT_AD<24> 31B7< 54C7<
WL_PCI_IDSEL 59A5>

16

17

R951NOSTUFF
0 2 MF

1
1/16W

59

PCIT_AD<3>

NC_WL<1>
NC_WL<3>
NC_WL<5>
NC_WL<7>
NC_WL<9>
NC_WL<11>
NC_WL<13>
NC_WL<15>
NC_WL<17>
NC_WL<19>
NC_WL<21>
NC_WL<23>

BOT_CONTACTS

PCIT_AD<4>
PCIT_AD<2>
PCIT_AD<0>

31C6< 54C7<
31C6< 54C7< 59C3>
31C6< 54C7<

NC_USB_M
NC_USB_P
NC_WL<2>
NC_WL<4>
NC_WL<6>
NC_WL<8>
NC_WL<10>
NC_WL<12>
NC_WL<14>
NC_WL<16>
NC_WL<18>
NC_WL<20>

(516S0046)
WIRELESS CARD MOUNTING HARDWARE SUPPORT
PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

815-7245

WIRELESS CARD GUIDE,J25

J251

452-0411

NUT,HEX,M2 X 1.5H, J25

J252,J253

452-0412

SCREW,M2 X 0.4 X 6.0 L,J25

J254,J255

CRITICAL

BOM OPTION

WIRELESS PCI

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:29:20 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569
A
31 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

+3V_MAIN
USB2

+3V_MAIN
0.1UF

0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

USB2
1 C523

USB2
1 C541

USB2
1 C548

USB2
1 C555

0.1UF

20%
2 10V
CERM
402

0.1UF

USB2
1 C573

NOSTUFF
1 C574

USB2
1 C531

10UF

10UF

10UF

10UF

N20P80%
2 10V
Y5V
805

N20P80%
2 10V
Y5V
805

N20P80%
2 10V
Y5V
805

N20P80%
2 10V
Y5V
805

53A6< 31B7< 30C4<> 30C1<>

P4
N4
M3
N3
M1
L2
L1
K2
L3
K1
K3
J2
J1
F2
E3
E1
D3
D1
D2
C2
C1
B4
A4
B5

PCI_AD<27>

C4

PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>

A5

PCI_CBE<0>
PCI_CBE<1>
PCI_CBE<2>
PCI_CBE<3>

M2

PCI_PAR
59A5> 53A6< 31B7< 30C5<> 30B7< PCI_FRAME_L
54D7< 31B7< 30C5<> 30B7< PCI_IRDY_L
59A5> 54D7< 31B7< 30C5<> 30B7< PCI_TRDY_L
59A5> 54D7< 31B7< 30C5<> 30B7< PCI_STOP_L
USB2_IDSEL
59A5> 54D7< 31B7< 30C5<> 30B7< PCI_DEVSEL_L
30D5<> 30B7< PCI_SLOTD_REQ_L
30D5<> 30B5< PCI_SLOTD_GNT_L
PCI_SLOTD_PERR_L
33PCI_SLOTD_SERR_L
28B8< 28B5<> INT_EXTINT17_PU

J4

53A6< 31B6< 30C4<> 30C1<>


53A6< 31B7< 30C4<> 30C1<>
59B3> 53A6< 31B6< 30C4<> 30C1<>
53A6< 31B7< 30C4<> 30C1<>
59A5> 53A6< 31B7< 30C5<>
53A6< 31B7< 30C5<>
53A6< 31B7< 30C5<>
53A6< 31B7< 30C5<>

+3V_MAIN

C5
B6
A6

J3
F1
C3

59A5> 54D7< 31B7< 30C5<>

USB2
1

R127
4.7K

5%
1/16W
MF
402 2

USB2
1

USB2

R128
4.7K

R494
22 2
1

5%
1/16W
MF
402 2

5%
1/16W
MF
402

F3
F4
G1
G3
B3
G2
C6
D6
H2
OD

H1

OD

C7

OD
OD

54A7< 30D7<
USB2

44B2<> 31C2< 28B5<>


59A5>

28B5<>

PMU_PME_L

CLK33M_PCI_SLOTD

IO_RESET_L
USB2_CRUN_L
USB2_PME_L

OD

NC_USB2_SMI_L

OD

N6
D9
C9

5%
1/16W
402

28A8< USB2_CRUN_L_INT

A7

B8

59A7> 44D3< 44B8<> 35B8<

R484
0 2

B7

A8

L6

R373 NOSTUFF
0 2

L7

RSDM1
DM1
DP1
RSDP1

M14

56B3> USB2_RSDAM

M13

USB2_DAN_F
USB2_DAP_F
56B3> USB2_RSDAP

RSDM2
DM2
DP2
RSDP2

K14

56B3> USB2_RSDBM

K12

J12

USB2_DBN_F
USB2_DBP_F
56B3> USB2_RSDBP

RSDM3
DM3
DP3
RSDP3

H11

56B3> USB2_RSDCM

G11

USB2_DCN_F
USB2_DCP_F
56B3> USB2_RSDCP

RSDM4
DM4
DP4
RSDP4

F12

E14

NC_USB2_RSDEP

RSDM5
DM5
DP5
RSDP5

E13

NC_USB2_RSDFM

N10

R129
100

1%
1/16W
MF
2 402

L14
K13

1
USB2

R464
35.7 2

J14

CRITICAL

G13
G14

USB2_DAN_F

33B7< 56B3>

R465
1

USB2_DAP_F

33B7< 56B3>

R466
35.7 2
1

USB2_DBN_F

33C7< 56B3>

R467
35.7 2
1

USB2_DBP_F

33C7< 56B3>

USB2_DCN_F

33D7< 56B3>

USB2_DCP_F

33D7< 56B3>

2
USB2

USB2

USB2

R468
35.7 2

R469
1

35.7

56B3> RREF

USB2

NC_USB2_RSDEM

OVERLAP STUFFING OF 35.7OHMS HERE WITH 0OHMS ON SH31 TO MINIMIZE STUBS

F14
E12

+3V_MAIN

D14
C13
C14

P11

NC_USB2_RSDFP
USB2_RREF

USB2
1

USB2

R476
9.09K2
1

TIED TO BALL N11

1%
1/16W
MF
402

PAR
FRAME
IRDY
TRDY
STOP
IDSEL
DEVSEL
REQ
GNT
PERR
SERR
INTA
INTB
INTC
PCLK
VBBRST
CRUN
PME
VCCRST
SMI

OCI1
OCI2
OCI3
OCI4
OCI5

B12

PPON1
PPON2
PPON3
PPON4
PPON5

C12

R480
4.7K

5%
1/16W
MF
2 402

USB_PWR_FLT*

USB_PWR_FLT*

28B3< 28C1< 33A7>

B11
B10
A10

U_USB_PWR_FLT*

B9

A11
C11
C10
A9

+3V_MAIN
NC_USB2_PPON1
NC_USB2_PPON2
NC_USB2_PPON3
NC_USB2_PPON4
NC_USB2_PPON5

NC1
NC2

P6
M6

USB2_NC1
USB2_NC2

NTEST1

M8

NC_USB2_NTEST1

STARTUP & RESTARTS

SMC

M7

NC_USB2_SMC

STARTUP, RESTARTS, WAKEUP

TEB
AMC

N7
P7

NC_USB2_TEB
NC_USB2_AMC

TEST

L8

NC_USB2_TEST

M10

NC_USB2_NANDTEST
NC_USB2_SRCLK
NC_USB2_SRDTA
NC_USB2_SRMOD

USB2
1

R470
2.2K

5%
1/16W
MF
2 402

USB2
1

R490
2.2K

5%
1/16W
MF
2 402

LEGC

AVSS(R)

NANDTEST
SRCLK
SRDTA
SRMOD

D8

F11

J11

G4

D12

H12

L12

M11

B13

N13

N2

B2

A2

B14

H14

N14

N1

P10

VSS

R1029

56B3> USB2_XT1
56B3> USB2_XT2

L9

5%
2 50V
CERM
402

USB2
1

35.7

FBGA

+3V_MAIN
1

P8

CBE0
CBE1
CBE2
CBE3

B1

D7

U11
NEC_UPD720101_USB2

R78
1K

XT1/SCLK
XT2

C114
10PF

USB2

5%
1/16W
402

1%
1/16W
MF
402 2

H4

G12

D13

F13

VDD

N12

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

USB2
1

M9
N9
P9

USB2 CONTROLLER

AVSS

NOTICE OF PROPRIETARY PROPERTY

M12

NOSTUFF
1 C517

N5

P13

20%
2 10V
CERM
402

P5

USB2

N11

20%
2 10V
CERM
402

20%
2 10V
CERM
402

0.1UF

M5

53A6< 31C7< 30D4<> 30C2<


53A6< 31C7< 30D4<> 30C2<

8X4.5MM-SM
USB2

5%
50V
CERM 2
402

AVDD

0.1UF

PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
53A6< 31C7< 30D4<> 30C2< PCI_AD<3>
59C3> 53A6< 31C7< 30D4<> 30C2< PCI_AD<4>
53A6< 31C7< 30D4<> 30C2< PCI_AD<5>
59C3> 53A6< 31C7< 30D4<> 30C2< PCI_AD<6>
53A6< 31C7< 30D4<> 30C2< PCI_AD<7>
53A6< 31C7< 30D4<> 30C2< PCI_AD<8>
59C3> 53A6< 31C7< 30D4<> 30C2< PCI_AD<9>
53A6< 31C7< 30C4<> 30C2< PCI_AD<10>
59C3> 53A6< 31C7< 30C4<> 30B2< PCI_AD<11>
53A6< 31C7< 30C4<> 30B2< PCI_AD<12>
59C3> 53A6< 31C7< 30C4<> 30B2< PCI_AD<13>
53A6< 31C7< 30C4<> 30B2< PCI_AD<14>
59B3> 53A6< 31C7< 30C4<> 30B2< PCI_AD<15>
59B3> 53A6< 31C7< 30C4<> 30B2< PCI_AD<16>
53A6< 31C6< 30C4<> 30B2< PCI_AD<17>
59B3> 53A6< 31C7< 30C4<> 30B2< PCI_AD<18>
53A6< 31C6< 30C4<> 30B2< PCI_AD<19>
59B3> 53A6< 31C6< 30C4<> 30B2< PCI_AD<20>
53A6< 31C7< 30C4<> PCI_AD<21>
59B3> 53A6< 31C6< 30C4<> PCI_AD<22>
53A6< 31C7< 30C4<> PCI_AD<23>
59B3> 53A6< 31B6< 30C4<> 30C1<> PCI_AD<24>
53A6< 31B7< 30C4<> 30C1<> PCI_AD<25>
59B3> 53A6< 31B6< 30C4<> 30C1<> PCI_AD<26>
59C3> 53A6< 31C7< 30D4<> 30C2<

H13

USB2
1 C530

J13

USB2
1 C570

L13

USB2
1 C515

N8

USB2
1 C536

E2

20%
2 10V
CERM
402

Y7
30.0000M
1
2 CRITICAL
USB2

0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C511
10UF

N20P80%
10V
2 Y5V
805

C77
10PF
A3

0.1UF

20%
2 10V
CERM
402

0.1UF

C529
0.1UF

20%
10V
2 CERM
402

USB2
1 C537

20%
2 10V
CERM
402

0.1UF

C526
0.1UF

NEC_XT2_B

1%
1/16W
MF
402

USB2
1

20%
2 10V
CERM
402

A12

0.1UF

USB2
1

20%
10V
2 CERM
402

A13

0.1UF

USB2
1 C516

USB2
1

P12

USB2
1 C546

SM

P3

USB2
1 C559

0.1UF

20%
2 10V
CERM
402

NOSTUFF

R89
100K 2
1

52A3> NEC_AVDD

P2

0.1UF

20%
2 10V
CERM
402

C8

0.1UF

L58
100-OHM-EMI

USB2
1 C547

M4

0.1UF

USB2
1 C527

H3

USB2
1 C522

VDD_PCI

USB2
1 C519

LAST_MODIFIED=Mon Oct 27 12:30:14 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

4.7K
5%
1/16W
MF
2 402
D3_HOT

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

D3_COLD

R1028
44C4<> 31D4< 30B2< 17C8<
59A5>

MAIN_RESET_L

SIZE

USB2_VCCRST

APPLE COMPUTER INC.

5%
1/16W
MF
402

D
SCALE

DRAWING NUMBER

REV.

051-6569
A
32 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

NOSTUFF

R1007

USB1

58B5> 28B2<

USB_DCN_F

USB2_DCN_F

58B5> 28B2<

USB_DCP_F

TH-1
7

USBT_DCN_F

SYM_VER-2

L100

59B5> 52A3> 33C3<> 33B3<> 33A4<>

165-OHM
SM

USB_PORT_PWR
USB_DCN_CON
USB_DCP_CON

1
2

59C5> 56A3>
59C5> 56A3>

USB PORT 3

3
4

USB_GND

USB1

R43
0

SYM_VER-2

6
2

56A3>

USBT_DCP_F

R1006

5%
1/16W
MF
402

R454
15K

R455
15K

USB1
1

5%
1/16W
MF
402
NOSTUFF

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
402

1
1

R461
0 2
1

USB2_DCP_F

J7
F-RT-USB-NMP1

5%
1/16W
MF
402

56A3>

USB2

56B3> 32C1<>

R460
0 2
5%
1/16W
MF
402

5%
1/16W
MF
402

USB2

56B3> 32C1<>

R44
0

C2
10UF

USB1

C403
33PF

5%
50V
2 CERM
402

(514-0048)

2 N20P80%
10V
Y5V
805

C404
33PF

5%
50V
2 CERM
402

C405
0.01UF

10%
16V
2 CERM
402

C397
0.01UF

2 10%
16V
CERM
402
ALT
CHASSIS

C413
0.01UF

ALT
CHASSIS

10%
2 16V
CERM
402

PLACE UNDER
USB CONNECTOR
ALT
CHASSIS

NOSTUFF

R1008

USB1

58B5> 28B2<

USB_DBN_F

USB2_DBN_F

58B5> 28B2<

USB_DBP_F

56A3>

USB2_DBP_F

TH-1
7

USBT_DBN_F

59C5>

USB_PORT_PWR
56A3> USB_DAN_CON
56A3> USB_DAP_CON

R45
0

SYM_VER-2

56A3>

5%
1/16W
MF
402

NOSTUFF

USBT_DBP_F

R1009
1
1

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

R453
15K

USB1

5%
1/16W
MF
402

R452
15K

C1
10UF

USB1

C387
33PF

5%
50V
2 CERM
402

5%
50V
2 CERM
402

10%
16V
2 CERM
402

C433
0.01UF

ALT
CHASSIS

10%
16V
2 CERM
402

25B3<>
25C3<
33B4<
33C2<
33C4<
33D4<
36A7<>
36B2<
36B6<>
36B6<
36C1<>
36C1<
52C4

PLACE UNDER
USB CONNECTOR
ALT
CHASSIS

J6
F-RT-USB-NMP1

5%
1/16W
MF
402

5%
1/16W
402
MF

TH-1
7

SYM_VER-2

L102
165-OHM

R456
0 2
1

56B3>

SM

USBT_DAN_F

59B5>
52A3> 33D3<>
33C3<> 33A4<> USB_PORT_PWR
59C5> 56A3> USB_DBN_CON

USB_DBP_CON

59C5> 56A3>

5%
1/16W
MF
402

2 10%
16V
CERM
402

R1010

USB2

C386
0.01UF

C380
0.01UF

USB1

NOSTUFF

R48
0

(514-0048)

N20P80%
2 10V
Y5V
805

C383
33PF

ALT
CHASSIS

USB2_DAN_F

USB PORT 2

6
2

PLACE NEAR CONNECTOR

56B3> 32C1<>

5%
1/16W
MF
402

58B5> 28B2<

USB_GND

USB1

R459
0 2

USB_DAN_F

SYM_VER-2

59B5>
52A3> 33D3<>
33B3<> 33A4<>
59C5>

USB2

56B3> 32C1<>

J4
F-RT-USB-NMP1

165-OHM
SM

5%
1/16W
MF
402

L101

R458
0 2
1
5%
1/16W
MF
402

1
2

5%
1/16W
MF
402

USB2

56B3> 32C1<>

R46
0

USB PORT 1

4
1

USB1

USB_GND

SYM_VER-2

58B5> 28B2<

USB_DAP_F

USB2

56B3> 32C1<>

R47
0

6
2

56B3>

R1011
1
1

R450
15K

5%
1/16W
MF
2 402

5%
1/16W
MF
402

USB1

5%
1/16W
MF
402

R451
15K

R457
0 2
1

USB2_DAP_F

USBT_DAP_F

5%
1/16W
MF
402

5%
1/16W
MF
2 402

5%
50V
2 CERM
402

NOSTUFF

C389
33PF

5%
50V
2 CERM
402

2 N20P80%
10V
Y5V
805

C398
0.01UF

10%
16V
2 CERM
402

2 10%
16V
CERM
402

ALT
CHASSIS

(514-0048)

C385
0.01UF

THE ABOVE RESISTORS SHARE


THE SAME PIN-2 PAD AND ARE
LOCATED AT THE USB2 CHIP

+5V_MAIN

C391
33PF

C6
10UF

USB1

C417
0.01UF

10%
16V
2 CERM
402

ALT
CHASSIS

PLACE UNDER
USB CONNECTOR

USB_PWR 25B5<>

U3501

ALT
CHASSIS

25C2< 25D3<> 52A3>

L2
FERRITE-4532

TPS2023
SOI
2

IN_0

OUT_0 8

IN_1

OUT_1 7

OUT_2 6
USB_PWR_EN
1

R3501
47

5%
1/16W
MF
2 402

4
1

C3502
0.1UF

EN

OC

GND

59B5> 52A3> 33D3<> 33C3<> 33B3<>

USB_PORT_PWR

SM

NOSTUFF NOSTUFF
1
C7
C5
150UF
150UF

USB_PWR_FLT*
10K PULLUP ON PAGE 28

28B3< 28C1< 32B1<

20%
2 6.3V
POLY
SMD

20%
2 6.3V
POLY
SMD

C396
0.01UF

10%
16V
2 CERM
402

C377
0.01UF

10%
16V
2 CERM
402

C382
0.01UF

10%
16V
2 CERM
402

20%
2 10V
CERM
402

USB CONNS & PWR

USB_GND

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:30:16 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
33 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

D
CLKENET_LINK_TX
57C5> 35C6<

35C8<
57C5>

ENET_PHY_TX_EN

R307
33 2

57C5>

ENET_LINK_TX_EN

57C5>

ENET_LINK_TX_ER

5%
1/16W
MF
402

57C5> 35C6<

ENET_PHY_TX_ER

R303
33 2

H9

57C5>
57C5>
57C5>
57C5>

35C6<> ENET_PHY_TXD<0>
35C6<> ENET_PHY_TXD<1>
35C6<> ENET_PHY_TXD<2>
35C6<> ENET_PHY_TXD<3>

A7

4
3
2
1

RP70
33
1/16W
5%
SM1

6
7
8

ENET_LINK_TXD<0>
ENET_LINK_TXD<1>
57C5> ENET_LINK_TXD<2>
57C5> ENET_LINK_TXD<3>
NC_ENET_LINK_TXD<4>
NC_ENET_LINK_TXD<5>
NC_ENET_LINK_TXD<6>
NC_ENET_LINK_TXD<7>

H10

57C5>
57C5>

E9
D8
A6
B7
G10
D9
E10

57C5> 35C8< CLKENET_LINK_RX


57B5> 35B8<
57B5> 35B8<

57B5> 35C8<
57B5> 35C8<
57B5> 35C8<
57B5> 35B8<

ENET_RX_DV
ENET_RX_ER

D3
E7
D6
B4

2
3
4

RP76
33
1/16W
5%
SM1

7
6
5

ENET_LINK_RXD<4>
ENET_LINK_RXD<5>
ENET_LINK_RXD<6>
ENET_LINK_RXD<7>
CLKENET_LINK_GBE_REF
NC_CLKENET_LINK_GTX

A4
D7
G9
E8
L13
H12

ENET_CRS
57B5> 35B8< ENET_COL
35A8<> ENET_MDIO
35B6< ENET_MDC

E6

JTAG_ASIC_TDI

AK8

35B3< 28C6< JTAG_INTRP_TDO


59D7> 35C4< 8A4<> JTAG_ASIC_TCK

AT5

57B5> 35B8<

C5
B5
B6

AP5

JTAG_ASIC_TMS
JTAG_ASIC_TRST_L
34C1< INT_JTAG_TEI
INT_TST_MONIN_PD

AR5

59D7> 35B4<> 35A2< 8A4<>

34C1<

AN6
AH10
AM7

NC_INT_TST_MONOUT_TP
28C6<

TXD_0
TXD_1
TXD_2
TXD_3
TXD_4
TXD_5
TXD_6
TXD_7

(ON PAGE 12)

MISC

RX_CLK
C4 RX_DV
D2
RX_ER

59C7> 8A4<>

BGA
(4 OF 9)

NO_TEST

AK10

INT_TST_PLLEN_PD

AR6

RXD_0
RXD_1
RXD_2
RXD_3
RXD_4
RXD_5
RXD_6
RXD_7
GBE_REFCLK
GTX_CLK
CRS
COL
MDIO
MDC

TDI
TDO
TCK
TMS
TRSTN
TEI
TST_MONIN
TST_MONOUT
TST_PLLEN

GB ETHERNET

INT_RESET_L

5%
1/16W
MF
402

U5

RINT_RESET_L

PURESET

T2

RINT_PU_RESET_L

L4

57A5> FW_LINK_DATA<0> 1

M4

57A5> FW_LINK_DATA<1> 2
57A5> FW_LINK_DATA<2> 3

PHY_LPS
PHY_CTL0
PHY_CTL1
PHY_LREQ
FWR_PCLK

M1

P7

57A5> FW_LINK_DATA<3> 4
57A5> FW_LINK_DATA<4> 4

N5
K1
K2

57A5> FW_LINK_DATA<5> 3

L2

57A5> FW_LINK_DATA<6> 2
57A5> FW_LINK_DATA<7> 1

N4

M2

U14

FWR_LCLK
FW_LINKON N2
FW_PINT N1

FW_SCLK

INT_PU_RESET_L 15B3<

NO_TEST

RP65
22

NO_TEST

5%
1/16W
SM1

NO_TEST

FW_D<0> 36C8<
FW_D<1> 36C8<
FW_D<2> 36B8<
FW_D<3> 36B8<
FW_D<4> 36B8<
FW_D<5> 36B8<
FW_D<6> 36B8<
FW_D<7> 36B8<

R269
22 2

FW_CNTL0

NO_TEST

5%
1/16W
SM1

NO_TEST

NO_TEST

57A5>
57A5>
57A5>

34B5<>

36C8< 57A5>

R709
22 2
1

FW_CNTL1
FW_LREQ

57A5>

+3V_MAIN

36C8< 57A5>

36C8< 57A5>

34B5<>

IICCLK_1 AK5
IICDATA_1 AM3

INT_I2C_CLK1
INT_I2C_DATA1

RP119
4.7K 5
4

INT_I2C_CLK0R

5%
1/16W
SM1

36C8< 57A5>
34B5<>

5%
1/16W
MF
402

RP119
4.7K 7

INT_I2C_DATA0R

34A3<>

34A3<>

INT_I2C_CLK0

5%
1/16W
SM1

RP101
4.7K 8

INT_I2C_CLK1

5%
1/16W
SM1

MF

34C1<
34C1<

R684
10K 2

57A5>
57A5>

402 5%
MF
1/16W

R702
22 2
1

R257
0 2
1
INT_I2C_CLK0R
INT_I2C_DATA0R

1%
1/16W
MF
402

INT_V2

IICCLK_0 AN2
IICDATA_0 AN1

FW_PINT

57A5>
57A5>

1%
1/16W
MF
2 402

TEST

1%
1/16W
MF
402

R576
1K 2
1

INT_TST_MONIN_PD

R575
1K 2

I2C 3.3V PULL-UPS

402 5%
MF
1/16W

CLKFW_LINK_LCLK
FW_C_LKON 28B6< 36B5<>
1
FW_PINT 34C1<
R673
1K

1%
1/16W
MF
402

INT_JTAG_TEI

44C2<>
34B7<

RP112
22

57A5> FW_LINK_CNTL<1>
57A5> FW_LINK_LREQ

L1

T7

34B7<

R275
47 2
1

FW_LPS 36C8<
57A5> FW_LINK_CNTL<0>

P5

35B8< 41A7< 43C7< 44D2<>

5%
1/16W
MF
402

RESET

PHY_DATA0
PHY_DATA1
PHY_DATA2
PHY_DATA3
PHY_DATA4
PHY_DATA5
PHY_DATA6
PHY_DATA7
FIREWIRE

TEST PULL-DOWNS

R707
47 2

SEE_TABLE

J12

ENET_LINK_RXD<0>
ENET_LINK_RXD<1>
ENET_LINK_RXD<2>
ENET_LINK_RXD<3>

59D7> 28C6< 8A4<>

U25
INTREPID

TX_CLK
TX_EN
A5
TX_ER

5%
1/16W
MF
402

INT_I2C_DATA1

RP101
4.7K 6

5%
1/16W
SM1

14A6<> 15A6<

5%
402
1/16W

INT_V2
1

R254
0 2

MF

INT_I2C_DATA0

14A6<> 15A6<

5%
402
1/16W
INT_V1

NOSTUFF

R714
1K

1%
1/16W
MF
2 402

C92
47PF

59A7> 39B1<> 29C7<> 28D1< 28A3<>

INT_I2C_CLK2

R637
0 2

MF

5%
2 50V
CERM
402

INT_V1

59A7> 39B1<> 29C7<> 28D1< 28A3<>

INT_I2C_DATA2

5%
402
1/16W

R647
0 2
1
MF

5%
402
1/16W

NOSTUFF

+3V_MAINJ18

M-ST-LK
TH
1

INT_I2C_CLK1
INT_I2C_DATA1

2
3
4

INTREPID VERSION 1 HAS AN I2C BUS PROBLEM


USE KEY LARGOS I2C INSTEAD.
FIXED IN INTREPID VERSION 2

(515-1560)
I2C DEBUG HEADER

INT_I2C_CLK1

34B1<

INT_I2C_DATA1

34B1<

INTREPID ENET & FW

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:30:17 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
34 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

PLACE CLOSER TO PIN 22


ENET_DVDD

PIN 12

PIN 55

PIN 27, 28

MIN_LINE_WIDTH=20

ENET_AVDD 35D2<>

52C6>

MIN_LINE_WIDTH=20

+3V_MAIN
PIN 46

PIN 8

C57
10UF

N20P80%
10V
2 Y5V
805

PLACE NEAR PIN 20


PIN 3

C67
0.01UF

C53
0.1UF

20%
10V
2 CERM
402

10%
16V
2 CERM
402

C56
0.01UF

10%
2 16V
CERM
402

MIN_LINE_WIDTH=20

C44
0.1UF

20%
2 10V
CERM
402

C52
10UF

N20P80%
2 10V
Y5V
805

ENET_AVDD 35D4<>
RE-PLACE NEAR PIN 1>

C41
0.1UF

20%
2 10V
CERM
402

C66
0.1UF

C37
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C65
0.1UF

C3501
0.1UF

20%
2 10V
CERM
402

C68
10UF

N20P80%
2 10V
Y5V
805

C438
0.1UF

20%
10V
2 CERM
402

NC_UB3P4

52C6>

C434
0.1UF

2 20%
10V
CERM
402

NO_TEST

ENET_COL

ENET_PHY_RXD<0>
ENET_PHY_RXD<1>
57B5> ENET_PHY_RXD<2>
57B5> ENET_PHY_RXD<3>

48

ENET_PHY_RX_DV
ENET_PHY_RX_ER

49

ENET_PHY_CRS
57B5> ENET_PHY_COL
ETHPHYRESET_L

RP15

2
1/16W

1
1/16W

33
RP15

5%

62

402 MF

57B5>
57B5>

RP15

33

R29
33

57B5>
57B5>

5%
1/16W
MF
402

47
44
43

51

57B5>

5%

3
1/16W

33
34B7>

5%

61
9

ENET_MDC

42
41

5%
1/16W
MF
402

B
INT_ENET_RST_L

57B5> CLK25M_ENET_XIN
57B5> CLK25M_ENET_XOUT

R76
1K

28B5<>
28D1<

1%
1/16W
MF
402

44D3<
32A6< IO_RESET_L
44B8<>
59A7>

10
11
12
13
14

8X4.5MM-SM

D9
3

NC
NC
NC
NC
NC

CRITICAL
Y6
25.0000M

1N914
SOT23

C74
27PF

5%
50V
CERM 2
402

C76
27PF

5%
50V
2 CERM
402

40

OVDD/NC

22

BIASVDD

REFCLK

46

OVDD2

OVDD1

28

AVDD2

27

AVDD1

55

DVDD2

DVDD1

SEE_TABLE

1%
1/16W
MF
402 2

J1
TH-NMP-1

10

T1
XFR-100BT
MDIX

SYM_VER-2

SM

ENET_TDP

ENET_AVDD

15

14

ENET_TDN
NC_TX1_1 NO_TEST
NC_TX1_2 NO_TEST
57B5> ENET_RDP
57B5>

57B5> RJ45_TREF

57B5>
57B5>

RJ45_TXP
RJ45_TXN
RJ45_RXP

NC_TX1_3
NC_TX1_4

57B5>
57B5>
57B5>

RJ45_4_5
RJ45_RXN
RJ45_7_8

16

57B5>

1
2
3

+3V_MAIN
R27
10K

FDX
F100/JTAG_TCK
ANEN/JTAG_TRST
TESTEN
MII_EN
LOW_PWR

39
37

LNKLED/JTAG_TDI*
SPDLED/JTAG_TMS*
XMTLED*
RCVLED/JTAG_TDO*

FDX 35A5<
JTAG_ASIC_TCK

8A4<> 34B7<
59D7>

TESTEN

15

NC4
NC3

13

NO_TEST

12

NO_TEST

11

ENET_AVDD

10

ENET_RDN

1%
1/16W
MF
2 402

57B5>

R165
10K

1%
1/16W
MF
2 402

ENET_ENERGY_DET 28B5<>

R3941 R3931 R3911


75
75
75
1%
1/16W
MF
402 2

JTAG_ENET_TDI
JTAG_ENET_TDI

1%
1/16W
MF
402 2

1%
1/16W
MF
402 2

35A2<

57B5>

JTAG_INTRP_TDO 28C6<

RJ45_F_TREF
1

34B7>

33

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

8A4<> 34B7< 35A2< 59D7>


8A4<> 59D7>

+3V_MAIN

R42
1.27K

B
DEV
1

DEV
1

DEV
1

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

R486
330

R485
4.7K

R491
330

DS1P1

DS2P1

DEV

DEV

DEV

DS1
GREEN
2

59D7> 35B4<> 34B7< 8A4<>

RP16
10K
FDX
TESTEN
LOW_PWR
OGND3_JTAG_EN
35C4<

35C4<

35B4<

35B5<>

DS3
GREEN
2

R96
4.7K

DS2
GREEN

SM

10/100

5%
1/16W
MF
2 402

SM
2

XMIT

LINK

JTAG_ASIC_TMS
35B4<>

5%

R492
330

DS3P1

SM

1%
1/16W
MF
2 402

C3
0.001UF

20%
2KV
2 CERM
1808

JTAG_ASIC_TMS
XMIT_LED 35A2<
JTAG_ASIC_TDO

36

(514-0030)

1%
1/16W
MF
402 2

5%
1/16W
MF
402

34

+3V_MAIN

R3901
75

28C1<

R326

MIN_LINE_WIDTH=20

C400
0.1UF

20%
10V
2 CERM
402

LOW_PWR 35A5<

ENET_RDAC_PD

PHY ADDRESS 00000

R28
1.5K

RX

MII_EN

16

R26
10K

57B5> RJ45_RREF

5%
1/16W
MF
2 402

ADD DUAL LAYOUT SUPPORT


FOR ALTERNATE CRYSTAL

35A5<

18

35

TX

NC1
NC2

ANEN

38

ENERGY_DET 17
RDAC 23

NC
1

RXC
RXD0
RXD1
RXD2
RXD3
RXDV
RXER
CRS
COL
RESET*
MDC
MDIO
XTALI
XTALO
PHYAD0
PHYAD1
PHYAD2
PHYAD3
PHYAD4
OGND1

R75
1K

NOSTUFF

43C7<
34C3< INT_RESET_L
41A7<
44D2<>

R301
49.9

1%
1/16W
MF
402 2

BIASGND

R331
49.9

1%
1/16W
MF
402 1

24

57B5> 34B7<

50

57C5>

TXEN
TXER

PLLGND

1/16W 5%

ENET_RX_DV

34C7< ENET_RX_ER
57B5>
57B5> 34C7< ENET_CRS

CLKENET_PHY_RX

52

1/16W
SM1

57B5> 34C7<

R34
33

5%

57B5> 34C7<

56

AGND2

RP1
33
57B5> 34C7<
57B5> 34C7<

ENET_PHY_TX_EN
ENET_PHY_TX_ER

57C5> 34D7<
57C5> 34D7<

CRITICAL

32

57C5> 34C7< CLKENET_LINK_RX

60

AGND1

57C5>

59

29

58

DGND2

ENET_LINK_RXD<0>
ENET_LINK_RXD<1>
ENET_LINK_RXD<2>
ENET_LINK_RXD<3>

R402
49.9

1%
1/16W
MF
402 1

57B5>

TD+ 31
TD- 30
RD+ 26
RD- 25
SD+ 21
SD- 19

FLAS-1
TRANSC_BCM5221

DGND1

57

57C5>
57C5>

ENET_PHY_TXD<0>
34C7< ENET_PHY_TXD<1>
34C7< ENET_PHY_TXD<2>
34C7< ENET_PHY_TXD<3>

63

57C5> 34C7<

U37

TXC
TXD0
TXD1
TXD2
TXD3

54

53

57C5>

OGND3/
JTAG_EN

5%
1/16W
MF
402

57B5> 34C7<

20%
10V
2 CERM
402

NOTE: 1.5MM SPACE FROM TRACE TO GND

R372
49.9

C401
0.1UF

CLKENET_PHY_TX

NO_TEST

64

OGND2

CLKENET_LINK_TX

45

57C5> 34D7<

R38
33

REGAVDD

REGDVDD

20

MIN_LINE_WIDTH=20

XMIT_LED

JTAG_ENET_TDI

5
1/16W
SM1

ETHERNET PHY

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:30:19 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

TABLE_5_HEAD

34B7<>

ENET_MDIO

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

CRITICAL

ENET_BCM5231

TABLE_5_ITEM

338S0127

IC,BCM5231,FAST ENET XCVR,64P,TQFP

U37

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569
A
35 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

FW_12V

D8
MURS320T3
FW_PWR_SW

52B6> 51D2<>

NOSTUFF

R1016
50D5< 44D7<> 44C6< 44C2<
52C2> 52C1>

3.8V_TRICKLE

SEE_TABLE

52B6> FW_VP

D47
MURS320T3
51D4<> 50C6<> 29B3< FW_PWR
52B6>

FW_VREG_FB

R39
390K

FW_24V

R409
4.7K

U22_8

C27
1UF

FWPHYRST

5%
1/16W
MF
2 402

R438
2K 2

C12
22UF

20%
2 4V
ELEC
SM

C10
22UF

20%
2 4V
ELEC
SM
NOSTUFF

C477
27PF

3
1

R4171
10K

Q30
2N3904

1
2

FW_XI
NOSTUFF
1

30
31
43

R422
5.1M

Y1
24.576M

50

5%
1/16W
MF
402 2

SM
2 CRITICAL

C500
27PF
1

R418
100 2

51
24

CPS
XI
60 XO
19 PD
28 SE
29 SM
61 RESET
23 ISO
16 LPS
1 LREQ
57 PLLVDD
63 SYSCLK
3 CTL0
4 CTL1
59

57A5> FW_XO

5%
50V
CERM
402

FW_PHY_RST*
FW_PHY_ISO*
34C4<> FW_LPS
57A5> 34C3< FW_LREQ
57A5>
34C5<>
34C3<
57A5>
34C3<
57A5>

FW_SCLK
FW_CNTL0
FW_CNTL1

33

1/16W 5%

RP2
33 5%

1/16W

57A5> 34C3< FW_D<2>


8

1/16W

57A5> 34C3< FW_D<5>


57A5> 34C3< FW_D<6>

34C3< FW_D<7>

5
SM1

1/16W

57A5> FW_PHY_D<0>

57A5> FW_PHY_D<1>
57A5> FW_PHY_D<2>

57A5> FW_PHY_D<5>
57A5> FW_PHY_D<6>

11

57A5> FW_PHY_D<7>

13

D0
D1
D2
D3
D4
D5
D6
D7

15

CNA

57A5> FW_PHY_D<3>
57A5> FW_PHY_D<4>

9
10

12

RP3

NOSTUFF
1

MF 402

5
SM1

5%

FW_PHY_CNTL1

33

5%

R431

33

57A5> 1

57A5> 34C3< FW_D<0>


57A5> 34C3< FW_D<1>
57A5> 34C3< FW_D<3>
57A5> 34C3< FW_D<4>

57A5> FW_PHY_CNTL0

MF 402

MF 402

[OUT]

57A5> FW_PHY_SCLK

1/16W 5%

R432

57A5>

R424

33

U4
FW802A
AVDD0 TQFP DVDD0
AVDD1
DVDD1
AVDD2
DVDD2
AVDD3
DVDD3
AVDD4
DVDD4

C42
47PF

C490
0.01UF

10%
16V
CERM 2
402

R4301
4.7K

R4331
4.7K

5%
1/16W
MF
402 2

5%
1/16W
MF
402 2

2
14

R0
R1
PC2
PC1
PC0

25
56
64

DGND0
DGND1
DGND2
DGND3
DGND4

26

FW_TPO1N

36D1<>
57A5>

FW_TPI1P

SOT-363
2

SOT-363

C428
0.1UF

20%
10V
2 CERM
402

C424
0.1UF

C4
0.1UF

20%
10V
2 CERM
402

20%
10V
CERM 2
402

C406
0.001UF

10%
50V
2 CERM
402

ALT
CHASSIS

1N5227B

36D1<>
57A5>

D4
BAV99DW

57A5> 36A8<>

FW_TPO1N

57A5> 36A8<>

FW_TPI1P

57A5> 36A8<>

FW_TPI1N
FW_VP1

52B6> 36D3<>
2

TPO#
TPI
TPI#

VP

VGND

C378
0.01UF

5%
50V
CERM 2
603

1%
1/16W
MF
2 603

1%
1/16W
MF
2 603

1%
1/16W
MF
2 603

1%
1/16W
MF
2 603

R9
56.2

36

57A5> FW_TPA1P

35
34

57A5> FW_TPA1N
57A5> FW_TPB1P

33

57A5> FW_TPB1N

41

57A5> FW_TPA2P
57A5> FW_TPA2N

40

R8
56.2

R13
56.2

R12
56.2

38

C/LKON

SM

SYM_VER-2

NOSTUFF

C440
10PF

R423
4.7K

1%
1/16W
MF
2 603

1%
1/16W
MF
2 603

R10
56.2

FW_C_LKON 28B6<

1%
1/16W
MF
2 603

1%
1/16W
MF
2 603

R15
56.2

C457
0.47UF

20%
16V
2 CERM
805

C446
10PF

FW_TPO2N

57A5> 36A8<>

FW_TPI2P

57A5> 36A8<>

FW_TPI2N
FW_VP2

TPO

TPI

TPI#

VP

5%
50V
CERM 2
402

R14
56.2
1

C439
10PF

5%
50V
2 CERM
402

1
R402
C452
220PF 4.99K
1%

5%
25V
2 CERM
402

C456
0.47UF

C375
0.01UF

VGND

5%
50V
CERM 2
603

1
7

ALT
CHASSIS

5%
50V
CERM 2
402

5%
50V
CERM 2
603

NOSTUFF

C444
10PF

1
R16
C450
220PF 4.99K
1%

5%
25V
2 CERM
402

1/16W
MF
2 603

C379
0.01UF

5%
2 50V
CERM
402

20%
16V
2 CERM
805

FW_TPB1

C445
10PF

TPO#

NOSTUFF
1

NOSTUFF

5%
50V
CERM 2
402

5%
1/16W
MF
2 402

53

FW_TPB2
NOSTUFF

52

R11
56.2

1%
1/16W
MF
2 603

49

57A5> 36A8<>

C441
10PF

5%
2 50V
CERM
402

FW_R0
FW_R1 1
R411
2.49K

32

FW_TPO2P

NOSTUFF

5%
50V
CERM 2
402

20

18

L6
165-OHM

57A5> 36A8<>

52B6> 36D3<>

10PF

44

TH-NMP-UF1161C

SYM_VER-2

NOSTUFF
C442 1

45

58

J2

SM

46

21

PORT 2
(514-0023)

L5
165-OHM

47

22

5%
50V
CERM 2
603

ALT
CHASSIS

57A5> FW_TPB2P
57A5> FW_TPB2N

39

55

ALT
CHASSIS

62

54

TPO

27

PLLVSS

AGND0
AGND1
AGND2
AGND3

SYM_VER-2

C376
0.001UF

10%
2 50V
CERM
402

(155S0109)

FW_TPO1P

NOSTUFF
1

ALT
CHASSIS

C443
10PF

5%
2 50V
CERM
402

1/16W
MF
2 603

34C5<>

FW_DIODE_BYPASS_V

SM52B6> 36B7<>

1%
1/16W
MF
402

52B6> 36B6<> FW_DIODE_BYPASS_V


5

R395
10K 2

SOT23
3

D25

FW_PHY_3_3
52B6>

D4
BAV99DW

1
1

165-OHM
SM

57A5> 36B8<>

NO_TEST

L32
100-OHM-EMI
1
2
FW_DIO_V

52B6> 36D7< 36B5<

L8
FW_VP2

57A5> FW_BIAS1
FW_BIAS2
57A5>

17

NC_FW_CNA

FW_TPO1P

C384
0.01UF

5%
2 50V
CERM
402

36D1<>
57A5>

3A

C418
0.1UF

TPBIAS0 37
TPBIAS1 42
NC_48 48
TPA0+
TPA0TPB0+
TPB0TPA1+
TPA1TPB1+
TPB1NC_47
NC_46
NC_45
NC_44

J5

SYM_VER-2

TH-NMP-UF1161C

10%
2 50V
CERM
1210

1%
1/16W
MF
402
1

1%
1/16W
MF
603 2

SM

R425
4.7K

2 57A5> 1

5%
50V
CERM
402

5%
1/16W
MF
402 2

165-OHM
SM

52B6>
36C1<> 1

52B6> FW_VP_2

PORT 1
(514-0023)

L7

R1
0 DO NOT STUFF R1 PER SAFETY REQUIREMENTS

SM

5%
1/16W
MF
402

10%
50V
2 CERM
402

NOSTUFF

L3
FERRITE-4532

SM

C381
0.001UF

5%
1/8W
FF
2 1206

52B6>
36B7< 36B5< FW_PHY_3_3
36D7<

FW_PHY_RST

F3
0.75AMP

5%
1/16W
MF
2 402

20%
25V
CERM
1206

28C5<>

8
2

5%
1W
FF
2512

FW_VP1

(155S0109)

SEE_TABLE

R35
47

FW_CPS

R404
56 2

PHY_LEAKS
1

FW_XI_A

3A

C410
0.1UF

10%
50V
2 CERM
1210

5%
1/16W
MF
2 603

PHY_NOT_LEAKS
1

52B6> 36D7< 36B7< 36B5< FW_PHY_3_3

+12V_MAIN

52B6>
36D1<> 1

52B6> FW_VP_1

2
SM

SM

VTAP
U3
LP2951
SOI-3.3V
IN
OUT
SENSE ERR
SHUT FDBK
GND

SM

5%
1/16W
MF
603

L1
FERRITE-4532

F2
0.75AMP

SM

52B6>
36B7< FW_PHY_3_3
36D7<

DVDD BYPASS
1

C484
10UF

N20P80%
10V
2 Y5V
805

ALT
CHASSIS

C455
0.01UF

10%
16V
2 CERM
402

C463
0.01UF

C464
0.01UF

10%
16V
2 CERM
402

10%
16V
2 CERM
402

C471
0.01UF

10%
16V
2 CERM
402

C458
0.01UF

10%
16V
2 CERM
402

C481
0.01UF

10%
16V
2 CERM
402

NOSTUFF
C483
10UF

NOSTUFF
C482
10UF

N20P80%
10V
2 Y5V
805

N20P80%
10V
2 Y5V
805

10%
16V
2 CERM
402

C451
0.01UF

C496
0.01UF

10%
16V
2 CERM
402

C495
0.01UF

10%
16V
2 CERM
402

C468
0.01UF

10%
16V
2 CERM
402

C472
0.01UF

10%
16V
2 CERM
402

C485
0.01UF

10%
16V
2 CERM
402

1
5
3

D3
BAV99DW
4

36D1<>
57A5>

FW_TPI1N

36C1<>
57A5>

FW_TPO2P

D3
BAV99DW

SOT-363

SOT-363
2
6

C399
0.001UF

C392
0.001UF

C393
0.001UF

C390
0.001UF

10%
2 50V
CERM
402

10%
2 50V
CERM
402

10%
2 50V
CERM
402

10%
50V
2 CERM
402

1
5
3

D2
BAV99DW
4

36C1<>
57A5>

D2
BAV99DW

SOT-363

SOT-363
2

C395
0.001UF

10%
2 50V
CERM
402

C394
0.001UF

10%
2 50V
CERM
402

C407
0.001UF

10%
50V
2 CERM
402

TABLE_5_HEAD

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION

FIREWIRE PHY

6
TABLE_5_ITEM

FW_TPI2P

10%
2 50V
CERM
402

PART#

FW_TPO2N
5

36C1<>
57A5>

C411
0.001UF

ONE CAP FOR EACH DIODE PIN


AVDD BYPASS

740S0527

FUSE,0.75A,30V,SMD

F2,F3

PWRS_Q26

740S0506

FUSE,0.5A,SMD

F2,F3

PWRS_Q59

NOTICE OF PROPRIETARY PROPERTY

D1
BAV99DW

3
4

LAST_MODIFIED=Mon Oct 27 12:30:22 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

SOT-363

D1
BAV99DW

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

SOT-363
2

36C1<>
57A5>

FW_TPI2N

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

6
1

APPLE COMPUTER INC.

D
SCALE

ALT
CHASSIS

TABLE_5_ITEM

DRAWING NUMBER

REV.

051-6569 A
36 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

+5V_SLEEP

3_6V_SLEEP

51C1<

+5V_SLEEP
NOSTUFF
NOSTUFF

1
1

R623
10K

R754
1K

R768
10K

1%
1/16W
MF
402 2

R6351
10K

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

R944
4.7K

1%
1/16W
MF
402 2

NOSTUFF

5%
1/16W
MF
2 402

R941
4.7K

1%
1/16W
MF
2 402

R767
10K

1%
1/16W
MF
2 402

R7591
4.7K
5%
1/16W
MF
402 2

NOSTUFF
1

R943
10K

C3901
0.1UF

10%
16V
2 X7R
603

5%
1/16W
MF
2 402

D
U25
INTREPID
BGA
(5 OF 9)
SEE_TABLE

(ON PAGE 12)

UATA100

ATA_D0
ATA_D1
ATA_D2
ATA_D3
ATA_D4
ATA_D5
ATA_D6
ATA_D7
ATA_D8
ATA_D9
ATA_D10
ATA_D11
ATA_D12
ATA_D13
ATA_D14
ATA_D15

UIDE_DATA<0> 37C3< 58C5>


UIDE_DATA<1> 37C3< 58C5>
UIDE_DATA<2> 37C3< 58C5>
UIDE_DATA<3> 37C3< 58C5>
UIDE_DATA<4> 37B3< 58C5>
UIDE_DATA<5> 37B3< 58C5>
UIDE_DATA<6> 37B3< 58C5>
UIDE_DATA<7> 37B3< 58C5>
UIDE_DATA<8> 37B3< 58C5>
UIDE_DATA<9> 37B3< 58C5>
UIDE_DATA<10> 37B3< 58C5>
UIDE_DATA<11> 37B3< 58C5>
UIDE_DATA<12> 37B3< 58C5>
UIDE_DATA<13> 37A3< 58C5>
UIDE_DATA<14> 37A3< 58C5>
UIDE_DATA<15> 37A3< 58C5>

V5
T1
U1
U2
V4
V2
W1
V1
W2
W8
W4
W5
Y2
Y1
W7
Y8

UIDE_ADDR<0>
UIDE_ADDR<1>
UIDE_ADDR<2>

ATA_A0 Y5
ATA_A1 AB1
ATA_A2 Y7

R627
33 2
1

58D5> 37A7> EIDE_RST_L

58D5> 37A7<>

EIDE_DMACK_L

58D5> 37A7>

58D5> 37A7>

58D5> 37A7<

5%
1/16W
MF
402

R258
22 2
1

EIDE_STOP

5%
1/16W
MF
402

EIDE_HSTB_RDY

C917
10PF

5%
1/16W
MF
402

R263
22 2
1

R761
82.5 2
1

EIDE_DSTB_RDY

CD_RESET_L
R774
22 2
1

5%
1/16W
MF
402

CD_DMACK_L

CD_STOP

38C6<> 58D5>

38C6<> 58D5>

38C6<> 58D5>

CD_HSTB_RDY 38C6<>
CD_DSTB_RDY 38C6<>

58C5> 37C7<> UIDE_RST_L

58C5> 37C7<>

58D5>

58C5> 37C7<>

58C5> 37C7<

5%
1/16W
MF
402

5%
1/16W
MF
402

UIDE_DIOW_L

R270
22 2
1
5%
1/16W
MF
402

R753
82.5 2
1

UIDE_IOCHRDY
C911
10PF

5%
50V
CERM 2
402

38B4< 58B5>
38B4< 58B5>

R773
22 2
1

R273
22 2
1

UIDE_DIOR_L

1%
1/16W
MF
402

5%
1/16W
MF
402

UIDE_DMACK_L

58C5> 37C7<>

58D5>

R626
33 2
1

HD_RESET_L

38C3<> 58C5>

HD_DMACK_L

38C3<> 58C5>

HD_DIOR_L 38C3<>

58C5>

HD_DIOW_L 38C3<>

58C5>

HD_IOCHRDY

38C3<> 58C5>

1%
1/16W
MF
402

5%
50V
CERM 2
402
NOSTUFF

38A4< 58B5>
NOSTUFF

ATA_VREF
ATA_RST
ATA_WR
ATA_RD
ATA_CHRDY
ATA_CS0
ATA_CS1
ATA_DMACK
ATA_DMARQ
ATA_INTRQ

UIDE_REF
UIDE_RST_L 37D3< 58C5>
UIDE_DIOW_L 37C3< 58C5>
UIDE_DIOR_L 37D3< 58C5>
UIDE_IOCHRDY 37C3< 58C5>
UIDE_CS1FX_L 38B4< 58B5>
UIDE_CS3FX_L 38B4< 58B5>
UIDE_DMACK_L 37D3< 58C5>
UIDE_DMARQ 38C4< 58C5>
UIDE_INTRQ 38C4< 58C5>

Y15
Y4
AA1
AA2
AA5
AA4
AB2
AC1
AC2
AA8

58D5> 37B7<>

RP111
33 8

EIDE_DATA<0>

5%
1/16W
SM1

58D5> 37B7<>

EIDE_DATA<1>

58D5> 37B7<>

EIDE_DATA<2>

CARDSLOT

IDE

NC_CSLOT_CE1_L
NC_CSLOT_CE2_L
NC_CSLOT_IORD_L
NC_CSLOT_IOWR_L
NC_CSLOT_OE_L
NC_CSLOT_WE_L
52A8> CSLOT_IOWAIT_L

AD1
AB4
AB5
AD2
AC4
AE1
AE2

RP111
33 6
5%
1/16W
SM1

58D5> 37B7<>

AC5

1%
1/16W
MF
402 2

58D5> 37B7<>

IDEA0
IDEA1
IDEA2
IDEA3
IDEA4
IDEA5
IDEA6
IDEA7
IDEA8
IDEA9

AF5

AF1
AG1
AF2
AH1
AD5
AG2
AE4
AE5
AF4
AH2
AD7
AG4
AJ1
AJ2

58D5> 37B7<>

AK1
AG5
AH4
AL1
AK2
AH5
AF7
AG7

IDECHRDY AK4
IDECS0 AB7
IDECS1 AM1

EIDE_DSTB_RDY 37C5< 58D5>


EIDE_CS1FX_L 38B8< 58C5>
EIDE_CS3FX_L 38B8< 58C5>

AJ4

EIDE_RST_L 37D5< 58D5>


EIDE_STOP 37D5< 58D5>
EIDE_HSTB_RDY 37C5< 58D5>
EIDE_DMACK_L 37D5< 58D5>
EIDE_DMARQ 38C8< 58D5>
EIDE_INTRQ 38C8< 58C5>

EIDE_DATA<4>

58D5> 37B7<>

58D5> 37B7<>

RP104
33 6
3

EIDE_DATA<7>
RP107
33 1
8

EIDE_DATA<8>

5%
1/16W
SM1

58D5> 37B7<>

58D5> 37B7<>

EIDE_DATA<9>
RP107
33 3
6

EIDE_DATA<10>

5%
1/16W
SM1

58D5> 37B7<>

58D5> 37B7<>

EIDE_DATA<11>
RP115
33 8
1

EIDE_DATA<12>

5%
1/16W
SM1

58D5> 37B7<>

58D5> 37B7<>

EIDE_DATA<13>
RP115
33 6
3

EIDE_DATA<14>

5%
1/16W
SM1

58D5> 37B7<>

EIDE_DATA<15>
1

IDERST
IDEWR
IDERD
IDEDMACK
IDEDMARQ
IDEINTRQ

AM2
AL2
AG8
AH7
AA7

R640
10K

RP118
33 8

UIDE_DATA<0>

5%
1/16W
SM1

UATAD<1>

UATAD<2>

38C6<> 58D5>

58C5> 37D7<>

UIDE_DATA<1>

38C6<> 58D5>

58C5> 37D7<>

UIDE_DATA<2>

RP118
33 6

UATAD<3>

38C6<> 58D5>

58C5> 37D7<>

RP104
33 7
2

38C6<> 58D5>

58C5> 37D7<>

RP103
33

UIDE_DATA<4>

UATAD<5>
UATAD<6>

RP104
33 5
4

38C6<> 58D5>

58C5> 37D7<>

38C6<> 58D5>

58C5> 37D7<>

5%
1/16W
SM1

UATAD<7>

UATAD<8>

38C6<> 58D5>

58C5> 37D7<>

UIDE_DATA<7>

38C6<> 58D5>

58C5> 37D7<>

RP106
33 1
8

UIDE_DATA<8>

5%
1/16W
SM1

UATAD<9>

38C6<> 58D5>

58C5> 37D7<>

UIDE_DATA<9>

5%
1/16W
SM1

UATAD<10> 38C6<>
RP107
33 4
5

58D5>

58C5> 37C7<>

RP106
33 3
6

UIDE_DATA<10>

5%
1/16W
SM1

UATAD<11> 38C6<>

58D5>

58C5> 37C7<>

UIDE_DATA<11>

5%
1/16W
SM1

UATAD<12> 38C6<>
RP115
33 7
2

58D5>

58C5> 37C7<>

RP114
33 1
8

UIDE_DATA<12>

5%
1/16W
SM1

UATAD<13> 38C6<>

58D5>

58C5> 37C7<>

UIDE_DATA<13>

5%
1/16W
SM1

UATAD<14> 38C6<>
RP115
33 5
4

RP103
33 6
3

UIDE_DATA<6>

58D5>

58C5> 37C7<>

RP114
33 3
6

UIDE_DATA<14>

5%
1/16W
SM1

UATAD<15> 38C6<>

58D5>

58C5> 37C7<>

UIDE_DATA<15>

5%
1/16W
SM1

58C2>

T_UD_IDEDD_2 38C3<>

58C2>

T_UD_IDEDD_3 38C3<>

58C2>

RP103
33 7
2

T_UD_IDEDD_4 38C3<>

58C2>

T_UD_IDEDD_5 38C3<>

58C2>

T_UD_IDEDD_6 38C3<>

58B2>

T_UD_IDEDD_7 38C3<>

58B2>

T_UD_IDEDD_8 38C2<>

58B2>

T_UD_IDEDD_9 38C2<>

58B2>

5%
1/16W
SM1

RP103
33 5
4
5%
1/16W
SM1

RP106
33 2
7
5%
1/16W
SM1

RP106
33 4
5

T_UD_IDEDD_10

38C2<> 58B2>

T_UD_IDEDD_11

38C2<> 58B2>

T_UD_IDEDD_12

38C2<> 58B2>

T_UD_IDEDD_13

38C2<> 58B2>

T_UD_IDEDD_14

38C2<> 58B2>

T_UD_IDEDD_15

38C2<> 58B2>

R679
10K

5%
1/16W
SM1

RP114
33 2
7
5%
1/16W
SM1

RP114
33 4
5

1%
1/16W
MF
2 402

INTREPID UATA/IDE
A

NOTICE OF PROPRIETARY PROPERTY

R624
1K

LAST_MODIFIED=Mon Oct 27 12:30:24 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

1%
1/16W
MF
1 402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
37 69
1
SHT

OF

NONE

5%
1/16W
SM1

1%
1/16W
MF
2 402

T_UD_IDEDD_1 38C3<>

5%
1/16W
SM1

UIDE_DATA<5>

5%
1/16W
SM1

RP107
33 2
7

RP118
33 5
4

5%
1/16W
SM1

5%
1/16W
SM1

58C2>

5%
1/16W
SM1

UIDE_DATA<3>

T_UD_IDEDD_0 38C3<>

RP118
33 7
2

5%
1/16W
SM1

UATAD<4>

EIDE_DATA<5>
EIDE_DATA<6>

58C5> 37D7<>

5%
1/16W
SM1

5%
1/16W
SM1

EIDE_ADDR<0> 38B8< 58C5>


EIDE_ADDR<1> 38B8< 58C5>
EIDE_ADDR<2> 38A8< 58C5>
NC_CSLOT_ADDR<3>
NC_CSLOT_ADDR<4>
NC_CSLOT_ADDR<5>
NC_CSLOT_ADDR<6>
NC_CSLOT_ADDR<7>
NC_CSLOT_ADDR<8>
NC_CSLOT_ADDR<9>

AE7

RP104
33
5%
1/16W
SM1

EIDE_DATA<0> 37C5< 58D5>


EIDE_DATA<1> 37C5< 58D5>
EIDE_DATA<2> 37C5< 58D5>
EIDE_DATA<3> 37C5< 58D5>
EIDE_DATA<4> 37B5< 58D5>
EIDE_DATA<5> 37B5< 58D5>
EIDE_DATA<6> 37B5< 58D5>
EIDE_DATA<7> 37B5< 58D5>
EIDE_DATA<8> 37B5< 58D5>
EIDE_DATA<9> 37B5< 58D5>
EIDE_DATA<10> 37B5< 58D5>
EIDE_DATA<11> 37B5< 58D5>
EIDE_DATA<12> 37B5< 58D5>
EIDE_DATA<13> 37A5< 58D5>
EIDE_DATA<14> 37A5< 58D5>
EIDE_DATA<15> 37A5< 58D5>

AD4

EIDE_DATA<3>

38C6<> 58D5>

5%
1/16W
SM1

RP111
33 5
4

R266
10K

58D5> 37B7<>

IDEDD0
IDEDD1
IDEDD2
IDEDD3
IDEDD4
IDEDD5
IDEDD6
IDEDD7
IDEDD8
IDEDD9
IDEDD10
IDEDD11
IDEDD12
IDEDD13
IDEDD14
IDEDD15

RP111
33 7
2

+3V_MAIN
CS_CE1
CS_CE2
CS_IORD
CS_IOWR
CS_OE
CS_WE
CS_WAIT

UATAD<0>

DRAWING

<XR_PAGE_TITLE>

OPTICAL DRIVE INTERFACE


58D5> 37A7<

EIDE_DMARQ

J15
ST-NC20

R737
82.5 2
1
1%
1/16W
MF
402

ATA-100 INTERFACE

TH

R744
5.6K

5%
1/16W
MF
2 402

CD_RESET_L
37B4< UATAD<7>
37B4< UATAD<6>
37B4< UATAD<5>
37B4< UATAD<4>
37C4< UATAD<3>
37C4< UATAD<2>
37C4< UATAD<1>
37C4< UATAD<0>

58C5> 37C7<>

58D5> 37D4<

58D5>
58D5>

58D5>
58D5>
58D5>
58D5>
58D5>
58D5>

10

11

12

13

14

15

16

17

18

1%
1/16W
MF
402

UATAD<8> 37B4< 58D5>


UATAD<9> 37B4< 58D5>
UATAD<10> 37B4<
58D5>
UATAD<11> 37B4<
58D5>
UATAD<12> 37B4<
58D5>
UATAD<13> 37A4< 58D5>
UATAD<14> 37A4< 58D5>
UATAD<15> 37A4< 58D5>

CD_DMARQ
58D5> 37D4< CD_STOP
58D5> 37C4< CD_HSTB_RDY
58D5> 37C4< CD_DSTB_RDY
58D5> 37D4< CD_DMACK_L
58D5> UATA0IRQ
CD_EIDE_ADDR<1>
58C5>
CD_EIDE_ADDR<0>
58C5>
58C5> CD_CS1FX_L

C
58C5> 37A7<

EIDE_INTRQ

R782
82.5 2
1
1%
1/16W
MF
402

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

58C5> 37B7>

EIDE_ADDR<1>

R775
6.2K

R784
33 2
1

5%
1/16W
MF
2 402

5%
1/16W
MF
402

58C5> 37B7>

EIDE_ADDR<0>

R781
1K

EIDE_CS1FX_L

100PF

52A8> EIDE_IOCS16_L

C921
0.047UF

+5V_SLEEP

58C5> 37A7>

EIDE_CS3FX_L

R783
82.5 2
1%
1/16W
MF
402

R760
0

5%
1/16W
MF
2 402

58B5> 37C7<>

10

11

12

13

14

15

16

17

18

UIDE_ADDR<1>

R785
33 2
1

R780
6.2K
5%
1/16W
MF
402

21

22

23

24

DS8
DS6_2

25

26

1 NOSTUFF

27

28

29

30

31

32

33

34

35

36

37

38

39

40

5%
1/16W
MF
2 402

58B5> 37C7<>

UIDE_ADDR<0>

52A8> UNUSED_ATAIOCS16_L

UIDE_PDIAG
58C5> HD_UIDE_ADDR<2>
58B5> HD_UIDE_CS3FX_L

C920
0.047UF

5%
2 16V
CERM
603

R758
0

5%
1/16W
MF
2 603

(515-1588)
+5V_SLEEP

DS2_2

R792
330

DS2_1

5%
1/16W
MF
2 402

GREEN

5%
1/16W
MF
402

SM

1
1

DEV
1

R787
33 2
1

GREEN

52A8> UIDE_CSELP_L

DS7

DS6_1

59D7>
51C8<
51C5<>
50D5<
46D6<>
46C7<

R779
1K

DEV

5%
1/16W
MF
2 402

DEV

T_UD_IDEDD_8 37B1< 58B2>


T_UD_IDEDD_9 37B1< 58B2>
T_UD_IDEDD_10 37B1< 58B2>
T_UD_IDEDD_11 37B1< 58B2>
T_UD_IDEDD_12 37B1< 58B2>
T_UD_IDEDD_13 37A1< 58B2>
T_UD_IDEDD_14 37A1< 58B2>
T_UD_IDEDD_15 37A1< 58B2>

5%
1/16W
MF
402

SM

ATA-100 ACTIVE

OPTICAL DRIVE ACTIVE


C924
100PF

5%
50V
CERM 2
402

UIDE_INTRQ

5%
2 16V
CERM
603

(515-1588)

HD_DMARQ
58C5> 37C1< HD_DIOW_L
58C5> 37D1< HD_DIOR_L
58C5> 37C1< HD_IOCHRDY
58C5> 37D1< HD_DMACK_L
58C5> HD_INTRQ
58C5> HD_UIDE_ADDR<1>
58C5> HD_UIDE_ADDR<0>
58B5> HD_UIDE_CS1FX_L
58C5>

58C5> 37C7<

19

EIDE_PDIAG
58C5> CD_EIDE_ADDR<2>
58C5> CD_CS3FX_L

R793
330

R790
33 2
1

58C2>
58C2>

PLACE NEAR CONNECTOR

52A8> EIDE_CSELP_L

5%
2 50V
CERM
603

R789
33 2
1

5%
1/16W
MF
402

58C2>

58C2>

DEV
1

5%
1/16W
MF
402

58C5> 37A7>

NOSTUFF
1 C919

58B2>
58B2>

5%
1/16W
MF
2 402

40

39

R745
5.6K

58C2>
58C2>

NOSTUFF
1

+5V_SLEEP

TH

HD_RESET_L
37B1< T_UD_IDEDD_7
37B1< T_UD_IDEDD_6
37B1< T_UD_IDEDD_5
37B1< T_UD_IDEDD_4
37C1< T_UD_IDEDD_3
37C1< T_UD_IDEDD_2
37C1< T_UD_IDEDD_1
37C1< T_UD_IDEDD_0

58C5> 37D1<

5%
1/16W
MF
2 402

+5V_SLEEP

19

58D5>

UIDE_DMARQ

J16
ST-NC20

R743
82.5 2
1

58B5> 37C7<>

UIDE_CS1FX_L

R268
33 2

5%
1/16W
MF
402

R791
33 2
5%
1/16W
MF
402

C923
100PF

58B5> 37C7<>

5%
50V
CERM 2
402

58C5> 37B7>

EIDE_ADDR<2>

UIDE_CS3FX_L

R265
33 2
5%
1/16W
MF
402

R788
33 2
5%
1/16W
MF
402

58B5> 37C7<>

UIDE_ADDR<2>

R786
33 2
5%
1/16W
MF
402

CD/HD CONS

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:30:26 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569
A
38 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

AUD_R_FB
6

41B8<> 39C6<>

+5V_AUDIO
8

+3V_AUDIO

43C6< 43B2< 40C3< 39D6< 39D2<

2
3

C549
0.1UF

20%
16V
2 CERM
603

VTAP
U14
LP2951
SOI-3.3V
IN
OUT
SENSE ERR
SHUT FDBK
GND

+3V_AUDIO 39D2<

39D7< 40C3< 43B2< 43C6<

NC_VR4

5
7

52C4 43C7< 42C8< 42B7< 42B5< 41A7< 41A5< 40D5<


59D7>

L63
100UH

+3V_MAIN

+3V_AUDIO 39D6<

C538
22UF

20%
2 10V
TANT
SMB

39D7< 40C3< 43B2< 43C6<

TAS_DVDD

SMA
1

OPA_STAR_GND 39A7<>

C600
3.3UF

C584
0.1UF

20%
2 16V
CERM
603

10%
2 16V
TANT
SMA

40C2< 43A4<

C599
0.1UF

20%
16V
CERM 2
603

NOSTUFF
C591
3.3UF

10%
2 16V
TANT
SMA

+3V_MAIN
R502
100K 2

TAS_STAR_GND 39A7<>
TAS_PWR_DOWN 39B4<

1%
1/16W
MF
402

3
D

59D5> 51C6< 50C8< 50C3< 42D8<

PWR_UP

R501
0 2 SLEEP_OFF_L2

Q32
2N7002
SM

5%
1/16W
MF
402

2
1

C579
1000pF

17

R5211
24.9K

AINLM
AINLP

46

AINRM
AINRP

43

UX6_LINB

48

1%
1/16W
MF
402 2
1

R517
24.9K

DIRECT FROM PS (TRACES)

51A7< 51A5< 50D5<>


51B7< 49D3<> 49C4<> 48D6<>
45B4<> 44D8< 42B3< 36D8< +12V_MAIN
51C3< 48C8<> 48C4<> 45D7< 45D3<>
50D2< 50C4<> 50B4<> 49D7<>
59D7> 52C1> 51D7<>

VR1
LM1117
IN
OUT 2

+5V_AUDIO

1%
1/16W
MF
2 402

C578
1000pF

40C2<

5%
2 25V
CERM
603

C121
0.1UF

20%
2 16V
CERM
603

39D7< 41B8<>

SOT-223-4

LINA

RINA
MIC_IN

28B1<

41

SND_TO_AUDIO

22
23

C597
0.01UF

5%
1/16W
MF
2 402

20%
2 16V
ELEC
SM

VR4210P1
R481
560

C539
22UF

C85
47UF

R5321
0

1%
1/16W
MF
402 2

5%
1/16W
MF
402 2

CY69P2

R524
5.11 2

C588
1UF

SM

HP_STAR_GND

CAP_PLL

10%
10V
CERM 2
805

41A8< 41B4< 41B8< 41C5< 41D4< 41D7<

R264P2

C595
0.1UF

NC_XTLINO

28B5<> 28A8<

AUD_GND

SDIN1
SDIN2

IFM/S
ALLPASS

45
44

13
NO_TEST

TAS_PWR_DOWN
SND_HW_RESET_L

14
8
6
9

42B2< 42C4< 42D3< 42D4< 42D6< 42D7< 43C2< 43D2< 43D4<

XW1
1

40B4<

C594
0.1UF

SM

REF_STAR_GND

39D2< TAS_STAR_GND

R531
47 2
1

U5_SDOUT
NC_TAS_SDOUT1
NC_SDOUT2

26

NO_TEST

24

NO_TEST

INPA

NO_TEST

LRCLK/O

19

MCLKO

12

AUDIO_TO_SND 28B1<

NC_INPA
SND_SYNC

SCL

15

INT_I2C_CLK2 28A3<>

SCLK/O

20

SND_SCLK

SDA

16

VRFILT

VCOM

38

TAS_VCOM

NC0
NC1

34
36

28A1<

INT_I2C_DATA2

TAS_VCOM

C580
22UF

20%
2 10V
TANT
SMB

28A3<> 28D1< 29C7<>


34B5< 59A7>

39B1<> 43D5< 39B1<> 43D5<

C127
22UF

20%
2 10V
TANT
SMB

TEST
4

28D1< 29C7<> 34B5<

59A7>

AVSS

28B1<

AVSS
(REF)
3

C587
0.1UF

20%
16V
CERM 2
603

C581
0.1UF

20%
16V
CERM 2
603

5%
50V
CERM
402

XW37
2

25

XTIN1/MCLK
XTLIN0
PWR_DN
RESET

C248
47PF

20%
16V
2 CERM
603

SDOUT0
SDOUT1
SDOUT2

VRFILT

NOSTUFF

SM

PSEUDO_STAR_GND

41C7< 43D3<

VREFM
VREFP

18

AOUTR

DVSS

37

RINA
RINB

CAP_PLL
CLKSEL
7 CS1

VREFM

SM
2

AOUTR

10

43A3< VREFP
28A1< SND_CLKOUT

20%
16V
2 CERM
603

XW5
1

41D7< 43D3<

11

39D7<

AOUTL

LINA
LINB

GPI0
GPI1
GPI2
31 GPI3
32 GPI4
33 GPI5
27

1%
1/10W
FF
805

10%
10V
CERM
805

XW32
2

PQFP

39

30

21

52C4

C592
1UF

SM
1

AINRM
AINRP

AOUTL

29

R5281
10K

5%
50V
CERM
603

5%
1/16W
MF
2 402

20%
2 10V
TANT
SMB

XW4

U15
TAS3004

28

R482
180

AINLM
AINLP

AVDD

UX6P23

(SYM_VER1)

20%
16V 2
ELEC
SM

42

40

40B2<
43B2<

47

ADJ/GND

C126
47UF

35

DVDD

5%
25V
2 CERM
603

XW38
SM
1

REF_STAR_GND 39A5<> 39A5<>

XW34

OMIT

SM
1

OPA_STAR_GND 39D6<

40C2< 43A4<

ZH3
50R28

AUDIO CODEC
& VOLTAGE REGS

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:30:27 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569
A
39 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

52C4 43C7< 42C8< 42B7< 42B5< 41A7< 41A5< 39D4<


59D7>

+3V_MAIN

5%
1/16W
MF
2 402

1%
1/16W
MF
2 402

R180
470K

R175
47.5K

SND_LIN_SENSE_L

28B5<> 59B5>
NOSTUFF

C505
560PF

L51
1000-OHM-EMI
59B5> 40B7<> LINE_IN_SENSE

L53
1000-OHM-EMI
L3202_1

LINSENSE

SM

Q35
2N7002
R442
14.7K2

SM

2
1

C454
100PF

C204
0.1UF

1%
1/16W
MF
402

20%
10V
2 CERM
402

5%
50V
2 CERM
402

C756_2

5%
50V
CERM
603

SM

43C6<
39D6< 39D2<
43B2< 39D7<

KEEP CLOSE TO IC

+3V_AUDIO
U6
TLV2362

C506
0.1UF

KEEP SHORT
U4202P3
L46
1000-OHM-EMI
59B5> 40B7<>

LINE_IN_L

L50
1000-OHM-EMI
L31_2

SM

C25
3.3UF
LP4202P2

C437
100PF

R435
C4237P2 147.5K2

U4202P2

C64
0.47UF
1

V-

LINA 39C4<

20%
16V
CERM
805

1%
1/16W
MF
402

10%
16V
TANT
SMA

R407
100K

5%
50V
2 CERM
402

J10
JA1333C-AN4

SOI

V+

SM
1

20%
10V
CERM 2
402

1%
1/16W
MF
2 402

F-RT-TH

NOSTUFF

C514
180PF
1

43A4< 39D6< 39A7<>

OPA_STAR_GND

L48
1000-OHM-EMI

1
3
4
2

LINE_IN_COM 59B5>
LINE_IN_SENSE 59B5>40C7<>
LINE_IN_R 59B5> 40B6<>
LINE_IN_L 59B5> 40C7<>

L52
1000-OHM-EMI
L32_2

SM

C479
3.3UF
LP4202P4

C4240P2

SM

R434
47.5K2

R474
14.7K2

1%
1/16W
MF
402

10%
16V
TANT
SMA

5%
50V
CERM
402

1%
1/16W
MF
402

OPA_VREF

43A4<>

NOSTUFF
7

C447
100PF

R410
100K

D5
15V

5%
50V
CERM 2
402

D29
15V

SOT23

1%
1/16W
MF
402 2

SOT23
2

C480
3.3UF

R420
100

5%
1/16W
MF
603 2

C4242P2

1%
1/16W
MF
402

10%
16V
TANT
SMA

C513
180PF

R436
47.5K2
1

R462
14.7K2

5%
50V
CERM
402

1%
1/16W
MF
402

(514-0084)
PSEUDO_STAR_GND

L36
1000-OHM-EMI
59B5> 40B7<>

LINE_IN_R

L49
1000-OHM-EMI
L36_2

SM

C4243P2

SM
1

R437
47.5K2
1

U4202P6

5%
50V
2 CERM
402

U6
TLV2362
SOI

R448
14.7K2

C63
0.47UF

40B5<>
35B1<
35C1<>
40C6<
41A2<>
52C4 43A5< 42A6<> 42A5<> 41D3< 41C3< 41B3< 41B1<> 41A4<

U4202P7

V4

1%
1/16W
MF
402

10%
16V
TANT
SMA

C431
100PF

U4202P5

V+

C24
3.3UF
LP4202P3

39B7<>

1%
1/16W
MF
402

NOSTUFF

C507
560PF
1

RINA 39C4<

20%
16V
CERM
805

5%
50V
CERM
603

LINE IN BUFFER
A

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:30:28 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569
A
40
69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

43D3< 39C2>

OGAL

R473
9.09K2

C499
100PF

R447
25.5K2

1%
1/16W
MF
402

10%
16V
TANT
SMA

1%
1/16W
MF
402

C525
3.3UF

1%
1/16W
MF
402

C26
100UF

5%
50V
CERM
402

+5V_HP

C43
0.001UF
HPIN_L

HP_STAR_GND
41B5< HPBYP

41B4<

PROBE_DIV
HPIN_R
1

C60
0.001UF

10%
50V
2 CERM
402

43D3< 39C2>

AOUTR

OGAR

R446
25.5K2
1

1%
1/16W
MF
402

1%
1/16W
MF
402

10%
16V
TANT
SMA

LPR1

HEADPHONE_L

SM

41B2<>

SM

C420
100PF

5%
50V
2 CERM
402

5%
1/16W
MF
2 402

IN1IN1+

BYPASS

VDD 10
VO1 1

HP_OUT_L
HP_OFF

SHUTDOWN 6

HP_STAR_GND

41A7<

39B7<> 41A8< 41B4< 41B8< 41C5< 41D7<

HP_OUT_R

VO2 9
GND 5

IN2+
8 IN2-

R4121
4.7K

C508
0.47UF

5%
1/16W
MF
402 2

39B7<> 41A8< 41B4<


41B8< 41D4< 41D7<

C503
100PF
1

L34
1000-OHM-EMI
HP_TL

20%
16V
2 CERM
805

R472
9.09K2
1

R419
4.7K

HP_STAR_GND
C524
3.3UF

HP16_L

5%
1/10W
FF
805

20%
16V
ELEC
SM

41A8<
41B7<>

L45
1000-OHM-EMI

R406
33 2

SOI
2

HPGAL_L

U8
TPA6112A2

10%
2 50V
CERM
402

41D4< 41C5< 41B8< 41B4< 41A8< 39B7<>

R441
20.5K2

LPL1

AOUTL

C13
100UF

5%
50V
CERM
402

HPGAL_R

L44
1000-OHM-EMI

R400
33 2

HP16_R

HP_TR

HEADPHONE_R

41B2<>

SM

5%
1/10W
FF
805

20%
16V
ELEC
SM

L27
1000-OHM-EMI

2
SM

R444
20.5K2
1

C412
100PF

5%
50V
2 CERM
402

1%
1/16W
MF
402

HEADPHONE DRIVER AND 2ND ORDER LPF

J8
JA1333C-AN4
F-RT-TH

39D7< 39C6<>

XW33

+5V_AUDIO

+5V_HP

SM
1

41A8< 41D5<

C512
22UF

C518
0.1UF

41D6<

HPBYP

10%
2 16V
X7R
603

10%
2 16V
X7R
603

10%
2 6.3V
TANT
SMA

C504
0.1UF

R478
9.09K2
1
1%
1/16W
MF
402

41D7<
41D7< 41D4<
41A8< 39B7<>
41C5< 41B4<

R477
20.5K2
1

L42
1000-OHM-EMI

C453
1UF
PB_GAL

1%
1/16W
MF
402

PB_AUD

L35
1000-OHM-EMI
C412P1

HEADPHONE_L
HEADPHONE_R
SND_HP_SENSE_CONN
HEADPHONE_COM
41D2<
41C2<

41A3<

2
4
3
1

SM

20%
25V
CERM
1206

SM
1

PROBE_DIV

C427
100PF

5%
50V
2 CERM
402

HP_STAR_GND

LOCATE CLOSE TO AMP

POWER SOURCE

(514-0084)

L47
FERR-250-OHM
1

41D7< 41D4< 41C5< 41B8< 41A8< 39B7<>

HP_STAR_GND

HP_TP

2
SM

5%
1/10W
FF
805

C408
0.1UF

GROUND NOISE CANCELLATION

R392
0 2
1
3

1
1

20%
16V
CERM 2
603

D26
15V

D24
15V

SOT23
2

SOT23
3

52C4 43C7< 42C8< 42B7< 42B5< 41A7< 40D5< 39D4<


59D7>

41D5< 41B7<> +5V_HP

+3V_MAIN

R440
100K

+3V_MAIN

1%
1/16W
MF
2 402

NOSTUFF

HP_OFF

41D5<

5%
1/16W
MF
402

3
D

Q31
2N7002

S
2

SND_HP_M_L

41B8< 41B4< 39B7<>


41D7< 41D4< 41C5<

R162
10K

1%
1/16W
MF
2 402

59B7> 28B5<>
8
Y

SND_HP_MUTE_L

R181
100K

SND_HP_SENSE_L

1%
1/16W
MF
2 402

28C5<>
3

U48
B

NC7WZ08
SOI

C4301
0.1UF

20%
10V
2 CERM
402

SM

R4301
0 2
1

39D4< 40D5< 41A5< 42B5< 42B7< 42C8< 43C7< 52C4 59D7>

INT_RESET_L

34C3< 35B8< 43C7< 44D2<>

L43
1000-OHM-EMI

Q5
2N7002
SM

Q25_1

HP_STAR_GND

R182
100K 2
1

L43_1

SND_HP_SENSE_CONN

NOTICE OF PROPRIETARY PROPERTY

41B2<>

LAST_MODIFIED=Mon Oct 27 12:30:29 2003

SM
1

C208
0.1UF

20%
10V
2 CERM
402

LO_T1

SM

1%
1/16W
MF
402

HEADPHONE OUT AMP

L39
1000-OHM-EMI

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

C436
100PF

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

5%
2 50V
CERM
402

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

HP DETECT

SIZE

MUTE & SHUTDOWN

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569
A
41 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

TPA_5V IS NOT USED IN THIS SCHEMATIC


C1068
10UF
43D4< 43D2< 43C2< 42D6< 42D4< 42D3< 42C4< 42B2< 39B7<> AUD_GND
51C6< 50C8< 50C3< 39C8<
59D5>

R108

42C7>

C36

14.7K1

1%
1/16W
MF
402

R982

24.9K

Q2

SM

R135

TI_SD*

42A8<

10UH

C1063 1

SPKROUT_L_N

PRESPK_LOUTN

C1099
42A8<

L90

C122

C154

0.1UF

0.1UF

5%
2 25V
CERM
805

NOSTUFF

PRESPK_LOUTP

NOSTUFF

5%
50V
2 CERM
603

R121

42D5< 42C4< 42B7< 42B2< +12V_TPA

23

TPA_VCLAMPL

C1066
U10_A

100K 2

1%
MF

U10 Y
B

R120

42D8<

L41

D48
SOT23E

+3V_MAIN

L41_FILT

C4201

1%

TPA_COSC
TPA_ROSC

2N7002
SM

12

26

THRML
PAD

42B2< 42B7<

1206

NET_PHYSICAL_TYPE=AUDIO 42C5< 42D5<

R526
249K

2700PF

49

C582

1%
1/16W
MF
2 402

10%
16V
2 CERM
1210

5%
1/16W
MF
2 402

NET_PHYSICAL_TYPE=AUDIO
1

118K

C1070

20%
25V
2 CERM
805

220PF

5%
25V
2 CERM
402

42B2< 42D3< 42D4< 42D6< 42D7< 43C2< 43D2< 43D4<

(+12V_TPA)

2
SM

39D4< 40D5< 41A5< 41A7< 42B7< 42C8< 43C7< 52C4 59D7>

R249
0

R240

2K

42_I295
1

R245
470K

4.7K 2
1

42C1< SPKROUT_R_P

MIN_LINE_WIDTH=25

42C8< SPKROUT_L_N

MIN_LINE_WIDTH=25

MIN_LINE_WIDTH=25

SPKR_JACK_DALLAS
SPKR_RM
SPKR_LP
INT_SPKR+
43D8<
INT_SPKR43D8<
SPKR_LM
SPKR_RP
NET32_B

29A3< 43D7< 58A5> 59B7>

5%
1/16W
MF
402

C1102 1

C1080 1

20%
16V 2
ELEC
SM-2

20%
16V 2
ELEC
SM-2

220UF

C1061
C1062
C1065
C1067

AND
AND
AND
AND

C4261
C4262
C4265
C4267

SHARE
SHARE
SHARE
SHARE

PAD
PAD
PAD
PAD

1
1
1
1

2700PF

C4262

2700PF

5%
50V
2 CERM
805

C4265

2700PF

5%
50V
2 CERM
805

10%
16V
2 CERM
1210

C1085
10UF

C1091
0.1UF

20%
16V
2 CERM
603

PLACE C4309 AND C4310


NEAR PINS 22,23, 19

(TPA_GND)

10%
2 16V
CERM
1210

C1092
0.1UF

20%
2 16V
CERM
603

PLACE C4311 AND C4312


NEAR PINS 38,39, 42

MIN_LINE_WIDTH=20

(+12V_TPA)

C1081

10%
2 16V
CERM
1210

20%
16V 2
ELEC
SM-2

5
3

C1086
10UF

220UF

C1093
0.1UF

20%
2 16V
CERM
603

PLACE C4313 AND C4314


NEAR PINS 46,47, 43

(TPA_GND)

1
8

(514-0020)

SPEAKER AMP

C4267
2700PF

5%
50V
2 CERM
805

C1084
10UF

220UF

9
1

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

0 OHM,5%,1/8W,RES-1206

L90,L91,L93,L96

BOM OPTION

NOTICE OF PROPRIETARY PROPERTY

TABLE_5_ITEM

101S8000

L26

L40

1000-OHM-EMI
NET32

LAST_MODIFIED=Mon Oct 27 12:30:33 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

PREVIOUS PART NUMBER FOR L90,L91,L93,L96 IS 155S0148

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

2
SM

NOSTUFF

2700PF

NOSTUFF
1

5%
50V
CERM 2
805

C1062
2700PF

NOSTUFF
1

5%
50V
CERM 2
805

C1065
2700PF

NOSTUFF
1

5%
50V
CERM 2
805

C1067
2700PF

3
1

5%
50V
CERM 2
805

TABLE_5_HEAD

PART#

5%
50V
2 CERM
805

1000-OHM-EMI

C1061

NOSTUFF

SM

C4261

C4308
NEAR PINS 14,15, 18

0.1UF

(+12V_TPA)

MIN_LINE_WIDTH=25

42C1< SPKROUT_R_N

42B7< 42C4< 42C5< 42D5<

C1090MIN_LINE_WIDTH=25
PLACE C4307 AND

(+12V_TPA)
KS_INT_SPKR-

TH-2MT
10

39B7<> 42C4< 42D3< 42D4< 42D6< 42D7< 43C2< 43D2< 43D4<

MIN_LINE_WIDTH=20

5%
1/16W
MF
2 402

LP1

20%
16V
2 CERM
603

10%
16V
2 CERM
1210

R324

1%
1/8W
FF
2 1206

C1083
10UF

5%
1/16W
MF
402

2K

1%
1/8W
FF
2 1206

SM

C4306
NEAR PINS 33, 26

+12V_TPA

HSJ1724-REV-E-NMP

20%
16V
2 CERM
603

NOSTUFF

C1089PLACE
0.1UF

10%
16V
2 CERM
1210

J3

42C8< SPKROUT_L_P

C1082

AUD_GND

1%
1/16W
MF
2 402

42_I291

FERR-8A

NOSTUFF

MIN_LINE_WIDTH=12

47.5K

R239

47.5K

10UF

0.1UF

1UF

R242

R51

C108

C156

5%
25V
2 CERM
805

L99

2N7002
1

N20P80%
16V
2 CERM
805

NOSTUFF

C1073

4.7K

BAV99

42A8<

NET_PHYSICAL_TYPE=AUDIO

NET_PHYSICAL_TYPE=AUDIO

R9831

5%
25V
2 CERM
805

5%
50V NOSTUFF
2 CERM
805

CERM 2
805

C155
0.1UF

2700PF

5%
NOSTUFF50V
NET_PHYSICAL_TYPE=AUDIO

C1075

10UF

R4201

Q6

2.2UF

1%
1/16W
MF
2 402

1%
1/16W
MF
2 603

1NOSTUFF

SM-9

C1074 1

43

27

L94

10UH

SPDA

+12V_TPA

L93

TB321611B130

46
47

SPKROUT_R_P

1UF

PRESPK_ROUTP

C1100

FERRITE-4532

+3V_MAIN

42D5< 42C5< 42C4< 42B2< +12V_TPA

NET_PHYSICAL_TYPE=AUDIO

42A8<

20%
25V
2 CERM
805

SEE_TABLE

TPA_ROUTP

41

PRESPK_ROUTN

59D7> 52C1> 51D7<> 51C3< 51B7< 51A7< 51A5<


48C8<> 48C4<> 45D7< 45D3<> 45B4<> 44D8< 39C8< 36D8< +12V_MAIN
50D5<> 50D2< 50C4<> 50B4<> 49D7<> 49D3<> 49C4<> 48D6<>

Q4

NET_PHYSICAL_TYPE=AUDIO

AUD_GND 39B7<>

MF
402
1/16W

AGND

TB321611B130
1

SPKROUT_R_N

SM-9

L96
1206

30.1K

10%
16V
2 CERM
1210

1%
1/16W
MF
2 402

SND_SPKR_ID_U10

28

R4203

47.5K
121

COSC
ROSC

10UF

SM

R525

TPA_VCLAMPR

5%
50V
CERM 2
603

5%
2 50V
CERM
603

SEE_TABLE

0.01UF

1%
1/16W
MF
603

28B5<>

36

C1072

1
1

0.01UF

30.1K2

C45

43C7< 42C8< 42B5< 41A7< 41A5< 40D5< 39D4<


59D7> 52C4

SND_SPKR_ID

VCLAMPR

10UH
1

1000-OHM-EMI

R522

PGNDR0
PGNDR1

42

REF
GND

42B2< 42C4< 42D4< 42D6< 42D7< 43C2< 43D2< 43D4<

L95

TPA_BSRN
TPA_BSRP

R4202
TI_MODE_OUT_2

20%
25V
2 CERM
805

1%
1/16W 2
MF
402

38
39

FADE*

D
AUD_GND 39B7<>

TPA_ROUTN

1%
1/16W
MF
402 2

SM

100K

1%
1/16W
MF
2 402

C1071

RINP 43D4<
RINN 43C2<

PVCCR0
PVCCR1
PVCCR2
PVCCR3

VCLAMPL

30

1UF

100K

3
2

2
1

RINP
RINN

NC7WZ08

Q3

U10_OUT

48 NET_PHYSICAL_TYPE=AUDIO
37NET_PHYSICAL_TYPE=AUDIO

PVCCL0
PVCCL1
PVCCL2
PVCCL3

20%
25V
CERM 2
805

SOI

2N7002

SPKR_RMS

1/16W
402

8
1

BSRN
BSRP

40

25

R985

TPA_MODE

ROUTP0
ROUTP1

PGNDL0
PGNDL1

43C7<>

NC
NC

LOUTP0
LOUTP1

18
19

SND_AMP_M_L

TI_MODE_OUT

44
45

NET_PHYSICAL_TYPE=AUDIO

1UF

SPKR_RM

15
22

NET_PHYSICAL_TYPE=AUDIO

47.5K

R110

14

NET_PHYSICAL_TYPE=AUDIO

20
21

TPA_LOUTP

1%
1/16W
MF
2 402

NET_PHYSICAL_TYPE=AUDIO

ROUTN0
ROUTN1

LOUTN0
LOUTN1

NET_PHYSICAL_TYPE=AUDIO

5%
50V NOSTUFF
2 CERM
805

5%
50V
CERM 2
805

1%
1/16W
MF
2 402

6
16
17

SM

100K

PQFP

2700PF

2700PF

+3V_MAIN

U49

NET_PHYSICAL_TYPE=AUDIO

1206

C1060

NOSTUFF

CRITICAL

LINP
LINN

43D4<
43D2<

0.01UF

L91

C1059 1
59D7> 52C4 43C7<
41A5< 40D5< 39D4<
42B7< 42B5< 41A7<

LINP
LINN

C1064

TPA_LOUTN

TB321611B130

SM-9

32
31

L92

10UH

VAROUTR
VAROUTL

SN0210045A

35
34

BSLN
BSLP

SEE_TABLE

5%
2 25V
CERM
805

MODE_OUT
MODE

13
24

1206

20%
25V
CERM 2
805

SD*

TPA_VOL

5%
50V
CERM 2
603

TB321611B130

1UF

SPKROUT_L_P

TPA_BSLN
NET_PHYSICAL_TYPE=AUDIOTPA_BSLP

0.01UF

SEE_TABLE

SM-9

10
11

NET_PHYSICAL_TYPE=AUDIO

L89

NOSTUFF

29

VARDIFF
VARMAX
VOL

NET_PHYSICAL_TYPE=AUDIO

5%
1/16W
MF
402 2

1
9

33

V2P5 AVCC AVDD AVDD VREF


REF

42D7< 42D4< 42D3< 42C4< 42B2< 39B7<> AUD_GND


43D4< 43D2< 43C2<

1%
1/16W
MF
402 2

2N7002

R984

43D4<
43C2<
42D6<
42C4<
AUD_GND 39B7<>
42B2<
42D3<
42D7<
43D2<

2N7002

C1069

20%
25V
2 CERM
805

TPA_AVDD_REF

R981
1

1UF

1UF

20%
25V
2 CERM
805

Q36

MIN_LINE_WIDTH=25

5%
1/16W
MF
402

1%
1/16W
MF
2 402

Q2_GATE

5%
1/16W
MF
402

47.5K

R99

TPA_5V

20%
6.3V
CERM
1206

R109 NOSTUFF

160K 2
1

TPA_V2P5

MIN_LINE_WIDTH=25

PWR_UP

U10_OUT

42C5< 42C4< 42B7< 42B2< +12V_TPA

SM

D23

SOT23

5%
50V
2 CERM
603

BAS40-4

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

C388

SIZE

47PF
APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569
A
42 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

L97

TB321611B130
42A6<> INT_SPKR+ 1

41D7< 39C2>

KS_INT_SPKR+ 29A3<

58A5> 59B7>

C1076
1UF

1206

L98

TB321611B130

42A6<> INT_SPKR- 1

KS_INT_SPKR- 29A3<

10%
10V
CERM
805

42B4< 58A5> 59B7>

R986
200 2
1

VCOML

AUDIO

LINP

5%
1/16W
MF
402

AOUTL

C1088
1UF

42C5<

NET_PHYSICAL_TYPE=AUDIO
1

10%
10V
CERM 2
805

C1078
0.047UF

10%
16V
2 CERM
402

1206

LINN1

39B1<> TAS_VCOM

AUD_GND 39B7<>

5%
1/16W
MF
402

42B2< 42C4< 42D3< 42D4< 42D6< 42D7< 43C2< 43D2<

NET_PHYSICAL_TYPE=AUDIO
1

C1077
1UF
1

10%
10V
CERM
805

R4401
0 2

NOSTUFF

28C5<>

AUDIO

41C7< 39C2>

RINP

5%
1/16W
MF
402

5%
1/16W
MF
402
1

AOUTR

NET_PHYSICAL_TYPE=AUDIO

10%
10V
CERM 2
805

39D4< 40D5< 41A5< 41A7< 42B5< 42B7< 42C8< 52C4 59D7>

RINN1

SND_AMP_M_L

RINN
1

NC7WZ08
Y

39B7<> 42B2< 42C4< 42D3< 42D4< 42D6< 42D7< 43C2<


43D4<

R988
200 2

42C4<

C1094
0.047UF

10%
16V
2 CERM
402

SOI

U48

INT_RESET_L

C1095
0.047UF

AUD_GND

C1087
1UF

42C4<

5%
1/16W
MF
402
A

42C5<

10%
16V
2 CERM
402

10%
2 16V
CERM
402

R987
200 2

LINN
1

C1079
0.047UF

SND_AMP_MUTE_L

44D2<> 41A7< 35B8< 34C3<

+3V_MAIN

VCOMR

R989
200 2

42D3<

AUD_GND 39B7<> 42B2< 42C4< 42D3< 42D4< 42D6< 42D7<


43D2< 43D4<

C
R4507
330 2

+3V_AUDIO

43B2< 40C3< 39D7< 39D6< 39D2<

MIC_FIX

1/16W
5%
MF
402

518S0008
J4501
DF13B-4P-1.25V

J4502
DF13B-4P-1.25V

F-ST-SM
5

F-ST-SM
5

M1S
M1H
M1L

43A6<>
43B6<>
43A6<>

NEEDED FOR MIC NOISE


1

C4502
22UF

NOSTUFF

20%
2 10V
TANT
SMB

R421
2.2K
5%
1/16W
MF
402

NOSTUFF

43B6<>

M1FH

SM
1

R4501
R4504
0 2 JAZ 1 0 2

NO_TEST

5%
1/16W
MF
402

C642
47PF

L60
1000-OHM-EMI
M1H

M1HFILT

SM

5%
1/16W
MF
402

C35
2.2UF

R414
330 2

MIC1

5%
1/16W
MF
402

C478
470PF

10%
50V
2 CERM
402

43B6<>

M1FL

R4502
R4505
0 2 ASH 1 0 2
1

SM
1

5%
1/16W
MF
402

C675
47PF

NO_TEST

L59
1000-OHM-EMI
M1L

R4303
1

L59_2_I461

MIC3

5%
2 50V
CERM
402

330

1%
1/16W
MF
402

MIC1S1

V+

C4302
2.2UF
1

R4304

5%
1/16W
MF
402

20%
10V
CERM
805

R4503
0 2
5%
1/16W
MF
402

SM

KAVAN

R4506
0 2

43B6<> 1

NO_TEST

5%
1/16W
MF
402

M1S

R487
0 2

C551
0.1UF

20%
2 16V
CERM
603

MIC_I519
1

C4303
100PF

5%
2 50V
CERM
402

39B4<

R4305

1%
1/16W
MF
2 402

VREFP

SOI
3

Q33
2N3904

SM

U13
TLV2362

121K

MIC5

V+

MIC PREAMP

V-

40B3<

39D2< 39D6< 39D7< 40C3< 43C6<

2.2K 2
1
5%
1/16W
MF
402

39C4<

+3V_AUDIO

V-

R4302

8 SOI

MIC_IN

16V

CERM 603

U13
TLV2362

A
59A7> 58A5>

MIC4

20%

R413
47.5K

5%
1/16W
MF
2 402

L83
1000-OHM-EMI

C556
0.1UF

R489
121K 2
1%
1/16W
MF
402

5%
1/16W
MF
402

2.2K

29A5<> MICSHLD

MIC_C4302

SM

5%
1/16W
MF
402

1
MIC_I520

L81
1000-OHM-EMI
MICLOW

1
1

59A7> 58A5> 29A5<>

R488
2.2K
MIC2

20%
10V
CERM
805

5%
50V
2 CERM
402

50V
402

MICHIGH

L79
1000-OHM-EMI
59A7> 58A5> 29A5<>

5%
CERM

C542
100PF

C550
1UF

10%
10V
2 X5R
603

R498
47.5K

1%
1/16W
MF
2 402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

OPA_VREF

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

40C2< 39D6< 39A7<> OPA_STAR_GND

5%
1/16W
MF
402

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

APPLE COMPUTER INC.

PLACE R4501, R4502 AND R4503 NEAR AUDIO

D
SCALE

PLACE R4504, R4505 AND R4506 NEAR KITCHENSINK

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:30:34 2003

DRAWING NUMBER

REV.

051-6569 A
43 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

7
NOSTUFF

R693
100 2
5%
1W
FF
2512

+12V_DROPPED

SM

D12
SM
D11

59C5> 52B3> 44B5<


52B3> 44C2< 44B1< 44A5<> 29C3<>

R297
0

MBR0530
R281
787

1%
1/16W
MF
2 603

TL431
SOI

CAT
4
NC
5
NC
8
REF

QTY

DESCRIPTION

REFERENCE DES

341S1008

PMU,M16C62,64KB,PRMGD

U26

525-0057

CONN,BATTERY HOLDER

BT1

R287
4.7 2

5%
1/16W
MF
603

C759
0.1UF

20%
10V
2 CERM
402

C245
47UF

C783
0.1UF

59C7> 44C2< 8A3<> 7B3< 7A5< 7A3< 4B3<

+3V_MAIN

BATTERY HOLDER
(525-0057)

NOSTUFF

BT1
3.6V-850MAH

TH

3.8V_TRICKLE

VC_CNTL1

1/16W 5%

402

1%
1/16W
MF
2 402

NOSTUFF

NC_P00_D0
NC_P01_D1
NC_P02_D2
NC_P03_D3
NC_P04_D4
NC_P05_D5
NC_P6_D6
NC_P07_D7

NO_TEST

86

NO_TEST

85

NO_TEST

84

NO_TEST

83

NO_TEST

82

NO_TEST

81

NO_TEST

80

NO_TEST

79

NC_P10_D8 NO_TEST
NC_P11_D9 NO_TEST
NC_PPL*
PMU_PWR_LED*
POWER_UP*
1/16W 5% MF
(BACKUP SELECT) NC_P14_D12 NO_TEST
59D5> 44B1< 8A8<> PWR_SWITCH*
59D5> 29C5<> 28B8< 28B5<> COMM_RING_DET_L
28A5> INT_WATCHDOG_L

MF

R722
0 2
1

NO_TEST

78
77

402

POWER_UP*

NC_P20_A0_D0
NC_P21_A1_D1_D0
NC_P22_A2_D2_D1
NC_P23_A3_D3_D2
NC_P24_A4_D4_D3
NC_P25_A5_D5_D4
NC_P26_A6_D6_D5
NC_P27_A7_D7_D6

+3V_MAIN
NOSTUFF
1

R732
10K

5%
1/16W
MF
402 2

76
75
74
73
72
71

NO_TEST

70

NO_TEST

69

NO_TEST

68

NO_TEST

67

NO_TEST

66

NO_TEST

65

NO_TEST

64

NO_TEST

63

LOW INDICATES
DESKTOP SYSTEM

NOSTUFF
1

+MAXBUS_SLEEP

R731
10K

R726
10K

LOW INDICATES
IVAD PRESENT

1%
1/16W
MF
2 402

61

PMU_STRAP1
IO_RESET_L
NC_P33_A11 NO_TEST
NC_P34_A12 NO_TEST
NC_P35_A13 NO_TEST
NC_P36_A14 NO_TEST
NC_P37_A15 NO_TEST

IO_RESET_L

1%
1/16W
MF
2 402

59
58
57
56
55
54
53

PMU_INT_L
PMU_LOW_DSKTP
PMU_PRE_PLLSTOP
DRIVEN OPEN COLLECTOR
NC_P43_A19 NO_TEST
NEED TO VOLTAGE CONVERT
59C5> 50C2< SLEEP
NO_TEST
NC_P45_CS1_L
(WAS KW_SUSPEND_REQ*)
INT_SUSPEND_ACK_L
9B3>
INT_SUSPEND_REQ_L

52

28B8< 28B5<>

R725
6B8< CPU_PLL_STOP

22

AVCC

2
5%
402
1/16W
MF

NO

INT_SUSPEND_REQ_L

51
50
49
48
47
46
45

SEE_TABLE

P00_D0
P01_D1
P02_D2
P03_D3
P04_D4
P05_D5
P06_D6
P07_D7

U26
M16C62
FLAS

44

P50_WRL_WR
P51_WRH_BHE
P52_RD
P53_BCLK
P54_HLDA
P55_HOLD
P56_ALE
P57_RDY_CLKOUT

42
41
40
39

37

33
32
31
30
29

P80_TA4OUT_U
P81_TA4IN_U
P82_INT0
P83_INT1
P84_INT2
P85_NMI
P86_XCOUT
P87_XCIN
P90_TB0IN_CLK3
P91_TB1IN_SIN3
P92_TB2IN_SOUT3
P93_DA0_TB3IN
P94_DA1_TB4IN
P95_ANEX0_CLK4
P96_ANEX1_SOUT4
P97_ADTRG_SIN4
P100_AN0
P101_AN1
P102_AN2
P103_AN3
P104_AN4_KI0
P105_AN5_KI1
P106_AN6_KI2
P107_AN7_KI3
AVSS

B
R716
100K

1%
1/16W
MF
2 402

R733
100K

1%
1/16W
MF
2 402

R734
1K

1%
1/16W
MF
2 402

R653
1K

1%
1/16W
MF
2 402

44A5<>
59D5>

NOSTUFF
1

C862
0.001UF

10%
2 50V
CERM
402

11
13
10
96
7

BYTE
XOUT
XIN
RESET
VREF
CNVSS

NOSTUFF

LOCATE NEAR TO PMU

VSS

R636
5.1M 2

25
24

NO_TEST

23

NO_TEST

22

NO_TEST

21

NO_TEST

19
18

16

44B4<>

PMU_IIC_DAT

PMU_P64 29B2<>
R677
1K 2
1

ALSO "BUSY" FOR LOADING CODE

PMU_REQ_L 28A8<

ALSO "RXD" FOR LOADING CODE

5%
1/16W
MF
2 402

5%
1/16W
MF
2 402

R671
2K

ALSO "TXD" FOR LOADING CODE

SYSTEM_CLK_EN 28A5<
CPU_CLK_EN 9A3<
NC_P74_TA2OUT_W
NC_P75_TA2IN_W
NC_P76_TA3OUT
NC_P77_TA3IN

R665
2K

C
PMU_POWER 29C3<> 44A5<>
3.8V_TRICKLE 36D8< 44C6< 44D7<> 50D5<

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

R657
10K

R658
10K

15
9
8

44B1< 44D5<> 52B3>


52C1> 52C2>

NOSTUFF
1

R649
10K

R659
10K

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402
1

R646
0 2

1/16W 5%

402

PWR_FAIL* 50D5<

MF

31C2< 32A8< 59A5>

NOSTUFF

4
3

NO_TEST

NO_TEST

1
100
99

NO_TEST

NC_P92_TB2IN_SOUT3
NC_P93_DA0_TB3IN
INT_PROC_SLEEP_REQ_L 28A5<
(OK TO POWER UP
POWERUP_OK
NC_P96_ANEX0_CLK4

R648
5.1M 2
5%
1/16W
MF
402

SIGNAL)

R655
160K

5%
1/16W
MF
2 402

98
(THERMISTOR)

93

(TRICKLE_DETECT)

PWR_FAIL*

92
91

CRITICAL

NC_P103_AN3
PMU_IIC_CLK 44A8<
PMU_IIC_DAT 44A8<

NO_TEST

90
89

52B3> 44D5<> 44C2< 44A5<> 29C3<>

R692
10K

1%
1/16W
MF
2 402

1%
1/16W
MF
402 2

1%
1/16W
MF
2 603

PMU_CLKT

32.768K

NET40
1

R298
10K

58A5>

+3V_MAIN
R676
1K

SM

88
87

PMU_POWER

Y4

C715
10PF

5%
50V
2 CERM
402

R698
10K

C701
22PF

5%
50V
2 CERM
402

1%
1/16W
MF
2 402

59D5> 44C5<> 8A8<>

PWR_SWITCH*

S1
TACT-SPST

L57
1000-OHM-EMI

TH
1

S3700P2

1
1

L56
1000-OHM-EMI
S3700P1

PMU_POWER

C861
0.1UF

20%
10V
2 CERM
402

SM

PMU_SMB_SCK
PMU_SMB_SDA
44C2< 44B1< 29C3<>
52B3> 44D5<>

28C3>

1%
1/16W
MF
402

ALSO SCLK FOR LOADING CODE

INT_PEND_PROC_INT 28A5>
PMU_NMI
58A5> PMU_CLKOUT
58A5> PMU_CLKIN

94

62

34C3<

3.8VH_TRICKLE

MF 402

PMU_PME_L 28B5<>

1%
1/16W
MF
2 402

2
SM

R605
10K

Y3
10.0000M

PMU_XT

R686
4.7K 2
1
R687
4.7K 2
1

1/16W 5%

INT_PU_RESET_L 15B3< 44C2<>

52B3> 44D7<>
CPU_HRESET_L 4B3< 7A3< 7A5< 7B3< 8A3<> 44D2< 59C7>

17

R654
10K

1%
1/16W
MF
2 402

58A5>

1%
1/16W
MF
402

R689
47 1
2

CPU_STATE_LED* 51A8<
CPU_SMI_L 4B3< 7A5<
PWR_FAILPMU*

R656
10

PMU_IIC_CLK

1%
1/16W
MF
402

34C3< 35B8< 41A7< 43C7<

PMU_5V_SDA
PMU_5V_SCL

26

44B4<>

R688
10K 2
1

1
12

5%
1/16W
MF
402

IIC BUS PULLUPS


+3V_MAIN

R717
100K 2
1

27

95

5%
1/16W
MF
2 402

P40_A16
P41_A17
P42_A18
P43_A19
P44_CS0
P45_CS1
P46_CS2
P47_CS3

4D5< 6C5< 6D6< 7A3< 7B3< 7C3< 7C5< 7C7< 8A3<> 8D1<
8D4< 9B7< 9D8< 44B7< 44D1< 45D2<> 46D4< 52C6> 59C7>

INT_RESET_L

PMU_ACK_L 28C3<
PMU_CLK 28C3<>
PMU_FROM_INT 28C3<>
PMU_TO_INT 28C3<>
PMU_P64
LID_SWITCH 29B2<>
RESET_BUTTON* 29B2<> 59D5>
NMI_BUTTON* 29B2<> 59D5>

34

R690
2K

ALSO CE* FOR LOADING CODE

CPU_HDRST_L

35

7A3< 7B3<
7C3<

MF

38

20

9B3<

PMU_BYTE
58A5> PMU_XO
58A5> PMU_XI
29B3<> 8A8<> PMU_RST*
59C5>
44D4<> PMU_AVCC
52B3>
29B3<> PMU_CNVSS

1/16W 5%

402

28

P70_TXD2_SDA_TA0OUT
P71_RXD2_SCL_TA0IN_TB5IN
P72_CLK2_TA1OUT_V
P73_CTS2_RTS2_TA1IN_V
P74_TA2OUT_W
P75_TA2IN_W
P76_TA3OUT
P77_TA3IN

P30_A8_D7
P31_A9
P32_A10
P33_A11
P34_A12
P35_A13
P36_A14
P37_A15

2
3

+MAXBUS_SLEEP

R700
0 2
1

PMU_AP 29B3<>
INT_RESET_L
59A5>
MAIN_RESET_L 32A8<
17C8< 30B2<
31D4<
PMU_AGP_RESET
PMU_INT_NMI 28A8< 28B5<>
PMU_EPM* 29B3<>

43

36

P60_CTS0_RTS0
P10_D8
P61_CLK0
P11_D9
P62_RXD0
P12_D10 (SEC_FPB_LED*)
P13_D11
P63_TXD0
P14_D12
P64_CTS1_RTS1_CTS0_CLKS1
P15_D13_INT3
P65_CLK1
P66_RXD1
P16_D14_INT4
P17_D15_INT5
P67_TXD1
P20_A0_D0
P21_A1_D1_D0
P22_A2_D2_D1
P23_A3_D3_D2
P24_A4_D4_D3
P25_A5_D5_D4
P26_A6_D6_D5
P27_A7_D7_D6

CPU_HRESET_L

U46
SN74LVC1G04
4
VGER_INV_HRESET

MF

NOSTUFF

5%
1/16W
MF
2 402

BT1

R729
10K

R730
0 2
1

R701
4.7K

97

60

VCC

51A6<

52C2> 52C1> 50D5< 44D7<> 44C2< 36D8<

1/16W 5%

1
14

NOSTUFF

AGP_RESET_L IS USED AS MAIN_RESET_L FOR SIL1162


THROUGH R1027 AND IS NOT USED IN ANY OTHER DEVICE
NOSTUFF R699
0 2 402
1
AGP_RESET_L 17B8< 27C5<
32A6< IO_RESET_L

35B8<
59A7> 44B8<>

D36
SM
MBR0530

+MAXBUS_SLEEP

SOT23-5

20%
10V
2 CERM
402

1%
1/16W
MF
2 402

BOM OPTION

5
1

20%
2 16V
ELEC
SM

NET18

R282
1.5K

CRITICAL

59C7>
8D1< 8A3<> 7C7< 7C5< 7C3< 7B3< 7A3< 6D6< 6C5< 4D5<
52C6> 46D4< 45D2<> 44D2< 44B7< 9D8< 9B7< 8D4<

NO_TEST

518-0054

59D5> 51A8<

PART NUMBER
PMU_AVCC

D35
SM
MBR0530

45D8<

C267
2.2UF

N20P80%
16V
2 CERM
805

NET19

NET22
NC_UT164
NO_TEST NC_UT165
NET24

ANODE1
ANODE2
6
ANODE3
7
ANODE4

35B8< 32A6<
59A7> 44D3<

U28
3

5%
1/16W
MF
2 603

PMU_POWER

PMU OPERATES ON 2.7 TO 3.6 VOLTS

1%
1/16W
MF
603 2

36D8< 44C2< 44C6< 50D5< 52C1> 52C2>

SM
1

R290
787

PMU SUPPORT

5%
1/16W
MF
603

44C1<

3.8VH_TRICKLE 52B3>
Q12
MBR0530
2N3904

+12V_MAIN

3.8V_TRICKLE

R280
0 2

SM
CRITICAL

5%
1/16W
MF
402
1

5%
1/16W
MF
402

C705
22PF

5%
50V
2 CERM
402

1%
1/16W
MF
2 402

44B5<> 29B3<> 8A8<>


59D5>
1

C706
10PF

5%
50V
2 CERM
402

PMU NOT RATED STRONG ENOUGH FOR 1K

VCC

PMU RESET BUTTON

U21
59D5> 44A4<

SM

PMU_RST*
NOSTUFF

VOLTAGE DETECTOR
MC33465N_22ATR

VCC
U23

GND

SOT23-2.32V
MAX6328

MAIN RAIL, TO PREVENT LEAKAGE INTO UNPOWERED DEVICES

DELAY 5

RESET

PMURESETBUTTON*
1

C239
1UF

10%
10V
2 X5R
603

R604
33 2
1

PMU POWER MGR

S2
SM-SKQDAA

SB1P1

NOTICE OF PROPRIETARY PROPERTY

5%
1/16W
MF
402

LAST_MODIFIED=Mon Oct 27 12:30:37 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

3
II NOT TO REPRODUCE OR COPY IT
NOSTUFF
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

RESET
1

GND

R606
33 2

SIZE

5%
1/16W
MF
402

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569
A
44 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

51A5< 50D5<> 50D2< 50C4<> 50B4<>


45D3<> 45B4<> 44D8< 42B3< 39C8< 36D8< +12V_MAIN
49D7<> 49D3<> 49C4<> 48D6<> 48C8<> 48C4<>
59D7> 52C1> 51D7<> 51C3< 51B7< 51A7<

NO_TEST

VCORE_VIN

NOSTUFF 1

R931
510K

C1044
0.1UF

5%
1/16W
MF
2 603

Q29
2N7002

10%
16V
2 CERM
1210

VCOREIN

NC_VCORE10

45D5<>
45C5<> VCORE_INTVCC

45D7<> 45C5<>

D20
22

1%
1/16W
MF
603 2

VCORE_SGND
45B5< VCORE_TG_1
45B5< VCORE_BOOST2_1
45B5<> CORE_MOSFET_1
45B5< VCORE_BG_1

DONT EVER STUFF THIS


CONN NOT FIT ON PCB
FOR DANNY ITANI FMAX!!!

59D5>
45C8<>

NOSTUFF

J21
TH

45C8<>

45C8<>
45C7<>
45B7<> VCORE_SGND

VCORE_SF

SENSE+_1
SENSE-_1

SNS1+

8
1

5
6

19
14

C343
150UF

20%
2 16V
ELEC
SM-1

C357
150UF

C944
0.1UF

20%
16V
2 CERM
603

20%
2 16V
ELEC
SM-1

+MAXBUS_SLEEP

SENSE+
SENSE-

BRE

1
G

20

R929
10

45C6<> CORE_MOSFET

10%
50V
CERM
1210

NOSTUFF

R900
0 2

1%
1/16W

XW29

603

SM

5%
1/16W
MF
2 603

5%
1/16W
MF
2 603

MR_FLO

1000PF

MBRS340T31

5%
2 25V
CERM
603
NOSTUFF

SUD70N03
TO-252

S 3

45_I525

D 4

NOSTUFF
1

R4509

Q40

C949
0.0022UF

S 3

1%
1W
MF
2512

C1051
47PF

C372
47PF

5%
2 50V
CERM
402

R3891
475K

R4708
0

0.1%
1/8W
TF
805 2

5%
50V
CERM 2
402

C1045
0.047UF

5%
16V
CERM
603

5%
1/16W
MF
603

SM
2
1

XW27

C367
47PF

SEE_TABLE

CPU_VCORE_SLEEPA

SM

DUKE_BD
1

45_I408
1
R388
442K
1

C4701
220PF

R387
274K
1

45C7<>

R897
0 2

R898
10 2

1
1%
1/16W

CORE_MOSFET_1

45C7<>

SENSE+_1

45C7<

SENSE-_1

C374
0.001UF
1

TABLE_5_HEAD

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

RES,CER,374K,0.1%,1/10W,0805

R388

CRITICAL

1GHZ_DECOUP

103S0042

RES,CER,453K,0.1%,1/10W,0805

R388

CRITICAL

1_25GHZ_DECOUP

TABLE_5_ITEM

1
G

SUD70N03
TO-252

D4

R4508

C334
1000UF

20%
2 2.5V
POLY
SM

C1030
0.1UF

C1034
0.01UF

5%
2 50V
CERM
603

20%
2 16V
CERM
603

XW28
SM

SEE_TABLE
1

1%
1/10W
FF
2 805
NOSTUFF

10%
50V
CERM 2
603

20%
2 4V
TANT
SMD

SEE_TABLE
1

1%
1W
MF
2512

TO-252

C960
10UF

10%
2 16V
CERM
1210

R361
0.0082

S 3

C947
330UF

45_I526
SUD70N03

1
G

C4504

NOSTUFF

Q51

MR_FLO_1

C1029
0.0022UF

1%
1W
MF
2512

5%
2 25V
CERM
603
NOSTUFF

S 3

20%
2 2.5V
POLY
SM

20%
2 4V
TANT
SMD

SEE_TABLE
1

CPU_VCORE_SLEEP

1000PF

Q49

C336
1000UF

SEE_TABLE
1

C347
1000UF

20%
2 2.5V
POLY
SM

XW31

C361
1000UF

20%
2 2.5V
POLY
SM

SEE_TABLE
1

C362
330UF

20%
2 4V
TANT
SMD

SEE_TABLE
1

C348
1000UF

20%
2 2.5V
POLY
SM

SEE_TABLE
1

C957
330UF

20%
2 4V
TANT
SMD

SEE_TABLE
1

C346
1000UF

20%
2 2.5V
POLY
SM

SM
2
1

XW30
SM

R935
10 2
1
1%
1/16W

R362
0.0082

SM
1

SEE_TABLE
1

C340
330UF

R4705
0

D43
MBRS340T31

R386
0 2

10%
50V
CERM
402

TABLE_5_ITEM

103S0041

D 4 SEE_TABLE

MF 5% 603
1/16W

45C7<

5%
1/16W
MF
2 603

NOSTUFF 2

10%
50V
CERM
1210

MF
603

VCORE_BG_1

5%
1/16W
MF
2 603

L24
2.2UH

C1038
0.22UF
1

45C7<>

TO-252

CORE_MOSFET_1

20%
2 2.5V
POLY
SM

NOSTUFF
1

SMC

VCORE_BOOST_1

VCORE_TG_1
VCORE_BOOST2_1

NOSTUFF
1

R4704
0

SUD50N03

BRE_1

5%
1/16W
MF
603

PG_E

45C7>

R4702
7.5K
0.1%
1/8W
TF
805

Q50
1
G
S 3

0.1%
1/8W
TF
2805

0.1%
1/10W
FF SEE_TABLE
2805

5%
2 25V
CERM
402

SEE_TABLE

C335
1000UF

TRANS_ADJ

5%
1/16W
MF
603

D 4 SEE_TABLE

SEE_TABLE
1

C337
1000UF

20%
2 2.5V
POLY
SM

NOSTUFF

R4703
0 2
1

44D8< 45D3<> 45D7<


49C4<> 49D3<> 49D7<>
50D5<> 51A5< 51A7<
52C1> 59D7>

MBR0540

5%
2 50V
CERM
402

45C8<> 45C7<> VCORE_SGND

51B7< 51C3< 51D7<>


50B4<> 50C4<> 50D2<
48C8<> 48D6<>
+12V_MAIN 48C4<>
36D8< 39C8< 42B3<

D21

5%
50V
2 CERM
603

XW26

45D5<> 45D7<>

5%
1/16W
MF
2 603

5%
1/16W
MF
603

R47091
0

C1046
0.01UF

SM

VCORE_INTVCC

R4701
0 2
1

20%
16V
2 CERM
603

1%
1W
MF
2512

VCORE_SEN+

NOSTUFF

C1048
0.1UF

FLO_KNOWS_BEST

C1006
10UF

10%
16V
2 CERM
1210

R800
0.0082
1

1%
1/10W
FF
2 805
NOSTUFF

TO-252

10%
50V
CERM 2
603

1%
1/16W
MF
603

SUD70N03

4D3< 4D7< 8B7< 8C1< 52C6> 59B5> 59D7>

R801
0.0082

C4509

CPU_VCORE_SLEEP

R4706
0

SM

1
G

R928
10

D41

MF 5% 603
1/16W

SMC

1
G

NOSTUFF

L20
2.2UH

10%
50V
CERM
402

MF

TO-252

Q43
1

C953
10UF

R4707
0

D 4 SEE_TABLE

28

10%
2 16V
CERM
1210

SUD50N03

PGND

C966
10UF

10%
2 16V
CERM
1210

S 3

C1039
0.22UF

C371
0.001UF

SGND

C950
10UF

10%
2 16V
CERM
1210

Q44

1%
1/16W
MF
603

VOSNS2
ITH2 11
RUN/ 15
SS2

52C6> 59C7>
4D5< 6C5< 6D6< 7A3< 7B3< 7C3< 7C5< 7C7< 8A3<>
8D1< 8D4< 9B7< 9D8< 44B7< 44D1< 44D2< 46D4<

D44
SM
MBRS130T3

NOSTUFF

D 4 SEE_TABLE

VCORE_BOOST
R896
10 2
1

12

PGOOD

C951
10UF

10%
2 16V
CERM
1210

5%
1/16W
MF
603

45D8< 45C7< FLOW_SS

5%
16V
CERM
603 2

QTY

10%
16V
2 CERM
1210

45C7<> SUPER_FLO

C1049 1
0.047UF

PART#

C965
10UF

NOSTUFF

VCORE_INTVCC

MBR0540
R384
0 2
1

VCORE_TG
VCORE_BOOST2
CORE_MOSFET
VCORE_BG

SNS2- 13

VOSNS1
ITH1
RUN/
SS1
FCB
FREQSET
STBYMD

1%
1/16W
MF
603

5%
50V
CERM
603

SNS2+

45C8<> 3 SNS1-

45C8<>
45C7<>
45B7<> VCORE_SGND

R934
10K 1
2

16

17

10%
16V
2 CERM
1210

NOSTUFF

18

NOSTUFF
1

C952
10UF

SM
2

26

5%
50V
CERM
603 2

1%
1/16W
MF
2 603

5%
50V
CERM
603

C1052
470PF

45B5<
45B5<

SSOP
TG2
TG1
BOOST2
BOOST1
45C4<> SW2
SW1
23 BG1
BG2

VCORE_FREQSET
VCORE_STBY
C1050 1
0.01UF

R932
10K

C373
47PF

10

25

515-1563

24

U47
LTC3707

27

FLO_KNOWS_BEST
45C7<> SUPER_FLO
45D8< 45C6< FLOW_SS

SENSE- 45C6<
FLO_KNOWS_BEST 45C7<> 59D5>
VCORE_SGND 45B7<> 45C7<>

21

EXT INT VIN 3.3


VCC VCC
VOUT
45C8<>
45C7<> 45B7<>

10%
16V
2 CERM
1210

C1047
4.7UF

NO_TEST

R933
30.1K

C964
10UF

20%
16V
2 CERM
1206-1

VCORE_EXTVCC

SM

C963
10UF

VC_SENA

D45
SM
MBR0540

R899
0

10%
50V
2 CERM
1210

VC_CNTL1
44C7<

NOSTUFF
1

1
1

45C7< 45C6< FLOW_SS


3

+12V_MAIN 36D8<

5%
1/16W
MF
603

51B7< 51C3< 51D7<> 52C1> 59D7>


39C8< 42B3< 44D8< 45B4<> 45D7< 48C4<> 48C8<> 48D6<>
49C4<> 49D3<> 49D7<> 50B4<> 50C4<> 50D2< 50D5<> 51A5< 51A7<

R908
4.7 2

+5V_MAIN

5%
1/16W
MF
603

VCORE_SENA+

R936
10 2

1
1%
1/16W

VCORE_SEN+_1

MF
603

CPU_VCORE_SLEEPB

MF
603

CPU_VCORE_SLEEPC

CPU_VCORE_SLEEP
1.0GHZ,1.5V+30/-130MV,35W
1.25GHZ,1.57V+70/-70MV,35W
TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

128S0012

CAP,TANT,POLY,330UF,4.OV,D4

128S0410

CAP,TANT,POLY,1000UF,2.5V,D4

128S0022

12

C340,C947,C362,C957

1_25GHZ_DECOUP

CPU & AGP VREGS

TABLE_5_ITEM

C337,C335,C336,C334,C347,C361,C348,C346

1_25GHZ_DECOUP
TABLE_5_ITEM

CAP,EL,POLY,220UF,20%,2V

1GHZ_DECOUP

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION

C337,C335,C336,C334,C347,C361,C348,C346,C340,C947,C362,C957

376S0204

MOSFET,N-CH,30V,63A,V30284,TO-252

Q44,Q50

376S0207

MOSFET,N-CH,30V,70A,V30289,TO-252

Q43,Q49

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:30:39 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

TABLE_5_ITEM

TABLE_5_ITEM

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
45 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

INTREPID MAXBUS & CPU OVDD POWER CONVERTER


(OFF DURING SLEEP)

+MAXBUS_SLEEP 1.8V,+/-2%,.606W

D
+5V_SLEEP

59D7> 51C8< 51C5<> 50D5< 46C7< 38C1<

+1_8V_MAIN

+3V_MAIN
R372

D19
2

R385
0

MBRS130T3

5%
1/4W
FF
2 1210

SM

59D7> 51C8< 51C5<> 50D5< 46D6<> 38C1<

+5V_SLEEP

10K

1%
1/16W
MF
2 402

SOP-8
2

MAXBUS_PWR_EN

1%
1/16W
MF
603

IN
EN

OUT
ADJ

NOSTUFF
1

3
4

R959

MAX_PWR_ADJ

150

C4081
0.47UF

10%
16V
2 X7R
805

6 7

C363
22UF

1%
1/16W
MF
2 402

GND
1

4D5< 6C5< 6D6< 7A3< 7B3< 7C3< 7C5< 7C7< 8A3<> 8D1<
8D4< 9B7< 9D8< 44B7< 44D1< 44D2< 45D2<> 52C6> 59C7>

R927

MIC39102
KYLE

200K 2
1

+MAXBUS_SLEEP

CRITICAL

VR4
R4801

5%
1/4W
FF
1210

20%
2 10V
CERM
1210

C365
22UF

20%
10V
2 CERM
1210

R930
22.1K

1%
1/16W
MF
2 402

MAXBUS I/O SUPPLY SUPPORT


PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

114S4754

RES,FF,47.5K-OHM,1%

R930

CRITICAL

BOM OPTION
MAXIO_150V

114S3014

RES,FF,30.1K-OHM,1%

R930

MAXIO_165V

114S2674

RES,FF,26.7K-OHM,1%

R930

MAXIO_170V

114S2214

RES,FF,22.1K-OHM,1%

R930

MAXIO_180V

+1_5V_AGP 1.5V,+/-5%,.6W

AGP I/O POWER CONVERTER


+3V_MAIN

+1_5V_AGP 10D6<

11A6< 16A8< 16C2< 16D7< 17A3< 17A4< 17D5<


52C3> 59C7>

+3V_MAIN

NOSTUFF

R610

D33

+INTREPID_CORE_MAIN 10D6<

11D3< 47B2<> 59C7>

5%
1/4W
FF
1210

MBRS130T3
SM

R945

CRITICAL

100K

R518
10K

1%
1/16W
MF
2 402

1%
1/16W
MF
2 402

VR2
MIC39102

NOSTUFF
1

SOP-8
2
1

47A6<>

IN
EN

OUT
ADJ

R958

3
4

150

AGP_PWR_ADJ

1%
1/16W
MF
2 402

GND

IPWRGD

5 6

C1053
0.1UF

10%
16V
2 X7R
603

7 8

C171

C138
22UF

20%
10V
2 CERM
1210

R519

22UF

20%
2 10V
CERM
1210

47.5K
1%
1/16W
MF
2 402

AGP I/O SUPPLY SUPPORT

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

114S4754

RES,FF,47.5K-OHM,1%

R519

AGPIO_150V

114S3014

RES,FF,30.1K-OHM,1%

R519

AGPIO_165V

114S2674

RES,FF,26.7K-OHM,1%

R519

AGPIO_170V

114S2214

RES,FF,22.1K-OHM,1%

R519

AGPIO_180V

CPU & AGP VREGS

BOM OPTION
*

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:30:40 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
46 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

+5V_MAIN
XW14
SM

+5V_MAIN

RT401P1

10

1%
1/16W
MF
603

NOSTUFF

1K

MBR0530

C273

1000PF

NOSTUFF

C298

10UF

5%
25V
2 CERM
603

INTCORE_VCC

SM

R317

1%
1/16W
MF
603

R318

C297

10UF

10%
16V
2 CERM
1210

C305

10UF

10%
16V
2 CERM
1210

10%
16V
2 CERM
1210

C299

10UF

C301

150UF

10%
16V
2 CERM
1210

C300
150UF

20%
2 6.3V
POLY
SMD

20%
2 6.3V
POLY
SMD

D13

C283 1
0.1UF

+5V_MAIN

20%
16V
CERM 2
603

59C7> INTREPID_VSENSE

INTCORE_1

+5V_MAIN

INTCORE_BSTH_TERM

R299
51.1

Q26

R296
1

20

1/16W 603 1% MF

XW13
SM

INTCORE_OVP
ICORE_COMP

1UF

10%
10V
X5R
2 603

C286

0.1UF
2

C285

SM

10PF
2

5%
50V
CERM
603

5%
1/16W
MF
603

XW15
SM
INTCORE_GND

46A8<

0.1UF

RT406P2

C270

0.0022UF

XW12
SM
1

INTREPID_VPWRA

+3V_MAIN

C265

20%
16V
2 CERM
603

L19

D4901
SM
MBR0540
1

+INTREPID_CORE_MAIN 10D6<

11D3< 46B3< 59C7>

SM1

1
5

6 7

C4702
1000PF

IRF7807Z

SO-8

5%
25V
2 CERM
603
NOSTUFF

47_I66
1

R4710

NOSTUFF

3.8UH

Q25
INTREP_DLT

1/8W
TF
805

1UF

CRITICAL

6.98K
0.1%

1/16W
FF
603

10%
2 10V
CERM
805

2 3

R301

C282

C262

20K
0.1%

0.1UF

20%
2 16V
CERM
603

5%
25V
CERM
805

MBR0530

14

1/16W
MF
603

1%
1/16W
MF
2 402

R295

5%
1/16W
MF
603

D14

C266

PGND 7
PWRGD 2

12 COMP

GND

30.1K
1%
ICW

4 OCSET
PHASE 5
13 SS/SHDN
DL 8
11 SENSE
3 OVP

R320
INTCORE_DH
INTREPID_VPWR
INTCORE_DL

DH 6

NO_TEST

R316

R309
1K

SO

INTCORE_DHT

INTCORE_OCSET
GPWRGD

INTCORE_BSTH

BSTH 10
BSTL 9

SC2602

1%
1/16W
MF
603

CRITICAL

VCC

U31

7 8

SO-8

48A5<>

5 6

IRF7807Z

R304

1 2

10%
50V
CERM
402

CRITICAL

C284
0.1UF
20%
16V
CERM
603

C928
220UF

20%
2 2V
TANT
7343

CRITICAL CRITICAL

C296

220UF
20%
2V
TANT
7343

C935
220UF

20%
2 2V
TANT
7343

1%
1/10W
FF
2 805
NOSTUFF

NOSTUFF
1

R315

+INTREPID_CORE_MAIN (MEASURED), 1.7V +/-50MV, 3.752W


+INTREPID_CORE_MAIN (BUDGET MAX), 1.7V +/-50MV, 6W

100

5%
1/10W
FF
2 805

IPWRGD

INTREPID CORE
A

NOTICE OF PROPRIETARY PROPERTY

TABLES FOR INTREPID CORE RESISTOR VALUES TO VOLTAGES ARE LOCATED AT


KUMA SERVER(1):HARDWARE:KUMA DESIGNS;KUMA POWER SUPPLIES;ICORE R TOLERANCE

LAST_MODIFIED=Mon Oct 27 12:30:42 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
47 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

59D7> 52C1> 51D7<> 51C3< 51B7< 51A7<


51A5< 48C4<> 45D7< 45D3<> 45B4<> 44D8< 42B3< 39C8< 36D8< +12V_MAIN
50D5<> 50D2< 50C4<> 50B4<> 49D7<> 49D3<> 49C4<> 48C8<>

R523

D30

10
1%

XW7
SM

+12V_MAIN

C220

C634
10UF

150UF

10%
16V
2 CERM
1210

20%
2 16V
ELEC
SM-1

C633
10UF

10%
16V
2 CERM
1210

C631
10UF

10%
16V
2 CERM
1210

RB37P1

C632

10UF

C596
330PF

10%
16V
2 CERM
1210

10%
50V
2 CERM
603

GRAPH_CORE (NV18B), 1.6V +/-100MV, 12W


GRAPH_CORE (NV34), 1.45V +/-100MV, 16W

MBR0530
SM

1/16W
MF
603

2
TABLE_5_HEAD

PART#

GCORE_VCC

QTY

DESCRIPTION

R529

TABLE_5_ITEM

110S5233

RES,5.23K OHMS,1%,1/16W,0603

R499

NV18B

110S2943

RES,2.94K OHMS,1%,1/16W,0603

R499

NV34

TABLE_5_ITEM

1.5K

1%
1/16W
MF
2 603

R505

C589

10

0.1UF

1%
1/16W
MF
2 603

20%
16V
2 CERM
603

NO_TEST

SEE_TABLE

48B6<> GCORE_VSENSE

R499

5.23K
1%

BSTH 10

U40

BSTL 9

GCORE_OCSET
MPWRGD
GCORE_VSENSE
GCORE_OVP
GCORE_COMP
NO_TEST

48C4<>

R527

R503

1K
1%

C572

RB27-1

0.1UF

5%
2 25V
CERM
805

11 SENSE
3 OVP

(+12V_MAIN)

GCORE_DH
GRAPHICS_VPWR
GCORE_DL

5%
1/16W
MF
603

1%
1/16W
MF
2 603
SEE_TABLE
1

C552

L12

RES,3.92K,1%,1/16W,0603

R503

RES,2.61KK,1%,1/16W,0603

R503

2
SEE_TABLE

SMC

SUD70N03
0

D4

S 3

0.1UF

MBRS340T3

C528

1000UF

20%
16V
2 CERM
603

20%
2 2.5V
POLY
SM

SEE_TABLE
1

C106

NOSTUFF
1

1000UF

20%
2 2.5V
POLY
SM

C558

1000UF

20%
2 2.5V
POLY
SM

SEE_TABLE

C132
1

NOSTUFF
1

1000UF

20%
2.5V
2 POLY
SM

C59

1000UF

C88

1000UF

20%
2.5V
2 POLY
SM

20%
2 2.5V
POLY
SM

NOSTUFF
1

C71

1000UF

20%
2 2.5V
POLY
SM

NOSTUFF
1

R475
100

5%
1/10W
FF
2 805

48_I99
1

NOSTUFF

Q34

D4

SUD70N03
TO-252

QT1P1

NV34

C543

5%
2 25V
CERM
603

5%
1/16W
MF
603

NV18B

C4801
1000PF

1
G

R515
1

SEE_TABLE

NOSTUFF
1

NOSTUFF

D31
SM
Q7

TABLE_5_ITEM

110S2613

MBRS130T3
1

2.2UH

TABLE_5_ITEM

110S3923

S 3

GCORE_GND

D34
SM

TO-252

QT2P3

20%
16V
CERM 2
603

17D4< 23C7<> 52A6>

SUD50N03

BOM OPTION

GRAPH_CORE

RB22P2

Q8
1
G

C585 1

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)

20%
16V
2 CERM
603

+2_5V_MAIN
NOSTUFF

0.1UF

20%
2 16V
CERM
603
SEE_TABLE

C564
0.1UF

TO-252

MBR0530

10PF

0.1UF

1%
1/16W
MF
2 402

5%
1/16W
MF
2 603

D32
SM

C563

5%
50V
CERM
603 2

51.1

XW2
SM

SEE_TABLE
1

R496

GCORE_1 NO_TEST

R4803

SUD50N03

XW6
SM

GND

S 3

PWRGD 2

XW39
SM
DESCRIPTION

SEE_TABLE

D 4

14

1/16W
MF
603

20%
25V
2 CERM
603

PGND 7

12 COMP

C576

Q9

QT2P1

20K
1%

0.1UF

1
G

TO-252

QTY

D4

R150

PART#

R504

3.92K

1/16W
MF
603
2

SO

4 OCSET
PHASE 5
13 SS/SHDN
DL 8

51B7<
50B4<>
45D7<
36D8< +12V_MAIN
44D8<
49C4<>
50D5<>
52C1>

NO_TEST
GCORE_BSTH

SC2602

DH 6

1/16W
MF
603
48_I10

51D7<> 51C3<
50D2< 50C4<>
48D6<> 48C8<>
42B3< 39C8<
45D3<> 45B4<>
49D7<> 49D3<>
51A7< 51A5<
59D7>

VCC

MPWRGD

BOM OPTION

49B5<> 48B7< 49B5<> 48B7<

REFERENCE DESIGNATOR(S)

GCORE_BSTH_TERM

1
G
S 3

R4802
1

1%
1/10W
FF
2 805
TABLE_5_HEAD

NOSTUFF
TABLE_5_ITEM

132S1057

CAP,0.1UF,16V,20%,0603

C552

NV18B

132S0059

CAP,0.15UF,10V,10%,0603

C552

NV34

C586

10%
50V
CERM
402

PART#

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

0.0022UF

TABLE_5_ITEM

QTY

128S0410

CAP,TANT,POLY,1000UF,2.5V,D4

C106,C132,C88

1_25GHZ_DECOUP

128S0410

CAP,TANT,POLY,1000UF,2.5V,D4

C106,C132,C88

1GHZ_DECOUP

TABLE_5_ITEM

TABLE_5_ITEM

131S1013

CAP,10PF,50V,5%,0603

C563

NV18B

131S4715

CAP,47PF,50V,5%,0603

C563

NV34

GPWRGD 47B8<
TABLE_5_ITEM

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION

GRAPHICS CORE

TABLE_5_ITEM

376S0204

MOSFET,N-CH,30V,63A,V30284,TO-252

Q9

376S0207

MOSFET,N-CH,30V,70A,V30289,TO-252

Q7

TABLE_5_ITEM

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:30:43 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
48 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

D
59D7> 52C1> 51D7<> 51C3< 51B7< 51A7< 51A5<
48C4<> 45D7< 45D3<> 45B4<> 44D8< 42B3< 39C8< 36D8< +12V_MAIN
50D5<> 50D2< 50C4<> 50B4<> 49D3<> 49C4<> 48D6<> 48C8<>

MAIN MEMORY DDR AND FRAME BUFFER POWER CONVERTER (2.50VDC)


+12V_MAIN

R888

10
1%

51B7< 51C3< 51D7<> 52C1> 59D7>


36D8< 39C8< 42B3< 44D8< 45B4<> 45D3<> 45D7< 48C4<> 48C8<>
48D6<> 49C4<> 49D7<> 50B4<> 50C4<> 50D2< 50D5<> 51A5< 51A7<

XW25
SM

1/16W
MF
603
2

RB227P1

25V_VCC
1

C1019 1
20%
16V
CERM 2
603

NOSTUFF

R884

1K
1%

0.1UF

10UF

C968
10UF

10%
2 16V
CERM
1210

10%
2 50V
CERM
402

C959

470PF

1/16W
MF
603

MBR0530

C1005

10%
2 16V
CERM
1210

C975
10UF

C989

10UF

10%
2 16V
CERM
1210

C342
150UF

10%
2 16V
CERM
1210

SM

C351
150UF

20%
2 16V
ELEC
SM-1

20%
2 16V
ELEC
SM-1

D18

25V_OCSET

25V_VSENSE NO_TEST
25V_BSTH_TERM

25V_BSTH

1%
1/16W
MF
603

VCC
BSTH 10

U45

BSTL 9

R873

SC2602

SO
25V_DH
DH 6
4 OCSET
49C4<>
PHASE 525V_VPWR
13 SS/SHDN
25V_DL
DL 8

PGOOD

R883
4.75K
25V_COMP_DWN

C1015

0.1UF

5%
25V
CERM 2
805
1

C359

R371

1K

0.1UF

1%
1/16W
MF
603

20%
2 16V
CERM
603

2
1%
1/16W
MF
603

11 SENSE
3 OVP

25V_OVP
12
25V_COMP
NO_TEST

25V_DHT

5%
1/16W
MF
603

1
G

25_CORE_1 NO_TEST

C962
0.1UF

20%
2 16V
CERM
603

RB213P2

+2_5V_MAIN

TO-252

L21

S 3

XW23
SM

D46
SM

59D7>
52C4
30B3<

+3V_MAIN

MBRS130T3
1
2
1
D 4 SEE_TABLE

R827
0

25V_DLT

5%
1/16W
MF
603

Q27
1
G

SUD70N03
TO-252

S 3

C948

49_I70

2 NOSTUFF

NOSTUFF
1

C330

C323

330UF

20%
2 6.3V
POLY
SMD

MBRS340T3

330UF

20%
2 6.3V
POLY
SMD

C332
330UF

20%
2 6.3V
POLY
SMD

20%
2 6.3V
POLY
SMD

R334
100

C329 1
0.1UF

1%
1/10W
FF
2 805
NOSTUFF

C218
330UF

D15
SM

10%
50V
2 CERM
402

MPWRGD

5%
2 25V
CERM
603
NOSTUFF

R4901

0.0022UF

XW41
SM

C4901

1000PF

NOSTUFF
1

25V_GND

1/16W
MF
603

4.0UH

10PF

1/16W
MF
603

SM1

C1000

5%
50V
2 CERM
603

20%
25V
2 CERM
603

GND

20%
2 16V
CERM
603

0.1UF

PWRGD 2

COMP

MBR0530 1

0.1UF

C358

22.1K
1%

25V_VPWRA

D42

C1004

20K
1%

SUD50N03

PGND 7

14

1%
1/16W
MF
2 402

R871

Q28

SM

51.1

R880

XW24
SM

50A6> 49B7< 50A6> 49B7< PGOOD

R872

49B5<> 25V_VPWR
49D3<>
48C4<> 51D7<>
45B4<> 51A7<
39C8< 36D8< +12V_MAIN
44D8< 42B3<
45D7< 45D3<>
48D6<> 48C8<>
50B4<> 49D7<>
50D2< 50C4<>
51A5< 50D5<>
51C3< 51B7<
59D7> 52C1>
D 4 SEE_TABLE

R369
20

20%
16V
CERM
603 2

NOSTUFF

C324

330UF
20%
6.3V
POLY
SMD

C235

330UF
20%
6.3V
POLY
SMD

C331

5%
1/10W
FF
2 805

330UF
20%
6.3V
POLY
SMD

48B7<

+2_5V_MAIN, 1.61V +/-50MV, 12.908W

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

376S0204

MOSFET,N-CH,30V,63A,V30284,TO-252

Q28

376S0207

MOSFET,N-CH,30V,70A,V30289,TO-252

Q27

MEMORY PS

TABLE_5_ITEM

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:30:44 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
49 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

59D7> 52C1> 51D7<> 51C3< 51B7< 51A7<


51A5< 48C4<> 45D7< 45D3<> 45B4<> 44D8< 42B3< 39C8< 36D8< +12V_MAIN
50D2< 50C4<> 50B4<> 49D7<> 49D3<> 49C4<> 48D6<> 48C8<>
DEV

R3701

787

C339
100UF

100UF

20%
2 35V
ELEC
SM-1

PWRS_Q59

20%
2 35V
ELEC
SM-1

100UF
20%
35V
3.8V_TRICKLE
36D8<
44C2<
44C6<
44D7<>
52C1>
52C2>
ELEC
SM-1

R1013
10K

R682

FERR-250-OHM

TH
1

PWR_UP*

16

15

14

13

11

10

50C3< 42D8< 39C8<


59D5> 51C6<

22.1K2

PWR_UP

C955

C356

10UF

100UF

10%
16V
2 CERM
1210

10%
16V
2 CERM
1210

C354
100UF

20%
2 35V
ELEC
SM-1

C355
100UF

20%
2 35V
ELEC
SM-1

20%
2 35V
ELEC
SM-1

SM

C971

10UF

PWR_FAIL* 44B1<>

10UF

10%
16V
2 CERM
1210

L86

C970

C986

10UF

10%
16V
2 CERM
1210

C985

10UF 51B7<

10%
16V
2 CERM
1210

10%
16V
2 CERM
1210

51A7< 51A5< 50D5<> 50C4<> 50B4<>


45D7< 45D3<> 45B4<> 44D8< 42B3< 39C8< 36D8< +12V_MAIN
49D7<> 49D3<> 49C4<> 48D6<> 48C8<> 48C4<>
59D7> 52C1> 51D7<> 51C3<

PWR_FAIL_T
+12VSD_T
+5VSD_T

R323

+12V_SLEEP

47K

29A3< 29A8< 29C5<> 51A5< 51C2< 51D6<> 52C1> 59D7>

L84

FERR-250-OHM

50C8<

+5V_SLEEP 38C1<

2N7002
1

(517-0886)

FW_PWR

2N3904

SM

46C7< 46D6<> 51C5<> 51C8< 59D7>


2

SM

Q39

Q22

RUNSS

NOSTUFF

SHS

1%
1/16W
MF
603

5%
1/16W
MF
2 603

SM

3
1

SW5V_RUNSS

50B8<

FERR-250-OHM

PWRS_Q26

R721

C956
10UF

10%
16V
2 CERM
1210

DEV

10UF

GREEN

SM

12

C979

DS9

1%
1/16W
MF
2 402

L85

M-ST-43045

1%
1/16W
MF
2 402

10%
16V
2 CERM
1210

MAIN_SUPPLY_LED
1

10K

J17

C978
10UF

1%
1/16W
MF
603 2

C338

CRITICAL

C349

29B3< 36D6< 51D4<> 52B6>

C241

3
1

10UF

Q23

59D5> 51C6< 50C8< 42D8< 39C8<

PWR_UP

SM

R322

2N7002

2N7002

20%
2 16V
ELEC
SM

Q24

47UF

10%
2 16V
CERM
1210

SM

C295

SM

SW3V_RUNSS

5%
1/16W
MF
2 603

Q21

2N7002

PWRS_Q59

R1014
47K

SW3V5V_12VIN

5%
1/16W
MF
603

C937

59C5> 44B5<>
5 6

R794
0
50B8<> 50B7<> 50A8<> 50A7<>

MBR0540
SW3V5V_VIN

RT418P2

21

XW17
SM
50B5< SW5V_TG1
50A5< SW5V_BOOST1

C930

180PF
1

50A5<>
50A5<

5%
50V
CERM
402

R799

VOSNS1 2 107K 1
MF

50B8<> 50B7<>
50C7< 50A8<> 50A7<> SW3V5V_SGND

470PF402
1

SW5V_SW1
SW5V_BG1

SW5VITH1R

5%
25V 50C7<
CERM 50B8<>
603 50B7<>

SW3V_SNSP

50A5<

SW5V_SNSM

SNS1-

SNS2- 13

SW3V_SNSM

SW5V_VOSNS
SW5V_ITH1

VOSNS1
ITH1
RUN/
SS1
FCB
FREQSET
STBYMD

8
1

50C7<
50A8<> 50A7<>
50B8<>

SW3V5V_SGND

7
5

STBYMD

CERM

50A8<> 50A7<> SW3V5V_SGND

15K

17
19

SNS2+ 14

R331

1000PF

18

C341 1

C321

20%
16V
CERM 2
1206-1

5%
50V
CERM
603

4.7UF

1%
1/16W
MF
603

50B8<>
50B7<>
50C7< 50A7<> SW3V5V_SGND

C316

220PF402
1

SW3V_ITH2

5%

PGOOD 28

XW22
SM

1%
1/16W
MF
2 603

50B7<>

SW3VITH2R

5%
25V
CERM
603

15K

1%
1/16W
MF
603

50B7<> 50A5<>

R3321

C322

5%
50V
CERM
603

5%
50V
CERM 2
603

2200PF

C933
0.01UF

5%
50V
CERM
603

SW5V_BOOST1

SW5V_SW1

DESCRIPTION

REFERENCE DESIGNATOR(S)

10

MOSFET,N-CH,30V,63A,V30284,TO-252

XW19
SM
1

51B7< 51C3< 51D7<> 52C1> 59D7>


36D8< 39C8< 42B3< 44D8< 45B4<> 45D3<> 45D7< 48C4<> 48C8<>
48D6<> 49C4<> 49D3<> 49D7<> 50C4<> 50D2< 50D5<> 51A5< 51A7<

RB160P1

R815

Q48

1%
1W
MF
2512

SUD50N03

1
G

TO-252
S 3

10%
50V
CERM
1210

L22
4.0UH

Q47

1
G

NOSTUFF

C938

0.01UF
1

R798
10

R797
10
1%
1/16W
MF
603

5%
25V
CERM 2
603
50_I410
NOSTUFF

D 4 SEE_TABLE

C932
2

SM1

1000PF

MF 5% 603
1/16W

5%
50V
CERM
603

SUD50N03
TO-252

+5V_MAIN

C309
150UF

R805

20%
2 6.3V
POLY
SMD

0.0052

NOSTUFF
1

NOSTUFF

C306

150UF

C307
150UF

20%
2 6.3V
POLY
SMD

20%
2 6.3V
POLY
SMD

NOSTUFF

D40
SM
1

MBRS340T3

20%
2 6.3V
POLY
SMD

XW18
SM
1

C308
150UF

1%
1/16W
MF
603

C302
150UF

20%
2 6.3V
POLY
SMD

C287
10UF

10%
2 16V
CERM
1210

C293

0.1UF

20%
2 16V
CERM
603

R5003

C294

0.01UF

5%
2 50V
CERM
603

470
5%
1/10W
FF
2 805

CRITICAL

R5002

1%
1/10W
FF
2 805
NOSTUFF

5%
1W
MPL
2512

1
2

S 3

C5002 1

SW5V_BG1R

R810

49B7<

MBRS130T3

0.0102
1

D 4 SEE_TABLE

SW5V_SW1
1

SW3V5V_SGND

D37
SM
2

NOSTUFF

DC/DC CONVERTER

C310

150UF

20%
2 6.3V
POLY
SMD

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:30:47 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

XW16
SM

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

SW5V_5VSENSE

1
II NOT TO REPRODUCE OR COPY IT

SW5V_SNSMA

TABLE_5_ITEM

376S0204

5%
50V
CERM 2
603

+5V_MAIN, 5.1V +/-3%, 32.172W

+12V_MAIN

C940
1

10%
50V
CERM
402

BOM OPTION

C927 1

0.01UF

SW5V_TG1R

5% 603

SW5V_BG1
SW5V_SNSP
SW5V_SNSM

TABLE_5_HEAD

QTY

1%
1/16W
MF
603

PART#

10%
16V
2 CERM
1210

20%
2 6.3V
POLY
SMD

50C6<>

0.001UF

PGOOD

20%
16V
2 CERM
603

0.22UF

50B7<

10UF

150UF

20%
2 6.3V
POLY
SMD

C934

R807

R335

50B7<

C328

150UF

150UF

XW20
SM

MBRS340T31

(THIS PAGE)

MF

50B8<>
50B7<>
50C7< 50A8<>

0.01UF

20K

1%
1/16W
MF
603 2

C939 1

1 NOSTUFF

C326

1%
1/16W
MF
603

SW3V5V_INTVCC

1/16W

SW5V_TG1

50A5<>
50B7<>
50B7<>

1%
1/10W
FF
2 805
NOSTUFF

D39
SM

20%
2 6.3V
POLY
SMD

SM
2

R330

1000PF

MBR0540

R795

2 3

C327

NOSTUFF 2
1

0.1UF

SW3V_3VSENSE
5V_XRA

D17

R5001

C926

10

1%
1/16W
MF
603

VOSNS2

5%
50V
CERM
402

R803

R802

180PF

50_I408

SO-8

5%
50V
CERM
603

10

C333

IRF7807Z

NOSTUFF

0.01UF

1
1

5%
1/16W
MF
603

20

CRITICAL

1%
1W
MF
2512

10%
50V
CERM
402

62K

SW3V_BG2R

C344

PGND

6 7

5%
25V
CERM 2
603
NOSTUFF

Q45

MF 5% 603
1/16W

20K

CERM

1000PF

0.0082
1

2
SM1

C5001

R337

R804

XW21
SM

25V

C315
2

50B6>

50B6<> SW3V_SW2

+3V_MAIN

R808

10UH

1%
1/16W
MF
603

0.01UF

L23

C931
+3V_MAIN0.001UF

50B7>

SW3V_VOSNS NO_TEST
VOSNS2 12
SW3V_ITH2 50A7<
ITH2 11
15
50C1< SW3V_RUNSS
RUN/
SS2

10%
50V
CERM
1210

SW3V_TG2 NO_TEST
SW3V_BOOST2
SW3V_SW2 50C4<>
SW3V_BG2

SNS1+

SGND

C317

16

10%

SSOP
TG2
TG1
25 BOOST1
BOOST2
26 SW1
SW2
23 BG1
BG2

SW5V_SNSP

NO_TEST

C318
50V

27

50A5<

1%
603
1/16W

50D1< SW5V_RUNSS

10

U33
LTC3707

R811

10

24

+3V_MAIN, 3.3V +/-3%,7.567W

SW3V_BOOST2R

EXT INT VIN 3.3


VCC VCC
VOUT

20%
2 10V
CERM
402

SO-8

C941

NC_SW3V5V_33OUT
NO_TEST

C303

0.22UF
2

MBR0540
22

IRF7807Z

1 2

D16
SM

50B5<> SW3V5V_INTVCC

+5V_MAIN

SW3V_TG2R

1%
1/16W
MF
603

D38
SM

5%
1/16W
MF
603 2

SW3V5V_SGND

10

SM

Q46

R336

0.1UF

SLEEP

7 8

CRITICAL

20%
25V
2 CERM
603

NOSTUFF

5%
1/16W
MF
603

+5V_MAIN

0.1UF

4.7

SW3V_RUNSSR

51C3< 51D7<> 52C1> 59D7>


39C8< 42B3< 44D8< 45B4<> 45D3<> 45D7< 48C4<> 48C8<>
48D6<> 49C4<> 49D3<> 49D7<> 50B4<> 50D2< 50D5<> 51A5< 51A7<

+12V_MAIN 51B7<
36D8<

R806

SW3V_SW2A

SW5V_SW1A

50D3< RUNSS

50B6<

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

Q47,Q48
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569
A
50 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

7
+12V MAIN POWER SWITCH
(OFF DURING SLEEP)

+12V_SLEEP

3
FIREWIRE POWER SWITCH

EVALUATE CIRCUIT FOR SURGE PROTECTION FOR Q59C


FW_12V U35
SI4435DY

29A3< 29A8< 29C5<> 50D5< 51A5< 51C2< 52C1> 59D7>

SOI

50B4<> 49D7<> 49D3<>


45B4<> 44D8< 42B3<
48D6<> 48C8<> 48C4<>
51A7< 51A5< 50D5<>
59D7>

49C4<> 51B7<
39C8< 36D8< +12V_MAIN
45D7< 45D3<>
50D2< 50C4<>
52C1> 51C3<

52B6> 50C6<> 36D6< 29B3<

FW_PWR

Q20
1

FDC602P

R769

SOT-6

470K 2

S1

GATE
1

C915
CERM

47UF

C918

0.01UF
10% 402
16V

R770
100K

FW_12V

FW_12V

100K
5%
1/16W
MF
2 603

5%
1/16W
MF
603

Q1P3
3

Q1

2N7002

Q1P1

SM

R21

1%
1/16W
MF
2 603

Q14

470K 2

R22

10%
50V
CERM
402

10K

2N7002

SLEEP_OFF_L

1FW_12V

51B6<

Q42P4

2
5% 603
50V

R23

+5V_MAIN

SW12V_SL
D

C473
0.0022UF

FW_12V

1%
1/16W
MF
402 2

C18
CERM

10%
50V
CERM
402

52B6>

0.01UF
1

20%
2 16V
ELEC
SM

0.0022UF
SW12V_SLEEP

FW_PWR_SW 36D6<

FW_12V

20%
2 35V
ELEC
SM

C269

C19

47UF

D4
D3
D2
D1

5%
1/16W
MF
402

S3
S2

SM

FW_12V
2

R739
0

5%
1/16W
MF
2 402

+3.3VFPD (3_6V_SLEEP), 3.6V +/-50MV, 3.32W


PWR_UP

+5V_SLEEP

R300

R1017

Q37

+5V_MAIN

5%
1/8W
FF
2 1206

+5V_SLEEP 38C1<

1 DEV

DS5

C773

0.01UF
1

R645

R664

470K

5%
1/16W
MF
2 402

3_5_HONKER

C238

+5V_MAIN
FPD_3V3 1
+5V_MAIN
SENSE

150UF

0.0022UF
SWITCH5V_4

CERM 10% 402


16V

+5V POWER LED

20%
2 6.3V
POLY
SMD

10%
50V
CERM
402

100K

SWITCH5V_3

52C4 51B4<>
59D7>

59D7> 52C4 51B4<>

EZ1582
SM
VPWR VOUT
VCTRL VOUT
TAB
ADJ

2N7002

SLEEP_OFF_L

FPD_3V3

SM

5%
1/16W
MF
402

102

1%
1/16W
MF
2 402

10%
16V
2 CERM
1210

NOSTUFF

20%
2 6.3V
POLY
SMD

R277

100K

10%
50V
CERM
402

R279
10K

10K

1% FPD_3V3&FPD_12VM
1/16W
MF
2 402

1%
1/16W
MF
2 402

1%
1/16W
MF
402
2FPD_3V3&FPD_12VM

SWITCH5V_5

R601

TMDS_EN 23D7<>

NOSTUFF
1

182
1%
1/16W
MF
2 402

C254

R10121

C258
0.01UF

SEE_TABLE

20%
2 16V
CERM
402

100K
1%
1/16W
MF
402 2

FPD_12VS&FPD_12VM

DZ1

52B3>

1N5227B

44D6<>

SM

FPD_PWR_ON_T

5%
1/16W
MF
402

TESTPOINT

2N7002

NOSTUFF
1

R615

DEV
1

R302

5%
1/16W
MF
2 402

330

5%
1/16W
MF
2 402

47.5K
1%
1/16W
MF
2 402

R607
0

NOSTUFF
1

NOSTUFF
1

5%
1/16W
MF
2 402

R609

R740
10K

TESTPOINT

5%
1/16W
MF
2 402

TESTPOINT

TESTPOINT

RT373P1

DS6

1
NOSTUFF

R614

BT1_LED

470

2N7002

+5V/+12V, AUDIO
FW & TMDS PWR

BOM OPTION

114S1005

RES,100K OHM,1%,1/16W,O4O2,SMD

R1012

FPD_12VM

116S1000

RES,0 OHM,5%,1/16W,O4O2,SMD

R1012

FPD_3V3

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

DS10
RED

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

SM
2

JAZ1 1

SM
2

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

TESTPOINT

SIZE

TH-TP50
2

APPLE COMPUTER INC.

GENERAL POWER LED


(NOT ILLUMINATED = OK TO ADD MEMORY)

SLEEP LED

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:34:44 2003

SM

REFERENCE DESIGNATOR(S)

2N7002

DESCRIPTION

TABLE_5_ITEM

PWR_LED

1%
1/16W
MF
603

5%
1/16W
MF
402

Q19

787

QTY

TABLE_5_ITEM

SM
DEV

SLEEP_LED_BD

PART#

R612

3 DEV

5%
1/16W
MF
2 402

SLEEP2

R751

1%
1/16W
MF
2 402
FPD_3V3&FPD_12VM

TABLE_5_HEAD

TESTPOINT

GREEN

1%
1/16W
MF
2 402

Q18

100K

R608

SLEEPLED_TERM

R284

51C3< 51D7<> 52C1> 59D7>


39C8< 42B3< 44D8< 45B4<> 45D3<> 45D7< 48C4<> 48C8<>
48D6<> 49C4<> 49D3<> 49D7<> 50B4<> 50C4<> 50D2< 50D5<> 51A7<
+12V_SLEEP 29A3< 29A8< 29C5<> 50D5< 51C2< 51D6<> 52C1> 59D7>

TESTPOINT

SM

FPD_3V3&FPD_12VM

51B7<
+12V_MAIN 36D8<
TESTPOINT

Q13

TESTPOINT

R741

+12V_MAIN

+5V_MAIN

BT1

+3V_MAIN

23D7<>

(TESTPOINT LED IS USED TO FOR SERVICE AND


IF NOT ILLUMINATED, TELLS USER ITS OK TO ADD MEMORY)

CHOC_BROWNIE

FPD_PWR_ON

+5V POWER, SLEEP & TESTPOINT LEDS

3
D

0.022UF

10%
50V
2 CERM
805

FPD_3V3

R278

R283

SM

Q15

SM

CPU_SLEEPIN

2N7002

SLEEP1

C236

FPD_3V3&FPD_12VM

2N7002

5%
1/16W
MF
402

2N7002

10UF

10%
16V
2 CERM
1210

Q17

R5101

Q16

FPD_3V3
1

R738

5%
1/16W
MF
402

C653

C246
150UF

HONK_ADJ

FPD_3V3
1

402 10% CERM


16V

FPD_3V3
1

0.0022UF
SWITCH5V_6

37D1<

10%
16V
2 CERM
1210

C252

0.01UF

R251

3_6V_SLEEP

10UF

FPD_3V3&FPD_12VM

C257

FPD_3V3

5%
NOSTUFF
1/16W
MF
402

SOT23
1

5%
1/16W
MF
2 402

C654
10UF

LED_RET 29A3<
4.7K

44C4<>

Q38

R685
51C7< 1

CPU_STATE_LED*

R5301

50C4<> 50B4<> 49D7<> 49D3<> 52C1>


45D3<> 45B4<> 44D8< 42B3< 39C8< 36D8<
49C4<> 48D6<> 48C8<> 48C4<> 45D7<
51D7<> 51C3< 51B7< 51A5< 50D5<> 50D2<
59D7>

FPD_3V3&FPD_12VM

VR3

1%
1/16W
MF
2 402

24D7< 52B6>

C742

+3.3VFPD

SOT-6

46C7< 46D6<> 50D5< 51C8< 59D7>

2 SM

Q11

FDC602P

GREEN

51C3< 51A7< 51A5< 50D5<>


49D3<> 49C4<> 48D6<>
45B4<> 44D8< 42B3< 39C8< 36D8< +12V_MAIN
48C8<> 48C4<> 45D7< 45D3<>
50D2< 50C4<> 50B4<> 49D7<>
59D7> 52C1> 51D7<>

FPD_3V3&FPD_12VM

0
1
2

RUNLED1

POWER_UP*

5%
1/8W
FF
2 1206

FPD_12VM

FDC602P
SOT-6

5%
1/16W
MF
2 402

59D5> 44C7<>

FPD_12VS

R1018

59D7> 52C1> 51D7<> 51B7< 51A7< 51A5<


48C8<> 48C4<> 45D7< 45D3<> 45B4<> 44D8< 42B3< 39C8< 36D8< +12V_MAIN
50D5<> 50D2< 50C4<> 50B4<> 49D7<> 49D3<> 49C4<> 48D6<>

(OFF DURING SLEEP)

330

29A3< 29A8< 29C5<> 50D5< 51A5<


51D6<> 52C1> 59D7>

+5V POWER SWITCH

DEV
1

+12V_SLEEP

VOLTAGE TO SUPPORT 3.3V AT PANEL


VOLTAGE HERE WILL EXCEED 3.3V

(OFF DURING SLEEP)

46D6<> 46C7< 38C1<


59D7> 51C5<> 50D5<

TMDS POWER CONVERTER & SWITCH

39C8< 42D8< 50C3< 50C8< 59D5>

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
51 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

INTREPID POWER CONSTRAINT TABLE


SIG_NAME

MIN_NECK_WIDTH

VOLTAGE

MIN_LINE_WIDTH

+1_5V_INTREPID_PLL
+1_5V_INTREPID_PLL1
+1_5V_INTREPID_PLL2
+1_5V_INTREPID_PLL3
+1_5V_INTREPID_PLL4
+1_5V_INTREPID_PLL5
+1_5V_INTREPID_PLL6
+1_5V_INTREPID_PLL7
+1_5V_INTREPID_PLL8
+1_5V_AGP
INT_AGP_VREF

10
10
10
10
10
10
10
10
10
10
10

1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.75

20
20
20
20
20
20
20
20
20
20
20

D
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

CPU POWER CONSTRAINT TABLE


SIG_NAME
OUT
OUT
OUT

MIN_NECK_WIDTH

VOLTAGE

10
10
10

1.8
1.85
1.85

+MAXBUS_SLEEP
CPU_AVDD
CPU_VCORE_SLEEP

OUT

20
20
20

4D5< 6C5< 6D6< 7A3< 7B3< 7C3< 7C5< 7C7< 8A3<> 8D1< 8D4< 9B7< 9D8< 44B7<
44D1< 44D2< 45D2<> 46D4< 59C7>
4D3<
4D3< 4D7< 8B7< 8C1< 45D2<> 59B5> 59D7>

OUT

59D7> 49B2<> 30B3<


43C7< 42C8< 42B7< 42B5< 41A7< 41A5< 40D5< 39D4<
59D7>

ETHERNET POWER CONSTRAINT TABLE

OUT
OUT
OUT

59D7> 51B4<>
OUT

SIG_NAME

MIN_NECK_WIDTH

VOLTAGE

MIN_LINE_WIDTH

OUT
OUT

OUT

10

ENET_AVDD

2.5

9D4< 16D6< 28D6<> 30D5<


28C4<
28D4<
28D4<
28D4<
16D5<
30D4<
9D2<
28D4<
10D6< 11A6< 16A8< 16C2< 16D7< 17A3< 17A4< 17D5< 46B4<> 59C7>
16A7< 16C6<>

MIN_LINE_WIDTH

59D7>

20

35D2<> 35D4<>
OUT

39B7<>
41B3< 41B1<> 41A4< 41A2<> 40C6< 40B6< 40B5<> 35C1<> 35B1<
43A5< 42A6<> 42A5<> 41D3< 41C3<
36B6<> 36B2< 36A7<> 33D4< 33C4< 33C2< 33B4< 25C3< 25B3<>
36C1< 36C1<> 36B6<
43B7< 43A7< 29A3< 24B3<

OUT
OUT
OUT
OUT

FIREWIRE POWER CONSTRAINT TABLE

+1_8V_MAIN
+2_5V_MAIN
+3V_MAIN

MAIN POWER CONSTRAINT TABLE


SIG_NAME

MIN_NECK_WIDTH

VOLTAGE

MIN_LINE_WIDTH

+1_8V_MAIN
+2_5V_MAIN
+3V_MAIN
3.8V_TRICKLE
+5V_MAIN
+12V_MAIN
+12V_SLEEP

10
10
10
10
10
10
10

1.8
2.5
3.3
3.8
5
12
12

20
20
20
20
20
20
20

GND
AGND
ANALOGGND
ALTCHGND
CHGND

10
10
10
10
10

0
0
0
0
0

20
20
20
20
20

3.8V_TRICKLE

+5V_MAIN
+12V_MAIN

+12V_SLEEP

ALT
CHASSIS

SIG_NAME
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

MIN_NECK_WIDTH

VOLTAGE

MIN_LINE_WIDTH

10
10
10
10
10
10
10
10
10
10
10

3.3
3.3
24
24
3.3
0
12
12
12
12
12

20
20
20
20
20
20
20
20
20
20
20

FW_DIO_V
FW_DIODE_BYPASS_V
FW_PWR
FW_PWR_SW
FW_PHY_3_3
FW_VGND
FW_VP
FW_VP1
FW_VP2
FW_VP_1
FW_VP_2

PMU POWER CONSTRAINT TABLE

36B6<
36B6<> 36B7<>
29B3< 36D6< 50C6<> 51D4<>
36D6< 51D2<>

SIG_NAME

MIN_NECK_WIDTH

VOLTAGE

10
10
10

3.8
3.5
3.5

MIN_LINE_WIDTH

36B5< 36B7< 36D7<


OUT

36D5<
36D1<> 36D3<>

OUT
OUT

3.8VH_TRICKLE
PMU_AVCC
PMU_POWER

20
20
20

44C1< 44D7<>
44B5< 44D4<> 59C5>
29C3<> 44A5<> 44B1< 44C2< 44D5<>

36C1<> 36D3<>
36D4<
36D4<

SYSTEM POWER CONSTRAINT TABLE

SIG_NAME

GRAPHICS POWER CONSTRAINT TABLE


SIG_NAME

VOLTAGE

MIN_NECK_WIDTH

MIN_LINE_WIDTH

OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

10
10
10
10
10
10
10
10
10
10
10
10
10
10
10

+3.3VFPD
DAC2VDD
DACVDD
DDC_VCC_3
DDC_VCC_5
DDR_VREF
IFP0AVCC
IFP0VREF
INT_TMDS_3V
GPU_AGP_VREF
GPU_FB_VREF
GRAPH_CORE
NVPLLVDD
SGRAVREF
SGRBVREF

3.6
3.3
3.3
3.3
5
1.25
3.8
3.8
3.6
0.75
1.25
1.6
3.3
1.25
1.25

20
20
20
20
20
20
20
20
20
20
20
20
20
20
20

24D7< 51C1<>

OUT

22C5<
22C4<

OUT

24B3<> 59B7>
25C4< 59B7>

OUT

OUT

OUT

17A5<

MIN_LINE_WIDTH

10
10
10
10
10
10
10

12
12
5
5
5
0
0

20
20
20
20
20
20
20

29A5<>
29A5<> 59C7>
29A5<> 59A7>
29A8<
29A5<> 59A7>
29A3< 51B6<
29A5<> 59A7>

23B4<>
24C3<> 59C7>
17A2< 17A8<

USB POWER CONSTRAINT TABLE

18C8<
17D4< 23C7<> 48C2<>
22D5<
20A3< 20C4< 20C8<

SIG_NAME

MIN_NECK_WIDTH

VOLTAGE

10
10
10
10
10

3.3
3.3
0
5
5

MIN_LINE_WIDTH

21A3< 21C4< 21C8<

OUT

1.5
0
0

GPU_50PULLUP
GPU_50PULLDWN
GPU_TMODE

VOLTAGE

12A7< 14D2<> 14D8<> 15D8<


23A6< 23C1<

OUT

17B5<>
17A5<>

+12VSD_FILT
FAN_12V_FILT
KS5VSD
LED_5V
LED_5V_FILT
LED_RET
LED_RET_FILT

MIN_NECK_WIDTH

OUT

OUT
OUT

OUT
OUT

+3V_INTREPID_USB
NEC_AVDD
USB_GND
USB_PORT_PWR
USB_PWR

20
20
20
20
20

28C4<
32D5<
33A4<> 33B3<> 33C3<>
33D3<> 59B5>
25B5<> 25C2< 25D3<> 33A6<>

POWER CONSTRAINTS

NOTICE OF PROPRIETARY PROPERTY

OUT

LAST_MODIFIED=Mon Oct 27 12:26:14 2003


22B2< 22A5<
22D4<

0
0

GPU_XTALSSIN
VIPCLK

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

OUT

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

OUT

II NOT TO REPRODUCE OR COPY IT

3.3
0
5
0
5

37B7< CSLOT_IOWAIT_L
38C6<> EIDE_CSELP_L
38C6<> EIDE_IOCS16_L
38C2<> UIDE_CSELP_L
38C2<> UNUSED_ATAIOCS16_L

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

OUT
OUT

SIZE

OUT

OUT

APPLE COMPUTER INC.

OUT

SCALE

DRAWING NUMBER

REV.

051-6569 A
52 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

RATSNEST_SCHEDULE
RELATIVE_PROPAGATION_DELAY
MAX_VIAS
PROPAGATION_DELAY
STUB_LENGTH

SIG_NAME

13B2<> 13A5<>

13C4<> 13B6<> 13B3<> 13A6<> 12D8<> 12C8<> 12B8<> MEM_DATA<0..63>


14D6<> 14D4<> 14C6<>
13C8<>
13D4<> 13C7<> 13C4<> 13C2<> 13B5<> 13B2<> RAM_DATA_A<0..63>
14C4<> 14B6<> 14B4<> 14A6<> 14A4<> 13D7<>
RAM_DATA_B<0..63>
15D6< 13A2<> 15A6< 15B4> 15B6< 15C4> 15C6< 15D4>
13C8<> 13C4<> 13B3<> 13A6<> 12C6<> MEM_DQS<0..7>
14A6<> 13D7<> 13D4<> 13C7<> 13C4<> 13B5<> 13B2<> RAM_DQS_A<0..7>
14D6<> 14C8< 14C6<> 14B8< 14B6<> 14A8<
13C7<> 13C4<> 13B7<> 13B4<> 13B2<> 13A5<> 13A2<> RAM_DQS_B<0..7>
15D6< 15C8< 15C6< 15B8< 15B6< 15A8< 15A6<
13C8<> 13C4<> 13B3<> 13A6<> 12C6<> MEM_DQM<0..7>
13D7<> 13D4<> 13C7<> 13C4<> 13B5<> 13B2<> 13A5<> RAM_DQM_A<0..7>
14D4<> 14C4<> 14B4<> 14A4<>
13C7<> 13C4<> 13B7<> 13B4<> 13B2<> 13A5<> 13A2<> RAM_DQM_B<0..7>
15D4> 15C4> 15B4> 15A4>
12D6<> 12D3< 12D2< 12C3< 12C2< 12B3< MEM_ADDR<0..12>
15B4> 14B6<> 14B4<> 12D3< 12D1< 12C3< 12C1< 12B3< RAM_ADDR<0..12>
15C6< 15C4> 15B6<
12D6<> 12B3< MEM_BA<0..1>
15B6< 14B6<> 14B4<> 12B3< RAM_BA<0..1>

MEM_CS_L<0..3>
RAM_CS_L<0..1>
12B1< RAM_CS_L<2..3>
12C6<> 12A3< MEM_RAS_L
12C6<> 12A3< MEM_CAS_L

12C6<> 12C2< 12B2<


14B6<> 14B4<> 12C1<
15B4>

L:S::1300
L:S::1800
L:S::2400
L:S::1300
L:S::1700
L:S::2400
L:S::1300
L:S::1800
L:S::2400

MEM_ADDR:G:L:S:0:200
RAM_ADDR:G:L:S:0:1300
MEM_ADDR:G:L:S:0:1300
RAM_ADDR:G:L:S:0:1300
MEM_ADDR:G:L:S:0:200
RAM_CS_GROUP0:G:L:S:0:400
RAM_CS_GROUP1:G:L:S:0:350
MEM_ADDR:G:L:S:0 MIL:200 MIL
MEM_ADDR:G:L:S:0 MIL:200 MIL

3
4
3
4
3
3
2
3
3

L:S::600
L:S::3500
L:S::600
L:S::4000
L:S::600
L:S:2000:3500
L:S:2000:3500
L:S::600 MIL
L:S::600 MIL

SYSCLK_DDRCLK_A2_L
SYSCLK_DDRCLK_B0_UF
SYSCLK_DDRCLK_B0_L_UF
15B4> 12B4< SYSCLK_DDRCLK_B0
12B4< 15B3> SYSCLK_DDRCLK_B0_L
12B6<>

12B6<>

SYSCLK_DDRCLK_B1_UF

12B6<> SYSCLK_DDRCLK_B1_L_UF
15D6< 12A4< SYSCLK_DDRCLK_B1
15C6< 12A4< SYSCLK_DDRCLK_B1_L
12B6<> SYSCLK_DDRCLK_B2_UF
12B6<> SYSCLK_DDRCLK_B2_L_UF
15A6< 12A4< SYSCLK_DDRCLK_B2
15A6<

12A4<

SYSCLK_DDRCLK_B2_L

NO_TEST

FUNC_TEST

PULSE_PARAM

167
167
167
167
167
167
167
167
167

MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ

270
270
270
270
270
270
270

167
167
167
167
167
167
167
167
167
167

MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ

270
270
270
270
270
270
270
270

167
167
167
167
167
167
167
167

MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ

270
270
270
270
270
270
270
270

167
167
167
167
167
167
167
167

MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ

200

SYSCLK_DDRCLKA1:G:L:S:0 MIL:100 MIL 3 L:S::2600 MIL


200
L:S:500
3
MIL:850 MIL
L:S:500
3
MIL:850 MIL
3 L:S::750 MIL
L:S:500
3
MIL:850 MIL
L:S:500
3
MIL:850 MIL
SYSCLK_DDRCLKB0:G:L:S:0 MIL:100 MIL 3 L:S::3500 MIL
200
SYSCLK_DDRCLKB0:G:L:S:0 MIL:100 MIL 3 L:S::3500 MIL
200

12B6<>

MAX_EXPOSED_LENGTH

200

SYSCLK_DDRCLK_A1_L

12B6<> SYSCLK_DDRCLK_A2_UF
12B6<> SYSCLK_DDRCLK_A2_L_UF

MIN_NECK_WIDTH
NET_SPACING_TYPE

3
3
3
3
3
3
3
3
3

3 L:S::600 MIL
4 L:S::4000 MIL
200
4 L:S::4000 MIL
200
4 L:S::4000 MIL
200
3
L:S::600
3
L:S::2500
2
L:S::2500
3
L:S::1000
3
L:S::1000
200
4 L:S::2000 MIL
200
4 L:S::2000 MIL
L:S:500
3
MIL:850 MIL
L:S:500
3
MIL:850 MIL
SYSCLK_DDRCLKA0:G:L:S:0 MIL:100 MIL 3 L:S::2600 MIL
200
SYSCLK_DDRCLKA0:G:L:S:0 MIL:100 MIL 3 L:S::2600 MIL
200
L:S:500
3
MIL:850 MIL
L:S:500
3
MIL:850 MIL
SYSCLK_DDRCLKA1:G:L:S:0 MIL:100 MIL 3 L:S::2600 MIL
200

14A4<> 12B4<

MEM_ADDR:G:L:S:0 MIL:280 MIL


RAM_ADDR:G:L:S:0 MIL:2000 MIL
RAM_ADDR:G:L:S:0 MIL:2000 MIL
RAM_ADDR:G:L:S:0 MIL:2000 MIL
MEM_ADDR:G:L:S:0:200
RAM_CS_GROUP0:G:L:S:0:400
RAM_CS_GROUP1:G:L:S:0:350

L:S:500
3
MIL:850 MIL
L:S:500
3
MIL:850 MIL
SYSCLK_DDRCLKB1:G:L:S:0 MIL:100 MIL 3 L:S::3500 MIL
200
SYSCLK_DDRCLKB1:G:L:S:0 MIL:100 MIL 3 L:S::3200 MIL
200
L:S:500
3
MIL:850 MIL
L:S:500
3
MIL:850 MIL
SYSCLK_DDRCLKB2:G:L:S:0 MIL:100 MIL 3 L:S::3500 MIL
200
SYSCLK_DDRCLKB2:G:L:S:0 MIL:100 MIL 3 L:S::3500 MIL
200

10 MIL SPACING
10 MIL SPACING
10 MIL SPACING

10 MIL SPACING
10 MIL SPACING
10 MIL SPACING

8
8
8
8
8
8
8

MIL
MIL
MIL
MIL
MIL
MIL
MIL

SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING

8 MIL SPACING
8 MIL SPACING
8 MIL SPACING
8 MIL SPACING
8 MIL SPACING
8 MIL SPACING
8 MIL SPACING
8 MIL SPACING
8
8
8
8
8
8
8
8

MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL

SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING

28A6< INT_REF_CLK_IN_PD
31C6< 31B7< 31B6< 30D4<> 30C4<> 30C2< 30C1<> 30B2< PCI_AD<31..0>
59C3> 59B3> 32C6<> 32B7<> 32B6<> 31C7<
59A5> 32B6<> 31B7< 30C5<> PCI_CBE<3..0>
59A5> 32B6<> 31B7< 30C5<> 30B7< PCI_FRAME_L

8
8
2
3
3
2
3
3
2

MEM_WE_L
RAM_CAS_L
RAM_RAS_L
RAM_WE_L
15B6< 14B6<> 12B3<
12C6<> 12C2< 12B6<> 12B2< MEM_CKE<0..3>
15C1< 14B6<> 14B4<> 12C1< 12B1< RAM_CKE<0..1>
15C6< 15C4> 15B1< 15A1< 12C1< 12B1< RAM_CKE<2..3>
12B6<> MEM_MUXSEL_H<0..1>
12B6<> MEM_MUXSEL_L<0..1>
13C4<> 13A3<> 12D4< MUX_SEL_H
13C8<> 13A6<> 12D4< MUX_SEL_L
12B6<> SYSCLK_DDRCLK_A0_UF
12B6<> SYSCLK_DDRCLK_A0_L_UF
14D6<> 12C4< SYSCLK_DDRCLK_A0
14D6<> 12C4< SYSCLK_DDRCLK_A0_L
12B6<> SYSCLK_DDRCLK_A1_UF
12B6<> SYSCLK_DDRCLK_A1_L_UF
14A4<> 12C4< SYSCLK_DDRCLK_A1
12C6<> 12B3<

15B6< 14B4<> 12A2<


15B4> 14B4<> 12A2<

MEM_GROUP0:G:L:S:0:150
RAM_GROUP0_A:G:L:S:0:180
RAM_GROUP0_B:G:L:S:0:180
MEM_GROUP0:G:L:S:0:180
RAM_GROUP0_A:G:L:S:0:180
RAM_GROUP0_B:G:L:S:0:180
MEM_GROUP0:G:L:S:0:180
RAM_GROUP0_A:G:L:S:0:180
RAM_GROUP0_B:G:L:S:0:180

MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN

8 L:S::2500 MIL
6 L:S:6000:8000
500
6 L:S:6000:8000
500
L:S:6000
7
MIL:8000 MIL
500

10 MIL SPACING

270

66.56 MHZ
33 MHZ
33 MHZ
33 MHZ

SIGNAL CONSTRAINTS

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:26:14 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

DIGITAL SIGNAL CONSTRAINTS

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
53 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

SIG_NAME

RATSNEST_SCHEDULE
RELATIVE_PROPAGATION_DELAY
MAX_VIAS
PROPAGATION_DELAYSTUB_LENGTH

L:S:6000
6
MIL:8000 MIL
500
L:S:6000
6
MIL:8000 MIL
500
59A5> 32B6<> 31B7< 30C5<> 30B7< PCI_TRDY_L
L:S:6000
6
MIL:8000 MIL
500
59A5> 32B6<> 31B7< 30C5<> 30B7< PCI_DEVSEL_L
L:S:6000
6
MIL:8000 MIL
500
59A5> 32B6<> 31B7< 30C5<> 30B7< PCI_STOP_L
L:S:6000
6
MIL:8000
MIL
500
59A5> 32B6<> 31B7< 30C5<> PCI_PAR
L:S:600
3
MIL:1000 MIL
200
30D5<> CLK33M_PCI_SLOTB_UF
L:S:600
3
MIL:1200 MIL
200
30D5<> CLK33M_PCI_SLOTC_UF
L:S:600
3
MIL:1000 MIL
200
30D5<> CLK33M_PCI_SLOTD_UF
L:S:3000
5
MIL:4000 MIL
200
59A5> 31C2<> 30D7< CLK33M_PCI_SLOTB
4
L:S::1000 MIL 200
30C5<> INT_PCI_FB_OUT
4
L:S::200 MIL
200
30D8< PCI_FBO_PLUS2
L:S:1900
4
MIL:2000 MIL
30C8< PCI_FB_PLUS4
L:S:1900
4
MIL:2000 MIL
200
30C8< PCI_FBI_PLUS2
L:S:2000
4
MIL:3000 MIL
200
30C7< PCI_FBI_EQUAL
L:S:5900
4
MIL:6000 MIL
30C7< PCI_FB_PLUS6
4
L:S::1080
MIL
200
30C5< INT_PCI_FB_IN
3
L:S::1000
31C3<> 31C2<> 31B7< 31B6< 31B3<> 31B2<> PCIT_AD<31..0>
59C3> 59B3> 31C7<
3
L:S::1000
59A5> 31C3<> 31B6< 31B2<> PCIT_CBE<31..0>
3
L:S::1000 MIL
31C2<> 31B6< PCIT_FRAME_L
3
L:S::1000 MIL
59B5> 31C3<> 31B6< PCIT_IRDY_L
3
L:S::1000 MIL
31C2<> 31B6< PCIT_TRDY_L
3
L:S::1000 MIL
31C2<> 31B6< PCIT_DEVSEL_L
3
L:S::1000 MIL
31C2<> 31B6< PCIT_STOP_L
3
L:S::1000 MIL
31C2<> 31B6< PCIT_PAR
AGP_GROUP0:G:L:S:0:280
5
L:S::4500
17D8< 17C8< 16C4<> AGP_AD<0..15>
AGP_GROUP0:G:L:S:0:330
5
L:S::4500
17C8< 16B4<> AGP_CBE<0..1>
4
L:S::4400 MIL 200
17B8< 16B3< 16A4<> AGP_AD_STB<0> AGP_GROUP0:G:L:S:0 MIL:330 MIL
4
L:S::4400 MIL 200
17B8< 16D1< 16A4<> AGP_AD_STB_L<0> AGP_GROUP0:G:L:S:0 MIL:330 MIL
AGP_GROUP0:G:L:S:0:280
5
L:S::4500
17C8< 16C4<> 16B4<> AGP_AD<16..31>
AGP_GROUP0:G:L:S:0:280
5
L:S::4500
17C8< 16B4<> AGP_CBE<2..3>
4
L:S::4400 MIL 200
17B8< 16B3< 16A4<> AGP_AD_STB<1> AGP_GROUP0:G:L:S:0 MIL:280 MIL
4
L:S::4400 MIL 200
17B8< 16D1< 16A4<> AGP_AD_STB_L<1> AGP_GROUP0:G:L:S:0 MIL:330 MIL
L:S:4000
5
MIL:4500 MIL
17B8< 16C3< 16B4<> AGP_FRAME_L
L:S:4000
5
MIL:4500 MIL
17B8< 16C3< 16B4<> AGP_IRDY_L
L:S:4000
5
MIL:4500 MIL
17B8< 16B4<> 16B3< AGP_TRDY_L
L:S:4000
5
MIL:4500 MIL
17B8< 16C3< 16B4<> AGP_DEVSEL_L
L:S:4000
5
MIL:4500 MIL
17B8< 16B4<> 16B3< AGP_STOP_L
L:S:4000
5
MIL:4500 MIL
17B8< 16B4<> AGP_PAR
5
L:S:4000:4500
17A8< 16C1< 16B4< 16B4<> 16B1< 16A4<> AGP_SBA<0..7>
5
AGP_GROUP99:G:L:S:0
MIL:200
MIL
L:S::4500
MIL
17B8< 16B3< 16A4<>
AGP_SB_STB
5
L:S::4500 MIL
17A8< 16D1< 16A4<> AGP_SB_STB_L AGP_GROUP99:G:L:S:0 MIL:200 MIL
5
L:S:4500:5000
17B6< 16B1< 16A4<> AGP_ST<0..2>
L:S:4000
5
MIL:4500 MIL
17B8< 16B3< 16A4<> AGP_PIPE_L
L:S:4000
5
MIL:4500 MIL
17B8< 16B3< 16A4<> AGP_RBF_L
L:S:4500
5
MIL:5000 MIL
17B6<> 16C4<> 16C3< AGP_REQ_L
L:S:4500
5
MIL:5000 MIL
17B6< 16C4<> 16C3< AGP_GNT_L
L:S:4000
5
MIL:4500 MIL
17B8< 16B1< 16A6<> AGP_WBF_L
L:S:4500
5
MIL:5000 MIL
17A8> 16D3< 16D1< 16C6<> AGP_BUSY_L
L:S:4500
5
MIL:5000 MIL
17A8< 16D3< 16C6<> STOP_AGP_L
GPU_AGP_GROUP0:G:L:S:0:100
3
L:S::600
17D7<> 17D6<> 17C6<> GPU_AGP_AD<0..15>
GPU_AGP_GROUP0:G:L:S:0:100 3
L:S::600
17C6<> GPU_AGP_CBE<0..1>
GPU_AGP_STB0:G:L:S:0 MIL:50 MIL
3
L:S::450 MIL
AGP_AD_STB_GPUUF<0>
17B6<
GPU_AGP_STB0:G:L:S:0 MIL:50 MIL
3
L:S::800 MIL
AGP_AD_STB_L_GPUUF<0>
17B6<
GPU_AGP_GROUP1:G:L:S:0:100
3
L:S::600
17C6<> GPU_AGP_AD<16..31>
GPU_AGP_GROUP1:G:L:S:0:100 3
L:S::600
17C6<> GPU_AGP_CBE<2..3>
GPU_AGP_STB1:G:L:S:0 MIL:50 MIL
3
L:S::800 MIL
AGP_AD_STB_GPUUF<1>
17B6<
GPU_AGP_STB1:G:L:S:0
MIL:50
MIL
3
L:S::800
MIL
AGP_AD_STB_L_GPUUF<1>
17B6<
3L:S:300 MIL:600 MIL
17B6<> GPU_AGP_FRAME_L
3L:S:300 MIL:600 MIL
17B6<> GPU_AGP_IRDY_L
3L:S:300 MIL:600 MIL
17B6<> GPU_AGP_TRDY_L
3L:S:300 MIL:600 MIL
17B6<> GPU_AGP_DEVSEL_L
3L:S:300 MIL:600 MIL
17B6<> GPU_AGP_STOP_L
3L:S:300 MIL:600 MIL
17B6<> GPU_AGP_PAR
3
L:S:300:600
17A6<> GPU_AGP_SBA<0..7>
3L:S:300 MIL:600 MIL
17B6<> GPU_AGP_SB_STB GPU_AGP_SBSTB:G:L:S:0 MIL:50 MIL
3L:S:300 MIL:600 MIL
17A6<> GPU_AGP_SB_STB_L GPU_AGP_SBSTB:G:L:S:0 MIL:50 MIL
3L:S:300 MIL:600 MIL
17B6<> GPU_AGP_PIPE_L
3L:S:300 MIL:600 MIL
17B6<> GPU_AGP_RBF_L
32B6<> 31B7< 30C5<> 30B7< PCI_IRDY_L

31C6<

DIFFERENTIAL_PAIR
MAX_EXPOSED_LENGTH
FUNC_TEST

MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN

10 MIL SPACING

8 MIL SPACING
8 MIL SPACING
8 MIL SPACING
8 MIL SPACING

450
450
450
450
450
450
450
450
450
450
450

500
500
500
500

AGP_ADSTBDP1
AGP_ADSTBDP1

33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
266
266
133
133
266
266
133
133
66
66
66
66
66
66

MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ

I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
I12
I13
I14
I15
I16
I17
I18
I19
I20
I21
I22
I23
I24
I25
I26

I27
I28
I29
I30
I31
I32
I33
I34
I35
I36
I37
I38
I39
I40
I41
I42
I43
I44
I45
I46
I47
I48

8 MIL SPACING
8 MIL SPACING
8 MIL SPACING
8 MIL SPACING

500
500
500
500

GPU_ADSTBDP0
GPU_ADSTBDP0
GPU_ADSTBDP1
GPU_ADSTBDP1

266
266
133
133
266
266
133
133
66
66
66
66
66
66

MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ

I49
I50
I51
I52

I53
I54
I55
I56
I57
I58
I59
I60
I61
I62
I63
I64

GPU_SBSTBB
GPU_SBSTBB

I65
I66
I67
I68

L:S:1000
3
MIL:1100 MIL
L:S:3700
4
MIL:3900 MIL
200
L:S:1400
4
MIL:1500 MIL
200
L:S:900
4
MIL:1080 MIL
200
L:S:1900
4
MIL:2000 MIL
4
L:S::200 MIL
200
4
L:S::1200 MIL 200
3L:S:600 MIL:800 MIL
3
L:S::2800 MIL

10 MIL SPACING
10 MIL SPACING

10 MIL SPACING
8 MIL SPACING

250
250
250
250
250
250
250
250
250

CLK33M_PCI_SLOTD

L:S:3000
4
MIL:3500 MIL
200

8 MIL SPACING

250

32A6< 30D7<

AGP_ADSTBDP0
AGP_ADSTBDP0

PULSE_PARAM

AGP_SBSTBB
AGP_SBSTBB

CLK66M_GPU_UF
17C6< 16D8< CLK66M_GPU_AGP
16C6<> INT_AGP_FB_OUT
16B7< AGP_FBO_EQUAL
16B8< AGP_FB_PLUS2
16C7< AGP_FBI_EQUAL
16C6< INT_AGP_FB_IN
30C5<> 30A7< 16D7< INT_ROM_OVERLAY_PU
56B3> 16C7< 9B4< 8A2< INT_ANALYZER_CLK
16C6<>

59A7>

NET_SPACING_TYPE

66
66
66
66
66
66
66
66
166

MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ

33 MHZ

I70
I71
I72
I73
I74
I75
I76
I77

SIGNAL CONSTRAINTS

I78

NOTICE OF PROPRIETARY PROPERTY

I79

LAST_MODIFIED=Mon Oct 27 12:26:15 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
54 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

DIGITAL
GROUP

SIG_NAME
FBD<0..63>
RFBD<0..63>
FBDQM<0..7>
RFBDQM<0..7>
FBA<0..12>
RFBA<0..11>
FBABA<0..1>
RFBABA<0..1>
FBARAS_L
FBACAS_L
FBAWE_L
FBACS0_L
FBACKE
RFBARAS_L
RFBACAS_L
RFBAWE_L
RFBACS0_L
RFBACKE
FBDQS<0..7>
FBDQSTERM<0..7>
RFBDQS<0..7>
FBACLK0
FBACLK0_L
FBACLK1
FBACLK1_L
RFBACLK1
RFBACLK1_L
RFBACLK0
RFBACLK0_L

SIGNALS

RELATIVE_PROPAGATION_DELAY MAX VIAS

GPU_FBDATA_A:G:L:S:0:225
4
L:S::800
4
L:S::1000
RAM_FBDATA_A:G:L:S:0:300
4
L:S::800
GPU_FBDQM_A:G:L:S:0:200
4
L:S::1000
RAM_FBDQM_A:G:L:S:0:200
4
L:S::700
GPU_FBADDR_A:G:L:S:0:200
5
L:S::2400
RAM_FBADDR_A:G:L:S:0:530
4
L:S::600
GPU_FBADDR_A:G:L:S:0:200
5
L:S::2400
RAM_FBADDR_A:G:L:S:0:530
4
MIL
GPU_FBCNTL_A:G:L:S:0 MIL:200 L:S::400
MIL
4
MIL
GPU_FBCNTL_A:G:L:S:0 MIL:200 L:S::400
MIL
MIL
GPU_FBCNTL_A:G:L:S:0 4
MIL:200 L:S::400
MIL
MIL
GPU_FBCNTL_A:G:L:S:0 4
MIL:200 L:S::400
MIL
5
L:S::400
MIL
GPU_FBCNTL_A:G:L:S:0 MIL:200 MIL
MIL
RAM_FBCNTL_A:G:L:S:0 5
MIL:350 L:S::2700
MIL
MIL
RAM_FBCNTL_A:G:L:S:0 5
MIL:500 L:S::2700
MIL
5
L:S::2700
MIL
RAM_FBCNTL_A:G:L:S:0 MIL:500 MIL
5
L:S::2700
MIL
RAM_FBCNTL_A:G:L:S:0 MIL:350 MIL
MIL
RAM_FBCNTL_A:G:L:S:0 5
MIL:500 L:S::2700
MIL
3
L:S::350
GPU_FBDQS_A:G:L:S:0:100
3
L:S::1500
FB_DQSTERM_A:G:L:S:0:50
L:S::150
RAM_FBDQS_A:G:L:S:0:55
3
3
GPU_FBCLK_A:G:L:S:0 MIL:50
MIL
L:S::150 MIL
3
GPU_FBCLK_A:G:L:S:0 MIL:50
MIL
L:S::150 MIL
3
GPU_FBCLK_A:G:L:S:0 MIL:50
MIL
L:S::150 MIL
3
GPU_FBCLK_A:G:L:S:0 MIL:50 MIL
L:S::150 MIL
3
RAM_FBCLK_A:G:L:S:0 MIL:80
MIL
L:S::2500 MIL
3
RAM_FBCLK_A:G:L:S:0 MIL:80
MIL
L:S::2500 MIL
3
RAM_FBCLK_A:G:L:S:0 MIL:70 MIL
L:S::2500 MIL
3
RAM_FBCLK_A:G:L:S:0 MIL:70 MIL
L:S::2500 MIL

RATSNEST_SCHEDULE

PROPAGATION_DELAY STUB_LENGTH

4
FBD<64..127>
GPU_FBDATA_B:G:L:S:0:225
L:S::800
4
RAM_FBDATA_B:G:L:S:0:325
L:S::1000
RFBD<64..127>
4
GPU_FBDQM_B:G:L:S:0:120
L:S::800
FBDQM<8..15>
4
RAM_FBDQM_B:G:L:S:0:120
L:S::1000
RFBDQM<8..15>
4
GPU_FBADDR_B:G:L:S:0:120
L:S::600
FBBA<0..12>
RAM_FBADDR_B:G:L:S:0:370
5
L:S::2400
RFBBA<0..11>
4
GPU_FBADDR_B:G:L:S:0:120
L:S::600
FBBBA<0..1>
RAM_FBADDR_B:G:L:S:0:370
5
L:S::2400
RFBBBA<0..1>
4
GPU_FBCNTL_B:G:L:S:0 MIL:120 MIL
L:S::400 MIL
FBBRAS_L
GPU_FBCNTL_B:G:L:S:0 4
MIL:120 MIL
L:S::400 MIL
FBBCAS_L
GPU_FBCNTL_B:G:L:S:0 4
MIL:120 MIL
L:S::400 MIL
FBBWE_L
4
GPU_FBCNTL_B:G:L:S:0 MIL:120 MIL
L:S::400 MIL
FBBCS0_L
GPU_FBCNTL_B:G:L:S:0
5
MIL:120
MIL
L:S::400 MIL
FBBCKE
RAM_FBCNTL_B:G:L:S:0 5
MIL:2000 L:S::3500
MIL
MIL
RFBBRAS_L
RAM_FBCNTL_B:G:L:S:0 5
MIL:2000 L:S::3500
MIL
MIL
RFBBCAS_L
RAM_FBCNTL_B:G:L:S:0 5
MIL:2000 L:S::3500
MIL
MIL
RFBBWE_L
RFBBCS0_L
RAM_FBCNTL_B:G:L:S:0 5
MIL:2000 L:S::3500
MIL
MIL
RFBBCKE
RAM_FBCNTL_B:G:L:S:0 MIL:2000
L:S::3500
MIL
MIL
5
FBDQS<8..15>
GPU_FBDQS_B:G:L:S:0:100
L:S::350
3
FBDQSTERM<8..15> FB_FBDQSTERM_B:G:L:S:0:60
3
L:S::1500
RFBDQS<8..15>
RAM_FBDQS_B:G:L:S:0:50
3
L:S::150
FBBCLK0
GPU_FBCLK_B:G:L:S:0 MIL:50
3
MIL L:S::150 MIL
FBBCLK0_L
GPU_FBCLK_B:G:L:S:0 MIL:50
MIL
L:S::150 MIL
3
FBBCLK1
GPU_FBCLK_B:G:L:S:0 MIL:50
3
MIL L:S::150 MIL
FBBCLK1_L
GPU_FBCLK_B:G:L:S:0 MIL:50
3
MIL L:S::150 MIL
RFBBCLK1
RAM_FBCLK_B:G:L:S:0 MIL:90
4
MIL L:S::2500 MIL
RFBBCLK1_L
RAM_FBCLK_B:G:L:S:0 MIL:90
3
MIL L:S::2500 MIL
RFBBCLK0
RAM_FBCLK_B:G:L:S:0 MIL:90
3
MIL L:S::2500 MIL
RFBBCLK0_L
RAM_FBCLK_B:G:L:S:0 MIL:90
3
MIL L:S::2500 MIL

NET_SPACING_TYPE

MAX EXPOSED LENGTH

2350
50

100
50
50
50
50
50
10 MIL SPACING
10 MIL SPACING
200
200
200
200
200
200
200
200

PULSE PARAM

300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300

MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ

300 MHZ

50
50

100
3550
3550
3550
3550
3550
10 MIL SPACING
10 MIL SPACING
10 MIL SPACING
200
200
200
200
200
200
200
200

300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300
300

MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ

300
300
300
300
300

MHZ
MHZ
MHZ
MHZ
MHZ

18E8<> 18F8<> 18G8<> 19C5< 19C8< 19D5< 19D8<


19C4< 19C7< 19D4< 19D7< 20B1<> 20B5<> 20C1<> 20C5<>
18D8> 18G3<
18G2< 20C2< 20C6<
18C8> 18D8> 18E3< 18F3<
18E2<> 18F2<> 20C2< 20C6< 20D2< 20D6<

18C8<> 18E3<
18E2<> 20C2< 20C6<
18C8> 18G3<
18C8> 18G3<
18C8> 18F3<
18C8> 18F3<
18D3< 18D7<>
18G2<> 20B2< 20B6<
18G2<> 20B2< 20B6<
18F2<> 20B2< 20B6<
18F2<> 20B2< 20B6<
18D2<> 20C2< 20C6<
18C7<> 19A8<
19A7<
19A6< 20C2<> 20C6<>
18D7> 19C3<
18D7> 19C3<
18D7> 19D3<
18D7> 19D3<
19D1< 20C2<
19D1< 20C2<
19C1< 20C6<
19C1< 20C6<

18E5<> 18F5<> 18G5<> 19B5< 19B8< 19C5< 19C8<


19B4< 19B7< 19C4< 19C7< 21B1<> 21B5<> 21C1<> 21C5<>

18C3< 18D3< 18D5>


18C2< 18D2< 21C2< 21C6<
18A3< 18B3< 18C3< 18C5<> 18D5<>
18B2<> 18C2<> 21C2< 21C6< 21D2< 21D6<
18A3< 18C5<>
18A2<> 21C2< 21C6<
18C3< 18D4<>
18C3< 18D4<>
18C3< 18D4<>
18C3< 18C4<>
18A3< 18C4<>
18C2<> 21B2< 21B6<
18C2<> 21B2< 21B6<
18C2<> 21B2< 21B6<
18C2<> 21B2< 21B6<
18A2<> 21C2< 21C6<
18D4<> 19A5<
19A4<
19A3< 21C2<> 21C6<>
18C5<> 19B3<
18C5<> 19B3<
18C5<> 19C3<
18C5<> 19B3<
19C1< 21C2<
19B1< 21C2<

19B1< 21C6<
19B1< 21C6<

SIGNAL CONSTRAINTS

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:26:16 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
55 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

DIGITAL SIGNALS
D

SIG_NAME

GROUP

MAXBUS

I1
I2
I4
I3
I5
I6
I7
I9
I8
I10
I11
I12
I14
I13
I15
I16
I17
I18
I19
I20
I21
I22

I23
I25
I24
I26

I27
I28
I29
I30

I31
I33
I32
I34

I35

I36
I37
I38
I40
I39
I41
I42

I43
I45
I44
I46
I47
I48
I50
I49
I51
I52
I53
I55
I54
I56
I57
I58
I59
I60
I61
I63
I62

RELATIVE_PROPAGATION_DELAY
MAX_VIAS

PROPAGATION_DELAY
STUB_LENGTH

L:S::5000
CPU_ADDR<0..31> CPU_ADDR_GROUP:G:L:S:0:1250
7
:::5000
CPU_DATA<0..63>CPU_DATA_GROUP:G:L:S:0:1400
7
:::5000
CPU_BR_L
CPU_CNTL_GROUP:G:L:S:0
7
MIL:1100
:::5000
CPU_BG_L
CPU_CNTL_GROUP:G:L:S:0
7
MIL:1100
:::5000
CPU_TS_L
CPU_CNTL_GROUP:G:L:S:0
7
MIL:1000
:::5000
CPU_TT<0..4>
CPU_CNTL_GROUP:G:L:S:0:1300
7
:::5000
CPU_TBST_L
CPU_CNTL_GROUP:G:L:S:0
7
MIL:1100
:::5000
CPU_TSIZ<0..2> CPU_CNTL_GROUP:G:L:S:0:1260
7
:::5000
CPU_ARTRY_L
CPU_CNTL_GROUP:G:L:S:0
7
MIL:1000
:::5000
CPU_AACK_L
CPU_CNTL_GROUP:::1000
7
:::1000
CPU_GBL_L
CPU_CNTL_GROUP:::1000
3
:::3500
CPU_INT_GBL_L CPU_CNTL_GROUP:G:L:S:0
5
MIL:1100
:::5000
CPU_CI_L
CPU_CNTL_GROUP:G:L:S:0
7
MIL:1000
:::5000
CPU_HIT_L
CPU_CNTL_GROUP:G:L:S:0
7
MIL:1000
:::3500
CPU_DBG_L
CPU_CNTL_GROUP:G:L:S:0
7
MIL:1000
:::500
CPU_DRDY_L
CPU_CNTL_GROUP:G:L:S:0
5
MIL:1100
:::5000
CPU_WT_L
CPU_CNTL_GROUP:G:L:S:0
7
MIL:1000
:::5000
CPU_DRDY_L_UF
2
:::5000
CPU_DTI<0..2> CPU_CNTL_GROUP:G:L:S:0:1150
7
:::5000
CPU_TA_L
CPU_CNTL_GROUP:G:L:S:0
7
MIL:1100
:::5000
CPU_TEA_L
CPU_CNTL_GROUP:G:L:S:0
7
MIL:1100
:::5000
CPU_QREQ_L
CPU_CNTL_GROUP:G:L:S:0
7
MIL:1000

250
1550
250
MIL
MIL
250
250
MIL
250
250
MIL
250
250
MIL
250
250
MIL
250
250
MIL
MIL
250
MIL
250
MIL
250
MIL
250
250
250
MIL
250
MIL
250
MIL
250

:::4000
CPU_CNTL_GROUP:G:L:S:0
MIL:1000 MIL
250
CPU_QACK_L
8
SYSCLK_CPU_UF
2
:::150
SYSCLK_CPU
4
::2200:2400 200
200
INT_CPU_FB_OUT
3
:::1000

NET_SPACING_TYPE

NO_TEST

PULSE_PARAM

166 MHZ
166 MHZ
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10

MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL

SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING

10 MIL SPACING
10 MIL SPACING
10 MIL SPACING

MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ

166
166
166
166

MHZ
MHZ
MHZ
MHZ

315
315
315

166
166
166
166

MHZ
MHZ
MHZ
MHZ

315
315
315
315

MHZ
MHZ
MHZ
MHZ

315
315

3
3
4
4

200
:::200
::1400:1500 200
200
::900:1000
200
:::1000

CPU_FB_PLUS2
CPU_FB_PLUS3
INT_ANALYZER_CLK
SYSCLK_LA

3
3
3
2

::900:1000
::2900:3000
:::300
:::2000

166
166
166
166

INT_CLOCK_OUT

:::3000

166 MHZ

:::1000
3
:::1000
3
:::100
3
:::100
2
:::500
USB2_RSDA:G:L:S:02 MIL:20
MIL
:::500
USB2_RSDA:G:L:S:02 MIL:20
MIL
:::500
USB2_RSDB:G:L:S:02 MIL:20
MIL
:::500
USB2_RSDB:G:L:S:02 MIL:20
MIL
:::500
USB2_RSDC:G:L:S:02 MIL:20 MIL
:::500
USB2_RSDC:G:L:S:02 MIL:20
MIL
:::500
USB2_DMA:G:L:S:0 MIL:30
3
MIL
:::500
USB2_DMA:G:L:S:0 MIL:30
3
MIL
:::500
USB2_DMB:G:L:S:0 MIL:20
3
MIL
:::500
USB2_DMB:G:L:S:0 MIL:20
3
MIL
:::500
USB2_DMC:G:L:S:0 MIL:20
3
MIL
:::500
USB2_DMC:G:L:S:0 MIL:20
3
MIL
:::3000
USB2_DMAT:G:L:S:04 MIL:60
MIL
:::3000
USB2_DMAT:G:L:S:04 MIL:60
MIL
:::3000
USB2_DMBT:G:L:S:04 MIL:60 MIL
:::3000
USB2_DMBT:G:L:S:04 MIL:60 MIL
:::3000
USB2_DMCT:G:L:S:04 MIL:60
MIL
:::3000
USB2_DMCT:G:L:S:04 MIL:60
MIL
:::750
USB2_CONA:G:L:S:02 MIL:30 MIL
:::750
USB2_CONA:G:L:S:02 MIL:30
MIL
:::750
USB2_CONB:G:L:S:02 MIL:30
MIL
:::750
USB2_CONB:G:L:S:02 MIL:30 MIL
:::750
USB2_CONC:G:L:S:02 MIL:30 MIL
:::750
USB2_CONC:G:L:S:0 MIL:30 MIL
2

4B7<> 4C7<> 8B4<> 8B5<> 8B7<> 8B8<> 8C4<> 8C5<> 8C7<> 8C8<>
9C3<> 9D3<> 9D5< 9D8<
5A4<> 5B4<> 5C4<> 5D4<> 6C4< 8C4<> 8C4< 8C5<> 8C7<> 8C7< 8C8<>
8D4<> 8D5<> 8D7<> 8D8<> 9A7< 9B1<> 9B7< 9C1<> 9C5< 9C8< 9D1<>
4D7> 7C7< 8B4<> 9D3<
4D7< 7B7< 8B4<> 9D3<>

166
166
166
166
166
166
166
166
166
166
166
166
166
166
166
166
166
166
166
166

CPU_FBO_PLUS1
CPU_FBI_PLUS1
CPU_FB_MINUS3
INT_CPU_FB_IN

USB2_XT1
USB2_XT2_B
USB2_XT2
USB2_RREF
USB2_RSDAM
USB2_RSDAP
USB2_RSDBM
USB2_RSDBP
USB2_RSDCM
USB2_RSDCP
USB2_DAN_F
USB2_DAP_F
USB2_DBN_F
USB2_DBP_F
USB2_DCN_F
USB2_DCP_F
USBT_DAN_F
USBT_DAP_F
USBT_DBN_F
USBT_DBP_F
USBT_DCN_F
USBT_DCP_F
USB_DAN_CON
USB_DAP_CON
USB_DBN_CON
USB_DBP_CON
USB_DCN_CON
USB_DCP_CON

MAX_EXPOSED_LENGTH

100
100
100

MIN_LINE_WIDTH
10 MIL SPACING
30 MHZ
10 MIL SPACING
30 MHZ
10 MIL SPACING
30 MHZ

50
50
50
50
50
50
2000
2000
2000
2000
2000
2000
50
50
50
50
50
50

8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

4D7<> 7C7< 8B7<> 9D3<>


4B7<> 7A7< 8B4<> 8B5<> 9B3<>
4B7> 7B7< 8B4<> 9B3<>
4B7> 8B5<> 8B7< 9B3<>
4A7<> 7C7< 8B8<> 9B3<>
4A7< 7B7< 8B5<> 9B3<>
4B8<> 8B5<>
4B8< 7B7< 9C3<>
4A7> 7A7< 8C5<> 9C3<>
4A7> 7C7< 8B8<> 9B3<
4C3< 7B7< 8B8<> 9B1<>
4C2< 7B7< 8B5<> 9B1<
4B7> 7A7< 8B5<> 9B3<>
4C3<>
4C3< 8B4<> 8B7<> 9A1<>
4C3< 7C7< 8C4<> 9A1<>
4C3< 7B7< 8B5<> 9A1<>
4C3> 7D5< 8B7<> 9B3<

4C3< 8B4<> 9B3<>


9A3<>
4D2< 9A4<
9B3<>
9A5<
9A5<
9A4<
9B3<
9A5<
9A4<
8A2< 9B4< 16C7< 54A7< 59A7>
8A2< 8D8<>
8B2<>

DIFFERENTIAL_PAIR
32C4<
32C4<>
32B4<>

MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL

SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING

3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5

480
480
480
480
480
480
480
480
480
480
480
480
480
480
480
480
480
480
480
480
480
480
480

MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ

480 MHZ

32C4<>
32C4<>
32C4<>
32C4<>

32C4<> RATSNEST_SCEDULE
32C4<>

USB2_DMA_DP
USB2_DMA_DP
USB2_DMB_DP
USB2_DMB_DP
USB2_DMC_DP
USB2_DMC_DP
USB2_DMAT_DP
USB2_DMAT_DP
USB2_DMBT_DP
USB2_DMBT_DP
USB2_DMCT_DP
USB2_DMCT_DP
USB2_CONA_DP
USB2_CONA_DP
USB2_CONB_DP
USB2_CONB_DP
USB2_CONC_DP
USB2_CONC_DP

MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN
MIN_DAISY_CHAIN

32C1<> 33B7<
32C1<> 33B7<
32C1<> 33C7<
32C1<> 33C7<
32C1<> 33D7<
32C1<> 33D7<
33B6<>
33B6<>
33C6<>
33C6<>
33D6<>
33D6<>
33C3<> 59C5>
33C3<> 59C5>
33B3<> 59C5>
33B3<> 59C5>
33D3<> 59C5>
33D3<> 59C5>

SIGNAL CONSTRAINTS

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:26:16 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569
A
56 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

7
DIGITAL SIGNALS

DIGITAL SIGNALS
MIN_LINE_WIDTH

GROUP

NEW
STUFF
HERE

SIG_NAME

RELATIVE_PROPAGATION_DELAY
MAX_VIAS

3
4
3
5
4
4
4
2
2
2

VSYNC*
ANALOG_VSYNC*
HSYNC*
ANALOG_HSYNC*
ANALOG_BLU
ANALOG_GRN
ANALOG_RED
FILT_ANALOG_RED
FILT_ANALOG_GRN
FILT_ANALOG_BLU
DAC2RSET
DAC2VREF
NV11_XTALIN
NV11_XTALOUT

4
4

PROPAGATION_DELAY
STUB_LENGTH NET_SPACING_TYPE

L:S::1000 MIL
L:S::3500 MIL
L:S::1000 MIL
L:S::3500 MIL
L:S::4000 MIL
200
L:S::4000 MIL
200
L:S::4000 MIL
200
L:S::500 MIL
L:S::500 MIL
L:S::500 MIL
L:S::1000 MIL
L:S::1000 MIL
L:S::1000 MIL
100
L:S::1000 MIL
100

MIN_LINE_WIDTH
GROUP

MAX_EXPOSED_LENGTH PULSE_PARAM

22C5<>
22D7< 25C6<> 26B5< 59B7>
22C5<>
22D7< 25D6<> 26B5< 59B7>

10
10
10
10
10
10
10

MIL
MIL
MIL
MIL
MIL
MIL
MIL

SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING

5.8
5.8
5.8
5.8
5.8
5.8

SIG_NAME

HERE

I281
I278

22C7<> 25C6<
22C7<> 25C6<

I277

22C7<> 25B6<
25C5< 59B7>

I280

25C5< 59B7>

I274

25C5< 59B7>
22C5<>

I275

I279

I276

I282

10 MIL SPACING
8 MIL SPACING
8 MIL SPACING

27 MHZ
27 MHZ

22C5<>
22B4<>

I284
I283

22B4<>

I285

I286
I289
I288

I291
I290
I293
I292

TMDSFILT:G:L:S:02 MIL:110
TMDSFILT:G:L:S:02 MIL:110
TMDSFILT:G:L:S:02 MIL:110
TMDSFILT:G:L:S:02 MIL:110
TMDSFILT:G:L:S:02 MIL:110

MIL
MIL
MIL
MIL
MIL

TD1M
TD2P
TD2M

TMDSFILT:G:L:S:02 MIL:110 MIL


TMDSFILT:G:L:S:02 MIL:110 MIL
TMDSFILT:G:L:S:02 MIL:110 MIL

110
110
110
110
110
110
110
110

8
8
8
8
8

MIL
MIL
MIL
MIL
MIL

SPACING
SPACING
SPACING
SPACING
SPACING

I294

TMDSFILT_CLK
TMDSFILT_CLK
TMDSFILT_D0
TMDSFILT_D0
TMDSFILT_D1

24C4<>
24C3<>

I295
I296

24C3<>
24C4<>

I297

24C4<>

8 MIL SPACING TMDSFILT_D1


8 MIL SPACING TMDSFILT_D2
8 MIL SPACING TMDSFILT_D2

I299
I300

24C3<>
24C3<>

I298
I302

24C4<>
I301

ENET_LINK_TX_EN
ENET_LINK_TX_ER
ENET_LINK_TXD<0..3>
ENET_PHY_TX_EN
ENET_PHY_TX_ER
ENET_PHY_TXD<0..3>
CLKENET_LINK_TX

4
4
4
4
4
4
4
4
4
4
4

CLKENET_PHY_TX
CLKENET_LINK_RX
CLKENET_PHY_RX
ENET_PHY_RXD<0..3>
ENET_PHY_RX_DV
ENET_PHY_RX_ER
ENET_PHY_CRS
ENET_PHY_COL
ENET_LINK_RXD<0..3>
ENET_CRS
ENET_COL
ENET_RX_DV
ENET_RX_ER
CLK25M_ENET_XIN
CLK25M_ENET_XOUT

ENET_TDP
ENET_TDN
ENET_RDP
ENET_RDN
RJ45_TXP
RJ45_TXN
RJ45_RXP
RJ45_RXN

ETHTD:G:L:S:0
ETHTD:G:L:S:0
ETHRD:G:L:S:0
ETHRD:G:L:S:0
RJTXD:G:L:S:0
RJTXD:G:L:S:0
RJRXD:G:L:S:0
RJRXD:G:L:S:0

4
4
4
4
4
4
4
4
4
3
3

L:S::1000 MIL
L:S::1000 MIL
L:S::1000
L:S::5600 MIL
L:S::5600 MIL
L:S:4600:5600
L:S:4600 MIL:5600
L:S::1000 MIL
L:S:4600 MIL:5600
L:S::1000 MIL
L:S::1000
L:S::1000 MIL
L:S::1000 MIL
L:S::1000 MIL
L:S::1000 MIL
L:S:4600:5600
L:S:4600 MIL:5600
L:S:4600 MIL:5600
L:S:4600 MIL:5600
L:S:4600 MIL:5600
L:S::1000 100
MIL
100
L:S::1000 MIL

MIL:70
3
3
MIL:70
3
MIL:70
3
MIL:70
MIL:70
2
2
MIL:70
2
MIL:70
MIL:70
2

MIL
L:S::4000
MIL
3150
MIL
L:S::4000
MIL
3150
MIL
L:S::4000
MIL
3150
MIL
L:S::4000
MIL
3150
MIL
L:S::750
MIL
MIL
L:S::750
MIL
MIL
L:S::750
MIL
MIL
L:S::750
MIL

FW_LINK_DATA<0..7>
FW_LINK_CNTL<0..1>
FW_LINK_LREQ
FW_SCLK
FW_D<0..7>
FW_CNTL0
FW_CNTL1
FW_LREQ
FW_PHY_SCLK
FW_PHY_CNTL0
FW_PHY_CNTL1
FW_PHY_D<0..7>
FW_XI
FW_XO
FW_BIAS1
FW_BIAS2
FW_TPA1P
FW_TPA1N
FW_TPB1P
FW_TPB1N
FW_TPA2P
FW_TPA2N
FW_TPB2P
FW_TPB2N
FW_TPO1P
FW_TPO1N
FW_TPI1P
FW_TPI1N
FW_TPO2P
FW_TPO2N
FW_TPI2P
FW_TPI2N

MIL

MIL
MIL
MIL
MIL
8 MIL SPACING
8 MIL SPACING
10 MIL SPACING
10 MIL SPACING
10 MIL SPACING
10 MIL SPACING
2KV_ISO
2KV_ISO
2KV_ISO
2KV_ISO

ETH_TXD
ETH_TXD
ETH_RXD
ETH_RXD
RJ45_TXD
RJ45_TXD
RJ45_RXD
RJ45_RXD

MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ

25
25
25
25
25
25
25
25
25
25
25
25
25
25
25

MHZ 35C6<>
MHZ 34C7< 35C8<
MHZ 35C6<>
MHZ 35B6<> 35C6<>
MHZ 35B6<>
MHZ 35B6<>
MHZ 35B6<>
MHZ 35B6<>
MHZ 34C7< 35B8< 35C8<
MHZ 34C7< 35B8<
MHZ 34B7< 35B8<
MHZ 34C7< 35B8<
MHZ 34C7< 35B8<
MHZ 35B6<
MHZ 35B6<>

100
100
100
100
100
100
100
100

FWTPA1:G:L:S:0
FWTPA1:G:L:S:0
FWTPB1:G:L:S:0
FWTPB1:G:L:S:0
FWTPA2:G:L:S:0
FWTPA2:G:L:S:0
FWTPB2:G:L:S:0
FWTPB2:G:L:S:0
FWTPO1:G:L:S:0
FWTPO1:G:L:S:0
FWTPL1:G:L:S:0
FWTPL1:G:L:S:0
FWTPO2:G:L:S:0
FWTPO2:G:L:S:0
FWTPL2:G:L:S:0
FWTPL2:G:L:S:0

4
4
4
4
4
4
4
4
4
4
4
4
3
3

L:S::1000
L:S::1000
L:S::1000 MIL
L:S:3500 MIL:4500
L:S:3700:4700
L:S:3700 MIL:4700
L:S:3700 MIL:4700
L:S:3700 MIL:4700
L:S::500 MIL
L:S::1000 MIL
L:S::1000 MIL
L:S::1000
L:S::1000 MIL
100
L:S::1000 MIL
100

I303

34D6<>
34D6<>

I304
I305

34C6<>
I307

34D7< 35C6<
34D7< 35C6<

I306
I308

34C7< 35C6<>
34D7< 35C8<

MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ

2KV_ISO
2KV_ISO
2KV_ISO
2KV_ISO
2KV_ISO

RJ45_TREF
RJ45_RREF
RJ45_4_5
RJ45_7_8
RJ45_F_TREF

MIL

25
25
25
25
25
25
25

RELATIVE_PROPAGATION_DELAY
MAX_VIAS STUB_LENGTH NET_SPACING_TYPE

MAX_EXPOSED_LENGTH PULSE_PARAM

NEW
STUFF

I287

TCKP
TCKM
TD0P
TD0M
TD1P

I309

3
3
3
3
3
3
3
3

70
70
70
70
70
70
70
70

8
8
8
8
8
8
8
8

MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL

SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING

TMDS_CLK
TMDS_CLK
TMDS_D0
TMDS_D0
TMDS_D1
TMDS_D1
TMDS_D2
TMDS_D2

MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL

3
3
3
3
3
3
3
3

50
50
50
50
50
50
50
50

8
8
8
8
8
8
8
8

MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL

SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING

G_TMDS_CLK
G_TMDS_CLK
G_TMDS_D0
G_TMDS_D0
G_TMDS_D1
G_TMDS_D1
G_TMDS_D2
G_TMDS_D2

MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL

3
3
3
3
3
3
3
3

50
50
50
50
50
50
50
50

8
8
8
8
8
8
8
8

MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL

SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING

S_TMDS_CLK
S_TMDS_CLK
S_TMDS_D0
S_TMDS_D0
S_TMDS_D1
S_TMDS_D1
S_TMDS_D2
S_TMDS_D2

MIL:400
MIL:400
MIL:400
MIL:400
MIL:400
MIL:400
MIL:400
MIL:400
MIL:400
MIL:400
MIL:400
MIL:400

MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL

TMDS_CKP
TMDS_CKM
TMDS_D0P
TMDS_D0M
TMDS_D1P
TMDS_D1M
TMDS_D2P
TMDS_D2M

TMDS:G:L:S:0
TMDS:G:L:S:0
TMDS:G:L:S:0
TMDS:G:L:S:0
TMDS:G:L:S:0
TMDS:G:L:S:0
TMDS:G:L:S:0
TMDS:G:L:S:0

GPU_TMDS_CKP
GPU_TMDS_CKM
GPU_TMDS_D0P
GPU_TMDS_D0M
GPU_TMDS_D1P
GPU_TMDS_D1M
GPU_TMDS_D2P
GPU_TMDS_D2M

GTMDS:G:L:S:0
GTMDS:G:L:S:0
GTMDS:G:L:S:0
GTMDS:G:L:S:0
GTMDS:G:L:S:0
GTMDS:G:L:S:0
GTMDS:G:L:S:0
GTMDS:G:L:S:0

MIL:120
MIL:120
MIL:120
MIL:120
MIL:120
MIL:120
MIL:120
MIL:120

SI_TMDS_CKP
SI_TMDS_CKM
SI_TMDS_D0P
SI_TMDS_D0M
SI_TMDS_D1P
SI_TMDS_D1M
SI_TMDS_D2P
SI_TMDS_D2M

STMDS:G:L:S:0
STMDS:G:L:S:0
STMDS:G:L:S:0
STMDS:G:L:S:0
STMDS:G:L:S:0
STMDS:G:L:S:0
STMDS:G:L:S:0
STMDS:G:L:S:0

MIL:120
MIL:120
MIL:120
MIL:120
MIL:120
MIL:120
MIL:120
MIL:120

DVOD0
DVOD1
DVOD2
DVOD3
DVOD4
DVOD5
DVOD6
DVOD7
DVOD8
DVOD9
DVOD10
DVOD11

MIL:120
MIL:120
MIL:120
MIL:120
MIL:120
MIL:120
MIL:120
MIL:120

TMDS_XMIT:G:L:S:0
TMDS_XMIT:G:L:S:0
TMDS_XMIT:G:L:S:0
TMDS_XMIT:G:L:S:0
TMDS_XMIT:G:L:S:0
TMDS_XMIT:G:L:S:0
TMDS_XMIT:G:L:S:0
TMDS_XMIT:G:L:S:0
TMDS_XMIT:G:L:S:0
TMDS_XMIT:G:L:S:0
TMDS_XMIT:G:L:S:0
TMDS_XMIT:G:L:S:0

MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL

23D1< 24B7<> 27C2< 59A7>


23D1< 24A7<> 27C2< 59A7>
23D1< 24B7<> 27C2< 59B7>
23D1< 24B7<> 27C2< 59A7>
23D1< 24C7<> 27C2< 59B7>
23D1< 24C7<> 27C2< 59B7>

23C2< 23D3<>
23C2< 23D3<>
23C2< 23D3<>
23C2< 23D3<>
23C2< 23D3<>
23C2< 23D3<>
23C2< 23D3<>
23C2< 23D3<>
27C3<>
27C3<>
27C3<>
27C3<>
27C3<>
27C3<>
27C3<>
27C3<>

165MHZ
165MHZ
165MHZ
165MHZ
165MHZ
165MHZ
165MHZ
165MHZ
165MHZ
165MHZ
165MHZ
165MHZ

200
200
200
200
200
200
200
200
200
200
200
200

23D1< 24D7<> 27C2< 59B7>


23D1< 24D7<> 27C2< 59B7>

22C5<> 27A8< 27C5<


22C5<> 27A8< 27C5<
22C5<> 26D1< 27C5<
22B5<> 26D1< 27C5<
22B5<> 27A8< 27C5<
22B5<> 27A8< 27C5<

22B5<> 27A8< 27C5<


22B5<> 27A8< 27C5<
22B5<> 26B1< 27C5<
22B5<> 27A8< 27C5<
22B5<> 27A8< 27B5<
22B5<> 27A8< 27B5<

35C3<>
35C3<>
35C3<>
35C3<>

35C1<>
35C1<>
35C1<>
35C1<>

35C2<>
35C2<>
35C1<>
35C1<>
35B2<
34C4<>

49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
24.576
24.576

MIL
MIL
MIL
MIL

8 MIL SPACING
8 MIL SPACING

MHZ 34C4<>
MHZ 34C4<>
MHZ 34C5<> 36C8<
MHZ 34C3< 36B8< 36C8<
MHZ 34C3< 36C8<
MHZ 34C3< 36C8<
MHZ 34C3< 36C8<
MHZ 36C7<>
MHZ 36C7<>
MHZ 36C7<>
MHZ 36B7<> 36C7<>
MHZ 36C6<
MHZ 36C6<>
36C5<>
36C5<>

MIL:50L:S::1220
MIL
3
MIL:50L:S::1220
MIL
3
MIL:50L:S::1220
MIL
3
MIL:50
MIL
3
L:S::1220
MIL:50L:S::1220
MIL
3
MIL:50
MIL
3
L:S::1220
MIL:50L:S::1220
MIL
3
MIL:50L:S::1220
MIL
3
MIL:50L:S::1220
MIL
3
MIL:50L:S::1220
MIL
3
MIL:50L:S::1220
MIL
3
MIL:50
MIL
3
L:S::1220
MIL:50L:S::1220
MIL
3
MIL:50L:S::1220
MIL
3
MIL:50L:S::1220
MIL
3
MIL:50L:S::1220
MIL
3

MIL
5000
MIL
5000
MIL
5000
MIL
5000
MIL
5000
MIL
5000
5000
MIL
MIL
5000
MIL
5000
MIL
5000
MIL
5000
5000
MIL
5000
MIL
MIL
5000
5000
MIL
5000
MIL

FW_TPA1
FW_TPA1
FW_TPB1
FW_TPB1
FW_TPA2
FW_TPA2
FW_TPB2
FW_TPB2
FW_TPO1
FW_TPO1
FW_TPL1
FW_TPL1
FW_TPO2
FW_TPO2
FW_TPL2
FW_TPL2

400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400

MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ
MHZ

36C5<>
36C5<>
36C5<>
36C5<>
36C5<>
36C5<>
36C5<>
36C5<>
36B8<> 36D1<>
36A8<> 36D1<>

SIGNAL CONSTRAINTS

NOTICE OF PROPRIETARY PROPERTY

LAST_MODIFIED=Mon Oct 27 12:26:17 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

36A8<>
36A8<>
36A8<>
36A8<>
36A8<>
36A8<>

36D1<>
36D1<>
36C1<>
36C1<>
36C1<>
36C1<>

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
57 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

DIGITAL SIGNALS (CONTD)


MAX_VIAS

GROUP
CD DRIVE BUS

I17
I18
I19
I20

I21
I22
I23
I24
I25
I26
I27
I28
I29
I30
I31
I32
I33
I34
I35
I36
I37

STUB_LENGTH

NET_SPACING_TYPE
SIG_NAME
RELATIVE_PROPAGATION_DELAY PROPAGATION_DELAY
L:S:3500 MIL:5500 MIL
EIDE_RST_L
L:S:3500 MIL:5500 MIL
EIDE_DMACK_L
L:S::5500 MIL
EIDE_STOP
L:S::5500 MIL
EIDE_HSTB_RDY
L:S:3500 MIL:5500 MIL
EIDE_DSTB_RDY
L:S:3500:5500
EIDE_DATA<0..15>
L:S::1000 MIL
CD_RESET_L
L:S::4000 MIL
CD_DMACK_L
L:S::5000 MIL
CD_STOP
L:S::5000 MIL
CD_HSTB_RDY
L:S::1000 MIL
CD_DSTB_RDY
L:S::1000
UATAD<0..15>
L:S::1000 MIL
CD_DMARQ
L:S:3500 MIL:5500 MIL
EIDE_DMARQ
L:S::1000 MIL
UATA0IRQ
L:S:3500 MIL:5500 MIL
EIDE_INTRQ
CD_EIDE_ADDR<0..2>
L:S::1000
EIDE_ADDR<0..2>
L:S:3500:5500
CD_CS1FX_L
L:S::1000 MIL
EIDE_CS1FX_L
L:S:3500 MIL:5500 MIL
CD_CS3FX_L
L:S::1000 MIL
EIDE_CS3FX_L
L:S:3500 MIL:5500 MIL

MAX_EXPOSED_LENGTH

I38

PULSE_PARAM

33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33

MHZ 37A7> 37D5<


MHZ 37A7<> 37D5<
MHZ 37A7> 37D5<
MHZ 37A7> 37C5<
MHZ 37A7< 37C5<
MHZ 37A5< 37B5< 37B7<> 37C5<
MHZ 37D4< 38C6<>
MHZ 37D4< 38C6<>
MHZ 37D4< 38C6<>
MHZ 37C4< 38C6<>
MHZ 37C4< 38C6<>
MHZ 37A4< 37B4< 37C4< 38C6<>
MHZ 38C6<>
MHZ 37A7< 38C8<
MHZ 38C6<>
MHZ 37A7< 38C8<
MHZ 38C6<>
MHZ 37B7> 38A8< 38B8<
MHZ 38C6<>
MHZ 37A7> 38B8<
MHZ 38C6<>
MHZ 37A7> 38B8<

HD DRIVE BUS
I39
I40
I41
I42
I43
I44
I45

I46
I47

I48
I49

I50
I51
I52
I53
I54
I55
I56
I57
I58

L:S:100 MIL:6000
UIDE_RST_L
HD_DATA:G:L:S:0 MIL:5500 MIL
500
MIL:6000
UIDE_DMACK_L HD_DATA:G:L:S:0 L:S:100
MIL:5500 MIL
500
MIL:6000
UIDE_DIOR_L HD_DATA:G:L:S:0 L:S:100
MIL:5500 MIL
MIL
UIDE_DIOW_L HD_DATA:G:L:S:0 L:S::6000
MIL:5500 MIL
MIL:6000
UIDE_IOCHRDY HD_DATA:G:L:S:0 L:S:100
MIL:5500 MIL
500
L:S:100:6000
UIDE_DATA<0..15>
HD_DATA:G:L:S:0:5500
HD_RESET_L
L:S::1000 MIL
L:S::1000 MIL
HD_DMACK_L
L:S::5500 MIL
HD_DIOR_L
L:S::55000 MIL
HD_DIOW_L
HD_IOCHRDY
L:S::1000 MIL

MIL
MIL
MIL
MIL

100
100
100
100
100

MHZ
MHZ
MHZ
MHZ
MHZ

37C7<> 37D3<
37C7<> 37D3<

100
100
100
100

MHZ
MHZ
MHZ
MHZ

37A3< 37B3< 37C3< 37C7<> 37D7<>


37D1< 38C3<>

100 MHZ
100 MHZ
100 MHZ
100
100
100
100
100
100
100

CLK_18M_INT_XOUT
CLK_18M_INT_XOUT

3
3

I62

CLK_18M_INT_XOUT

I63
I64
I65
I66
I67

I68

I69
I70
I71
I72
I73
I74
I75
I77
I78
I79
I80
I81
I82

L:S::1000 100
L:S::1000
100
L:S::200 50

8 MIL SPACING
8 MIL SPACING
8 MIL SPACING

I85
I86
I87
I88
I84

I89

I90
I91
I92
I93

L:S::1000
L:S::1000
L:S::300
L:S::1000
L:S::1000
L:S::300

MIL
100
MIL
100
MIL
50
MIL
100
MIL
100
MIL
50

100 MHZ

L:S::1000 MIL

100 MHZ

T_UD_IDEDD_3

L:S::1000 MIL

100 MHZ

T_UD_IDEDD_4

L:S::1000 MIL

100 MHZ

T_UD_IDEDD_5

L:S::1000 MIL

100 MHZ

T_UD_IDEDD_6

L:S::1000 MIL

100 MHZ

T_UD_IDEDD_7

L:S::1000 MIL

100 MHZ

T_UD_IDEDD_8

L:S::1000 MIL

100 MHZ

T_UD_IDEDD_9

L:S::1000 MIL

100 MHZ

T_UD_IDEDD_10

L:S::1000 MIL

100 MHZ

T_UD_IDEDD_11

L:S::1000 MIL

100 MHZ

T_UD_IDEDD_12

L:S::1000 MIL

100 MHZ

T_UD_IDEDD_13

L:S::1000 MIL

100 MHZ

T_UD_IDEDD_14

L:S::1000 MIL

100 MHZ

T_UD_IDEDD_15

L:S::1000 MIL

100 MHZ

I7

38C3<>
37C7<> 38B4<

I8

38C2<>
37C7<> 38B4<

I9

18.432 MHZ

58B5>

I12

28A3< 28B3<>
28A3< 28B3<>

I13

28B2< 33B7<

I15

37C1< 38C3<>
37C1< 38C3<>

37B1< 38C3<>
37B1< 38C3<>
37B1< 38C3<>
37B1< 38C2<>

37B1< 38C2<>
37B1< 38C2<>
37B1< 38C2<>
37A1< 38C2<>
37A1< 38C2<>

I16

28B2< 33B7<
28A3< 28B3<>

37C1< 38C3<>

37B1< 38C2<>

I10

I11

37C1< 38C3<>

37B1< 38C3<>

I6

I14

37A1< 38C2<>

28A3< 28B3<>
28B2< 33C7<
28B2< 33C7<
28A3< 28B3<>
28A3< 28B3<>
28B2< 33D7<
28B2< 33D7<
28B3<>
28B3<>
28B2< 29D3<> 59B5>
28B2< 29D3<> 59B5>
28B3<>
28B3<>
28B2< 29C5<> 59B5>
28B2< 29C5<> 59B5>

8
8
8
8
8
8
10
10
10
10
10

MICSHLD
MICHIGH
MICLOW
KS_INT_SPKR+
KS_INT_SPKR-

38C2<> 38C3<>
37C7<> 38A4< 38B4<

58B5>

USBA:G:L:S:0 MIL:500 MIL


USBA:G:L:S:0 MIL:500 MIL
100
USBA_F:G:L:S:0 MIL:500 MIL
100
USBA_F:G:L:S:0 MIL:500 MIL
USBB:G:L:S:0 MIL:500 MIL
USBB:G:L:S:0 MIL:500 MIL
USBB_F:G:L:S:0 MIL:500 MIL 100
USB_DBP_F
100
USB_DBN_F
USBB_F:G:L:S:0 MIL:500 MIL
USB_DCP
USBC:G:L:S:0 MIL:500 MIL
USBC:G:L:S:0
MIL:500
MIL
USB_DCN
USBC_F:G:L:S:0 MIL:500 MIL 100
USB_DCP_F
USBC_F:G:L:S:0 MIL:500 MIL 100
USB_DCN_F
USBE:G:L:S:0 MIL:500 MIL
USB_DEP
USBE:G:L:S:0 MIL:500 MIL
USB_DEN
USBE_F:G:L:S:0 MIL:500 MIL 100
BT_USB_DP
USBE_F:G:L:S:0 MIL:500 MIL 100
BT_USB_DM
USBF:G:L:S:0 MIL:500 MIL
USB_DFP
USBF:G:L:S:0 MIL:500 MIL
USB_DFN
MODEM_USB_DP USBF_F:G:L:S:0 MIL:500 MIL 100
MODEM_USB_DM USFE_F:G:L:S:0 MIL:500 MIL 100

3
3
3
3
3
3

L:S::1000 MIL

T_UD_IDEDD_2

I5

58B5>

USB_DAP
USB_DAN
USB_DAP_F
USB_DAN_F
USB_DBP
USB_DBN

PMU_XO
PMU_XI
PMU_XT
PMU_CLKOUT
PMU_CLKIN
PMU_CLKT

T_UD_IDEDD_1

I4

18.432 MHZ
18.432 MHZ

I83

I76

100 MHZ

I3

38C3<>
MHZ 37C7< 38C4<

MHZ
MHZ
MHZ
MHZ
MHZ
MHZ

L:S::1000 MIL

I2

38C3<>
37C7<> 38C4<

PROPAGATION_DELAY
PULSE_PARAM

T_UD_IDEDD_0
I1

37C1< 38C3<>

37C1< 38C3<>

L:S::1000 MIL
HD_DMARQ
L:S:100 MIL:6000
MIL
MIL
UIDE_DMARQ HD_DATA:G:L:S:0 MIL:5500
HD_INTRQ
L:S::1000 500
MIL
HD_DATA:G:L:S:0
MIL:5500
L:S:100
MIL:6000
MIL
MIL
UIDE_INTRQ
HD_UIDE_ADDR<0..2>
L:S::1000
HD_DATA:G:L:S:0:5500
L:S:100:6000
UIDE_ADDR<0..2>
HD_UIDE_CS1FX_L
L:S::6000 MIL
L:S::6000MIL
MIL
UIDE_CS1FX_LHD_DATA:G:L:S:0 MIL:5500
HD_UIDE_CS3FX_L
L:S::6000 MIL
L:S::6000MIL
MIL
UIDE_CS3FX_LHD_DATA:G:L:S:0 MIL:5500

I61

SIG_NAME

37D1< 38C3<>
37D1< 38C3<>

100 MHZ
100 MHZ

I59

I60

37C7<> 37D3<

37C3< 37C7<>
37C3< 37C7<

MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL

SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING
SPACING

10 MHZ

44B5<

10 MHZ 44B5<
10 MHZ 44A6<
32.768 MHZ 44B4<>
32.768 MHZ 44B4<>
32.768 MHZ 44B2<>

SIGNAL CONSTRAINTS

29A5<> 43A8< 59A7>


29A5<> 43B8< 59A7>
29A5<> 43A8< 59A7>

NOTICE OF PROPRIETARY PROPERTY

29A3< 43D7< 59B7>

LAST_MODIFIED=Mon Oct 27 12:26:18 2003

29A3< 42B4< 43D7< 59B7>

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6569 A
58 69
1
SHT

OF

NONE

DRAWING

<XR_PAGE_TITLE>

7
FUNC_TEST
+1_8V_MAIN

52C1> 51D7<>
51B7< 51A7< 51A5< 50D5<> 50D2< 50C4<>
45D7< 45D3<> 45B4<> 44D8< 42B3< 39C8<
49D7<> 49D3<> 49C4<> 48D6<> 48C8<>
51D6<> 51C2< 51A5< 50D5< 29C5<> 29A8<

52C4
51C3<
50B4<> +12V_MAIN
36D8<
48C4<>
+12V_SLEEP
29A3<
52C1>

29D7<> 28D1< 28C5<>

OUT

25C6< 23D7<>

OUT

45C8<> 45C7<>

OUT

44C4<> 29B2<>

OUT

59D5> 44C5<> 44B1< 8A8<>

OUT

44B5<> 44A5<> 29B3<> 8A8<>

OUT
OUT

PMU_RST*

+2_5V_MAIN
44A4<

OUT

+3V_MAIN

OUT

PWR_SWITCH*
OUT

59D5> 44C5<> 44B1< 8A8<>

OUT

51C6< 50C8< 50C3< 42D8< 39C8<

OUT

51A8< 44C7<>

OUT

44C4<> 29B2<>

OUT

44C5<> 29C5<> 28B8< 28B5<>

OUT

31B4<> 30B2<

CPU_VCORE_SLEEP

OUT

PWR_UP

JTAG_ASIC_TCK

OUT

POWER_UP*

35C4< 34B7< 8A4<>

JTAG_ASIC_TDI

OUT

RESET_BUTTON*

34B7< 28C6< 8A4<>

JTAG_ASIC_TDO

OUT

COMM_RING_DET_L

35B4<> 8A4<>

JTAG_ASIC_TMS

OUT

ROM_ONBOARD_CS_L

35B4<> 35A2< 34B7< 8A4<>

OUT

COMM_DTR_L

JTAG_ASIC_TRST_L
34B7< 8A4<>

OUT

29C7<> 28C3>

OUT

29C7<> 28C3<>

OUT

29C7<> 28D3< 28C3<>

INT_TMDS_3V

OUT

COMM_TXD_L

52A6> 24C3<>

+1_5V_AGP

OUT

COMM_TRXC

FAN_12V_FILT
29D5<> 28C3>

+INTREPID_CORE_MAIN
47C6<>

29C5<> 28C3<>
29C5<> 28D3< 28C3<>

FUNC_TEST

50C2< 44B5<>
8A3<> 7A5< 4B3<
52B3> 44D4<> 44B5<

OUT

24B3<>
24B4<>

OUT

8A3<> 4C3>

56A3> 33D3<>
56A3> 33D3<>
56A3> 33B3<>

JTAG_CPU_TRST_L

56A3> 33B3<>
56A3> 33C3<>

OUT

56A3> 33C3<>
58B5> 29D3<> 28B2<
58A5> 29D3<> 28B2<
58A5> 29C5<> 28B2<
58A5> 29C5<> 28B2<

25C4<>

OUT

57D5> 25C5<

25C4<>

40B7<>
40B7<> 40B6<>
40C7<> 40B7<>
40C7<> 40B7<>
40D4< 28B5<>

TMDS_D2P

OUT_R

OUT

TMDS_D2M

LINEOUT_COMM2

OUT

LINE_OUT_L

TMDS_D1M

OUT

PCIT_AD<10>

OUT

OUT

53A6< 32C6<> 31C7< 30C4<> 30B2<

PCI_AD<11>

OUT

OUT

54C7< 31C6< 31B3<>

PCIT_AD<12>

OUT

OUT

53A6< 32C6<> 31C7< 30C4<> 30B2<

PCI_AD<13>

OUT

OUT

54C7< 31C6< 31C3<>

PCIT_AD<14>

OUT

OUT

53A6< 32C6<> 31C7< 30C4<> 30B2<

PCI_AD<15>

OUT

OUT

53A6< 32C6<> 31C7< 30C4<> 30B2<

PCI_AD<16>

OUT

OUT

54C7< 31C7< 31C3<>

PCIT_AD<17>

OUT

OUT

53A6< 32C6<> 31C7< 30C4<> 30B2<

PCI_AD<18>

OUT

OUT

54C7< 31C7< 31C3<>

PCIT_AD<19>

OUT

OUT

53A6< 32C6<> 31C6< 30C4<> 30B2<

PCI_AD<20>

OUT

OUT

54C7< 31C6< 31C3<>

PCIT_AD<21>

OUT

OUT

53A6< 32C6<> 31C6< 30C4<>

PCI_AD<22>

OUT

OUT

54C7< 31C6< 31C3<>

PCIT_AD<23>

OUT

OUT

53A6< 32C6<> 31B6< 30C4<> 30C1<>

PCI_AD<24>

OUT

OUT

54C7< 31C3<> 31B6<

PCIT_AD<25>

OUT

OUT

53A6< 32B6<> 31B6< 30C4<> 30C1<>

PCI_AD<26>

OUT

OUT

54C7< 31C3<> 31B6<

PCIT_AD<27>

OUT

OUT

54C7< 31C2<> 31B7<

PCIT_AD<28>

OUT

OUT

54C7< 31C3<> 31B6<

PCIT_AD<29>

OUT

OUT

53A6< 32B6<> 31B6< 30C4<> 30C1<>

PCI_AD<30>

OUT

OUT

54C7< 31C3<> 31B6<

PCIT_AD<31>

OUT

FUNC_TEST
FUNC_TEST

54C7< 31C3<> 31B6<

RF_CLKRUN_L

OUT

31C3<>

TMDS_D0M
57D2> 27C2< 24B7<> 23D1<

PCI_AD<9>

54C7< 31C6< 31B3<>

PCIT_IRDY_L

OUT

TMDS_D0P
57D2> 27C2< 24B7<> 23D1<

53A6< 32C6<> 31C7< 30D4<> 30C2<

OUT

FUNC_TEST

OUT

TMDS_D1P
57D2> 27C2< 24C7<> 23D1<

OUT

SND_LIN_SENSE_L

OUT

57D2> 27C2< 24C7<> 23D1<

OUT

LINE_IN_L

OUT

KS_INT_SPKR-

57D2> 27C2< 24D7<> 23D1<

PCIT_AD<8>

LINE_IN_SENSE

OUT

KS_INT_SPKR+

57D2> 27C2< 24D7<> 23D1<

54C7< 31C6< 31B3<>

LINE_IN_R

OUT

GND

58A5> 43D7< 42B4< 29A3<

OUT

OUT

LINE_IN_COM

OUT

58A5> 43D7< 29A3<

PCIT_AD<7>

CPU_VCORE_SLEEP
59D7> 52C6> 45D2<> 8C1< 8B7< 4D7< 4D3<

FILT_ANALOG_GRN
57D5> 25C5<

54C7< 31C6< 31B3<>

VGA_IIC_DAT

OUT

FILT_ANALOG_BLU
FILT_ANALOG_RED

OUT

OUT

VGA_IIC_CLK

OUT

57D5> 25C5<

PCI_AD<6>

USB_PORT_PWR
52A3> 33D3<> 33C3<> 33B3<> 33A4<>

ANALOG_VSYNC*
57D5> 26B5< 25C6<> 22D7<

53A6< 32C6<> 31C7< 30D4<> 30C2<

MODEM_USB_DM

OUT

SND_HP_SENSE_L
57D5> 26B5< 25D6<> 22D7<

OUT

OUT

MODEM_USB_DP

OUT

DDC_VCC_5
OUT

PCIT_AD<5>

BT_USB_DM

OUT

DDC_VCC_3

ANALOG_HSYNC*

54C7< 31C6< 31B3<>

BT_USB_DP

OUT

ROM_RW_L

41A5< 28B5<>

OUT

OUT

USB_DAP_CON

ROM_OE_L

52A6> 25C4<

PCI_AD<4>

USB_DAN_CON

OUT

ROM_CS_L

52B6> 24B3<>

53A6< 32C6<> 31C7< 30D4<> 30C2<

USB_DBP_CON

OUT

+MAXBUS_SLEEP

31B4<> 30B6< 30B2<

OUT

OUT

USB_DBN_CON

OUT

31B2<> 30C6< 30B2<

PCIT_AD<3>

USB_DCP_CON

OUT

JTAG_CPU_TMS
8A3<> 7C5< 4C3<

54C7< 31C6< 31B3<>

USB_DCN_CON

JTAG_CPU_TDO
8A3<> 7A5< 4C3<

OUT

OUT

TMDS_DDC_DAT

OUT

JTAG_CPU_TDI
8A3<> 7A5< 4C3<

PCIT_AD<2>

TMDS_DDC_CLK

JTAG_CPU_TCK
8A3<> 7D5< 4C3<

54C7< 31C6< 31B2<>

PMU_AVCC

OUT

CPU_HRESET_L
44D2< 44C2< 8A3<> 7B3< 7A5< 7A3< 4B3<

OUT

OUT

CPU_SRESET_L

OUT

CPU_CHKSTP_IN_L
7B5< 4B3<

PCIT_AD<1>

OUT

SLEEP

OUT

CPU_CHKSTP_OUT_L
8D5<> 8A3<> 7B5< 4B3>

OUT

54C7< 31C6< 31B3<>

53A6< 32C6<> 31C7< 30D4<> 30C2<

COMM_GPIO_L

OUT

OVDD_ADJ

PCI_AD<0>

OUT

COMM_RXD

OUT

INTREPID_VSENSE

NC_RF_DISABLE_L

OUT

FUNC_TEST
OUT

TMDS_CKP
57D2> 27C2< 24B7<> 23D1<

OUT

TMDS_CKM

PCI_DEVSEL_L
54D7< 32B6<> 31B7< 30C5<> 30B7<

57D2> 27C2< 24A7<> 23D1<

OUT

INV_CUR_HI_FILT
29A5<>

OUT

PCI_STOP_L
54D7< 32B6<> 31B7< 30C5<> 30B7<

OUT

IO_RESET_L

OUT

PCI_TRDY_L
54D7< 32B6<> 31B7< 30C5<> 30B7<

44D3< 44B8<> 35B8< 32A6<

OUT

KS5VSD

OUT

PCI_FRAME_L
53A6< 32B6<> 31B7< 30C5<> 30B7<

52B3> 29A5<>

OUT

54D7< 32B6<> 31B7< 30C5<>


OUT

31C2<>
OUT

31C2<> 28B7<>
OUT

OUT

PMU_PME_L

LAMP_STS_FILT
29A5<>

OUT

33SLOTB_INT_L

INT_ANALYZER_CLK
56B3> 54A7< 16C7< 9B4< 8A2<

OUT

WL_PCI_IDSEL

INT_I2C_DATA2
39B1<> 34B5< 29C7<> 28D1< 28A3<>

OUT

PCI_PAR

INT_I2C_CLK2
39B1<> 34B5< 29C7<> 28D1< 28A3<>

44B2<> 32A8< 31C2< 28B5<>

OUT

CONSTRINT TABLES

OUT

LCD_PWM_FILT
29A5<>

31C2<> 30D5<> 30B5<

PCI_SLOTB_GNT_L

OUT

OUT

LED_5V_FILT

54D7< 31C2<> 30D7<

52B3> 29A5<>

OUT

LED_RET_FILT
52A3> 29A5<>

CLK33M_PCI_SLOTB
PCI_SLOTB_REQ_L

31C3<> 30D5<> 30B7<

NOTICE OF PROPRIETARY PROPERTY

OUT

LAST_MODIFIED=Mon Oct 27 12:26:19 2003


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

OUT

OUT

MICSHLD

44C4<> 32A8< 31D4< 30B2< 17C8<

58A5> 43A8< 29A5<>

MAIN_RESET_L

OUT

PCI_CBE<0>

OUT

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

OUT

MICHIGH

53A6< 32B6<> 31B7< 30C5<>

58A5> 43B8< 29A5<>

II NOT TO REPRODUCE OR COPY IT

OUT

MICLOW
58A5> 43A8< 29A5<>

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

54C7< 31C3<> 31B6<

PCIT_CBE<1>

OUT

54C7< 31C3<> 31B6<

PCIT_CBE<2>

OUT

54C7< 31C3<> 31B6<

PCIT_CBE<3>
UNUSED_GPIO15

OUT

COMM_RESET_L
29D5<> 28C5<>

SIZE

OUT

IIC_ADD
29C6<>

OUT

ROM_WP_L

28C1< 28B5<>

30B2<

FUNC_TEST

OUT

COMM_RTS_L
OUT

47B2<> 46B3< 11D3< 10D6<

OUT

PMURESETBUTTON*

52C4 49B2<> 30B3<

OUT

PWR_SWITCH*

+5V_SLEEP

8D1< 8A3<> 7C7< 7C5< 7C3< 7B3< 7A3< 6D6< 6C5< 4D5<
52C6> 46D4< 45D2<> 44D2< 44D1< 44B7< 9D8< 9B7< 8D4<
31B4<> 30C6< 30B4<

OUT

NMI_BUTTON*

FUNC_TEST

51C8< 51C5<> 50D5< 46D6<> 46C7< 38C1<

OUT

FLO_KNOWS_BEST

+5V_MAIN

17A4< 17A3< 16D7< 16C2< 16A8< 11A6< 10D6<


52C3> 46B4<> 17D5<
52B3> 29A5<>

MON_DETECT

52C4 51B4<>

42C8< 42B7< 42B5< 41A7< 41A5< 40D5< 39D4<


52C4 43C7<
59B5> 52C6> 45D2<> 8C1< 8B7< 4D7< 4D3<

COMM_SHUTDOWN

OUT

+12V_SLEEPA

5
FUNC_TEST

APPLE COMPUTER INC.

OUT

SCALE
OUT

DRAWING NUMBER

REV.

051-6569 A
59 69
1
SHT

OF

NONE

OUT

DRAWING

8
*** Signal Cross-Reference for the entire design ***
+1_5V_AGP

10D6< 11A6< 16A8< 16C2< 16D7<


17A3< 17A4< 17D5< 46B4<> 52C3> 59C7>

+1_5V_INTREPID_PLL 9D4< 16D6< 28D6<> 30D5< 52D3>


+1_5V_INTREPID_PLL1 28C4< 52D3>
+1_5V_INTREPID_PLL2 28D4< 52D3>
+1_5V_INTREPID_PLL3 28D4< 52D3>
+1_5V_INTREPID_PLL4 28D4< 52D3>
+1_5V_INTREPID_PLL5 16D5< 52D3>
+1_5V_INTREPID_PLL6 30D4< 52D3>
+1_5V_INTREPID_PLL7 9D2< 52D3>
+1_5V_INTREPID_PLL8 28D4< 52D3>
+1_8V_MAIN
52C4 59D7>
+2_5V_MAIN
30B3< 49B2<> 52C4 59D7>
+3.3VFPD
24D7< 51C1<> 52B6>
+3V_AUDIO
39D2< 39D6< 39D7< 40C3< 43B2<
43C6<
+3V_GPU_SS
22A6< 22A8< 22B7<
+3V_INTREPID_USB 28C4< 52A3>
+3V_MAIN
39D4< 40D5< 41A5< 41A7< 42B5<
42B7< 42C8< 43C7< 52C4 59D7>
+5VSD_T
50D6<>
+5V_AUDIO
39C6<> 39D7< 41B8<>
+5V_HP
41A8< 41B7<> 41D5<
+5V_MAIN
51B4<> 51B4<> 52C4 59D7>
+5V_SLEEP
38C1< 46C7< 46D6<> 50D5< 51C5<>
51C8< 59D7>
+12VSD_FILT
29A5<> 52B3>
+12VSD_T
50D6<>
+12V_DROPPED
44D8<
+12V_MAIN
36D8< 39C8< 42B3< 44D8< 45B4<>
45D3<> 45D7< 48C4<> 48C8<> 48D6<>
49C4<> 49D3<> 49D7<> 50B4<> 50C4<>
50D2< 50D5<> 51A5< 51A7< 51B7< 51C3<
51D7<> 52C1> 52C1> 59D7>
+12V_SLEEP
29A3< 29A8< 29C5<> 50D5< 51A5<
51C2< 51D6<> 52C1> 52C1> 59D7>
+12V_SLEEPA
59D7>
+12V_TPA
42B2< 42B7< 42C4< 42C5< 42D5<
+INTREPID_CORE_MAIN 10D6< 11D3< 46B3< 47B2<> 59C7>
+MAXBUS_SLEEP

4D5< 6C5< 6D6< 7A3< 7A3< 7B3< 7C3<


7C3< 7C5< 7C7< 8A3<> 8D1< 8D4< 9B7<
9D8< 44B7< 44D1< 44D2< 45D2<> 46D4<
52C6> 59C7>
3.8VH_TRICKLE
44C1< 44D7<> 52B3>
3.8V_TRICKLE
36D8< 44C2< 44C6< 44D7<> 50D5<
52C1> 52C2>
3V_SI_AVCC
27D4<
3V_SI_PLLVCC
27D4<
3V_SI_VCC
27B2< 27D3<
3_5_HONKER
51C4<>
3_6V_SLEEP
37D1< 51C1<
5V_XRA
50B4<>
15_I282
15B2<
15_I286
15B3<
18P_GND
29B5<>
25V_BSTH
49C5<>
25V_BSTH_TERM
49C5<>
25V_COMP
49B6<
25V_COMP_DWN
49B6<
25V_DH
49B5<>
25V_DHT
49B5<>
25V_DL
49B5<>
25V_DLT
49B4<>
25V_GND
49B6<>
25V_OCSET
49C5<>
25V_OVP
49B6<>
25V_VCC
49C6<
25V_VPWR
49B5<> 49C4<>
25V_VPWRA
49B4<>
25V_VSENSE
49C4<>
25_CORE_1
49C3<
33PCI_SLOTD_SERR_L 32B6<>
33SLOTB_INT_L
28B7<> 28B7<> 28B7<> 31C2<> 59A5>
42_I291
42B6<
42_I295
42B5<
45_I408
45B6<
45_I525
45C4<
45_I526
45B3<
47_I66
47B4<
48_I10
48C3<
48_I99
48B4<
49_I70
49B4<
50_I408
50B3<
50_I410
50A3<
AGND
39B7<> 52C4
AGP_AD<0>
16C4<> 17D8<
AGP_AD<0..15>
54C7<
AGP_AD<1>
16C4<> 17D8<
AGP_AD<2>
16C4<> 17D8<
AGP_AD<3>
16C4<> 17D8<
AGP_AD<4>
16C4<> 17D8<
AGP_AD<5>
16C4<> 17D8<
AGP_AD<6>
16C4<> 17D8<
AGP_AD<7>
16C4<> 17D8<
AGP_AD<8>
16C4<> 17D8<
AGP_AD<9>
16C4<> 17D8<
AGP_AD<10>
16C4<> 17D8<
AGP_AD<11>
16C4<> 17D8<
AGP_AD<12>
16C4<> 17D8<
AGP_AD<13>
16C4<> 17D8<
AGP_AD<14>
16C4<> 17D8<
AGP_AD<15>
16C4<> 17C8<
AGP_AD<16>
16C4<> 17C8<
AGP_AD<16..31>
54C7<
AGP_AD<17>
16C4<> 17C8<
AGP_AD<18>
16C4<> 17C8<

AGP_AD<19>
16C4<> 17C8<
AGP_AD<20>
16C4<> 17C8<
AGP_AD<21>
16C4<> 17C8<
AGP_AD<22>
16C4<> 17C8<
AGP_AD<23>
16C4<> 17C8<
AGP_AD<24>
16B4<> 17C8<
AGP_AD<25>
16B4<> 17C8<
AGP_AD<26>
16B4<> 17C8<
AGP_AD<27>
16B4<> 17C8<
AGP_AD<28>
16B4<> 17C8<
AGP_AD<29>
16B4<> 17C8<
AGP_AD<30>
16B4<> 17C8<
AGP_AD<31>
16B4<> 17C8<
AGP_AD_STB<0>
16A4<> 16B3< 17B8< 54C7<
AGP_AD_STB<1>
16A4<> 16B3< 17B8< 54C7<
AGP_AD_STB_GPUUF<0> 17B6< 54B7<
AGP_AD_STB_GPUUF<1> 17B6< 54B7<
AGP_AD_STB_L<0> 16A4<> 16D1< 17B8< 54C7<
AGP_AD_STB_L<1> 16A4<> 16D1< 17B8< 54C7<
AGP_AD_STB_L_GPUUF<0> 17B6< 54B7<
AGP_AD_STB_L_GPUUF<1> 17B6< 54B7<
AGP_BUSY_L
16C6<> 16D1< 16D3< 17A8> 54B7<
AGP_CBE<0>
16B4<> 17C8<
AGP_CBE<0..1>
54C7<
AGP_CBE<1>
16B4<> 17C8<
AGP_CBE<2>
16B4<> 17C8<
AGP_CBE<2..3>
54C7<
AGP_CBE<3>
16B4<> 17C8<
AGP_DEVSEL_L
16B4<> 16C3< 17B8< 54C7<
AGP_FBI_EQUAL
16C7< 54A7<
AGP_FBO_EQUAL
16B7< 54A7<
AGP_FB_PLUS2
16B8< 54A7<
AGP_FRAME_L
16B4<> 16C3< 17B8< 54C7<
AGP_GNT_L
16C3< 16C4<> 17B6< 54B7<
AGP_INT_L
17B6<> 28B5<> 28B8<
AGP_IRDY_L
16B4<> 16C3< 17B8< 54C7<
AGP_PAR
16B4<> 17B8< 54B7<
AGP_PIPE_L
16A4<> 16B3< 17B8< 54B7<
AGP_PLLVDD
17C5<
AGP_PWR_ADJ
46A5<>
AGP_RBF_L
16A4<> 16B3< 17B8< 54B7<
AGP_REQ_L
16C3< 16C4<> 17B6<> 54B7<
AGP_RESET_L
17B8< 27C5< 44D3<
AGP_SBA<0>
16B4< 16C1< 17A8<
AGP_SBA<0..7>
54B7<
AGP_SBA<1>
16B4<> 16C1< 17A8<
AGP_SBA<2>
16B1< 16B4<> 17A8<
AGP_SBA<3>
16B4<> 16C1< 17A8<
AGP_SBA<4>
16B4<> 16C1< 17A8<
AGP_SBA<5>
16B4<> 16C1< 17A8<
AGP_SBA<6>
16A4<> 16B1< 17A8<
AGP_SBA<7>
16A4<> 16B1< 17A8<
AGP_SB_STB
16A4<> 16B3< 17B8< 54B7<
AGP_SB_STB_L
16A4<> 16D1< 17A8< 54B7<
AGP_ST<0>
16A4<> 16B1< 17B6<
AGP_ST<0..2>
54B7<
AGP_ST<1>
16A4<> 16B1< 17B6<
AGP_ST<2>
16A4<> 16B1< 17B6<
AGP_STOP_L
16B3< 16B4<> 17B8< 54C7<
AGP_TRDY_L
16B3< 16B4<> 17B8< 54C7<
AGP_WBF_L
16A6<> 16B1< 17B8< 54B7<
AINLM
39C4<
AINLP
39C4<
AINRM
39C4<
AINRP
39C4<
ALTCHGND
25B3<> 25C3< 33B4< 33C2< 33C4<
33C4< 33D4< 36A7<> 36B2< 36B6<>
36B6< 36C1< 36C1<> 36C1<> 52C4
ANALOGGND
35B1< 35C1<> 40B5<> 40B6< 40C6<
40C6< 41A2<> 41A4< 41B1<> 41B3<
41C3< 41D3< 42A5<> 42A6<> 43A5< 52C4
ANALOG_BLU
ANALOG_GRN
ANALOG_HSYNC*
ANALOG_RED
ANALOG_VSYNC*
ANEN
AOUTL
AOUTR
ASH
AUDIO_TO_SND
AUD_GND

22C7<> 25C6< 57D5>


22C7<> 25C6< 57D5>
22D7< 25D6<> 26B5< 57D5> 59B7>
22C7<> 25B6< 57D5>
22D7< 25C6<> 26B5< 57D5> 59B7>
35C4<
39C2> 41D7< 43D3<
39C2> 41C7< 43D3<
43A6<
28B1< 39C1<
39B7<> 42B2< 42C4< 42D3< 42D4<
42D6< 42D7< 43C2< 43D2< 43D4<
AUD_R_FB
39D6<
BRE
45C5<>
BRE_1
45B5<>
BT1
44D6<> 51A6<
BT1_LED
51A6<
BT_USB_DM
28B2< 29D3<> 58A5> 59B5>
BT_USB_DP
28B2< 29D3<> 58B5> 59B5>
C412P1
41B3<
C756_2
40D3<>
C4237P2
40C4<
C4240P2
40C4<
C4242P2
40B4<
C4243P2
40B4<
CAP_PLL
39B4<
CD_CS1FX_L
38C6<> 58C5>
CD_CS3FX_L
38C6<> 58C5>
CD_DMACK_L
37D4< 38C6<> 58D5>
CD_DMARQ
38C6<> 58D5>
CD_DSTB_RDY
37C4< 38C6<> 58D5>
CD_EIDE_ADDR<0> 38C6<>
CD_EIDE_ADDR<0..2> 58C5>
CD_EIDE_ADDR<1> 38C6<>
CD_EIDE_ADDR<2> 38C6<>
CD_HSTB_RDY
37C4< 38C6<> 58D5>
CD_RESET_L
37D4< 38C6<> 58D5>
CD_STOP
37D4< 38C6<> 58D5>

5
CHGND
24B3< 29A3< 43A7< 43B7< 52C4
CHOC_BROWNIE
51B2<
CLK18M_INT_EXT
28B6<>
CLK18M_INT_XIN
28A5<
CLK18M_INT_XO
28A6<
CLK18M_INT_XOUT 28A5<>
CLK25M_ENET_XIN 35B6< 57B5>
CLK25M_ENET_XOUT 35B6<> 57B5>
CLK27M_MEM_SS
22A6<>
CLK33M_PCI_SLOTB 30D7< 31C2<> 54D7< 59A5>
CLK33M_PCI_SLOTB_UF 30D5<> 54D7<
CLK33M_PCI_SLOTC_UF 30D5<> 54D7<
CLK33M_PCI_SLOTD 30D7< 32A6< 54A7<
CLK33M_PCI_SLOTD_UF 30D5<> 54D7<
CLK66M_GPU_AGP
16D8< 17C6< 54A7<
CLK66M_GPU_UF
16C6<> 54A7<
CLKENET_LINK_GBE_REF 34C6<
CLKENET_LINK_RX 34C7< 35C8< 57C5>
CLKENET_LINK_TX 34D7< 35C8< 57C5>
CLKENET_PHY_RX
35C6<> 57C5>
CLKENET_PHY_TX
35C6<> 57C5>
CLKFW_LINK_LCLK 34C5<>
CLK_18M_INT_XOUT 58B5> 58B5> 58B5>
COMM_DTR_L
28C3> 29C7<> 59C5>
COMM_GPIO_L
28C3<> 28D3< 29C5<> 59C5>
COMM_RESET_L
28C5<> 29D5<> 59A7>
COMM_RING_DET_L 28B5<> 28B8< 29C5<> 44C5<> 59D5>
COMM_RTS_L
28C3> 29D5<> 59C5>
COMM_RXD
28C3<> 29C5<> 59C5>
COMM_SHUTDOWN
28C5<> 28D1< 29D7<> 59D5>
COMM_TRXC
28C3<> 28D3< 29C7<> 59C5>
COMM_TXD_L
28C3<> 29C7<> 59C5>
CORE_MOSFET
45C4<> 45C6<>
CORE_MOSFET_1
45B5<> 45C7<>
CPU_AACK_L
4A7< 7B7< 8B5<> 9B3<> 56C3>
CPU_ADDR<0>
4C7<> 8B4<> 9D3<>
CPU_ADDR<0..31> 56D3>
CPU_ADDR<1>
4C7<> 8B5<> 9D3<>
CPU_ADDR<2>
4C7<> 8B4<> 9D3<>
CPU_ADDR<3>
4C7<> 8B8<> 9D3<>
CPU_ADDR<4>
4C7<> 8B5<> 9D3<>
CPU_ADDR<5>
4C7<> 8B7<> 9D3<>
CPU_ADDR<6>
4C7<> 8C4<> 9D3<>
CPU_ADDR<7>
4C7<> 8B7<> 9D3<>
CPU_ADDR<8>
4C7<> 8C5<> 9D3<>
CPU_ADDR<9>
4C7<> 8B8<> 9C3<>
CPU_ADDR<10>
4C7<> 8B8<> 9C3<>
CPU_ADDR<11>
4C7<> 8C4<> 9C3<>
CPU_ADDR<12>
4C7<> 8B7<> 9C3<>
CPU_ADDR<13>
4C7<> 8B8<> 9C3<>
CPU_ADDR<14>
4C7<> 8B7<> 9C3<>
CPU_ADDR<15>
4C7<> 8B7<> 9C3<>
CPU_ADDR<16>
4C7<> 8B8<> 9C3<>
CPU_ADDR<17>
4C7<> 8B8<> 9C3<>
CPU_ADDR<18>
4C7<> 8C8<> 9C3<>
CPU_ADDR<19>
4C7<> 8B7<> 9C3<>
CPU_ADDR<20>
4C7<> 8B8<> 9C3<>
CPU_ADDR<21>
4C7<> 8C7<> 9C3<>
CPU_ADDR<22>
4C7<> 8C7<> 9C3<>
CPU_ADDR<23>
4C7<> 8C8<> 9C3<>
CPU_ADDR<24>
4B7<> 8B7<> 9C3<>
CPU_ADDR<25>
4B7<> 8B8<> 9C3<>
CPU_ADDR<26>
4B7<> 8C8<> 9C3<>
CPU_ADDR<27>
4B7<> 8C8<> 9C3<>
CPU_ADDR<28>
4B7<> 8C7<> 9C3<>
CPU_ADDR<29>
4B7<> 8C8<> 9C3<>
CPU_ADDR<30>
4B7<> 8C7<> 9C3<>
CPU_ADDR<31>
4B7<> 8C7<> 9C3<>
CPU_ARTRY_L
4A7<> 7C7< 8B8<> 9B3<> 56C3>
CPU_AVDD
4D3< 52C6>
CPU_BG_L
4D7< 7B7< 8B4<> 9D3<> 56D3>
CPU_BR_L
4D7> 7C7< 8B4<> 9D3< 56D3>
CPU_BUS_VSEL
4D3< 7C4<
CPU_CHKSTP_IN_L 4B3< 7B5< 59C7>
CPU_CHKSTP_OUT_L 4B3> 7B5< 8A3<> 8D5<> 59C7>
CPU_CI_L
4A7> 7A7< 8C5<> 9C3<> 56C3>
CPU_CLK_EN
9A3< 44C4<>
CPU_DATA<0>
5D4<> 8C4<> 9D1<>
CPU_DATA<0..63> 56D3>
CPU_DATA<1>
5D4<> 8C7<> 9D1<>
CPU_DATA<2>
5D4<> 8C8<> 9D1<>
CPU_DATA<3>
5D4<> 8C5<> 9D1<>
CPU_DATA<4>
5D4<> 8C7<> 9D1<>
CPU_DATA<5>
5D4<> 8C8<> 9D1<>
CPU_DATA<6>
5D4<> 8C4<> 9D1<>
CPU_DATA<7>
5D4<> 8C8<> 9D1<>
CPU_DATA<8>
5D4<> 8C5<> 9D1<>
CPU_DATA<9>
5D4<> 8C4<> 9D1<>
CPU_DATA<10>
5D4<> 8C7<> 9D1<>
CPU_DATA<11>
5C4<> 8C5<> 9D1<>
CPU_DATA<12>
5C4<> 8C5<> 9D1<>
CPU_DATA<13>
5C4<> 8C7<> 9D1<>
CPU_DATA<14>
5C4<> 8C8<> 9D1<>
CPU_DATA<15>
5C4<> 8C5<> 9D1<>
CPU_DATA<16>
5C4<> 8C4<> 9C1<>
CPU_DATA<17>
5C4<> 8C7<> 9C1<>
CPU_DATA<18>
5C4<> 8C4<> 9C1<>
CPU_DATA<19>
5C4<> 8C4<> 9C1<>
CPU_DATA<20>
5C4<> 8C4<> 9C1<>
CPU_DATA<21>
5C4<> 8C8<> 9C1<>
CPU_DATA<22>
5C4<> 8C7<> 9C1<>
CPU_DATA<23>
5C4<> 8C8<> 9C1<>
CPU_DATA<24>
5C4<> 8D4<> 9C1<>
CPU_DATA<25>
5C4<> 8D7<> 9C1<>
CPU_DATA<26>
5C4<> 8C5<> 9C1<>
CPU_DATA<27>
5C4<> 8C7<> 9C1<>
CPU_DATA<28>
5C4<> 8D8<> 9C1<>
CPU_DATA<29>
5C4<> 8C8<> 9C1<>
CPU_DATA<30>
5C4<> 8C5<> 9C1<>
CPU_DATA<31>
5C4<> 8D7<> 9C1<>

CPU_DATA<32>
CPU_DATA<33>
CPU_DATA<34>
CPU_DATA<35>
CPU_DATA<36>
CPU_DATA<37>
CPU_DATA<38>
CPU_DATA<39>
CPU_DATA<40>
CPU_DATA<41>
CPU_DATA<42>
CPU_DATA<43>
CPU_DATA<44>
CPU_DATA<45>
CPU_DATA<46>
CPU_DATA<47>
CPU_DATA<48>
CPU_DATA<49>
CPU_DATA<50>
CPU_DATA<51>
CPU_DATA<52>
CPU_DATA<53>
CPU_DATA<54>
CPU_DATA<55>
CPU_DATA<56>
CPU_DATA<57>
CPU_DATA<58>
CPU_DATA<59>
CPU_DATA<60>
CPU_DATA<61>
CPU_DATA<62>
CPU_DATA<63>
CPU_DBG_L
CPU_DRDY_L
CPU_DRDY_L_UF
CPU_DTI<0>
CPU_DTI<0..2>
CPU_DTI<1>
CPU_DTI<2>
CPU_EDTI
CPU_EMODE0_L
CPU_EMODE1_L
CPU_FBI_PLUS1
CPU_FBO_PLUS1
CPU_FB_MINUS3
CPU_FB_PLUS2
CPU_FB_PLUS3
CPU_GBL_L
CPU_HDRST_L
CPU_HIT_L
CPU_HRESET_L

5C4<> 8D7<> 9B7< 9C1<>


5C4<> 8D8<> 9B7< 9C1<>
5C4<> 8D8<> 9B7< 9C1<>
5C4<> 8D7<> 9B7< 9C1<>
5C4<> 8D4<> 9A7< 9C1<>
5B4<> 8D5<> 9C1<>
5B4<> 8D5<> 9C1<>
5B4<> 8D5<> 9C1<>
5B4<> 6C4< 8D7<> 9C1<>
5B4<> 6C4< 8C4<> 9C1<>
5B4<> 6C4< 8C5<> 9B1<>
5B4<> 6C4< 8C4< 9B1<>
5B4<> 6C4< 8C8<> 9B1<>
5B4<> 6C4< 8C7<> 9B1<>
5B4<> 6C4< 8C4<> 9B1<>
5B4<> 6C4< 8C7< 9B1<>
5B4<> 8C5<> 9B1<> 9D8<
5B4<> 8C4<> 9B1<> 9D8<
5B4<> 8C8<> 9B1<> 9D8<
5B4<> 8C8<> 9B1<> 9D8<
5B4<> 8C5<> 9B1<> 9C8<
5B4<> 8C7<> 9B1<> 9C8<
5B4<> 8D7<> 9B1<> 9C8<
5B4<> 8C5<> 9B1<> 9C8<
5B4<> 8D8<> 9B1<>
5B4<> 8D5<> 9B1<> 9D5<
5B4<> 8D4<> 9B1<> 9D5<
5B4<> 8D8<> 9B1<> 9D5<
5B4<> 8D8<> 9B1<> 9D5<
5B4<> 8D4<> 9B1<> 9C5<
5B4<> 8D4<> 9B1<> 9C5<
5A4<> 8D5<> 9B1<> 9C5<
4C3< 7B7< 8B8<> 9B1<> 56C3>
4C2< 7B7< 8B5<> 9B1< 56C3>
4C3<> 56C3>
4C3< 8B7<> 9A1<>
56C3>
4C3< 8B4<> 9A1<>
4C3< 8B4<> 9A1<>
4C3< 7C5<
4B3< 7A4<
4B3< 7A4<
9A5< 56C3>
9A5< 56C3>
9A4< 56C3>
9A5< 56C3>
9A4< 56B3>
4B8<> 8B5<> 56C3>
44C4<>
4A7> 7C7< 8B8<> 9B3< 56C3>
4B3< 7A3< 7A5< 7B3< 7B3< 8A3<>
44C2< 44D2< 59C7>
CPU_INT_GBL_L
4B8< 7B7< 9C3<> 56C3>
CPU_L1TSTCLK
4C3< 7B4<
CPU_L2TSTCLK
4C3< 7C4<
CPU_LSSD_MODE
4C3< 7B5<
CPU_MCP_L
4B3< 7B5<
CPU_PLL_CFG<0>
4D3< 6C6< 8A8<>
CPU_PLL_CFG<1>
4D3< 6C6< 8A8<>
CPU_PLL_CFG<2>
4D3< 6C6< 8A8<>
CPU_PLL_CFG<3>
4C3< 6C6< 8A8<>
CPU_PLL_CFGEXT
4C3< 6C6< 8A8<>
CPU_PLL_STOP
6B8< 44B8<
CPU_PMONIN_L
4B3< 7C5<
CPU_PULLDOWN
4A3< 4D7<> 7C5<
CPU_PULLUP
4A3< 7A5<
CPU_QACK_L
4C3< 8B4<> 9B3<> 56C3>
CPU_QREQ_L
4C3> 7D5< 8B7<> 9B3< 56C3>
CPU_SHD0_L
4A7<> 7B5<
CPU_SHD1_L
4A7<> 7B5<
CPU_SLEEPIN
51B7<
CPU_SMI_L
4B3< 7A5< 44C4<>
CPU_SRESET_L
4B3< 7A5< 8A3<> 59C5>
CPU_STATE_LED*
44C4<> 51A8<
CPU_TA_L
4C3< 7C7< 8C4<> 9A1<> 56C3>
CPU_TBEN
4C3< 7C5< 9A3<>
CPU_TBST_L
4B7> 7B7< 8B4<> 9B3<> 56D3>
CPU_TEA_L
4C3< 7B7< 8B5<> 9A1<> 56C3>
CPU_TSIZ<0>
4B7> 8B5<> 9B3<>
CPU_TSIZ<0..2>
56D3>
CPU_TSIZ<1>
4B7> 8B5<> 9B3<>
CPU_TSIZ<2>
4B7> 8B7< 9B3<>
CPU_TS_L
4D7<> 7C7< 8B7<> 9D3<> 56D3>
CPU_TT<0>
4B7<> 7A7< 8B4<> 9B3<>
CPU_TT<0..4>
56D3>
CPU_TT<1>
4B7<> 7A7< 8B5<> 9B3<>
CPU_TT<2>
4B7<> 7A7< 8B4<> 9B3<>
CPU_TT<3>
4B7<> 7A7< 8B5<> 9B3<>
CPU_TT<4>
4B7<> 7A7< 8B4<> 9B3<>
CPU_VCORE_SLEEP 4D3< 4D7< 8B7< 8C1< 45D2<> 52C6>
59B5> 59D7>
CPU_VCORE_SLEEPA 45C3<>
CPU_VCORE_SLEEPB 45A4<>
CPU_VCORE_SLEEPC 45A1<>
CPU_WT_L
4B7> 7A7< 8B5<> 9B3<> 56C3>
CSLOT_IOWAIT_L
37B7< 52A8>
CVBS_CNT
22B7< 23D7<>
CVBS_D
22B7<
CY69P2
39B5<
CY811_S0
22A7<
CY811_S1
22A7<
DAC2RSET
22C5<> 57D5>
DAC2VDD
22C5< 52B6>
DAC2VREF
22C5<> 57D5>
DACRSET
22C4<
DACVDD
22C4< 52B6>
DACVREF
22C4<
DDC_VCC_3
24B3<> 52B6> 59B7>
DDC_VCC_5
25C4< 52A6> 59B7>
DDR_VREF
12A7< 14D2<> 14D8<> 15D8< 52A6>

DS1P1
35B2<
DS2P1
35B1<
DS2_1
38B2<
DS2_2
38B2<>
DS3P1
35B2<
DS6_1
38B6<
DS6_2
38B6<>
DUKE_BD
45B5<
DVOCLKIN
22C5<
DVOCLKOUT
22C5> 27B5<
DVOCLKOUT*
22C5<> 27B6<
DVOD0
22C5<> 27A8< 27C5< 57C2>
DVOD1
22C5<> 27A8< 27C5< 57C2>
DVOD2
22C5<> 26D1< 27C5< 57C2>
DVOD3
22B5<> 26D1< 27C5< 57C2>
DVOD4
22B5<> 27A8< 27C5< 57C2>
DVOD5
22B5<> 27A8< 27C5< 57C2>
DVOD6
22B5<> 27A8< 27C5< 57C2>
DVOD7
22B5<> 27A8< 27C5< 57C2>
DVOD8
22B5<> 26B1< 27C5< 57C2>
DVOD9
22B5<> 27A8< 27C5< 57C2>
DVOD10
22B5<> 27A8< 27B5< 57C2>
DVOD11
22B5<> 27A8< 27B5< 57C2>
DVODE
22C5<> 27B5<
DVOHSYNC
22C5> 26D7< 27B5<
DVOVREF
22C5<>
DVOVSYNC
22C5> 27B5<
DVO_PD
22B5<
DVO_PU
22B5<
EIDE_ADDR<0>
37B7> 38B8<
EIDE_ADDR<0..2> 58C5>
EIDE_ADDR<1>
37B7> 38B8<
EIDE_ADDR<2>
37B7> 38A8<
EIDE_CS1FX_L
37A7> 38B8< 58C5>
EIDE_CS3FX_L
37A7> 38B8< 58C5>
EIDE_CSELP_L
38C6<> 52A8>
EIDE_DATA<0>
37B7<> 37C5<
EIDE_DATA<0..15> 58D5>
EIDE_DATA<1>
37B7<> 37C5<
EIDE_DATA<2>
37B7<> 37C5<
EIDE_DATA<3>
37B7<> 37C5<
EIDE_DATA<4>
37B5< 37B7<>
EIDE_DATA<5>
37B5< 37B7<>
EIDE_DATA<6>
37B5< 37B7<>
EIDE_DATA<7>
37B5< 37B7<>
EIDE_DATA<8>
37B5< 37B7<>
EIDE_DATA<9>
37B5< 37B7<>
EIDE_DATA<10>
37B5< 37B7<>
EIDE_DATA<11>
37B5< 37B7<>
EIDE_DATA<12>
37B5< 37B7<>
EIDE_DATA<13>
37A5< 37B7<>
EIDE_DATA<14>
37A5< 37B7<>
EIDE_DATA<15>
37A5< 37B7<>
EIDE_DMACK_L
37A7<> 37D5< 58D5>
EIDE_DMARQ
37A7< 38C8< 58D5>
EIDE_DSTB_RDY
37A7< 37C5< 58D5>
EIDE_HSTB_RDY
37A7> 37C5< 58D5>
EIDE_INTRQ
37A7< 38C8< 58C5>
EIDE_IOCS16_L
38C6<> 52A8>
EIDE_PDIAG
38C6<>
EIDE_RST_L
37A7> 37D5< 58D5>
EIDE_STOP
37A7> 37D5< 58D5>
ENET_AVDD
35D2<> 35D4<> 52C6>
ENET_COL
34B7< 35B8< 57B5>
ENET_CRS
34C7< 35B8< 57B5>
ENET_DVDD
35D6<>
ENET_ENERGY_DET 28B5<> 28C1< 35B4>
ENET_LINK_RXD<0> 34C7< 35C8<
ENET_LINK_RXD<0..3> 57B5>
ENET_LINK_RXD<1> 34C7< 35C8<
ENET_LINK_RXD<2> 34C7< 35C8<
ENET_LINK_RXD<3> 34C7< 35B8<
ENET_LINK_RXD<4> 34C6<
ENET_LINK_RXD<5> 34C6<
ENET_LINK_RXD<6> 34C6<
ENET_LINK_RXD<7> 34C6<
ENET_LINK_TXD<0> 34C6<>
ENET_LINK_TXD<0..3> 57C5>
ENET_LINK_TXD<1> 34C6<>
ENET_LINK_TXD<2> 34C6<>
ENET_LINK_TXD<3> 34C6<>
ENET_LINK_TX_EN 34D6<> 57C5>
ENET_LINK_TX_ER 34D6<> 57C5>
ENET_MDC
34B7> 35B6<
ENET_MDIO
34B7<> 35A8<>
ENET_PHY_COL
35B6<> 57B5>
ENET_PHY_CRS
35B6<> 57B5>
ENET_PHY_RXD<0> 35C6<>
ENET_PHY_RXD<0..3> 57B5>
ENET_PHY_RXD<1> 35C6<>
ENET_PHY_RXD<2> 35C6<>
ENET_PHY_RXD<3> 35B6<>
ENET_PHY_RX_DV
35B6<> 57B5>
ENET_PHY_RX_ER
35B6<> 57B5>
ENET_PHY_TXD<0> 34C7< 35C6<>
ENET_PHY_TXD<0..3> 57C5>
ENET_PHY_TXD<1> 34C7< 35C6<>
ENET_PHY_TXD<2> 34C7< 35C6<>
ENET_PHY_TXD<3> 34C7< 35C6<>
ENET_PHY_TX_EN
34D7< 35C6< 57C5>
ENET_PHY_TX_ER
34D7< 35C6< 57C5>
ENET_RDAC_PD
35B5<>
ENET_RDN
35C3<> 57B5>
ENET_RDP
35C3<> 57B5>
ENET_RX_DV
34C7< 35B8< 57B5>
ENET_RX_ER
34C7< 35B8< 57B5>
ENET_TDN
35C3<> 57B5>
ENET_TDP
35C3<> 57B5>
ETHPHYRESET_L
35B6<
EXTINT14
28A8< 28B5<>

1
FAN_12V_FILT
FBA<0>
FBA<0..12>
FBA<1>
FBA<2>
FBA<3>
FBA<4>
FBA<5>
FBA<6>
FBA<7>
FBA<8>
FBA<9>
FBA<10>
FBA<11>
FBA<12>
FBABA<0>
FBABA<0..1>
FBABA<1>
FBACAS_L
FBACKE
FBACLK0
FBACLK0_L
FBACLK1
FBACLK1_L
FBACS0_L
FBARAS_L
FBAWE_L
FBBA<0>
FBBA<0..12>
FBBA<1>
FBBA<2>
FBBA<3>
FBBA<4>
FBBA<5>
FBBA<6>
FBBA<7>
FBBA<8>
FBBA<9>
FBBA<10>
FBBA<11>
FBBA<12>
FBBBA<0>
FBBBA<0..1>
FBBBA<1>
FBBCAS_L
FBBCKE
FBBCLK0
FBBCLK0_L
FBBCLK1
FBBCLK1_L
FBBCS0_L
FBBRAS_L
FBBWE_L
FBCAL_CLK_GND
FBCAL_PD_VDDQ
FBCAL_PU_GND
FBCAL_TERM_GND
FBD<0>
FBD<0..63>
FBD<1>
FBD<2>
FBD<3>
FBD<4>
FBD<5>
FBD<6>
FBD<7>
FBD<8>
FBD<9>
FBD<10>
FBD<11>
FBD<12>
FBD<13>
FBD<14>
FBD<15>
FBD<16>
FBD<17>
FBD<18>
FBD<19>
FBD<20>
FBD<21>
FBD<22>
FBD<23>
FBD<24>
FBD<25>
FBD<26>
FBD<27>
FBD<28>
FBD<29>
FBD<30>
FBD<31>
FBD<32>
FBD<33>
FBD<34>
FBD<35>
FBD<36>
FBD<37>
FBD<38>
FBD<39>
FBD<40>
FBD<41>
FBD<42>
FBD<43>
FBD<44>
FBD<45>
FBD<46>
FBD<47>
FBD<48>
FBD<49>
FBD<50>
FBD<51>

29A5<> 52B3> 59C7>


18D8> 18F3<
55D3>
18D8> 18F3<
18D8> 18F3<
18D8> 18F3<
18D8> 18F3<
18D8> 18F3<
18D8> 18E3<
18D8> 18E3<
18D8> 18E3<
18D8> 18E3<
18D8> 18E3<
18C8> 18E3<
18C8> 18E3<
18C8<> 18E3<
55D3>
18C8<> 18E3<
18C8> 18G3< 55D3>
18D3< 18D7<> 55D3>
18D7> 19C3< 55C3>
18D7> 19C3< 55C3>
18D7> 19D3< 55C3>
18D7> 19D3< 55C3>
18C8> 18F3< 55D3>
18C8> 18G3< 55D3>
18C8> 18F3< 55D3>
18C3< 18D5<>
55C3>
18B3< 18D5<>
18B3< 18D5<>
18B3< 18D5<>
18B3< 18D5<>
18B3< 18D5<>
18B3< 18D5<>
18B3< 18D5<>
18B3< 18D5<>
18B3< 18D5<>
18B3< 18D5<>
18B3< 18C5<>
18A3< 18C5<>
18A3< 18C5<>
55C3>
18A3< 18C5<>
18C3< 18D4<> 55C3>
18A3< 18C4<> 55B3>
18C5<> 19B3< 55B3>
18C5<> 19B3< 55B3>
18C5<> 19C3< 55B3>
18C5<> 19B3< 55B3>
18C3< 18C4<> 55C3>
18C3< 18D4<> 55C3>
18C3< 18D4<> 55C3>
18A5< 18D7<
18D7<
18A5< 18D7<
18A5< 18D7<
18G8<> 19D8<
55D3>
18G8<> 19D8<
18G8<> 19D8<
18G8<> 19D8<
18G8<> 19D8<
18G8<> 19D8<
18G8<> 19D8<
18G8<> 19D8<
18G8<> 19D8<
18G8<> 19D8<
18G8<> 19D8<
18G8<> 19D8<
18G8<> 19D8<
18G8<> 19D8<
18G8<> 19D8<
18G8<> 19D8<
18G8<> 19D8<
18G8<> 19D8<
18G8<> 19D8<
18G8<> 19C8<
18G8<> 19C8<
18G8<> 19C8<
18G8<> 19C8<
18G8<> 19C8<
18G8<> 19C8<
18F8<> 19C8<
18F8<> 19C8<
18F8<> 19C8<
18F8<> 19C8<
18F8<> 19C8<
18F8<> 19C8<
18F8<> 19C8<
18F8<> 19D5<
18F8<> 19D5<
18F8<> 19D5<
18F8<> 19D5<
18F8<> 19D5<
18F8<> 19D5<
18F8<> 19D5<
18F8<> 19D5<
18F8<> 19D5<
18F8<> 19D5<
18F8<> 19D5<
18F8<> 19D5<
18F8<> 19D5<
18E8<> 19D5<
18E8<> 19D5<
18E8<> 19D5<
18E8<> 19D5<
18E8<> 19D5<
18E8<> 19D5<
18E8<> 19C5<

60

FBD<52>
FBD<53>
FBD<54>
FBD<55>
FBD<56>
FBD<57>
FBD<58>
FBD<59>
FBD<60>
FBD<61>
FBD<62>
FBD<63>
FBD<64>
FBD<64..127>
FBD<65>
FBD<66>
FBD<67>
FBD<68>
FBD<69>
FBD<70>
FBD<71>
FBD<72>
FBD<73>
FBD<74>
FBD<75>
FBD<76>
FBD<77>
FBD<78>
FBD<79>
FBD<80>
FBD<81>
FBD<82>
FBD<83>
FBD<84>
FBD<85>
FBD<86>
FBD<87>
FBD<88>
FBD<89>
FBD<90>
FBD<91>
FBD<92>
FBD<93>
FBD<94>
FBD<95>
FBD<96>
FBD<97>
FBD<98>
FBD<99>
FBD<100>
FBD<101>
FBD<102>
FBD<103>
FBD<104>
FBD<105>
FBD<106>
FBD<107>
FBD<108>
FBD<109>
FBD<110>
FBD<111>
FBD<112>
FBD<113>
FBD<114>
FBD<115>
FBD<116>
FBD<117>
FBD<118>
FBD<119>
FBD<120>
FBD<121>
FBD<122>
FBD<123>
FBD<124>
FBD<125>
FBD<126>
FBD<127>
FBDQM<0>
FBDQM<0..7>
FBDQM<1>
FBDQM<2>
FBDQM<3>
FBDQM<4>
FBDQM<5>
FBDQM<6>
FBDQM<7>
FBDQM<8>
FBDQM<8..15>
FBDQM<9>
FBDQM<10>
FBDQM<11>
FBDQM<12>
FBDQM<13>
FBDQM<14>
FBDQM<15>
FBDQS<0>
FBDQS<0..7>
FBDQS<1>
FBDQS<2>
FBDQS<3>
FBDQS<4>
FBDQS<5>
FBDQS<6>
FBDQS<7>
FBDQS<8>
FBDQS<8..15>
FBDQS<9>
FBDQS<10>
FBDQS<11>
FBDQS<12>

7
18E8<> 19C5<
18E8<> 19C5<
18E8<> 19C5<
18E8<> 19C5<
18E8<> 19C5<
18E8<> 19C5<
18E8<> 19C5<
18E8<> 19C5<
18E8<> 19C5<
18E8<> 19C5<
18E8<> 19C5<
18E8<> 19C5<
18G5<> 19C8<
55C3>
18G5<> 19C8<
18G5<> 19C8<
18G5<> 19C8<
18G5<> 19C8<
18G5<> 19C8<
18G5<> 19C8<
18G5<> 19C8<
18G5<> 19C8<
18G5<> 19C8<
18G5<> 19B8<
18G5<> 19B8<
18G5<> 19B8<
18G5<> 19B8<
18G5<> 19B8<
18G5<> 19B8<
18G5<> 19B8<
18G5<> 19B8<
18G5<> 19B8<
18G5<> 19B8<
18G5<> 19B8<
18G5<> 19B8<
18G5<> 19B8<
18G5<> 19B8<
18G5<> 19B8<
18F5<> 19B8<
18F5<> 19B8<
18F5<> 19B8<
18F5<> 19B8<
18F5<> 19B8<
18F5<> 19B8<
18F5<> 19B8<
18F5<> 19C5<
18F5<> 19C5<
18F5<> 19C5<
18F5<> 19C5<
18F5<> 19C5<
18F5<> 19C5<
18F5<> 19C5<
18F5<> 19C5<
18F5<> 19C5<
18F5<> 19C5<
18F5<> 19B5<
18F5<> 19B5<
18F5<> 19B5<
18E5<> 19B5<
18E5<> 19B5<
18E5<> 19B5<
18E5<> 19B5<
18E5<> 19B5<
18E5<> 19B5<
18E5<> 19B5<
18E5<> 19B5<
18E5<> 19B5<
18E5<> 19B5<
18E5<> 19B5<
18E5<> 19B5<
18E5<> 19B5<
18E5<> 19B5<
18E5<> 19B5<
18E5<> 19B5<
18E5<> 19B5<
18E5<> 19B5<
18E5<> 19B5<
18D8> 18G3<
55D3>
18D8> 18G3<
18D8> 18G3<
18D8> 18G3<
18D8> 18G3<
18D8> 18G3<
18D8> 18G3<
18D8> 18G3<
18D3< 18D5>
55C3>
18D3< 18D5>
18D3< 18D5>
18D3< 18D5>
18D3< 18D5>
18D3< 18D5>
18C3< 18D5>
18C3< 18D5>
18C7<> 19A8<
55C3>
18C7<> 19A8<
18C7<> 19A8<
18C7<> 19A8<
18C7<> 19A8<
18C7<> 19A8<
18C7<> 19A8<
18C7<> 19A8<
18D4<> 19A5<
55B3>
18D4<> 19A5<
18D4<> 19A5<
18D4<> 19A5<
18D4<> 19A5<

FBDQS<13>
18D4<> 19A5<
FBDQS<14>
18D4<> 19A5<
FBDQS<15>
18D4<> 19A5<
FBDQSTERM<0>
19A7<
FBDQSTERM<0..7> 55C3>
FBDQSTERM<1>
19A7<
FBDQSTERM<2>
19A7<
FBDQSTERM<3>
19A7<
FBDQSTERM<4>
19A7<
FBDQSTERM<5>
19A7<
FBDQSTERM<6>
19A7<
FBDQSTERM<7>
19A7<
FBDQSTERM<8>
19A4<
FBDQSTERM<8..15> 55B3>
FBDQSTERM<9>
19A4<
FBDQSTERM<10>
19A4<
FBDQSTERM<11>
19A4<
FBDQSTERM<12>
19A4<
FBDQSTERM<13>
19A4<
FBDQSTERM<14>
19A4<
FBDQSTERM<15>
19A4<
FB_DLLVDD
18C6< 18D7<
FDX
35A5< 35C4<
FILT_ANALOG_BLU 25C5< 57D5> 59B7>
FILT_ANALOG_GRN 25C5< 57D5> 59B7>
FILT_ANALOG_RED 25C5< 57D5> 59B7>
FLOW_SS
45C6< 45C7< 45D8<
FLO_KNOWS_BEST
45C7<> 45C8<> 59D5>
FPD_PWR_ON
23D7<> 51B3<
FPD_PWR_ON_T
51B3<
FWPHYRST
28C5<> 36C8<
FW_BIAS1
36C5<> 57A5>
FW_BIAS2
36C5<> 57A5>
FW_CNTL0
34C3< 36C8< 57A5>
FW_CNTL1
34C3< 36C8< 57A5>
FW_CPS
36C6<
FW_C_LKON
28B6< 34C5<> 36B5<>
FW_D<0>
34C3< 36C8<
FW_D<0..7>
57A5>
FW_D<1>
34C3< 36C8<
FW_D<2>
34C3< 36B8<
FW_D<3>
34C3< 36B8<
FW_D<4>
34C3< 36B8<
FW_D<5>
34C3< 36B8<
FW_D<6>
34C3< 36B8<
FW_D<7>
34C3< 36B8<
FW_DIODE_BYPASS_V 36B6<> 36B7<> 52B6>
FW_DIO_V
36B6< 52B6>
FW_LINK_CNTL<0> 34C4<>
FW_LINK_CNTL<0..1> 57A5>
FW_LINK_CNTL<1> 34C4<>
FW_LINK_DATA<0> 34C4<>
FW_LINK_DATA<0..7> 57A5>
FW_LINK_DATA<1> 34C4<>
FW_LINK_DATA<2> 34C4<>
FW_LINK_DATA<3> 34C4<>
FW_LINK_DATA<4> 34C4<>
FW_LINK_DATA<5> 34C4<>
FW_LINK_DATA<6> 34C4<>
FW_LINK_DATA<7> 34C4<>
FW_LINK_LREQ
34C4<> 57A5>
FW_LPS
34C4<> 36C8<
FW_LREQ
34C3< 36C8< 57A5>
FW_PHY_3_3
36B5< 36B7< 36D7< 36D7< 52B6>
FW_PHY_CNTL0
36C7<> 57A5>
FW_PHY_CNTL1
36C7<> 57A5>
FW_PHY_D<0>
36C7<>
FW_PHY_D<0..7>
57A5>
FW_PHY_D<1>
36C7<>
FW_PHY_D<2>
36B7<>
FW_PHY_D<3>
36B7<>
FW_PHY_D<4>
36B7<>
FW_PHY_D<5>
36B7<>
FW_PHY_D<6>
36B7<>
FW_PHY_D<7>
36B7<>
FW_PHY_ISO*
36C6<
FW_PHY_RST
36C8<
FW_PHY_RST*
36C6<
FW_PHY_SCLK
36C7<> 57A5>
FW_PINT
34B5<> 34C1<
FW_PWR
29B3< 36D6< 50C6<> 51D4<> 52B6>
FW_PWR_SW
36D6< 51D2<> 52B6>
FW_R0
36C5<>
FW_R1
36C5<>
FW_SCLK
34C5<> 36C8< 57A5>
FW_TPA1N
36C5<> 57A5>
FW_TPA1P
36C5<> 57A5>
FW_TPA2N
36C5<> 57A5>
FW_TPA2P
36C5<> 57A5>
FW_TPB1
36B3<
FW_TPB1N
36C5<> 57A5>
FW_TPB1P
36C5<> 57A5>
FW_TPB2
36B4<
FW_TPB2N
36C5<> 57A5>
FW_TPB2P
36C5<> 57A5>
FW_TPI1N
36A8<> 36D1<> 57A5>
FW_TPI1P
36A8<> 36D1<> 57A5>
FW_TPI2N
36A8<> 36C1<> 57A5>
FW_TPI2P
36A8<> 36C1<> 57A5>
FW_TPO1N
36A8<> 36D1<> 57A5>
FW_TPO1P
36B8<> 36D1<> 57A5>
FW_TPO2N
36A8<> 36C1<> 57A5>
FW_TPO2P
36A8<> 36C1<> 57A5>
FW_VGND
52B6>
FW_VP
36D5< 52B6>
FW_VP1
36D1<> 36D3<> 52B6>
FW_VP2
36C1<> 36D3<> 52B6>
FW_VP_1
36D4< 52B6>
FW_VP_2
36D4< 52B6>
FW_VREG_FB
36D7<

5
FW_XI
36C6< 57A5>
FW_XI_A
36C6<
FW_XO
36C6<> 57A5>
GCORE_1
48C2<
GCORE_BSTH
48C5<>
GCORE_BSTH_TERM 48C3<>
GCORE_COMP
48B6<
GCORE_DH
48B5<>
GCORE_DL
48B5<>
GCORE_GND
48B5<>
GCORE_OCSET
48B6<>
GCORE_OVP
48B6<>
GCORE_VCC
48C6<
GCORE_VSENSE
48B6<> 48C4<>
GPULNKON
23C4<>
GPU_50PULLDWN
17A5<> 52A8>
GPU_50PULLUP
17B5<> 52A8>
GPU_AGP_AD<0>
17D6<>
GPU_AGP_AD<0..15> 54B7<
GPU_AGP_AD<1>
17D6<>
GPU_AGP_AD<2>
17D6<>
GPU_AGP_AD<3>
17D6<>
GPU_AGP_AD<4>
17D7<>
GPU_AGP_AD<5>
17D7<>
GPU_AGP_AD<6>
17D7<>
GPU_AGP_AD<7>
17D7<>
GPU_AGP_AD<8>
17D6<>
GPU_AGP_AD<9>
17D6<>
GPU_AGP_AD<10>
17D6<>
GPU_AGP_AD<11>
17D6<>
GPU_AGP_AD<12>
17D6<>
GPU_AGP_AD<13>
17D6<>
GPU_AGP_AD<14>
17D6<>
GPU_AGP_AD<15>
17C6<>
GPU_AGP_AD<16>
17C6<>
GPU_AGP_AD<16..31> 54B7<
GPU_AGP_AD<17>
17C6<>
GPU_AGP_AD<18>
17C6<>
GPU_AGP_AD<19>
17C6<>
GPU_AGP_AD<20>
17C6<>
GPU_AGP_AD<21>
17C6<>
GPU_AGP_AD<22>
17C6<>
GPU_AGP_AD<23>
17C6<>
GPU_AGP_AD<24>
17C6<>
GPU_AGP_AD<25>
17C6<>
GPU_AGP_AD<26>
17C6<>
GPU_AGP_AD<27>
17C6<>
GPU_AGP_AD<28>
17C6<>
GPU_AGP_AD<29>
17C6<>
GPU_AGP_AD<30>
17C6<>
GPU_AGP_AD<31>
17C6<>
GPU_AGP_CBE<0>
17C6<>
GPU_AGP_CBE<0..1> 54B7<
GPU_AGP_CBE<1>
17C6<>
GPU_AGP_CBE<2>
17C6<>
GPU_AGP_CBE<2..3> 54B7<
GPU_AGP_CBE<3>
17C6<>
GPU_AGP_DEVSEL_L 17B6<> 54B7<
GPU_AGP_FRAME_L 17B6<> 54B7<
GPU_AGP_IRDY_L
17B6<> 54B7<
GPU_AGP_PAR
17B6<> 54B7<
GPU_AGP_PIPE_L
17B6<> 54A7<
GPU_AGP_RBF_L
17B6<> 54A7<
GPU_AGP_SBA<0>
17A6<>
GPU_AGP_SBA<0..7> 54A7<
GPU_AGP_SBA<1>
17A6<>
GPU_AGP_SBA<2>
17A6<>
GPU_AGP_SBA<3>
17A6<>
GPU_AGP_SBA<4>
17A6<>
GPU_AGP_SBA<5>
17A6<>
GPU_AGP_SBA<6>
17A6<>
GPU_AGP_SBA<7>
17A6<>
GPU_AGP_SB_STB
17B6<> 54A7<
GPU_AGP_SB_STB_L 17A6<> 54A7<
GPU_AGP_STOP_L
17B6<> 54B7<
GPU_AGP_TRDY_L
17B6<> 54B7<
GPU_AGP_VREF
17A2< 17A8< 52A6>
GPU_AGP_VREF_H
16A7<
GPU_AGP_VREF_L
16A7<
GPU_AGP_VREF_X
17A2<
GPU_AGP_VREF_Y
17A2<
GPU_AGP_WBF_L
17B6<>
GPU_FB_VREF
18C8< 52A6>
GPU_FPBCLK
23C4<>
GPU_FPBCLK_L
23C4<>
GPU_FW_PME_L
23C4<>
GPU_IFB1IOVDD
23B3<
GPU_IFP1PLLVDD
23B3<
GPU_MBDET_L
17A6<>
GPU_SS_XIN
22A7<
GPU_STEREO
23C4<>
GPU_STRAP<0>
22B4<> 26A4<
GPU_STRAP<1>
22B4<> 26B3<
GPU_STRAP<2>
22B4<> 26D3<
GPU_STRAP<3>
22B4<> 26D3<
GPU_SWAP_A
23C4<>
GPU_SWAP_B
23C4<>
GPU_TESTMECLK
23C4<>
GPU_TMDS_CKM
23C2< 23D3<> 57D2>
GPU_TMDS_CKP
23C2< 23D3<> 57D2>
GPU_TMDS_D0M
23C2< 23D3<> 57D2>
GPU_TMDS_D0P
23C2< 23D3<> 57D2>
GPU_TMDS_D1M
23C2< 23D3<> 57D2>
GPU_TMDS_D1P
23C2< 23D3<> 57D2>
GPU_TMDS_D2M
23C2< 23D3<> 57D2>
GPU_TMDS_D2P
23C2< 23D3<> 57D2>
GPU_TMODE
17A5< 52A8>
GPU_XTALOUTBUFF 22A8< 22B4<>
GPU_XTALSSIN
22A5< 22B2< 52A8>
GPWRGD
47B8< 48A5<>

4
GRAPHICS_VPWR
48B5<>
GRAPH_CORE
17D4< 23C7<> 48C2<> 52A6>
GRAPH_DDC_SCL
22D5<> 24A7<
GRAPH_DDC_SDA
22D5<> 24A7<
GRAPH_IIC_SCL2
23D3<>
GRAPH_IIC_SDA2
23D3<>
HD_DIOR_L
37D1< 38C3<> 58C5>
HD_DIOW_L
37C1< 38C3<> 58C5>
HD_DMACK_L
37D1< 38C3<> 58C5>
HD_DMARQ
38C3<> 58C5>
HD_INTRQ
38C3<> 58C5>
HD_IOCHRDY
37C1< 38C3<> 58C5>
HD_RESET_L
37D1< 38C3<> 58C5>
HD_UIDE_ADDR<0> 38C3<>
HD_UIDE_ADDR<0..2> 58C5>
HD_UIDE_ADDR<1> 38C3<>
HD_UIDE_ADDR<2> 38C2<>
HD_UIDE_CS1FX_L 38C3<> 58B5>
HD_UIDE_CS3FX_L 38C2<> 58B5>
HEADPHONE_COM
41B2<>
HEADPHONE_L
41B2<> 41D2<
HEADPHONE_R
41B2<> 41C2<
HONK_ADJ
51B4<>
HP16_L
41D4<
HP16_R
41C4<
HPBYP
41B5< 41D6<
HPGAL_L
41D4<
HPGAL_R
41C4<
HPIN_L
41D6<
HPIN_R
41D6<
HP_OFF
41A7< 41D5<
HP_OUT_L
41D5<>
HP_OUT_R
41D5<>
HP_STAR_GND
39B7<> 41A8< 41B4< 41B8< 41C5<
41D4< 41D7<
HP_TL
41D3<
HP_TP
41B3<
HP_TR
41C3<
HSYNC*
22C5<> 57D5>
ICORE_COMP
47B6<
ICW
47B7<
IFP0AVCC
23A6< 23C1< 52A6>
IFP0PLLVDD
23B4<
IFP0RSET
23B4<>
IFP0VREF
23B4<> 52A6>
IFP_AVCC
23A7<>
IFP_VADJ
23A8<
IIC_ADD
29C6<> 59A7>
INTCORE_1
47B3<
INTCORE_BSTH
47B6<>
INTCORE_BSTH_TERM 47B6<>
INTCORE_DH
47B6<>
INTCORE_DHT
47B5<>
INTCORE_DL
47B6<>
INTCORE_GND
47A7<>
INTCORE_OCSET
47B6<>
INTCORE_OVP
47B6<>
INTCORE_VCC
47C7<
INTREPID_ACS_REF 9A3<
INTREPID_VPWR
47B6<>
INTREPID_VPWRA
47B4<>
INTREPID_VSENSE 47C6<> 59C7>
INTREP_DLT
47B5<>
INT_AGPPVT
16C6<>
INT_AGP_FB_IN
16C6< 54A7<
INT_AGP_FB_OUT
16C6<> 54A7<
INT_AGP_VREF
16A7< 16C6<> 52C3>
INT_ANALYZER_CLK 8A2< 9B4< 16C7< 54A7< 56B3> 59A7>
INT_ANALYZER_CLKA 9B3<>
INT_CLOCK_OUT
8B2<> 56B3>
INT_CPU_FB_IN
9B3< 56C3>
INT_CPU_FB_OUT
9B3<> 56C3>
INT_ENET_RST_L
28B5<> 28D1< 35B8<
INT_EXTINT3_PU
28B5<> 28B8<
INT_EXTINT12_PU 28B5<> 28B8<
INT_EXTINT13_PU 28B5<> 28B8<
INT_EXTINT17_PU 28B5<> 28B8< 32B6>
INT_GPIO1_PD
28A8< 28C5<>
INT_GPIO9_PU
28B5<> 28B8<
INT_GPIO12_PU
28A8< 28B5<>
INT_I2C_CLK0
14A6<> 15A6< 34B3<
INT_I2C_CLK0R
34B5<> 34C1<
INT_I2C_CLK1
34A3<> 34B1<
INT_I2C_CLK2
28A3<> 28D1< 29C7<> 34B5< 39B1<>
59A7>
INT_I2C_DATA0
14A6<> 15A6< 34B3<
INT_I2C_DATA0R
34B5<> 34C1<
INT_I2C_DATA1
34A3<> 34B1<
INT_I2C_DATA2
28A3<> 28D1< 29C7<> 34B5< 39B1<>
59A7>
INT_JTAG_TEI
34B7< 34C1<
INT_MEM_REF
12B6<
INT_MEM_VREF
12A8<> 14A1<
INT_MOD_BITCLK
28A3<> 28A8< 28C6<
INT_MOD_CLKOUT
28A3> 28A8< 28C6<
INT_MOD_DTI
28A3< 28A8< 28C6<
INT_MOD_DTO
28A3> 28A8< 28C6<
INT_MOD_SYNC
28A3<> 28A8< 28C6<
INT_PCI_FB_IN
30C5< 54C7<
INT_PCI_FB_OUT
30C5<> 54D7<
INT_PEND_PROC_INT 28A5> 44B4<>
INT_PLL1_GND
28A5<> 28C4<
INT_PLL2_GND
28A5<> 28D4<
INT_PLL3_GND
28A4<> 28D4<
INT_PLL4_GND
30C4<> 30D4<
INT_PLL5_GND
16A5<> 16D5<
INT_PLL6_GND
9A2<> 9D3<
INT_PLL7_GND
28A4<> 28D4<
INT_PLL9_GND
28A4<> 28D4<

INT_PROC_SLEEP_REQ_L 28A5< 44B4<>


INT_PU_RESET_L
15B3< 34C3< 44C2<> 44C2<>
INT_REF_CLK_IN_PD 28A6< 53A6<
INT_RESET_L
34C3< 35B8< 41A7< 43C7< 44D2<>
INT_ROM_CS_L
30C5<>
INT_ROM_OE_L
30C5<>
INT_ROM_OVERLAY_PU 16D7< 30A7< 30C5<> 54A7<
INT_ROM_RW_L
30C5<>
INT_SND_CLKOUT
28A3<>
INT_SND_SCLK
28A3<>
INT_SND_SYNC
28B3<>
INT_SND_TO_AUDIO 28B3<>
INT_SPKR+
42A6<> 43D8<
INT_SPKR42A6<> 43D8<
INT_SUSPEND_ACK_L 9B3> 44B5<>
INT_SUSPEND_REQ_L 9B3< 44B8<>
INT_TMDS_3V
24C3<> 52A6> 59C7>
INT_TST_MONIN_PD 34B7< 34C1<
INT_TST_PLLEN_PD 28C6< 34B7<
INT_WATCHDOG_L
28A5> 44C5<>
INV_CUR_HI
23D7< 29B8<
INV_CUR_HI_FILT 29A5<> 59A7>
IO_RESET_L
32A6< 35B8< 44B8<> 44D3< 59A7>
IPWRGD
46A8< 47A6<>
JAZ
43B6<
JTAG_ASIC_TCK
8A4<> 34B7< 35C4< 59D7>
JTAG_ASIC_TDI
8A4<> 28C6< 34B7< 59D7>
JTAG_ASIC_TDO
8A4<> 35B4<> 59D7>
JTAG_ASIC_TMS
8A4<> 34B7< 35A2< 35B4<> 59D7>
JTAG_ASIC_TRST_L 8A4<> 34B7< 59C7>
JTAG_CPU_TCK
4C3< 7D5< 8A3<> 59C7>
JTAG_CPU_TDI
4C3< 7A5< 8A3<> 59C7>
JTAG_CPU_TDO
4C3> 8A3<> 59C7>
JTAG_CPU_TMS
4C3< 7A5< 8A3<> 59C7>
JTAG_CPU_TRST_L 4C3< 7C5< 8A3<> 59C7>
JTAG_ENET_TDI
35A2< 35B5<>
JTAG_INTRP_TDO
28C6< 34B7> 35B3<
KAVAN
43A6<
KS5VSD
29A5<> 52B3> 59A7>
KS_INT_SPKR+
29A3< 43D7< 58A5> 59B7>
KS_INT_SPKR+_FILT 29A5<>
KS_INT_SPKR29A3< 42B4< 43D7< 58A5> 59B7>
KS_INT_SPKR-_FILT 29A5<>
KYLE
46C6<
L31_2
40C6<
L32_2
40B6<>
L36_2
40B6<
L41_FILT
42B7<>
L43_1
41A4<
L59_2_I461
43A5<
L3202_1
40C6<
LAMP_STS
23D7< 29A3<
LAMP_STS_FILT
29A5<> 59A7>
LCD_PWM
23D7< 29A8<
LCD_PWM_FILT
29A5<> 59A7>
LED_5V
29A8< 52B3>
LED_5V_FILT
29A5<> 52B3> 59A7>
LED_RET
29A3< 51B6< 52B3>
LED_RET_FILT
29A5<> 52A3> 59A7>
LED_ROMCS
30B3<>
LED_ROMCS_L
30B4<
LED_ROMCS_LIGHT 30A3<
LID_SWITCH
29B2<> 44C4<>
LINA
39C4< 40C2<
LINEOUT_COMM2
59B5>
LINE_IN_COM
40B7<> 59B5>
LINE_IN_L
40B7<> 40C7<> 59B5>
LINE_IN_R
40B6<> 40B7<> 59B5>
LINE_IN_SENSE
40B7<> 40C7<> 59B5>
LINE_OUT_L
59B5>
LINN
42C5< 43D2<
LINN1
43D2<
LINP
42C5< 43D4<
LINSENSE
40C5<
LOW_PWR
35A5< 35B4<
LO_T1
41A4<
LP4202P2
40C5<
LP4202P3
40B5<
LP4202P4
40B5<
LPL1
41D6<
LPR1
41C6<
LT1962_INT_ADJ
28D7<
LT1962_INT_BYP
28D7<>
LT1962_INT_VIN
28D7<>
M1FH
43B7<>
M1FL
43A7<>
M1H
43B6<> 43B6<>
M1HFILT
43B5<
M1L
43A6<> 43B6<>
M1S
43A6<> 43B6<>
MAIN_RESET_L
17C8< 30B2< 31D4< 32A8< 44C4<>
59A5>
MAIN_RESET_L_PU 31D3<>
MAIN_SUPPLY_LED 50D5<
MAXBUS_PWR_EN
46C7<
MAX_PWR_ADJ
46C5<>
MEMREFG1
20A5<>
MEMREFG2
20A4<>
MEMREFG3
21A4<>
MEMREFG4
21A4<>
MEMREFN1
18B8<>
MEMREFN2
18B7<>
MEM_ADDR<0>
12C3< 12D6<>
MEM_ADDR<0..12> 53D6<
MEM_ADDR<1>
12C3< 12D6<>
MEM_ADDR<2>
12C3< 12D6<>
MEM_ADDR<3>
12D3< 12D6<>
MEM_ADDR<4>
12D3< 12D6<>
MEM_ADDR<5>
12C2< 12D6<>
MEM_ADDR<6>
12D2< 12D6<>

1
MEM_ADDR<7>
12D3< 12D6<>
MEM_ADDR<8>
12D2< 12D6<>
MEM_ADDR<9>
12C3< 12D6<>
MEM_ADDR<10>
12C3< 12D6<>
MEM_ADDR<11>
12B3< 12D6<>
MEM_ADDR<12>
12D2< 12D6<>
MEM_BA<0>
12B3< 12D6<>
MEM_BA<0..1>
53D6<
MEM_BA<1>
12B3< 12D6<>
MEM_CAS_L
12A3< 12C6<> 53C6<
MEM_CKE<0>
12C2< 12C6<>
MEM_CKE<0..3>
53C6<
MEM_CKE<1>
12B2< 12B6<>
MEM_CKE<2>
12B6<> 12C2<
MEM_CKE<3>
12B2< 12B6<>
MEM_CS_L<0>
12C2< 12C6<>
MEM_CS_L<0..3>
53C6<
MEM_CS_L<1>
12C2< 12C6<>
MEM_CS_L<2>
12B2< 12C6<>
MEM_CS_L<3>
12B2< 12C6<>
MEM_DATA<0>
12D8<> 13C8<>
MEM_DATA<0..63> 53D6<
MEM_DATA<1>
12D8<> 13C8<>
MEM_DATA<2>
12D8<> 13C8<>
MEM_DATA<3>
12D8<> 13C8<>
MEM_DATA<4>
12D8<> 13C8<>
MEM_DATA<5>
12D8<> 13C8<>
MEM_DATA<6>
12D8<> 13C8<>
MEM_DATA<7>
12D8<> 13C8<>
MEM_DATA<8>
12D8<> 13C8<>
MEM_DATA<9>
12D8<> 13C8<>
MEM_DATA<10>
12D8<> 13C8<>
MEM_DATA<11>
12D8<> 13C8<>
MEM_DATA<12>
12D8<> 13C8<>
MEM_DATA<13>
12D8<> 13C8<>
MEM_DATA<14>
12C8<> 13C8<>
MEM_DATA<15>
12C8<> 13C8<>
MEM_DATA<16>
12C8<> 13B6<>
MEM_DATA<17>
12C8<> 13B6<>
MEM_DATA<18>
12C8<> 13B6<>
MEM_DATA<19>
12C8<> 13B6<>
MEM_DATA<20>
12C8<> 13B6<>
MEM_DATA<21>
12C8<> 13B6<>
MEM_DATA<22>
12C8<> 13B6<>
MEM_DATA<23>
12C8<> 13B6<>
MEM_DATA<24>
12C8<> 13A6<>
MEM_DATA<25>
12C8<> 13A6<>
MEM_DATA<26>
12C8<> 13A6<>
MEM_DATA<27>
12C8<> 13A6<>
MEM_DATA<28>
12C8<> 13A6<>
MEM_DATA<29>
12C8<> 13A6<>
MEM_DATA<30>
12C8<> 13A6<>
MEM_DATA<31>
12C8<> 13A6<>
MEM_DATA<32>
12C8<> 13C4<>
MEM_DATA<33>
12C8<> 13C4<>
MEM_DATA<34>
12C8<> 13C4<>
MEM_DATA<35>
12C8<> 13C4<>
MEM_DATA<36>
12C8<> 13C4<>
MEM_DATA<37>
12C8<> 13C4<>
MEM_DATA<38>
12C8<> 13C4<>
MEM_DATA<39>
12C8<> 13C4<>
MEM_DATA<40>
12B8<> 13C4<>
MEM_DATA<41>
12B8<> 13C4<>
MEM_DATA<42>
12B8<> 13C4<>
MEM_DATA<43>
12B8<> 13C4<>
MEM_DATA<44>
12B8<> 13C4<>
MEM_DATA<45>
12B8<> 13C4<>
MEM_DATA<46>
12B8<> 13C4<>
MEM_DATA<47>
12B8<> 13C4<>
MEM_DATA<48>
12B8<> 13B3<>
MEM_DATA<49>
12B8<> 13B3<>
MEM_DATA<50>
12B8<> 13B3<>
MEM_DATA<51>
12B8<> 13B3<>
MEM_DATA<52>
12B8<> 13B3<>
MEM_DATA<53>
12B8<> 13B3<>
MEM_DATA<54>
12B8<> 13B3<>
MEM_DATA<55>
12B8<> 13B3<>
MEM_DATA<56>
12B8<> 13B3<>
MEM_DATA<57>
12B8<> 13B3<>
MEM_DATA<58>
12B8<> 13B3<>
MEM_DATA<59>
12B8<> 13B3<>
MEM_DATA<60>
12B8<> 13B3<>
MEM_DATA<61>
12B8<> 13B3<>
MEM_DATA<62>
12B8<> 13B3<>
MEM_DATA<63>
12B8<> 13B3<>
MEM_DQM<0>
12C6<> 13C8<>
MEM_DQM<0..7>
53D6<
MEM_DQM<1>
12C6<> 13C8<>
MEM_DQM<2>
12C6<> 13A6<>
MEM_DQM<3>
12C6<> 13A6<>
MEM_DQM<4>
12C6<> 13C4<>
MEM_DQM<5>
12C6<> 13C4<>
MEM_DQM<6>
12C6<> 13B3<>
MEM_DQM<7>
12C6<> 13B3<>
MEM_DQS<0>
12C6<> 13C8<>
MEM_DQS<0..7>
53D6<
MEM_DQS<1>
12C6<> 13C8<>
MEM_DQS<2>
12C6<> 13A6<>
MEM_DQS<3>
12C6<> 13A6<>
MEM_DQS<4>
12C6<> 13C4<>
MEM_DQS<5>
12C6<> 13C4<>
MEM_DQS<6>
12C6<> 13B3<>
MEM_DQS<7>
12C6<> 13B3<>
MEM_MUXSEL_H<0..1> 53C6<
MEM_MUXSEL_H<1> 12B6<>
MEM_MUXSEL_L<0..1> 53C6<
MEM_MUXSEL_L<1> 12B6<>
MEM_RAS_L
12A3< 12C6<> 53C6<
MEM_WE_L
12B3< 12C6<> 53C6<
MIC1
43B5<

61

MIC1S1
43A7<>
MIC2
43B4<
MIC3
43B4<
MIC4
43B3<>
MIC5
43A3<
MICHIGH
29A5<> 43B8< 58A5> 59A7>
MICLOW
29A5<> 43A8< 58A5> 59A7>
MICSHLD
29A5<> 43A8< 58A5> 59A7>
MIC_C4302
43A5<
MIC_FIX
43C5<
MIC_I519
43A4<
MIC_I520
43A5<
MIC_IN
39C4< 43B2<
MII_EN
35C4<
MODEM_USB_DM
28B2< 29C5<> 58A5> 59B5>
MODEM_USB_DP
28B2< 29C5<> 58A5> 59B5>
MON_DETECT
23D7<> 25C6< 59D5>
MON_I2C_SCL
22D5<> 25B6<
MON_I2C_SDA
22D5<> 25B6<
MPIC_CPU_INT_L
4B3< 7A5< 8D7<> 28B5>
MPWRGD
48B7< 48B7< 49B5<>
MR_FLO
45C5<>
MR_FLO_1
45B4<>
MUX_SEL_H
12D4< 13A3<> 13C4<> 53C6<
MUX_SEL_L
12D4< 13A6<> 13C8<> 53C6<
M_SPD_WP
15A7<
M_VDDID
15A7<
NC_-10VUNREG
29C7<>
NC_-12VREG
29C6<>
NC_AUDIO2MODEM
29C6<>
NC_AUDIO2MODEMRTN 29C6<>
NC_AUD_MODEM
29C6<>
NC_AUD_MODEM_RTN 29C6<>
NC_BIGDIMM9
15D6<
NC_BIGDIMM10
15D6<
NC_BIGDIMM44
15B6<
NC_BIGDIMM45
15B6<
NC_BIGDIMM47
15B6<
NC_BIGDIMM49
15B6<
NC_BIGDIMM51
15B6<
NC_BIGDIMM71
15A6<
NC_BIGDIMM101
15D4>
NC_BIGDIMM102
15D4>
NC_BIGDIMM103
15D4>
NC_BIGDIMM113
15C4>
NC_BIGDIMM134
15C4>
NC_BIGDIMM135
15B4>
NC_BIGDIMM140
15B4>
NC_BIGDIMM142
15B4>
NC_BIGDIMM144
15B4>
NC_BIGDIMM163
15A4>
NC_BIGDIMM167
15A4>
NC_BIGDIMM173
15A4>
NC_BRCLKO
28A5>
NC_BS1
29B7<>
NC_BS2
29B6<>
NC_BS3
29D1<>
NC_BS4
29D1<>
NC_BT1
29D2<>
NC_BT3
29D2<>
NC_BT4
29D2<>
NC_BT5
29D2<>
NC_BT6
29D2<>
NC_BUF_RST
22B5>
NC_CBUS_INT_L
28A8<
NC_CLK33M_PCI_SLOTC 30D7<
NC_CLKENET_LINK_GTX 34C6>
NC_CPUAP<0>
4B7<>
NC_CPUAP<1>
4B7<>
NC_CPUAP<2>
4B7<>
NC_CPUAP<3>
4B7<>
NC_CPUAP<4>
4B7<>
NC_CPUCRUD<0>
5D7<>
NC_CPUCRUD<1>
5D7<>
NC_CPUCRUD<2>
5D7<>
NC_CPUCRUD<3>
5D7<>
NC_CPUCRUD<4>
5D7<>
NC_CPUCRUD<5>
5D7<>
NC_CPUCRUD<6>
5D7<>
NC_CPUCRUD<7>
5D7<>
NC_CPUCRUD<8>
5D7<>
NC_CPUCRUD<9>
5D7<>
NC_CPUCRUD<10>
5D7<>
NC_CPUCRUD<11>
5D7<>
NC_CPUCRUD<12>
5D7<>
NC_CPUCRUD<13>
5D7<>
NC_CPUCRUD<14>
5D7<>
NC_CPUCRUD<15>
5D7<>
NC_CPUCRUD<16>
5D7<>
NC_CPUCRUD<17>
5C7<>
NC_CPUCRUD<18>
5C7<>
NC_CPUCRUD<19>
5C7<>
NC_CPUCRUD<20>
5C7<>
NC_CPUCRUD<21>
5C7<>
NC_CPUCRUD<22>
5C7<>
NC_CPUCRUD<23>
5C7<>
NC_CPUCRUD<24>
5C7<>
NC_CPUCRUD<25>
5C7<>
NC_CPUCRUD<26>
5C7<>
NC_CPUCRUD<27>
5C7<>
NC_CPUCRUD<28>
5C7<>
NC_CPUCRUD<29>
5C7<>
NC_CPUCRUD<30>
5C7<>
NC_CPUCRUD<31>
5C7<>
NC_CPUCRUD<32>
5C7<>
NC_CPUCRUD<33>
5C7<>
NC_CPUCRUD<34>
5C7<>
NC_CPUCRUD<35>
5C7<>
NC_CPUCRUD<36>
5C7<>
NC_CPUCRUD<37>
5C7<>

NC_CPUCRUD<38>
5C7<>
NC_CPUCRUD<39>
5C7<>
NC_CPUCRUD<40>
5C7<>
NC_CPUCRUD<41>
5B7<>
NC_CPUCRUD<42>
5B7<>
NC_CPUCRUD<43>
5B7<>
NC_CPUCRUD<44>
5B7<>
NC_CPUCRUD<45>
5B7<>
NC_CPUCRUD<46>
5B7<>
NC_CPUCRUD<47>
5B7<>
NC_CPUCRUD<48>
5B7<>
NC_CPUCRUD<49>
5B7<>
NC_CPUCRUD<50>
5B7<>
NC_CPUCRUD<51>
5B7<>
NC_CPUCRUD<52>
5B7<>
NC_CPUCRUD<53>
5B7<>
NC_CPUCRUD<54>
5B7<>
NC_CPUCRUD<55>
5B7<>
NC_CPUCRUD<56>
5B7<>
NC_CPUCRUD<57>
5B7<>
NC_CPUCRUD<58>
5B7<>
NC_CPUCRUD<59>
5B7<>
NC_CPUCRUD<60>
5B7<>
NC_CPUCRUD<61>
5B7<>
NC_CPUCRUD<62>
5B7<>
NC_CPUCRUD<63>
5B7<>
NC_CPUCRUD<64>
5B7<>
NC_CPUCRUD<65>
5B7<>
NC_CPUCRUD<66>
5B7<>
NC_CPUCRUD<67>
5A7<>
NC_CPUCRUD<68>
5A7<>
NC_CPUCRUD<69>
5A7<>
NC_CPUCRUD<70>
5A7<>
NC_CPUCRUD<71>
5A7<>
NC_CPUCRUD<72>
5A7<>
NC_CPUCRUD<73>
5A7<>
NC_CPUCRUD<74>
5A7<>
NC_CPUCRUD<75>
5A7<>
NC_CPUCRUD<76>
5A7<>
NC_CPUCRUD<77>
5A7<>
NC_CPUCRUD<78>
5A7<>
NC_CPUCRUD<79>
5A7<>
NC_CPUCRUD<80>
5A7<>
NC_CPUCRUD<81>
5A7<>
NC_CPUCRUD<82>
5A7<>
NC_CPUCRUD<83>
5A7<>
NC_CPUCRUD<84>
5A7<>
NC_CPUCRUD<85>
5A7<>
NC_CPUCRUD<86>
5A7<>
NC_CPUCRUD<87>
5A7<>
NC_CPUCRUD<88>
5A7<>
NC_CPUCRUD<89>
5A7<>
NC_CPUDP<0>
5A4<>
NC_CPUDP<1>
5A4<>
NC_CPUDP<2>
5A4<>
NC_CPUDP<3>
5A4<>
NC_CPUDP<4>
5A4<>
NC_CPUDP<5>
5A4<>
NC_CPUDP<6>
5A4<>
NC_CPUDP<7>
5A4<>
NC_CPU_CLKOUT
4D3>
NC_CSLOT_ADDR<3> 37B7>
NC_CSLOT_ADDR<4> 37A7>
NC_CSLOT_ADDR<5> 37A7>
NC_CSLOT_ADDR<6> 37A7>
NC_CSLOT_ADDR<7> 37A7>
NC_CSLOT_ADDR<8> 37A7>
NC_CSLOT_ADDR<9> 37A7>
NC_CSLOT_CE1_L
37C7>
NC_CSLOT_CE2_L
37C7>
NC_CSLOT_IORD_L 37C7>
NC_CSLOT_IOWR_L 37C7>
NC_CSLOT_OE_L
37B7>
NC_CSLOT_WE_L
37B7>
NC_DAA_CLKOUT
29C7<>
NC_DAA_LOADOUT
29C7<>
NC_DACC_BLU
22C4>
NC_DACC_GRN
22C4>
NC_DACC_RED
22C4>
NC_DACC_RSET
22C4>
NC_DFPCLK
23C3>
NC_DFPCLK*
23C3>
NC_DFPD0
23C3>
NC_DFPD1
23C3>
NC_DFPD2
23C3>
NC_DFPD3
23C3>
NC_DFPD5
23C3>
NC_DFPD6
23C3>
NC_ENET_LINK_TXD<4> 34C6>
NC_ENET_LINK_TXD<5> 34C6>
NC_ENET_LINK_TXD<6> 34C6>
NC_ENET_LINK_TXD<7> 34C6>
NC_EXT_TMDS_CKM 23C3>
NC_EXT_TMDS_CKP 23C3>
NC_EXT_TMDS_D0M 23C3>
NC_EXT_TMDS_D0P 23C3>
NC_EXT_TMDS_D1M 23C3>
NC_EXT_TMDS_D1P 23C3>
NC_EXT_TMDS_D2M 23C3>
NC_EXT_TMDS_D2P 23C3>
NC_FB1<0>
20B6<>
NC_FB1<1>
20B6<>
NC_FB1<2>
20B6<>
NC_FB1<3>
20B6<>
NC_FB1<4>
20B6<>
NC_FB1<5>
20B6<>
NC_FB1<6>
20B6<>
NC_FB1<7>
20B6<>
NC_FB1<8>
20B6<>
NC_FB1<9>
20B5<>

5
NC_FB1<10>
20B5<>
NC_FB2<0>
20B2<>
NC_FB2<1>
20B2<>
NC_FB2<2>
20B2<>
NC_FB2<3>
20B2<>
NC_FB2<4>
20B2<>
NC_FB2<5>
20B2<>
NC_FB2<6>
20B2<>
NC_FB2<7>
20B2<>
NC_FB2<8>
20B2<>
NC_FB2<9>
20B1<>
NC_FB2<10>
20B1<>
NC_FB3<0>
21B6<>
NC_FB3<1>
21B6<>
NC_FB3<2>
21B6<>
NC_FB3<3>
21B6<>
NC_FB3<4>
21B6<>
NC_FB3<5>
21B6<>
NC_FB3<6>
21B6<>
NC_FB3<7>
21B6<>
NC_FB3<8>
21B6<>
NC_FB3<9>
21B5<>
NC_FB3<10>
21B5<>
NC_FB4<0>
21B2<>
NC_FB4<1>
21B2<>
NC_FB4<2>
21B2<>
NC_FB4<3>
21B2<>
NC_FB4<4>
21B2<>
NC_FB4<5>
21B2<>
NC_FB4<6>
21B2<>
NC_FB4<7>
21B2<>
NC_FB4<8>
21B2<>
NC_FB4<9>
21B1<>
NC_FB4<10>
21B1<>
NC_FBACS1_L
18C8>
NC_FBBCS1_L
18C4<>
NC_FBDQS_L<0>
18C7<>
NC_FBDQS_L<1>
18C7<>
NC_FBDQS_L<2>
18C7<>
NC_FBDQS_L<3>
18C7<>
NC_FBDQS_L<4>
18C7<>
NC_FBDQS_L<5>
18C7<>
NC_FBDQS_L<6>
18C7<>
NC_FBDQS_L<7>
18C7<>
NC_FBDQS_L<8>
18D4<>
NC_FBDQS_L<9>
18D4<>
NC_FBDQS_L<10>
18D4<>
NC_FBDQS_L<11>
18D4<>
NC_FBDQS_L<12>
18D4<>
NC_FBDQS_L<13>
18D4<>
NC_FBDQS_L<14>
18D4<>
NC_FBDQS_L<15>
18D4<>
NC_FMAX7
8A8<>
NC_FMAX8
8A8<>
NC_FW_CNA
36B6>
NC_GPU<0>
17A6<>
NC_GPU<1>
17A6<>
NC_GPU<2>
17A6<>
NC_GPU<3>
17A6<>
NC_GPU<4>
17A6<>
NC_GPULPS
23C4<>
NC_GPU_DBI_LO
17B6<>
NC_GPU_INTB_L
17B6<>
NC_GPU_THERMA
23C4<>
NC_GPU_THERMC
23C4<>
NC_IFP1RSET
23B3<>
NC_IFP1VREF
23B3<>
NC_INPA
39C2>
NC_INT_TST_MONOUT_TP 34B6>
NC_JTAG7
8A4<>
NC_JTAG10
8A3<>
NC_LCENABLE
8A4<>
NC_MEM_MUXSEL_H<0> 12B6<>
NC_MEM_MUXSEL_L<0> 12B6<>
NC_MODEM_DETECT_L 29C7<>
NC_NVAGP_TDO
17A5<>
NC_P00_D0
44D5<>
NC_P01_D1
44D5<>
NC_P02_D2
44C5<>
NC_P03_D3
44C5<>
NC_P04_D4
44C5<>
NC_P05_D5
44C5<>
NC_P6_D6
44C5<>
NC_P07_D7
44C5<>
NC_P10_D8
44C5<>
NC_P11_D9
44C5<>
NC_P14_D12
44C5<>
NC_P20_A0_D0
44C5<>
NC_P21_A1_D1_D0 44C5<>
NC_P22_A2_D2_D1 44C5<>
NC_P23_A3_D3_D2 44C5<>
NC_P24_A4_D4_D3 44C5<>
NC_P25_A5_D5_D4 44C5<>
NC_P26_A6_D6_D5 44C5<>
NC_P27_A7_D7_D6 44C5<>
NC_P33_A11
44B5<>
NC_P34_A12
44B5<>
NC_P35_A13
44B5<>
NC_P36_A14
44B5<>
NC_P37_A15
44B5<>
NC_P43_A19
44B5<>
NC_P45_CS1_L
44B5<>
NC_P74_TA2OUT_W 44C4<>
NC_P75_TA2IN_W
44C4<>
NC_P76_TA3OUT
44C4<>
NC_P77_TA3IN
44C4<>
NC_P92_TB2IN_SOUT3 44B4<>
NC_P93_DA0_TB3IN 44B4<>
NC_P96_ANEX0_CLK4 44B4<>
NC_P103_AN3
44B4<>

4
NC_PCIR0
31B7<
NC_PCIR1
31B7<
NC_PCITR0
31B6<
NC_PCITR1
31B6<
NC_PMON_OUT_L
4B3>
NC_PMU_DL_10
29B2<>
NC_PMU_DL_12
29B2<>
NC_PPL*
44C6<
NC_RESET_BUTTON_L 8A8<>
NC_RFBA<12>
18E2<
NC_RFBBA<12>
18A2<
NC_RF_DISABLE_L 59A5>
NC_ROMCS_L
18C8>
NC_RP1PIN4
16B3<
NC_RP1399
30B5<
NC_RP2848
28A8<
NC_RP3319
28D3<
NC_RP3324_2
28C1<
NC_RPT48P1
28D3<
NC_RPT77P6
28B8<
NC_SDOUT2
39C2>
NC_SODIMM71
14C5<>
NC_SODIMM72
14C4<>
NC_SODIMM73
14C5<>
NC_SODIMM74
14C4<>
NC_SODIMM77
14C5<>
NC_SODIMM78
14C4<>
NC_SODIMM79
14C5<>
NC_SODIMM80
14C4<>
NC_SODIMM83
14C5<>
NC_SODIMM84
14C4<>
NC_SODIMM85
14C5<>
NC_SODIMM86
14C4<>
NC_SODIMM89
14C5<>
NC_SODIMM91
14C5<>
NC_SODIMM97
14B5<>
NC_SODIMM98
14B4<>
NC_SODIMM123
14B5<>
NC_SODIMM124
14B4<>
NC_SODIMM199
14A5<>
NC_SODIMM200
14A4<>
NC_SODIMM201
14D5<>
NC_SODIMM202
14A6<>
NC_SW3V5V_33OUT 50C6<
NC_SYSCLK_DDRCLK_A2 12B4<
NC_SYSCLK_DDRCLK_A2_L 12B4<
NC_TAS_SDOUT1
39C2>
NC_TESTMODE
8A4<>
NC_TMDS_TXD3M
23C3>
NC_TMDS_TXD3P
23C3>
NC_TMDS_TXD7M
23C3>
NC_TMDS_TXD7P
23C3>
NC_TX1_1
35C3<
NC_TX1_2
35C3<
NC_TX1_3
35C2<
NC_TX1_4
35C2<
NC_UB3P4
35D5<>
NC_USB2_AMC
32A4<
NC_USB2_NANDTEST 32A4<
NC_USB2_NTEST1
32A4<
NC_USB2_PPON1
32B4>
NC_USB2_PPON2
32B4>
NC_USB2_PPON3
32B4>
NC_USB2_PPON4
32B4>
NC_USB2_PPON5
32B4>
NC_USB2_RSDEM
32C4>
NC_USB2_RSDEP
32C4>
NC_USB2_RSDFM
32C4>
NC_USB2_RSDFP
32B4>
NC_USB2_SMC
32A4<
NC_USB2_SMI_L
32A6>
NC_USB2_SRCLK
32A4>
NC_USB2_SRDTA
32A4<>
NC_USB2_SRMOD
32A4<
NC_USB2_TEB
32A4<
NC_USB2_TEST
32A4<
NC_USB_M
31B2<>
NC_USB_P
31B2<>
NC_UT6P6
28D8<>
NC_UT6P7
28D8<>
NC_UT164
44D7<>
NC_UT165
44D7<>
NC_VCORE10
45D6<
NC_VIPHCLK
22D5>
NC_VR4
39D6<
NC_VTT<0>
18G7<
NC_VTT<1>
18G7<
NC_VTT<2>
18G7<
NC_VTT<3>
18G7<
NC_VTT<4>
18G7<
NC_VTT<5>
18G7<
NC_VTT<6>
18G7<
NC_VTT<7>
18G7<
NC_VTT<8>
18G7<
NC_VTT<9>
18F7<
NC_VTT<10>
18F7<
NC_VTT<11>
18F7<
NC_WL<1>
31B3<>
NC_WL<2>
31B2<>
NC_WL<3>
31B3<>
NC_WL<4>
31B2<>
NC_WL<5>
31B3<>
NC_WL<6>
31B2<>
NC_WL<7>
31B3<>
NC_WL<8>
31B2<>
NC_WL<9>
31B3<>
NC_WL<10>
31B2<>
NC_WL<11>
31B3<>
NC_WL<12>
31B2<>
NC_WL<13>
31B3<>

3
NC_WL<14>
NC_WL<15>
NC_WL<16>
NC_WL<17>
NC_WL<18>
NC_WL<19>
NC_WL<20>
NC_WL<21>
NC_WL<23>
NC_XTLINO
NEC_AVDD
NEC_XT2_B
NET18
NET19
NET22
NET24
NET32
NET32_B
NET40
NMI_BUTTON*
NV11_HSYNC
NV11_VSYNC
NV11_XTALIN
NV11_XTALOUT
NVAGP_TCLK
NVAGP_TDI
NVAGP_TMS
NVAGP_TRST_L
NVPLLVDD
NV_BLUE2
NV_GPIOD0
NV_GPIOD2
NV_GPIOD5
NV_GPIOD7
NV_GPIOD8
NV_GPIOD9
NV_GREEN2
NV_PCI_RST_L
NV_RED2
OGAL
OGAR
OGND3_JTAG_EN
OPA_STAR_GND
OPA_VREF
OUT_R
OVDD_ADJ
PB_AUD
PB_GAL
PCIT_AD<0>
PCIT_AD<31..0>
PCIT_AD<1>
PCIT_AD<2>
PCIT_AD<3>
PCIT_AD<4>
PCIT_AD<5>
PCIT_AD<6>
PCIT_AD<7>
PCIT_AD<8>
PCIT_AD<9>
PCIT_AD<10>
PCIT_AD<11>
PCIT_AD<12>
PCIT_AD<13>
PCIT_AD<14>
PCIT_AD<15>
PCIT_AD<16>
PCIT_AD<17>
PCIT_AD<18>
PCIT_AD<19>
PCIT_AD<20>
PCIT_AD<21>
PCIT_AD<22>
PCIT_AD<23>
PCIT_AD<24>
PCIT_AD<25>
PCIT_AD<26>
PCIT_AD<27>
PCIT_AD<28>
PCIT_AD<29>
PCIT_AD<30>
PCIT_AD<31>
PCIT_CBE<0>
PCIT_CBE<31..0>
PCIT_CBE<1>
PCIT_CBE<2>
PCIT_CBE<3>
PCIT_DEVSEL_L
PCIT_FRAME_L
PCIT_IRDY_L
PCIT_PAR
PCIT_STOP_L
PCIT_TRDY_L
PCI_AD<0>
PCI_AD<31..0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>

31B2<>
31B3<>
31B2<>
31B3<>
31B2<>
31B3<>
31B2<>
31B3<>
31B3<>
39B4<
32D5< 52A3>
32D3<
44D6<>
44D6<>
44D8<>
44D8<>
42A5<
42A5<>
44B4<>
29B2<> 44C4<> 59D5>
22C4<> 26D3<
22C4<> 26D3<
22B4<> 57D5>
22B4<> 57D5>
17A5<>
17A5<>
17A5<>
17A5<>
22D5< 52A6>
22C1<> 22C1<>
23D4<>
23D4<>
23D4<>
22A8< 23D5<>
22A6< 23D5<>
23C4<>
22C1<> 22C1<>
17C7<
22C1<> 22C1<>
41D7<
41C7<
35A5<>
39A7<> 39D6< 40C2< 43A4<
40B3< 43A4<>
59B5>
59C7>
41B4<
41B4<
31B2<> 31C6<
54C7<
31B3<> 31C6< 59C3>
31B2<> 31C6< 59C3>
31B3<> 31C6< 59C3>
31B2<> 31C6<
31B3<> 31C6< 59C3>
31B2<> 31C6<
31B3<> 31C6< 59C3>
31B3<> 31C6< 59C3>
31B2<> 31C6<
31B3<> 31C6< 59C3>
31B2<> 31C6<
31B3<> 31C6< 59C3>
31B2<> 31C6<
31C3<> 31C6< 59B3>
31C2<> 31C6<
31C2<> 31C6<
31C3<> 31C7< 59B3>
31C2<> 31C6<
31C3<> 31C7< 59B3>
31C2<> 31C7<
31C3<> 31C6< 59B3>
31C2<> 31C7<
31C3<> 31C6< 59B3>
31B7< 31C2<>
31B6< 31C3<> 59B3>
31B7< 31C2<>
31B6< 31C3<> 59B3>
31B7< 31C2<> 59B3>
31B6< 31C3<> 59B3>
31B7< 31C2<>
31B6< 31C3<> 59B3>
31B2<> 31B6<
54C7<
31B6< 31C3<> 59A5>
31B6< 31C3<> 59A5>
31B6< 31C3<> 59A5>
31B6< 31C2<> 54C7<
31B6< 31C2<> 54C7<
31B6< 31C3<> 54C7< 59B5>
31B6< 31C2<> 54C7<
31B6< 31C2<> 54C7<
31B6< 31C2<> 54C7<
30C2< 30D4<> 31C7< 32C6<>
53A6<
30C2< 30D4<> 31C7< 32C6<>
30C2< 30D4<> 31C7< 32C6<>
30C2< 30D4<> 31C7< 32C6<>
30C2< 30D4<> 31C7< 32C6<>
30C2< 30D4<> 31C7< 32C6<>
30C2< 30D4<> 31C7< 32C6<>
30C2< 30D4<> 31C7< 32C6<>
30C2< 30D4<> 31C7< 32C6<>
30C2< 30D4<> 31C7< 32C6<>
30C2< 30C4<> 31C7< 32C6<>
30B2< 30C4<> 31C7< 32C6<>
30B2< 30C4<> 31C7< 32C6<>
30B2< 30C4<> 31C7< 32C6<>
30B2< 30C4<> 31C7< 32C6<>
30B2< 30C4<> 31C7< 32C6<>
30B2< 30C4<> 31C7< 32C6<>

1
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>
PCI_CBE<0>
PCI_CBE<3..0>
PCI_CBE<1>
PCI_CBE<2>
PCI_CBE<3>
PCI_DEVSEL_L

30B2< 30C4<> 31C6< 32C6<>


30B2< 30C4<> 31C7< 32C6<> 59B3>
30B2< 30C4<> 31C6< 32C6<>
30B2< 30C4<> 31C6< 32C6<> 59B3>
30C4<> 31C7< 32C6<>
30C4<> 31C6< 32C6<> 59B3>
30C4<> 31C7< 32C6<>
30C1<> 30C4<> 31B6< 32C6<> 59B3>
30C1<> 30C4<> 31B7< 32C6<>
30C1<> 30C4<> 31B6< 32B6<> 59B3>
30C1<> 30C4<> 31B7< 32B7<>
30C1<> 30C4<> 31B6< 32B6<>
30C1<> 30C4<> 31B7< 32B6<>
30C1<> 30C4<> 31B6< 32B6<> 59B3>
30C1<> 30C4<> 31B7< 32B6<>
30C5<> 31B7< 32B6<> 59A5>
53A6<
30C5<> 31B7< 32B6<>
30C5<> 31B7< 32B6<>
30C5<> 31B7< 32B6<>
30B7< 30C5<> 31B7< 32B6<> 54D7<
59A5>
PCI_FBI_EQUAL
30C7< 54C7<
PCI_FBI_PLUS2
30C8< 54C7<
PCI_FBO_PLUS2
30D8< 54D7<
PCI_FB_PLUS4
30C8< 54C7<
PCI_FB_PLUS6
30C7< 54C7<
PCI_FRAME_L
30B7< 30C5<> 31B7< 32B6<> 53A6<
59A5>
PCI_IRDY_L
30B7< 30C5<> 31B7< 32B6<> 54D7<
PCI_PAR
30C5<> 31B7< 32B6<> 54D7< 59A5>
PCI_SLOTB_GNT_L 30B5< 30D5<> 31C2<> 59A5>
PCI_SLOTB_REQ_L 30B7< 30D5<> 31C3<> 59A5>
PCI_SLOTC_GNT_L 30B5< 30D5<>
PCI_SLOTC_REQ_L 30B7< 30D5<>
PCI_SLOTD_GNT_L 30B5< 30D5<> 32B6<
PCI_SLOTD_PERR_L 32B6<>
PCI_SLOTD_REQ_L 30B7< 30D5<> 32B6>
PCI_STOP_L
30B7< 30C5<> 31B7< 32B6<> 54D7<
59A5>
PCI_TRDY_L
30B7< 30C5<> 31B7< 32B6<> 54D7<
59A5>
PGOOD
49B7< 49B7< 50A6>
PG_E
45B6<
PMURESETBUTTON* 44A4< 44A4< 59D5>
PMU_5V_SCL
44C3<>
PMU_5V_SDA
44C3<>
PMU_ACK_L
28C3< 44C4<>
PMU_AGP_RESET
44C4<>
PMU_AP
29B3<> 44D4<>
PMU_AVCC
44B5< 44D4<> 52B3> 59C5>
PMU_BYTE
44B5<
PMU_CLK
28C3<> 44C4<>
PMU_CLKIN
44B4<> 58A5>
PMU_CLKOUT
44B4<> 58A5>
PMU_CLKT
44B2<> 58A5>
PMU_CNVSS
29B3<> 44B5<
PMU_EPM*
29B3<> 44C4<>
PMU_FROM_INT
28C3<> 44C4<>
PMU_IIC_CLK
44A8< 44B4<>
PMU_IIC_DAT
44A8< 44B4<>
PMU_INT_L
28B5<> 28B8< 44B5<>
PMU_INT_NMI
28A8< 28B5<> 44C4<>
PMU_LOW_DSKTP
44B5<>
PMU_NMI
44B4<>
PMU_P64
29B2<> 44C2<>
PMU_PME_L
28B5<> 31C2< 32A8< 44B2<> 59A5>
PMU_PME_LL
31C2<>
PMU_POWER
29C3<> 44A5<> 44B1< 44C2< 44D5<>
52B3>
PMU_PRE_PLLSTOP 44B5<>
PMU_PWR_LED*
44C5<>
PMU_REQ_L
28A8< 28C3> 44C2<
PMU_RST*
8A8<> 29B3<> 44A5<> 44B5<> 59D5>
PMU_SMB_SCK
44A3<>
PMU_SMB_SDA
44A3<>
PMU_STRAP1
44C5<>
PMU_TO_INT
28C3<> 44C4<>
PMU_XI
44B5< 58A5>
PMU_XO
44B5< 58A5>
PMU_XT
44A6< 58A5>
POWERUP_OK
44B4<>
POWER_UP*
44C7<> 51A8< 59D5>
PRESPK_LOUTN
42C7<
PRESPK_LOUTP
42C7<
PRESPK_ROUTN
42C3<
PRESPK_ROUTP
42C3<
PROBE_DIV
41B4< 41D7<
PSEUDO_STAR_GND 39B7<> 40B4<
PWR_FAIL*
44B1<> 50D5<
PWR_FAILPMU*
44B4<>
PWR_FAIL_T
50D6<>
PWR_LED
51A4<
PWR_SWITCH*
8A8<> 44B1< 44C5<> 59D5> 59D5>
PWR_UP
39C8< 42D8< 50C3< 50C8< 51C6<
59D5>
PWR_UP*
50D7<>
Q1P1
51C3<
Q1P3
51D3<
Q2_GATE
42D7<
Q25_1
41A5<
Q42P4
51D3<>
QT1P1
48A4<>
QT2P1
48B4<>
QT2P3
48B4<>
R264P2
39B4<
RAM_ADDR<0>
12C3< 14B4<> 15B6<
RAM_ADDR<0..12> 53D6<
RAM_ADDR<1>
12C3< 14B6<> 15B6<
RAM_ADDR<2>
12C3< 14B4<> 15C6<

59C3>

59C3>
59C3>

59C3>
59C3>
59C3>
59B3>
59B3>

62

RAM_ADDR<3>
12D3< 14B6<> 15C4>
RAM_ADDR<4>
12D3< 14B4<> 15C6<
RAM_ADDR<5>
12C1< 14B6<> 15C6<
RAM_ADDR<6>
12D1< 14B4<> 15C4>
RAM_ADDR<7>
12D3< 14B6<> 15C6<
RAM_ADDR<8>
12D1< 14B4<> 15C4>
RAM_ADDR<9>
12C3< 14B6<> 15C6<
RAM_ADDR<10>
12C3< 14B6<> 15B4>
RAM_ADDR<11>
12B3< 14B4<> 15C4>
RAM_ADDR<12>
12D1< 14B6<> 15C4>
RAM_BA<0>
12B3< 14B6<> 15B6<
RAM_BA<0..1>
53D6<
RAM_BA<1>
12B3< 14B4<> 15B6<
RAM_CAS_L
12A2< 14B4<> 15B6< 53C6<
RAM_CKE<0>
12C1< 14B4<> 15C1<
RAM_CKE<0..1>
53C6<
RAM_CKE<1>
12B1< 14B6<> 15C1<
RAM_CKE<2>
12C1< 15B1< 15C6<
RAM_CKE<2..3>
53C6<
RAM_CKE<3>
12B1< 15A1< 15C4>
RAM_CS_L<0>
12C1< 14B6<>
RAM_CS_L<0..1>
53C6<
RAM_CS_L<1>
12C1< 14B4<>
RAM_CS_L<2>
12B1< 15B4>
RAM_CS_L<2..3>
53C6<
RAM_CS_L<3>
12B1< 15B4>
RAM_DATA_A<0>
13D7<> 14D6<>
RAM_DATA_A<0..63> 53D6<
RAM_DATA_A<1>
13D7<> 14D6<>
RAM_DATA_A<2>
13D7<> 14D6<>
RAM_DATA_A<3>
13D7<> 14D6<>
RAM_DATA_A<4>
13D7<> 14D4<>
RAM_DATA_A<5>
13D7<> 14D4<>
RAM_DATA_A<6>
13D7<> 14D4<>
RAM_DATA_A<7>
13D7<> 14D4<>
RAM_DATA_A<8>
13C7<> 14D6<>
RAM_DATA_A<9>
13C7<> 14D6<>
RAM_DATA_A<10>
13C7<> 14D6<>
RAM_DATA_A<11>
13C7<> 14D6<>
RAM_DATA_A<12>
13C7<> 14D4<>
RAM_DATA_A<13>
13C7<> 14D4<>
RAM_DATA_A<14>
13C7<> 14D4<>
RAM_DATA_A<15>
13C7<> 14D4<>
RAM_DATA_A<16>
13B5<> 14D6<>
RAM_DATA_A<17>
13B5<> 14C6<>
RAM_DATA_A<18>
13B5<> 14C6<>
RAM_DATA_A<19>
13B5<> 14C6<>
RAM_DATA_A<20>
13B5<> 14D4<>
RAM_DATA_A<21>
13B5<> 14C4<>
RAM_DATA_A<22>
13B5<> 14C4<>
RAM_DATA_A<23>
13B5<> 14C4<>
RAM_DATA_A<24>
13B5<> 14C6<>
RAM_DATA_A<25>
13B5<> 14C6<>
RAM_DATA_A<26>
13B5<> 14C6<>
RAM_DATA_A<27>
13B5<> 14C6<>
RAM_DATA_A<28>
13B5<> 14C4<>
RAM_DATA_A<29>
13B5<> 14C4<>
RAM_DATA_A<30>
13B5<> 14C4<>
RAM_DATA_A<31>
13B5<> 14C4<>
RAM_DATA_A<32>
13D4<> 14B6<>
RAM_DATA_A<33>
13D4<> 14B6<>
RAM_DATA_A<34>
13D4<> 14B6<>
RAM_DATA_A<35>
13D4<> 14B6<>
RAM_DATA_A<36>
13D4<> 14B4<>
RAM_DATA_A<37>
13D4<> 14B4<>
RAM_DATA_A<38>
13D4<> 14B4<>
RAM_DATA_A<39>
13D4<> 14B4<>
RAM_DATA_A<40>
13D4<> 14B6<>
RAM_DATA_A<41>
13C4<> 14B6<>
RAM_DATA_A<42>
13C4<> 14A6<>
RAM_DATA_A<43>
13C4<> 14A6<>
RAM_DATA_A<44>
13C4<> 14B4<>
RAM_DATA_A<45>
13C4<> 14B4<>
RAM_DATA_A<46>
13C4<> 14A4<>
RAM_DATA_A<47>
13C4<> 14A4<>
RAM_DATA_A<48>
13C2<> 14A6<>
RAM_DATA_A<49>
13C2<> 14A6<>
RAM_DATA_A<50>
13C2<> 14A6<>
RAM_DATA_A<51>
13C2<> 14A6<>
RAM_DATA_A<52>
13C2<> 14A4<>
RAM_DATA_A<53>
13C2<> 14A4<>
RAM_DATA_A<54>
13B2<> 14A4<>
RAM_DATA_A<55>
13B2<> 14A4<>
RAM_DATA_A<56>
13B2<> 14A6<>
RAM_DATA_A<57>
13B2<> 14A6<>
RAM_DATA_A<58>
13B2<> 14A6<>
RAM_DATA_A<59>
13B2<> 14A6<>
RAM_DATA_A<60>
13B2<> 14A4<>
RAM_DATA_A<61>
13B2<> 14A4<>
RAM_DATA_A<62>
13B2<> 14A4<>
RAM_DATA_A<63>
13B2<> 14A4<>
RAM_DATA_B<0>
13C7<> 15D6<
RAM_DATA_B<0..63> 53D6<
RAM_DATA_B<1>
13C7<> 15D6<
RAM_DATA_B<2>
13C7<> 15D6<
RAM_DATA_B<3>
13C7<> 15D6<
RAM_DATA_B<4>
13C7<> 15D4>
RAM_DATA_B<5>
13C7<> 15D4>
RAM_DATA_B<6>
13C7<> 15D4>
RAM_DATA_B<7>
13C7<> 15D4>
RAM_DATA_B<8>
13C7<> 15D6<
RAM_DATA_B<9>
13C7<> 15D6<
RAM_DATA_B<10>
13C7<> 15C6<
RAM_DATA_B<11>
13C7<> 15C6<
RAM_DATA_B<12>
13C7<> 15D4>
RAM_DATA_B<13>
13B7<> 15D4>
RAM_DATA_B<14>
13B7<> 15C4>
RAM_DATA_B<15>
13B7<> 15C4>
RAM_DATA_B<16>
13A5<> 15C6<
RAM_DATA_B<17>
13A5<> 15C6<

7
RAM_DATA_B<18>
RAM_DATA_B<19>
RAM_DATA_B<20>
RAM_DATA_B<21>
RAM_DATA_B<22>
RAM_DATA_B<23>
RAM_DATA_B<24>
RAM_DATA_B<25>
RAM_DATA_B<26>
RAM_DATA_B<27>
RAM_DATA_B<28>
RAM_DATA_B<29>
RAM_DATA_B<30>
RAM_DATA_B<31>
RAM_DATA_B<32>
RAM_DATA_B<33>
RAM_DATA_B<34>
RAM_DATA_B<35>
RAM_DATA_B<36>
RAM_DATA_B<37>
RAM_DATA_B<38>
RAM_DATA_B<39>
RAM_DATA_B<40>
RAM_DATA_B<41>
RAM_DATA_B<42>
RAM_DATA_B<43>
RAM_DATA_B<44>
RAM_DATA_B<45>
RAM_DATA_B<46>
RAM_DATA_B<47>
RAM_DATA_B<48>
RAM_DATA_B<49>
RAM_DATA_B<50>
RAM_DATA_B<51>
RAM_DATA_B<52>
RAM_DATA_B<53>
RAM_DATA_B<54>
RAM_DATA_B<55>
RAM_DATA_B<56>
RAM_DATA_B<57>
RAM_DATA_B<58>
RAM_DATA_B<59>
RAM_DATA_B<60>
RAM_DATA_B<61>
RAM_DATA_B<62>
RAM_DATA_B<63>
RAM_DQM_A<0>
RAM_DQM_A<0..7>
RAM_DQM_A<1>
RAM_DQM_A<2>
RAM_DQM_A<3>
RAM_DQM_A<4>
RAM_DQM_A<5>
RAM_DQM_A<6>
RAM_DQM_A<7>
RAM_DQM_B<0>
RAM_DQM_B<0..7>
RAM_DQM_B<1>
RAM_DQM_B<2>
RAM_DQM_B<3>
RAM_DQM_B<4>
RAM_DQM_B<5>
RAM_DQM_B<6>
RAM_DQM_B<7>
RAM_DQS_A<0>
RAM_DQS_A<0..7>
RAM_DQS_A<1>
RAM_DQS_A<2>
RAM_DQS_A<3>
RAM_DQS_A<4>
RAM_DQS_A<5>
RAM_DQS_A<6>
RAM_DQS_A<7>
RAM_DQS_B<0>
RAM_DQS_B<0..7>
RAM_DQS_B<1>
RAM_DQS_B<2>
RAM_DQS_B<3>
RAM_DQS_B<4>
RAM_DQS_B<5>
RAM_DQS_B<6>
RAM_DQS_B<7>
RAM_RAS_L
RAM_SA0
RAM_WE_L
RB22P2
RB27-1
RB37P1
RB160P1
RB213P2
RB227P1
REF_STAR_GND
RESET_BUTTON*
RFBA<0>
RFBA<0..11>
RFBA<1>
RFBA<2>
RFBA<3>
RFBA<4>
RFBA<5>
RFBA<6>
RFBA<7>
RFBA<8>
RFBA<9>
RFBA<10>
RFBA<11>
RFBABA<0>
RFBABA<0..1>
RFBABA<1>
RFBACAS_L

13A5<> 15C6<
13A5<> 15C6<
13A5<> 15C4>
13A5<> 15C4>
13A5<> 15C4>
13A5<> 15C4>
13A5<> 15C6<
13A5<> 15C6<
13A5<> 15C6<
13A5<> 15C6<
13A5<> 15C4>
13A5<> 15C4>
13A5<> 15C4>
13A5<> 15C4>
13C4<> 15B6<
13C4<> 15B6<
13C4<> 15B6<
13C4<> 15B6<
13C4<> 15B4>
13C4<> 15B4>
13C4<> 15B4>
13C4<> 15B4>
13C4<> 15B6<
13C4<> 15B6<
13C4<> 15A6<
13C4<> 15A6<
13C4<> 15B4>
13C4<> 15B4>
13B4<> 15A4>
13B4<> 15A4>
13B2<> 15A6<
13B2<> 15A6<
13B2<> 15A6<
13B2<> 15A6<
13B2<> 15A4>
13B2<> 15A4>
13B2<> 15A4>
13B2<> 15A4>
13B2<> 15A6<
13A2<> 15A6<
13A2<> 15A6<
13A2<> 15A6<
13A2<> 15A4>
13A2<> 15A4>
13A2<> 15A4>
13A2<> 15A4>
13D7<> 14D4<>
53D6<
13C7<> 14D4<>
13B5<> 14C4<>
13A5<> 14C4<>
13D4<> 14B4<>
13C4<> 14A4<>
13B2<> 14A4<>
13B2<> 14A4<>
13C7<> 15D4>
53D6<
13B7<> 15D4>
13A5<> 15C4>
13A5<> 15C4>
13C4<> 15B4>
13B4<> 15B4>
13B2<> 15A4>
13A2<> 15A4>
13D7<> 14C8< 14D6<>
53D6<
13C7<> 14C8< 14D6<>
13B5<> 14C6<> 14C8<
13B5<> 14C6<> 14C8<
13D4<> 14B6<> 14B8<
13C4<> 14A6<> 14B8<
13B2<> 14A6<> 14B8<
13B2<> 14A6<> 14A8<
13C7<> 15C8< 15D6<
53D6<
13B7<> 15C8< 15D6<
13A5<> 15C6< 15C8<
13A5<> 15B8< 15C6<
13C4<> 15B6< 15B8<
13B4<> 15B6< 15B8<
13B2<> 15A6< 15B8<
13A2<> 15A6< 15A8<
12A2< 14B4<> 15B4> 53C6<
15A4<
12B3< 14B6<> 15B6< 53C6<
48B3<>
48B6<
48C6<>
50A5<>
49C3<>
49C5<>
39A5<> 39A5<>
29B2<> 44C4<> 59D5>
18F2<> 20D2< 20D6<
55D3>
18F2<> 20C2< 20C6<
18F2<> 20C2< 20C6<
18F2<> 20C2< 20C6<
18F2<> 20C2< 20C6<
18F2<> 20C2< 20C6<
18E2<> 20C2< 20C6<
18E2<> 20C2< 20C6<
18E2<> 20C2< 20C6<
18E2<> 20C2< 20C6<
18E2<> 20C2< 20C6<
18E2<> 20C2< 20C6<
18E2<> 20C2< 20C6<
55D3>
18E2<> 20C2< 20C6<
18G2<> 20B2< 20B6< 55D3>

5
RFBACKE
RFBACLK0
RFBACLK0_L
RFBACLK1
RFBACLK1_L
RFBACS0_L
RFBARAS_L
RFBAWE_L
RFBBA<0>
RFBBA<0..11>
RFBBA<1>
RFBBA<2>
RFBBA<3>
RFBBA<4>
RFBBA<5>
RFBBA<6>
RFBBA<7>
RFBBA<8>
RFBBA<9>
RFBBA<10>
RFBBA<11>
RFBBBA<0>
RFBBBA<0..1>
RFBBBA<1>
RFBBCAS_L
RFBBCKE
RFBBCLK0
RFBBCLK0_L
RFBBCLK1
RFBBCLK1_L
RFBBCS0_L
RFBBRAS_L
RFBBWE_L
RFBD<0>
RFBD<0..63>
RFBD<1>
RFBD<2>
RFBD<3>
RFBD<4>
RFBD<5>
RFBD<6>
RFBD<7>
RFBD<8>
RFBD<9>
RFBD<10>
RFBD<11>
RFBD<12>
RFBD<13>
RFBD<14>
RFBD<15>
RFBD<16>
RFBD<17>
RFBD<18>
RFBD<19>
RFBD<20>
RFBD<21>
RFBD<22>
RFBD<23>
RFBD<24>
RFBD<25>
RFBD<26>
RFBD<27>
RFBD<28>
RFBD<29>
RFBD<30>
RFBD<31>
RFBD<32>
RFBD<33>
RFBD<34>
RFBD<35>
RFBD<36>
RFBD<37>
RFBD<38>
RFBD<39>
RFBD<40>
RFBD<41>
RFBD<42>
RFBD<43>
RFBD<44>
RFBD<45>
RFBD<46>
RFBD<47>
RFBD<48>
RFBD<49>
RFBD<50>
RFBD<51>
RFBD<52>
RFBD<53>
RFBD<54>
RFBD<55>
RFBD<56>
RFBD<57>
RFBD<58>
RFBD<59>
RFBD<60>
RFBD<61>
RFBD<62>
RFBD<63>
RFBD<64>
RFBD<64..127>
RFBD<65>
RFBD<66>
RFBD<67>
RFBD<68>
RFBD<69>
RFBD<70>
RFBD<71>
RFBD<72>
RFBD<73>
RFBD<74>

18D2<> 20C2< 20C6<


19C1< 20C6< 55C3>
19C1< 20C6< 55C3>
19D1< 20C2< 55C3>
19D1< 20C2< 55C3>
18F2<> 20B2< 20B6<
18G2<> 20B2< 20B6<
18F2<> 20B2< 20B6<
18C2<> 21D2< 21D6<
55C3>
18B2<> 21C2< 21C6<
18B2<> 21C2< 21C6<
18B2<> 21C2< 21C6<
18B2<> 21C2< 21C6<
18B2<> 21C2< 21C6<
18B2<> 21C2< 21C6<
18B2<> 21C2< 21C6<
18B2<> 21C2< 21C6<
18B2<> 21C2< 21C6<
18B2<> 21C2< 21C6<
18B2<> 21C2< 21C6<
18A2<> 21C2< 21C6<
55C3>
18A2<> 21C2< 21C6<
18C2<> 21B2< 21B6<
18A2<> 21C2< 21C6<
19B1< 21C6< 55B3>
19B1< 21C6< 55B3>
19C1< 21C2< 55B3>
19B1< 21C2< 55B3>
18C2<> 21B2< 21B6<
18C2<> 21B2< 21B6<
18C2<> 21B2< 21B6<
19D7< 20C5<>
55D3>
19D7< 20C5<>
19D7< 20C5<>
19D7< 20C5<>
19D7< 20C5<>
19D7< 20C5<>
19D7< 20C5<>
19D7< 20C5<>
19D7< 20C5<>
19D7< 20C5<>
19D7< 20C5<>
19D7< 20C5<>
19D7< 20C5<>
19D7< 20C5<>
19D7< 20C5<>
19D7< 20C5<>
19D7< 20C5<>
19D7< 20C5<>
19D7< 20C5<>
19C7< 20C5<>
19C7< 20C5<>
19C7< 20C5<>
19C7< 20C5<>
19C7< 20C5<>
19C7< 20C5<>
19C7< 20C5<>
19C7< 20B5<>
19C7< 20B5<>
19C7< 20B5<>
19C7< 20B5<>
19C7< 20B5<>
19C7< 20B5<>
19D4< 20C1<>
19D4< 20C1<>
19D4< 20C1<>
19D4< 20C1<>
19D4< 20C1<>
19D4< 20C1<>
19D4< 20C1<>
19D4< 20C1<>
19D4< 20C1<>
19D4< 20C1<>
19D4< 20C1<>
19D4< 20C1<>
19D4< 20C1<>
19D4< 20C1<>
19D4< 20C1<>
19D4< 20C1<>
19D4< 20C1<>
19D4< 20C1<>
19D4< 20C1<>
19C4< 20C1<>
19C4< 20C1<>
19C4< 20C1<>
19C4< 20C1<>
19C4< 20C1<>
19C4< 20C1<>
19C4< 20C1<>
19C4< 20B1<>
19C4< 20B1<>
19C4< 20B1<>
19C4< 20B1<>
19C4< 20B1<>
19C4< 20B1<>
19C7< 21C5<>
55C3>
19C7< 21C5<>
19C7< 21C5<>
19C7< 21C5<>
19C7< 21C5<>
19C7< 21C5<>
19C7< 21C5<>
19C7< 21C5<>
19C7< 21C5<>
19C7< 21C5<>
19B7< 21C5<>

55C3>

55C3>
55D3>
55D3>

55B3>
55B3>

55B3>
55B3>
55B3>

RFBD<75>
RFBD<76>
RFBD<77>
RFBD<78>
RFBD<79>
RFBD<80>
RFBD<81>
RFBD<82>
RFBD<83>
RFBD<84>
RFBD<85>
RFBD<86>
RFBD<87>
RFBD<88>
RFBD<89>
RFBD<90>
RFBD<91>
RFBD<92>
RFBD<93>
RFBD<94>
RFBD<95>
RFBD<96>
RFBD<97>
RFBD<98>
RFBD<99>
RFBD<100>
RFBD<101>
RFBD<102>
RFBD<103>
RFBD<104>
RFBD<105>
RFBD<106>
RFBD<107>
RFBD<108>
RFBD<109>
RFBD<110>
RFBD<111>
RFBD<112>
RFBD<113>
RFBD<114>
RFBD<115>
RFBD<116>
RFBD<117>
RFBD<118>
RFBD<119>
RFBD<120>
RFBD<121>
RFBD<122>
RFBD<123>
RFBD<124>
RFBD<125>
RFBD<126>
RFBD<127>
RFBDQM<0>
RFBDQM<0..7>
RFBDQM<1>
RFBDQM<2>
RFBDQM<3>
RFBDQM<4>
RFBDQM<5>
RFBDQM<6>
RFBDQM<7>
RFBDQM<8>
RFBDQM<8..15>
RFBDQM<9>
RFBDQM<10>
RFBDQM<11>
RFBDQM<12>
RFBDQM<13>
RFBDQM<14>
RFBDQM<15>
RFBDQS<0>
RFBDQS<0..7>
RFBDQS<1>
RFBDQS<2>
RFBDQS<3>
RFBDQS<4>
RFBDQS<5>
RFBDQS<6>
RFBDQS<7>
RFBDQS<8>
RFBDQS<8..15>
RFBDQS<9>
RFBDQS<10>
RFBDQS<11>
RFBDQS<12>
RFBDQS<13>
RFBDQS<14>
RFBDQS<15>
RF_CLKRUN_L
RF_DISABLE_L
RINA
RINN
RINN1
RINP
RINT_PU_RESET_L
RINT_RESET_L
RJ45_4_5
RJ45_7_8
RJ45_F_TREF
RJ45_RREF
RJ45_RXN
RJ45_RXP
RJ45_TREF
RJ45_TXN
RJ45_TXP
ROMA14
ROMA15
ROM_CS_L
ROM_OE_L

19B7< 21C5<>
19B7< 21C5<>
19B7< 21C5<>
19B7< 21C5<>
19B7< 21C5<>
19B7< 21C5<>
19B7< 21C5<>
19B7< 21C5<>
19B7< 21C5<>
19B7< 21C5<>
19B7< 21C5<>
19B7< 21C5<>
19B7< 21C5<>
19B7< 21C5<>
19B7< 21C5<>
19B7< 21B5<>
19B7< 21B5<>
19B7< 21B5<>
19B7< 21B5<>
19B7< 21B5<>
19B7< 21B5<>
19C4< 21C1<>
19C4< 21C1<>
19C4< 21C1<>
19C4< 21C1<>
19C4< 21C1<>
19C4< 21C1<>
19C4< 21C1<>
19C4< 21C1<>
19C4< 21C1<>
19C4< 21C1<>
19B4< 21C1<>
19B4< 21C1<>
19B4< 21C1<>
19B4< 21C1<>
19B4< 21C1<>
19B4< 21C1<>
19B4< 21C1<>
19B4< 21C1<>
19B4< 21C1<>
19B4< 21C1<>
19B4< 21C1<>
19B4< 21C1<>
19B4< 21C1<>
19B4< 21C1<>
19B4< 21C1<>
19B4< 21C1<>
19B4< 21B1<>
19B4< 21B1<>
19B4< 21B1<>
19B4< 21B1<>
19B4< 21B1<>
19B4< 21B1<>
18G2< 20C6<
55D3>
18G2< 20C6<
18G2< 20C6<
18G2< 20C6<
18G2< 20C2<
18G2< 20C2<
18G2< 20C2<
18G2< 20C2<
18D2< 21C6<
55C3>
18D2< 21C6<
18D2< 21C6<
18D2< 21C6<
18D2< 21C2<
18D2< 21C2<
18C2< 21C2<
18C2< 21C2<
19A6< 20C6<>
55C3>
19A6< 20C6<>
19A6< 20C6<>
19A6< 20C6<>
19A6< 20C2<>
19A6< 20C2<>
19A6< 20C2<>
19A6< 20C2<>
19A3< 21C6<>
55B3>
19A3< 21C6<>
19A3< 21C6<>
19A3< 21C6<>
19A3< 21C2<>
19A3< 21C2<>
19A3< 21C2<>
19A3< 21C2<>
31C3<> 59B5>
31C3<>
39C4< 40B2<
42C4< 43C2<
43C2<
42C4< 43D4<
34C5<
34C5<
35C1<> 57B5>
35C1<> 57B5>
35B2< 57B5>
35C2<> 57B5>
35C1<> 57B5>
35C1<> 57B5>
35C2<> 57B5>
35C1<> 57B5>
35C1<> 57B5>
18C8> 26D8<
18C8< 26D8<
30B4< 30C6< 31B4<> 59C7>
30B2< 30C6< 31B2<> 59C7>

ROM_ONBOARD_CS_L 30B2< 31B4<> 59D5>


ROM_RW_L
30B2< 30B6< 31B4<> 59B7>
ROM_WP_L
30B2< 59A7>
RT373P1
51A5<
RT401P1
47C5<>
RT406P2
47B3<>
RT418P2
50C7<
RUNLED1
51C8<
RUNSS
50C8< 50D3<
S3700P1
44A1<>
S3700P2
44A1<>
SB1P1
44A3<
SENSE+
45C6<
SENSE+_1
45B5< 45C7<
SENSE45C6< 45C8<>
SENSE-_1
45B5< 45C7<
SGRAVREF
20A3< 20C4< 20C8< 52A6>
SGRBVREF
21A3< 21C4< 21C8< 52A6>
SHS
50C7<
SI_EDGE
27C5<
SI_EXT_SWING_SET 27B3<>
SI_I2C_OFF
27C5<
SI_IDCK_M
27B5<
SI_SCA
23D2< 27C5<
SI_SCL
23D2< 27C5<
SI_TMDS_CKM
27C3<> 57C2>
SI_TMDS_CKP
27C3<> 57C2>
SI_TMDS_D0M
27C3<> 57C2>
SI_TMDS_D0P
27C3<> 57C2>
SI_TMDS_D1M
27C3<> 57C2>
SI_TMDS_D1P
27C3<> 57C2>
SI_TMDS_D2M
27C3<> 57C2>
SI_TMDS_D2P
27C3<> 57C2>
SI_VREF
27B3<
SLEEP
44B5<> 50C2< 59C5>
SLEEP1
51A8<
SLEEP2
51A7<
SLEEPLED_TERM
51A6<
SLEEP_LED_BD
51A6<
SLEEP_OFF_L
51B6< 51C7<
SLEEP_OFF_L2
39C7<
SND_AMP_MUTE_L
28C5<> 43C8<
SND_AMP_M_L
42D3< 43C7<>
SND_CLKOUT
28A1< 39B4<
SND_HP_MUTE_L
28C5<> 41A7<
SND_HP_M_L
41A7<>
SND_HP_SENSE_CONN 41A3< 41B2<>
SND_HP_SENSE_L
28B5<> 41A5< 59B7>
SND_HW_RESET_L
28A8< 28B5<> 39B4<
SND_LIN_SENSE_L 28B5<> 40D4< 59B5>
SND_SCLK
28A1< 39B1<>
SND_SPKR_ID
28B5<> 42B8<
SND_SPKR_ID_U10 42B8<
SND_SYNC
28B1< 39C1<>
SND_TO_AUDIO
28B1< 39C4<
SNF_FSEL
28C5<> 28D3<
SPDA
42B7<
SPKROUT_L_N
42A8< 42C8<
SPKROUT_L_P
42A8< 42C8<
SPKROUT_R_N
42A8< 42C1<
SPKROUT_R_P
42A8< 42C1<
SPKR_JACK_DALLAS 42A5<>
SPKR_LM
42A5<>
SPKR_LP
42A5<>
SPKR_RM
42A5<>
SPKR_RMS
42C8<
SPKR_RP
42A5<>
STBYMD
50B7<>
STOP_AGP_L
16C6<> 16D3< 17A8< 54B7<
SUPER_FLO
45C7<> 45C7<>
SW3V5V_12VIN
50C7<>
SW3V5V_INTVCC
50B5<> 50C6<>
SW3V5V_SGND
50A7<> 50A8<> 50B7<> 50B8<> 50B8<>
50C7<
SW3V5V_VIN
50C6<>
SW3VITH2R
50A8<
SW3V_3VSENSE
50B4<>
SW3V_BG2
50B6<>
SW3V_BG2R
50B5<>
SW3V_BOOST2
50B6<>
SW3V_BOOST2R
50C5<>
SW3V_ITH2
50A7< 50B6>
SW3V_RUNSS
50B6< 50C1<
SW3V_RUNSSR
50C2<
SW3V_SNSM
50B6<
SW3V_SNSP
50B6<
SW3V_SW2
50B6<> 50C4<>
SW3V_SW2A
50B3<>
SW3V_TG2
50B6<>
SW3V_TG2R
50C5<>
SW3V_VOSNS
50B6<>
SW5VITH1R
50B8<
SW5V_5VSENSE
50A4<>
SW5V_BG1
50A5< 50B7<>
SW5V_BG1R
50A5<>
SW5V_BOOST1
50A5< 50B7<>
SW5V_ITH1
50B7<>
SW5V_RUNSS
50B8< 50D1<
SW5V_SNSM
50A5< 50B7<
SW5V_SNSMA
50A4<>
SW5V_SNSP
50A5< 50B7<
SW5V_SW1
50A5<> 50A5<> 50B7<>
SW5V_SW1A
50A3<>
SW5V_TG1
50B5< 50B7>
SW5V_TG1R
50B4<>
SW5V_VOSNS
50B7<>
SW12V_SL
51C7<
SW12V_SLEEP
51D7<>
SWITCH5V_3
51B6<
SWITCH5V_4
51B6<>

1
SWITCH5V_5
51B3<
SWITCH5V_6
51B2<>
SYSCLK_CPU
4D2< 9A4< 56C3>
SYSCLK_CPU_UF
9A3<> 56C3>
SYSCLK_DDRCLK_A0 12C4< 14D6<> 53C6<
SYSCLK_DDRCLK_A0_L 12C4< 14D6<> 53C6<
SYSCLK_DDRCLK_A0_L_UF 12B6<> 53C6<
SYSCLK_DDRCLK_A0_UF 12B6<> 53C6<
SYSCLK_DDRCLK_A1 12C4< 14A4<> 53C6<
SYSCLK_DDRCLK_A1_L 12B4< 14A4<> 53C6<
SYSCLK_DDRCLK_A1_L_UF 12B6<> 53C6<
SYSCLK_DDRCLK_A1_UF 12B6<> 53C6<
SYSCLK_DDRCLK_A2_L 53B6<
SYSCLK_DDRCLK_A2_L_UF 12B6<> 53B6<
SYSCLK_DDRCLK_A2_UF 12B6<> 53C6<
SYSCLK_DDRCLK_B0 12B4< 15B4> 53B6<
SYSCLK_DDRCLK_B0_L 12B4< 15B3> 53B6<
SYSCLK_DDRCLK_B0_L_UF 12B6<> 53B6<
SYSCLK_DDRCLK_B0_UF 12B6<> 53B6<
SYSCLK_DDRCLK_B1 12A4< 15D6< 53B6<
SYSCLK_DDRCLK_B1_L 12A4< 15C6< 53B6<
SYSCLK_DDRCLK_B1_L_UF 12B6<> 53B6<
SYSCLK_DDRCLK_B1_UF 12B6<> 53B6<
SYSCLK_DDRCLK_B2 12A4< 15A6< 53B6<
SYSCLK_DDRCLK_B2_L 12A4< 15A6< 53B6<
SYSCLK_DDRCLK_B2_L_UF 12B6<> 53B6<
SYSCLK_DDRCLK_B2_UF 12B6<> 53B6<
SYSCLK_LA
8A2< 8D8<> 56B3>
SYSTEM_CLK_EN
28A5< 44C4<>
TAS_DVDD
39D3<
TAS_PWR_DOWN
39B4< 39D7<
TAS_STAR_GND
39A7<> 39D2<
TAS_VCOM
39B1<> 39B1<> 43D5<
TCKM
24C3<> 57C5>
TCKP
24C4<> 57C5>
TD0M
24C4<> 57C5>
TD0P
24C3<> 57C5>
TD1M
24C3<> 57C5>
TD1P
24C4<> 57C5>
TD2M
24C4<> 57C5>
TD2P
24C3<> 57C5>
TESTEN
35A5< 35C4<
TI_MODE_OUT
42D4<>
TI_MODE_OUT_2
42C7<
TI_SD*
42D5<
TMDS_CKM
23D1< 24A7<> 27C2< 57D2>
TMDS_CKP
23D1< 24B7<> 27C2< 57D2>
TMDS_D0M
23D1< 24B7<> 27C2< 57D2>
TMDS_D0P
23D1< 24B7<> 27C2< 57D2>
TMDS_D1M
23D1< 24C7<> 27C2< 57D2>
TMDS_D1P
23D1< 24C7<> 27C2< 57D2>
TMDS_D2M
23D1< 24D7<> 27C2< 57D2>
TMDS_D2P
23D1< 24D7<> 27C2< 57D2>
TMDS_DDC_CLK
24B3<> 59C5>
TMDS_DDC_DAT
24B4<> 59C5>
TMDS_EN
23D7<> 51B1<>
TPA_5V
42D4<
TPA_AVDD_REF
42D4<
TPA_BSLN
42D5<>
TPA_BSLP
42D5<>
TPA_BSRN
42D4<>
TPA_BSRP
42D4<>
TPA_COSC
42C4<>
TPA_LOUTN
42C5<>
TPA_LOUTP
42C5<>
TPA_MODE
42D4<
TPA_ROSC
42C4<>
TPA_ROUTN
42C4<>
TPA_ROUTP
42C4<>
TPA_V2P5
42D5<
TPA_VCLAMPL
42C5<
TPA_VCLAMPR
42C4<
TPA_VOL
42D5<
TRANS_ADJ
45B3<
T_UD_IDEDD_0
37C1< 38C3<> 58C2>
T_UD_IDEDD_1
37C1< 38C3<> 58C2>
T_UD_IDEDD_2
37C1< 38C3<> 58C2>
T_UD_IDEDD_3
37C1< 38C3<> 58C2>
T_UD_IDEDD_4
37B1< 38C3<> 58C2>
T_UD_IDEDD_5
37B1< 38C3<> 58C2>
T_UD_IDEDD_6
37B1< 38C3<> 58B2>
T_UD_IDEDD_7
37B1< 38C3<> 58B2>
T_UD_IDEDD_8
37B1< 38C2<> 58B2>
T_UD_IDEDD_9
37B1< 38C2<> 58B2>
T_UD_IDEDD_10
37B1< 38C2<> 58B2>
T_UD_IDEDD_11
37B1< 38C2<> 58B2>
T_UD_IDEDD_12
37B1< 38C2<> 58B2>
T_UD_IDEDD_13
37A1< 38C2<> 58B2>
T_UD_IDEDD_14
37A1< 38C2<> 58B2>
T_UD_IDEDD_15
37A1< 38C2<> 58B2>
U5_SDOUT
39C3<>
U10_A
42C7<
U10_OUT
42C7> 42D8<
U22_8
36D8<
U4202P2
40C3<
U4202P3
40C3<
U4202P5
40B3<
U4202P6
40B3<
U4202P7
40B3<>
UATA0IRQ
38C6<> 58D5>
UATAD<0>
37C4< 38C6<>
UATAD<0..15>
58D5>
UATAD<1>
37C4< 38C6<>
UATAD<2>
37C4< 38C6<>
UATAD<3>
37C4< 38C6<>
UATAD<4>
37B4< 38C6<>
UATAD<5>
37B4< 38C6<>
UATAD<6>
37B4< 38C6<>
UATAD<7>
37B4< 38C6<>
UATAD<8>
37B4< 38C6<>

C
59A7>
59A7>
59A7>
59B7>
59B7>
59B7>
59B7>
59B7>

63

UATAD<9>
37B4< 38C6<>
UATAD<10>
37B4< 38C6<>
UATAD<11>
37B4< 38C6<>
UATAD<12>
37B4< 38C6<>
UATAD<13>
37A4< 38C6<>
UATAD<14>
37A4< 38C6<>
UATAD<15>
37A4< 38C6<>
UIDE_ADDR<0>
37C7<> 38B4<
UIDE_ADDR<0..2> 58B5>
UIDE_ADDR<1>
37C7<> 38B4<
UIDE_ADDR<2>
37C7<> 38A4<
UIDE_CS1FX_L
37C7<> 38B4< 58B5>
UIDE_CS3FX_L
37C7<> 38B4< 58B5>
UIDE_CSELP_L
38C2<> 52A8>
UIDE_DATA<0>
37C3< 37D7<>
UIDE_DATA<0..15> 58C5>
UIDE_DATA<1>
37C3< 37D7<>
UIDE_DATA<2>
37C3< 37D7<>
UIDE_DATA<3>
37C3< 37D7<>
UIDE_DATA<4>
37B3< 37D7<>
UIDE_DATA<5>
37B3< 37D7<>
UIDE_DATA<6>
37B3< 37D7<>
UIDE_DATA<7>
37B3< 37D7<>
UIDE_DATA<8>
37B3< 37D7<>
UIDE_DATA<9>
37B3< 37D7<>
UIDE_DATA<10>
37B3< 37C7<>
UIDE_DATA<11>
37B3< 37C7<>
UIDE_DATA<12>
37B3< 37C7<>
UIDE_DATA<13>
37A3< 37C7<>
UIDE_DATA<14>
37A3< 37C7<>
UIDE_DATA<15>
37A3< 37C7<>
UIDE_DIOR_L
37C7<> 37D3< 58C5>
UIDE_DIOW_L
37C3< 37C7<> 58C5>
UIDE_DMACK_L
37C7<> 37D3< 58C5>
UIDE_DMARQ
37C7<> 38C4< 58C5>
UIDE_INTRQ
37C7< 38C4< 58C5>
UIDE_IOCHRDY
37C3< 37C7< 58C5>
UIDE_PDIAG
38C2<>
UIDE_REF
37C7<>
UIDE_RST_L
37C7<> 37D3< 58C5>
UNUSED_ATAIOCS16_L 38C2<> 52A8>
UNUSED_EXTINT7
28B5<> 28B8<>
UNUSED_EXTINT8
28B5<> 28B8<>
UNUSED_GPIO15
28B5<> 28C1< 59A5>
USB2_CRUN_L
32A6<>
USB2_CRUN_L_INT 28A8< 28B5<> 32A8<
USB2_DAN_F
32C1<> 33B7< 56B3>
USB2_DAP_F
32C1<> 33B7< 56B3>
USB2_DBN_F
32C1<> 33C7< 56B3>
USB2_DBP_F
32C1<> 33C7< 56B3>
USB2_DCN_F
32C1<> 33D7< 56B3>
USB2_DCP_F
32C1<> 33D7< 56B3>
USB2_IDSEL
32B6<
USB2_NC1
32B4<>
USB2_NC2
32B4<>
USB2_PME_L
32A6<>
USB2_RREF
32B4<> 56B3>
USB2_RSDAM
32C4<> 56B3>
USB2_RSDAP
32C4<> 56B3>
USB2_RSDBM
32C4<> 56B3>
USB2_RSDBP
32C4<> 56B3>
USB2_RSDCM
32C4<> 56B3>
USB2_RSDCP
32C4<> 56B3>
USB2_VCCRST
32A6<
USB2_XT1
32C4< 56B3>
USB2_XT2
32C4<> 56B3>
USB2_XT2_B
56B3>
USBT_DAN_F
33B6<> 56B3>
USBT_DAP_F
33B6<> 56B3>
USBT_DBN_F
33C6<> 56A3>
USBT_DBP_F
33C6<> 56A3>
USBT_DCN_F
33D6<> 56A3>
USBT_DCP_F
33D6<> 56A3>
USB_DAN
28A3< 28B3<> 58B5>
USB_DAN_CON
33C3<> 56A3> 59C5>
USB_DAN_F
28B2< 33B7< 58B5>
USB_DAP
28A3< 28B3<> 58B5>
USB_DAP_CON
33C3<> 56A3> 59C5>
USB_DAP_F
28B2< 33B7< 58B5>
USB_DBN
28A3< 28B3<> 58B5>
USB_DBN_CON
33B3<> 56A3> 59C5>
USB_DBN_F
28B2< 33C7< 58B5>
USB_DBP
28A3< 28B3<> 58B5>
USB_DBP_CON
33B3<> 56A3> 59C5>
USB_DBP_F
28B2< 33C7< 58B5>
USB_DCN
28A3< 28B3<> 58B5>
USB_DCN_CON
33D3<> 56A3> 59C5>
USB_DCN_F
28B2< 33D7< 58B5>
USB_DCP
28A3< 28B3<> 58B5>
USB_DCP_CON
33D3<> 56A3> 59C5>
USB_DCP_F
28B2< 33D7< 58B5>
USB_DDN
28B3<>
USB_DDN_F_TERM
28B2<
USB_DDP
28B3<>
USB_DDP_F_TERM
28B2<
USB_DEN
28B3<> 58B5>
USB_DEP
28B3<> 58B5>
USB_DFN
28B3<> 58A5>
USB_DFP
28B3<> 58A5>
USB_GND
52A3>
USB_OC_EF_L
28B3< 28C2<
USB_PORT_PWR
33A4<> 33B3<> 33C3<> 33D3<> 52A3>
59B5>
USB_PWR
25B5<> 25C2< 25D3<> 33A6<> 52A3>
USB_PWREN_AB_L
28B3<> 28C2<
USB_PWREN_CD_L
28B3<> 28C2<
USB_PWREN_EF_L
28B3<> 28C2<
USB_PWR_EN
33A8<>
USB_PWR_FLT*
28B3< 28C1< 32B1< 33A7>
UX6P23
39C4<

7
UX6_LINB
U_USB_PWR_FLT*
VCOML
VCOMR
VCOREIN
VCORE_BG
VCORE_BG_1
VCORE_BOOST
VCORE_BOOST2
VCORE_BOOST2_1
VCORE_BOOST_1
VCORE_EXTVCC
VCORE_FREQSET
VCORE_INTVCC
VCORE_SEN+
VCORE_SEN+_1
VCORE_SENA+
VCORE_SF
VCORE_SGND

39C4<
32B4<
43D5<
43D5<
45D6<>
45C6<>
45B5< 45C7<>
45C5<>
45C6<>
45B5< 45C7<>
45B5<>
45D7<
45C7<
45C5<> 45D5<> 45D7<>
45C3<>
45A3<>
45C3<>
45C8<
45B7<> 45C7<> 45C7<> 45C8<> 45C8<>

VCORE_STBY
VCORE_TG
VCORE_TG_1
VCORE_VGATE
VCORE_VIN
VC_CNTL1
VC_SENA
VGA_IIC_CLK
VGA_IIC_DAT
VGER_INV_HRESET
VIPCLK
VIPD0
VIPD1
VIPD2
VIPD3
VIPD4
VIPD5
VIPD6
VIPD7
VIPHAD0
VIPHAD1
VIPHCTL
VIP_PD
VIP_PU
VOSNS1
VOSNS2
VR4210P1
VREFM
VREFP
VRFILT
VSYNC*
WL_PCI_IDSEL
XMIT_LED
ZT8P1
ZT9P1
ZT10P1
ZT11P1

45C7<>
45C6<>
45B5< 45C7>
28B5<> 28D3<
45D7<>
44C7< 45D8<
45B3<>
25C4<> 59B5>
25C4<> 59B5>
7A3< 7B3< 7B3< 7C3< 44D1>
22D4< 52A8>
22D4<> 26B7<
22D4<> 26B7<
22D4<> 26B8<
22D4<> 26D7<
22D4<> 26D7<
22D4<> 26D7<
22D4<> 26B8<
22D4<> 26C5<
22D5<> 26B7<
22D5<> 26B7<
22D5<> 26D5<
22D4<
22D4<
50B8<>
50B5<>
39B7<
39B4<
39B4< 43A3<
39B3<>
22C5<> 57D5>
31C2<> 59A5>
35A2< 35B4<>
4A1<>
4B2<>
4A2<>
4B1<>

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6569

D
SCALE

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

64

OF

A
69

8
*** Part Cross-Reference for the entire design ***

BS1
BS2
BS3
BS4
BT1
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
C71
C72
C73
C74
C75
C76
C77
C78
C79
C80
C81
C82
C83
C84
C85
C86
C87
C88
C89
C90
C91
C92
C93
C94
C95
C96
C97
C98
C99
C100
C101
C102
C103

PCB_STANDOFF 29B5
PCB_STANDOFF 29B6
PCB_STANDOFF 29D1
PCB_STANDOFF 29D1
BATTERY
44D6
CAP
33C4
CAP
33D4
CAP
35B1
CAP
36B6
CAP_P
33A5
CAP
33B4
CAP_P
33A5
CAP
21A4
CAP
21A4
CAP_P
36D7
CAP
21A4
CAP_P
36D7
CAP_P
41C4
CAP
12A7
CAP
21D2
CAP
21B4
CAP
21D5
CAP
51D3
CAP_P
51D4
CAP
21B2
CAP
21D5
CAP
21B4
CAP
21B4
CAP_P
40B4
CAP_P
40C4
CAP_P
41D4
CAP
36D8
CAP
21B1
CAP
21B3
CAP
12A6
CAP
21B2
CAP
21D4
CAP
21B2
CAP
21B3
CAP
43B5
CAP
42D7
CAP
35D7
CAP
21D2
CAP
21D5
CAP
21B3
CAP
35D8
CAP
36B8
CAP
41D6
CAP
35D4
CAP
42B8
CAP
14D8
CAP
14D8
CAP
15D8
CAP
15D8
CAP
15D7
CAP
15C3
CAP
35D4
CAP
35D5
CAP
18B8
CAP
15C1
CAP
35D4
CAP
35D6
CAP
15B1
CAP_P
48B2
CAP
41C6
CAP
18B6
CAP
18D6
CAP
40B2
CAP
40C2
CAP
35D7
CAP
35D7
CAP
35D5
CAP
35D6
CAP
18B5
CAP
18B6
CAP_P
48B1
CAP
18H7
CAP
18H7
CAP
35B7
CAP
18H5
CAP
35B7
CAP
32D3
CAP
18H6
CAP
18H4
CAP
18H2
CAP
18H7
CAP
18H4
CAP
18H3
CAP
18H8
CAP_P
39C6
CAP
18H8
CAP
17B2
CAP_P
48B1
CAP
18H2
CAP
18H7
CAP
17B3
CAP
34B6
CAP
17C3
CAP
17C3
CAP
18H5
CAP
18H2
CAP
17B3
CAP
18H6
CAP
17D1
CAP
17D3
CAP
17D2
CAP
17C2
CAP
17D2

7
C104
C105
C106
C107
C108
C109
C110
C111
C112
C113
C114
C115
C116
C117
C118
C119
C120
C121
C122
C123
C124
C125
C126
C127
C128
C129
C130
C131
C132
C133
C134
C135
C136
C137
C138
C139
C140
C141
C142
C143
C144
C145
C146
C147
C148
C149
C150
C151
C152
C153
C154
C155
C156
C157
C158
C159
C160
C161
C162
C163
C164
C165
C166
C167
C168
C169
C170
C171
C172
C173
C174
C175
C176
C177
C178
C179
C180
C181
C182
C183
C184
C185
C186
C187
C188
C189
C190
C191
C192
C193
C194
C195
C196
C197
C198
C199
C200
C201
C202
C203
C204
C205
C206
C207
C208
C209
C212
C213
C214
C215

CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP_P
CAP
CAP
CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP

17D4
17B2
48B2
24B2
42B7
17D3
17D2
17B3
17B2
27D5
32D3
18H3
17B3
17D3
17C3
23B5
17C3
39C4
42C8
30C3
18H1
23B6
39C7
39B2
22D3
17B3
23B6
23B4
48B2
18H6
17D3
17C2
17B3
17B4
46B4
17D1
17C2
20B3
20D5
20D5
20D5
18H2
17D1
17C3
17C4
17C3
17C3
17C2
23B5
22C7
42C8
42C1
42C1
20A4
20D5
18H5
23C6
17C4
22C6
22C6
22C6
20B3
20B3
18H5
17C3
17C2
22C7
46A6
20A4
20B2
20B4
18H3
17D2
17B4
17D4
17B3
17D3
17B2
17B1
17D2
17B2
17D3
17B4
17B3
17B1
23C7
22C7
20A5
17D4
17B5
20B4
20B1
20B2
20B2
20B4
18H3
17D4
17D4
17D3
17D2
40C5
20D2
22C2
22C7
41A5
22B6
22D6
22D6
17B3
17A3

C216
C217
C218
C219
C220
C222
C223
C224
C225
C226
C227
C228
C229
C230
C231
C232
C233
C234
C235
C236
C238
C239
C240
C241
C242
C243
C244
C245
C246
C248
C249
C250
C252
C254
C255
C256
C257
C258
C259
C260
C261
C262
C263
C264
C265
C266
C267
C269
C270
C271
C272
C273
C275
C276
C277
C278
C279
C280
C281
C282
C283
C284
C285
C286
C287
C288
C289
C290
C291
C292
C293
C294
C295
C296
C297
C298
C299
C300
C301
C302
C303
C304
C305
C306
C307
C308
C309
C310
C311
C312
C313
C314
C315
C316
C317
C318
C319
C320
C321
C322
C323
C324
C325
C326
C327
C328
C329
C330
C331
C332

CAP
CAP
CAP_P
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP_P
CAP
CAP
CAP
CAP_P
CAP_P
CAP_P
CAP
CAP
CAP
CAP_P
CAP_P
CAP_P
CAP_P
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP_P
CAP
CAP_P
CAP_P
CAP_P
CAP
CAP_P
CAP_P
CAP_P

20D2
17C1
49B3
17C2
48C8
16A8
17C2
22C2
30C2
22D6
22C3
22C3
28C6
13D7
11A6
11A6
28D6
28D7
49B2
51B3
51C5
44A4
11C8
50C5
14C2
14C2
14C3
44D5
51B3
39B4
31D1
31D2
51B2
51B1
14C2
14C1
51B2
51B2
31D1
31D2
14C1
47B4
14C2
11C4
47B3
47B8
44D6
51D6
47A5
11C8
27D4
47C5
14C2
14C2
11C8
11C6
11C5
11C6
11C6
47B6
47C7
47B4
47B7
47B7
50A2
11D8
11D8
11D8
11D8
11D4
50A1
50A1
50C5
47B3
47C4
47C5
47C4
47C3
47C4
50A2
50C2
14C2
47C4
50A2
50A2
50A3
50A3
50A2
14C1
29D3
14C3
29D3
50A8
50A8
50B8
50B8
14A7
14C2
50B7
50A7
49B2
49B2
27D4
50B2
50B2
50B2
49B3
49B2
49B2
49B2

C333
C334
C335
C336
C337
C338
C339
C340
C341
C342
C343
C344
C345
C346
C347
C348
C349
C350
C351
C352
C353
C354
C355
C356
C357
C358
C359
C360
C361
C362
C363
C364
C365
C366
C367
C368
C369
C370
C371
C372
C373
C374
C375
C376
C377
C378
C379
C380
C381
C382
C383
C384
C385
C386
C387
C388
C389
C390
C391
C392
C393
C394
C395
C396
C397
C398
C399
C400
C401
C403
C404
C405
C406
C407
C408
C409
C410
C411
C412
C413
C414
C415
C416
C417
C418
C420
C421
C422
C423
C424
C427
C428
C431
C432
C433
C434
C436
C437
C438
C439
C440
C441
C442
C443
C444
C445
C446
C447
C449
C450

CAP
CAP_P
CAP_P
CAP_P
CAP_P
CAP_P
CAP_P
CAP_P
CAP
CAP_P
CAP_P
CAP
CAP
CAP_P
CAP_P
CAP_P
CAP_P
CAP
CAP_P
CAP
CAP
CAP_P
CAP_P
CAP_P
CAP_P
CAP
CAP
CAP
CAP_P
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP

C451
C452
C453
C454
C455
C456
C457
C458
C460
C461
C462
C463
C464
C466
C467
C468
C469
C470
C471
C472
C473
C475
C476
C477
C478
C479
C480
C481
C482
C483
C484
C485
C486
C487
C488
C489
C490
C492
C493
C494
C495
C496
C499
C500
C503
C504
C505
C506
C507
C508
C509
C510
C511
C512
C513
C514
C515
C516
C517
C518
C519
C520
C521
C522
C523
C524
C525
C526
C527
C528
C529
C530
C531
C532
C533
C534
C535
C536
C537
C538
C539
C540
C541
C542
C543
C544
C545
C546
C547
C548
C549
C550
C551
C552
C553
C554
C555
C556
C557
C558
C559
C562
C563
C564
C565
C566
C567
C568
C569
C570

50B6
45C1
45C2
45C2
45C2
50D6
50D6
45C2
50B7
49C3
45D3
50B4
4B1
45B1
45B2
45B2
50D6
8D4
49C3
4B1
8D4
50D3
50D3
50D3
45D3
49C4
49B7
27D4
45B2
45B2
46C4
8C1
46C6
27D4
45B6
22B6
4A1
4A1
45C5
45B7
45C8
45B5
36C1
36D3
33A4
36C1
36C2
33C4
36D3
33A4
33C4
36C2
33B4
33C3
33C4
42A5
33B4
36A6
33B4
36A6
36A6
36A6
36A6
33A5
33D4
33B3
36A7
35C1
35D1
33D4
33D4
33D3
36B6
36A6
41B3
25B3
36D4
36A7
41C3
33D3
25B4
25A4
25A4
33B3
36D4
41D3
25D4
25C4
25C3
36B6
41B3
36B7
40B6
25B3
33C3
35D3
41A4
40C6
35D3
36B4
36B4
36C4
36C5
36B2
36B2
36C3
36C3
40B6
27D4
36B3

CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP_P
CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP

36B2
36B4
41B4
40C6
36B4
36B3
36B4
36B3
21D2
21B7
21B8
36B4
36B4
21B7
21D8
36B1
21B7
21B8
36B4
36B1
51D2
21B6
21B6
36C7
43A5
40C4
40B4
36B3
36B3
36B3
36B5
36B1
21B6
21D7
21B7
21B5
36B6
21D1
21D7
21D7
36B2
36B2
41D6
36C7
41C6
41B7
40D3
40C3
40B3
41C6
18B8
18B8
32D5
41B7
40B3
40C3
32C8
32D8
32C8
41B7
32D8
20D2
20D2
32D8
32D8
41C7
41D7
32D5
32D8
48B3
32D5
32C7
32C7
20D7
20D7
20B6
20B6
32C8
32D7
39D6
39B7
20D8
32D8
43B4
48B3
20D7
20B7
32D8
32D7
32D8
39D7
43A3
43B3
48B6
20B6
20B7
32D7
43B3
27D4
48B2
32D8
15D3
48B6
48C2
20B5
20B7
20B7
20B8
20B8
32C8

1
C572
C573
C574
C576
C578
C579
C580
C581
C582
C583
C584
C585
C586
C587
C588
C589
C591
C592
C593
C594
C595
C596
C597
C598
C599
C600
C601
C602
C603
C604
C605
C606
C607
C608
C609
C610
C611
C612
C613
C614
C615
C616
C617
C618
C619
C620
C621
C622
C623
C624
C625
C626
C627
C628
C629
C630
C631
C632
C633
C634
C635
C636
C637
C638
C639
C640
C641
C642
C643
C644
C645
C646
C647
C648
C649
C650
C651
C652
C653
C654
C655
C656
C657
C658
C659
C660
C661
C662
C663
C664
C665
C666
C667
C668
C669
C670
C671
C672
C673
C674
C675
C676
C677
C678
C679
C680
C681
C682
C683
C684

CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP

48B7
32C8
32C8
48C3
39C5
39C5
39B2
39B2
42B7
27D3
39D3
48B5
48A4
39B2
39B5
48C5
39D2
39B5
15D2
39B5
39B5
48C6
39C4
8B2
39D4
39D4
29A5
15D2
16A8
29A7
22C2
22C2
22C1
29A6
29A4
24A3
13D7
13D6
13D6
29A6
29A4
22A2
22A3
23A6
29C7
29C7
29D7
29D7
28D7
15D2
29A7
23A6
29A6
11A6
29A5
29A6
48C7
48C7
48C7
48C7
23A6
23A8
11C4
11A6
29A4
29A3
11C8
43B7
11C2
11B2
11B1
11B1
11A5
11A5
11A4
11A6
11A3
24B2
51B4
51B4
11C4
11C2
11B3
11B2
11B3
11B1
11A6
11A6
11A4
11A3
11A4
11A4
11A4
11B5
13C5
13C5
13C5
15D1
11B2
11A5
43A7
11B3
11B1
11B3
11B1
11C3
11B3
11B3
11A4
11A5

65

C685
C686
C687
C688
C689
C690
C691
C692
C693
C694
C695
C696
C697
C698
C699
C700
C701
C702
C703
C704
C705
C706
C707
C708
C709
C710
C711
C712
C713
C714
C715
C716
C717
C718
C719
C720
C721
C722
C723
C724
C725
C726
C727
C728
C729
C730
C731
C732
C733
C734
C735
C736
C741
C742
C743
C744
C745
C746
C747
C748
C749
C750
C751
C752
C753
C754
C755
C759
C760
C761
C762
C763
C764
C765
C766
C767
C768
C773
C774
C775
C776
C777
C778
C779
C780
C781
C782
C783
C784
C785
C786
C787
C788
C789
C790
C791
C792
C793
C794
C795
C796
C797
C798
C799
C800
C801
C802
C803
C805
C806

CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP

11A5
11A5
11B6
11C7
11C1
11B2
11C2
28D6
11A6
11A4
11A4
11A4
11A6
11C5
11B7
11C7
44B2
11D4
28D6
28D5
44A6
44A6
11B3
11B3
11A5
11A5
11A5
11B1
28D5
11B5
44B2
11B2
11C3
11B1
11D2
11C3
11D3
11B7
11B6
11B5
11C7
15D3
11D4
11C3
11B3
11D3
11D1
11D1
11A6
11D2
11B7
11B5
15D3
51C6
11B3
11B1
11C3
11D3
11D1
11D2
11D3
11B6
11B7
11B6
11B6
11B5
11B6
44D5
16D6
11B3
11C1
11D2
11D3
11D3
11D1
11C6
11B6
51C6
11C1
11C3
11B2
11C1
22B6
11D1
11D2
11B5
11B7
44D5
28A6
28C3
27D3
11D3
11D3
11D3
11D1
11B6
11B6
11C6
11C5
28C3
11C3
11D3
11D1
11D1
11D2
11B7
11B5
11B6
11B2
11C2

7
C807
C808
C809
C810
C811
C812
C813
C814
C815
C816
C817
C818
C819
C820
C821
C822
C823
C824
C825
C826
C827
C828
C829
C830
C831
C832
C833
C834
C835
C836
C837
C838
C839
C840
C841
C842
C843
C844
C845
C846
C848
C849
C850
C851
C852
C854
C855
C856
C857
C858
C859
C860
C861
C862
C863
C864
C865
C866
C867
C868
C869
C870
C871
C872
C873
C874
C875
C876
C877
C878
C879
C880
C881
C882
C883
C884
C885
C886
C887
C888
C889
C890
C891
C892
C893
C894
C895
C896
C897
C898
C899
C900
C901
C902
C903
C904
C908
C909
C910
C911
C914
C915
C917
C918
C919
C920
C921
C922
C923
C924

CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP

C925
C926
C927
C928
C929
C930
C931
C932
C933
C934
C935
C936
C937
C938
C939
C940
C941
C943
C944
C945
C947
C948
C949
C950
C951
C952
C953
C954
C955
C956
C957
C958
C959
C960
C961
C962
C963
C964
C965
C966
C967
C968
C969
C970
C971
C972
C973
C974
C975
C976
C977
C978
C979
C980
C981
C982
C983
C984
C985
C986
C987
C988
C989
C990
C991
C992
C993
C994
C995
C996
C997
C998
C999
C1000
C1001
C1002
C1003
C1004
C1005
C1006
C1007
C1008
C1009
C1010
C1011
C1012
C1013
C1014
C1015
C1016
C1017
C1018
C1019
C1020
C1021
C1022
C1023
C1024
C1025
C1026
C1027
C1028
C1029
C1030
C1031
C1032
C1033
C1034
C1035
C1036

11B2
11D2
11C3
11D2
11D2
11C2
11B5
11B6
11C6
11B6
11C6
11B5
15D3
28C3
11C1
11C1
11D7
11D6
11B7
11B7
11C5
11C1
11C2
11C3
11D3
11D7
11D3
11D6
11B3
11C6
11C7
11B7
11C6
28A6
11D4
11D6
11C7
11D6
11D6
11D7
30D5
11C6
11B3
11B3
11B2
9D3
11C5
11B7
11C6
13D4
13D3
13D4
44A1
44B7
11C2
15D2
11B1
11C3
11C3
11C2
11D5
11D6
11D6
11D5
11D5
11D5
11B3
11C5
11C7
11C7
11B2
11C5
11B3
11B1
11B2
11D6
11D7
11D5
11D7
11D6
11D6
11D7
11D6
11C4
11C1
11C2
11D5
11D5
11D6
11D5
11D5
11D7
11D7
11C7
11B2
11C6
13C2
13C2
13C1
37C2
15D2
51D7
37C5
51D6
38C7
38C1
38C5
15D2
38B5
38B7

CAP
CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP

C1037
C1038
C1039
C1040
C1041
C1042
C1043
C1044
C1045
C1046
C1047
C1048
C1049
C1050
C1051
C1052
C1053
C1054
C1055
C1056
C1057
C1058
C1059
C1060
C1061
C1062
C1063
C1064
C1065
C1066
C1067
C1068
C1069
C1070
C1071
C1072
C1073
C1074
C1075
C1076
C1077
C1078
C1079
C1080
C1081
C1082
C1083
C1084
C1085
C1086
C1087
C1088
C1089
C1090
C1091
C1092
C1093
C1094
C1095
C1096
C1097
C1098
C1099
C1100
C1101
C1102
C1103
C1401
C1402
C1403
C1404
C1405
C1406
C1407
C1408
C1409
C1410
C1411
C1412
C1413
C1414
C1415
C1416
C1417
C1418
C1419
C1420
C1421
C1501
C1502
C1503
C1504
C1505
C1506
C1507
C1508
C1509
C1510
C1511
C1512
C1513
C1514
C1515
C1601
C1602
C1702
C1801
C1802
C1901
C1902

15D3
50C1
50B1
47B4
14A7
50B8
50B5
50A5
50A6
50B1
47B3
15D3
50C7
50A4
50A6
50A5
50C5
15A3
45D3
15A2
45C1
49B4
45C5
45D4
45D4
45D4
45D4
4C2
50D3
50D4
45B1
8D4
49C4
45B2
8C2
49C3
45D4
45D4
45D4
45D4
8C1
49C4
8D4
50D4
50D4
8D2
8D1
8D1
49C4
8C1
8D1
50D4
50D4
8D2
8D2
8D2
8D3
27D3
50D3
50D4
8D2
8D3
49C3
8D1
8D1
8D3
8D1
8C2
8D2
8A7
8A6
8D2
8D1
49B6
8A6
8A7
8D1
49B6
49C4
45C2
8C2
8B6
8A7
8B6
8B6
8A7
8D2
8D2
49B7
8C1
8A6
8A6
49C6
8C1
8C1
8B7
8A6
8A6
8B6
8D2
8B7
8A6
45B4
45B2
8A6
8C2
8C1
45B2
4D3
4D3

5
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP

8C1
45B4
45C5
8C2
8D3
8C1
8D2
45D7
45B7
45C1
45D5
45C2
45B7
45C7
45B6
45C8
46A7
8B2
8B2
8B1
8B1
8B1
42C7
42C6
42A8
42A7
42C6
42C6
42A7
42C6
42A6
42D6
42D4
42C4
42C4
42C3
42C3
42C3
42C2
43D5
43D5
43D5
43D5
42B3
42A3
42B2
42B2
42B2
42B2
42A2
43D2
43D2
42B2
42B2
42B2
42B2
42A2
43C2
43D2
8A7
8A7
8B5
42C7
42C2
9D3
42B3
22B5
14D7
14D2
14C1
14C1
14C1
14C3
14C2
14C2
14C2
14C2
14C1
14C1
14C1
14B1
14C3
14C2
14C2
14C2
14C2
14C1
14C1
15D7
15D1
15D1
15D3
15D3
15D3
15D2
15D2
15D2
15D1
15D1
15D1
15D1
15C3
15C3
14D7
14D3
15D7
16D5
16A7
8A7
8A6

C1903
C1904
C1910
C1911
C1912
C1913
C1914
C2201
C2202
C2301
C2302
C2501
C3001
C3002
C3003
C3004
C3005
C3201
C3501
C3502
C3901
C4081
C4201
C4261
C4262
C4265
C4267
C4301
C4302
C4303
C4502
C4504
C4509
C4701
C4702
C4801
C4901
C5001
C5002
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D4901
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS9
DS10
DZ1
F2
F3
FL2
FL3
FL4
J1
J2
J3
J4
J5
J6
J7

1
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J30
J31
J32
J4501
J4502
JAZ1
L1
L2
L3
L4
L5
L6
L7
L8
L9
L12
L13
L16
L19
L20
L21
L22
L23
L24
L26
L27
L32
L33
L34
L35
L36
L39
L40
L41
L42
L43
L44
L45
L46
L47
L48
L49
L50
L51
L52
L53
L56
L57
L58
L59
L60
L63
L64
L65
L66
L67
L68
L69
L70
L71
L72
L73
L74
L75
L76
L77
L78
L79
L80
L81
L82
L83
L84
L85
L86
L87
L88
L89
L90
L91
L92
L93
L94
L95
L96
L97
L98
L99
L100

CAP
8A6
CAP
8A6
CAP
8A6
CAP
8C2
CAP
8C1
CAP
8C1
CAP
8C1
CAP
20C8
CAP
20C4
CAP
21C8
CAP
21C4
CAP_P
23A8
CAP
28C5
CAP
28D5
CAP
28D5
CAP
28D4
CAP
28D4
CAP
30D4
CAP
35D6
CAP
33A8
CAP
37D1
CAP
46C7
CAP
42B6
CAP
42A7
CAP
42A7
CAP
42A7
CAP
42A6
CAP
41A6
CAP
43A5
CAP
43A4
CAP_P
43B5
CAP
45B3
CAP
45C4
CAP
45B6
CAP
47B4
CAP
48B4
CAP
49B4
CAP
50C3
CAP
50A3
DIODE_DUAL_6P 36A7
DIODE_DUAL_6P 36A7
DIODE_DUAL_6P 36A7
DIODE_DUAL_6P 36B7
ZENER_MMBZ15VDLT1 40B6
DIODE_DUAL_6P 25D4
DIODE_DUAL_6P 25D4
DIODE
36D6
DIODE
35B8
DIODE_SCHOT 23B8
DIODE_SCHOT 44D7
DIODE_SCHOT 44D7
DIODE_SCHOT 47C7
DIODE_SCHOT 47B5
DIODE_SCHOT 49B3
DIODE_SCHOT 50C5
DIODE_SCHOT 50B5
DIODE_SCHOT 49C6
DIODE_SCHOT 46D6
DIODE_SCHOT 45D5
DIODE_SCHOT 45B5
DIODE_SCHOT_3P 42A6
ZENER_MMBZ15VDLT1 41B2
ZENER
36B6
ZENER_MMBZ15VDLT1 41B2
DIODE_DUAL_6P 25B4
DIODE_DUAL_6P 25B4
ZENER_MMBZ15VDLT1 40B5
DIODE_SCHOT 48C5
DIODE_SCHOT 48B3
DIODE_SCHOT 48B5
DIODE_SCHOT 46B6
DIODE_SCHOT 48B2
DIODE_SCHOT 44D6
DIODE_SCHOT 44D6
DIODE_SCHOT 50B2
DIODE_SCHOT 50C6
DIODE_SCHOT 50B4
DIODE_SCHOT 50A4
DIODE_SCHOT 45C4
DIODE_SCHOT 49B5
DIODE_SCHOT 45B4
DIODE_SCHOT 45D2
DIODE_SCHOT 45D6
DIODE_SCHOT 49B1
DIODE
36D6
DIODE_DUAL_SWI 42B6
DIODE_SCHOT 47B2
LED
35A2
LED
35A1
LED
35A1
LED
30A3
LED
51C8
LED
51A6
LED
38B2
LED
38B6
LED
50D5
LED
51A4
ZENER
51B1
FUSE
36D5
FUSE
36D5
FILTER_LC 25C6
FILTER_LC 25C6
FILTER_LC 25B6
CON_RJ45 35C1
CON_FWVERT_SKT 36C1
CON_F8RT_S_TH1 42B5
CON_F4RT_USB_UPRIGHT 33C3
CON_FWVERT_SKT 36D1
CON_F4RT_USB_UPRIGHT 33B3
CON_F4RT_USB_UPRIGHT 33D3

CON_F4RT_S4MT_TH1 41C1
CON_F14RT_D4MT_TH1 25C5
CON_F4RT_S4MT_TH1 40C7
CON_F184ST_DDRDIMM 15D5
CON_F21ST_D2MT_SM 24C4
CON_M40SM_635 29D6
CON_M18ST_D_TH 29B5
CON_M40ST_NC20 38D6
CON_M40ST_NC20 38D2
CON_M16ST_MICROFIT 50D7
CON_M4ST_LCK 34B4
CON_37SM_MTOR 8C4
CON_38SM_MTOR 8D7
CON_M3ST_LCK 45C8
CON_F20SM_KX 8A4
CON_F1ST_S2MT_SM 28B7
CON_M12ST_SM 29B3
CON_F100RT_LP_SM 31D3
CON_F200RT_DDRDIMM_SM2 14D5
CON_F1ST_S2MT_SM 8B1
CON_F10ST_D_SMA 29D2
CON_38SM_MTOR 8D4
CON_38SM_MTOR 8C7
CON_F12RT_S2MT_SM 8A8
CON_F4ST_S2MT_SM 43B6
CON_F4ST_S2MT_SM 43B6
TP
51A5
IND
36D4
IND
33A5
IND
36D4
IND
27D5
FILTER_4P 36C2
FILTER_4P 36C2
FILTER_4P 36D2
FILTER_4P 36D2
IND
25C2
IND
48B3
IND
22D7
IND
28C3
IND
47B4
IND
45C3
IND_3P
49B3
IND_3P
50A3
IND
50C3
IND
45B3
IND
42A6
IND
41C3
IND
36B6
IND
22B7
IND
41D3
IND
41B3
IND
40B6
IND
41A3
IND
42A5
IND
42B7
IND
41B3
IND
41A4
IND
41C3
IND
41D3
IND
40C6
IND
41B3
IND
40C6
IND
40B5
IND
40C5
IND
40D6
IND
40C5
IND
40D5
IND
44A1
IND
44A1
IND
32D6
IND
43A5
IND
43B5
IND
39D4
IND
24A5
IND
29A7
IND
29A3
FILTER_4P 24B5
IND
22D2
IND
29A3
IND
29A7
FILTER_4P 24B5
IND
29A7
IND
29A3
FILTER_4P 24C5
IND
29A7
FILTER_4P 24D5
IND
29B7
IND
29A3
IND
43B7
IND
29B3
IND
43A7
IND
24D5
IND
43A7
IND
50D6
IND
50D6
IND
50D6
IND
27D5
IND
27D2
IND
42D7
IND
42C6
IND
42C6
IND
42C7
IND
42C3
IND
42C2
IND
42D2
IND
42C3
IND
43D7
IND
43D7
IND
42B3
FILTER_4P 33D5

66

L101
L102
L103
L2401
L2501
LP1
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
Q18
Q19
Q20
Q21
Q22
Q23
Q24
Q25
Q26
Q27
Q28
Q29
Q30
Q31
Q32
Q33
Q34
Q35
Q36
Q37
Q38
Q39
Q40
Q41
Q42
Q43
Q44
Q45
Q46
Q47
Q48
Q49
Q50
Q51
Q52
Q53
Q54
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50

FILTER_4P 33C5
FILTER_4P 33B5
IND
29B3
IND
22C7
IND
23A6
LPAK4P
42A8
TRA_2N7002 51C3
TRA_2N7002 42D7
TRA_2N7002 42C7
TRA_2N7002 42B8
TRA_2N7002 41A5
TRA_2N7002 42B6
TRA_SUD70N03 48B4
TRA_SUD50N03 48B4
TRA_SUD50N03 48C4
TRA_2N7002 22B7
TRA_FDC602P 51C2
TRA_2N3904 44D7
TRA_2N7002 51B2
TRA_2N7002 51C7
TRA_2N7002 51A7
TRA_2N7002 51A7
TRA_2N7002 51B6
TRA_2N7002 51A7
TRA_2N7002 51A6
TRA_FDC602P 51D7
TRA_2N7002 50C1
TRA_2N7002 50D1
TRA_2N7002 50C2
TRA_2N7002 50C2
TRA_IRF7807Z 47B5
TRA_IRF7807Z 47B5
TRA_SUD70N03 49B4
TRA_SUD50N03 49B4
TRA_2N7002 45D8
TRA_2N3904 36C7
TRA_2N7002 41A8
TRA_2N7002 39C7
TRA_2N3904 43A2
TRA_SUD70N03 48B4
TRA_2N7002 40D4
TRA_2N7002 42D3
TRA_FDC602P 51C6
TRA_2N7002 51B6
TRA_2N3904 50C7
TRA_SUD70N03 45C4
TRA_2N7002 15B2
TRA_2N7002 15C2
TRA_SUD70N03 45C4
TRA_SUD50N03 45C4
TRA_IRF7807Z 50B4
TRA_IRF7807Z 50C4
TRA_SUD50N03 50A4
TRA_SUD50N03 50A4
TRA_SUD70N03 45B4
TRA_SUD50N03 45B4
TRA_SUD70N03 45B4
TRA_2N7002 15B2
TRA_2N7002 15A2
TRA_2N7002 15B2
RES
36D4
RES
25B4
RES
25B4
RES
21A4
RES
21A3
RES
21A4
RES
25B5
RES
36C4
RES
36C4
RES
36C4
RES
36C4
RES
36C3
RES
36C3
RES
36C3
RES
36C3
RES
36B3
RES
21A3
RES
21A4
RES
25B5
RES
19C2
RES
51D3
RES
51C4
RES
51D3
RES
19A3
RES
19A3
RES
35B4
RES
35C4
RES
35A8
RES
35B7
RES
35C3
RES
19A3
RES
19A3
RES
35C4
RES
35C7
RES
36D6
RES
18B8
RES
35C4
RES
35C7
RES
36D6
RES
35C4
RES
18B8
RES
35B4
RES
33D7
RES
33D7
RES
33C7
RES
33C7
RES
33B7
RES
33B7
RES
18B7
RES
18B7

7
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R65
R66
R67
R68
R69
R70
R71
R72
R73
R74
R75
R76
R77
R78
R79
R80
R81
R82
R83
R84
R85
R86
R87
R88
R89
R90
R91
R92
R93
R94
R95
R96
R97
R98
R99
R100
R101
R102
R103
R104
R105
R106
R107
R108
R109
R110
R111
R112
R113
R114
R115
R116
R117
R118
R119
R120
R121
R122
R123
R124
R125
R126
R127
R128
R129
R130
R131
R132
R133
R134
R135
R136
R137
R138
R139
R140
R141
R142
R143
R144
R145
R146
R147
R148
R149
R150
R151
R152
R153
R154
R155
R156
R157
R158
R159
R160

RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES

42B7
18C5
19A4
18D3
19A4
18D2
19A4
18D3
18C2
19A4
18A3
18A2
19A4
18D3
19A4
18D2
18D2
19A4
19A4
18D3
18D6
17A5
26C2
26D2
35B8
35B8
26D2
32A7
26C2
17A5
19A7
12A8
18A5
18G2
23D6
23D6
26B3
18A5
32D3
18G3
23D6
23D6
12A8
26A3
18A5
35B1
19A7
23D6
42D8
26A8
19A7
23C5
19B2
19B2
19C2
19C2
23D5
42D7
42D6
42C8
18G2
23D6
23D5
23C5
23C5
26C6
18G3
22D3
23C5
42B8
42C8
19A7
19D2
23C5
26D5
26C6
32B8
32B8
32D3
18D2
18D3
19D2
22D3
26B8
42D7
26C5
12B1
30B3
30B4
19A7
23B5
26C5
18G2
23B2
22D3
19A7
19A7
19C2
23B5
48C5
20A4
20A5
19A7
18G3
18G2
19C2
23B3
19D2
19A7
17A5

R161
R162
R163
R164
R165
R166
R167
R168
R169
R170
R171
R172
R173
R174
R175
R176
R177
R178
R179
R180
R181
R182
R183
R184
R185
R186
R187
R188
R191
R192
R193
R194
R195
R196
R197
R198
R199
R200
R203
R204
R205
R206
R207
R208
R210
R211
R212
R213
R214
R215
R216
R217
R218
R219
R220
R221
R222
R223
R224
R225
R226
R227
R228
R230
R231
R232
R233
R234
R235
R236
R237
R238
R239
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
R256
R257
R258
R259
R261
R262
R263
R264
R265
R266
R267
R268
R269
R270
R271
R272
R273
R274
R275
R276
R277

RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES

16D1
41A5
20A4
18G3
35C4
20A4
19A7
17A7
17A4
22B5
22B6
12A1
22C7
22C6
40D4
20A4
17A5
22C7
22C6
40D5
41A4
41A4
22C3
23C6
22B6
19A6
19A6
22B2
22B6
17A2
17A2
22B6
17A3
17A3
16A7
17C1
22D6
22D6
16C8
16B8
16A8
22D6
23D2
23D2
17B7
16C7
30B3
23C5
12B1
16C7
16B7
16D3
30D6
30D6
16C7
16D1
16D3
16D1
16C7
16D7
16C7
30C6
28C7
30C6
28C8
28C6
16B3
16D1
12A1
26D2
23C5
27A6
42B7
42B6
27A5
42B5
27A6
27A5
42B5
23B7
28A2
27A7
42B5
27A7
51B3
30C7
30C8
34B4
30C7
30C8
34B3
37D5
30C7
12D5
30C8
37D4
28D1
38B4
37C6
28B1
38B4
34C4
37D2
28B3
28B3
37D2
28C7
34C4
28C8
51B2

R278
R279
R280
R281
R282
R283
R284
R285
R286
R287
R288
R289
R290
R291
R292
R293
R294
R295
R296
R297
R298
R299
R300
R301
R302
R303
R304
R305
R306
R307
R308
R309
R310
R311
R312
R313
R314
R315
R316
R317
R318
R319
R320
R321
R322
R323
R324
R326
R328
R329
R330
R331
R332
R333
R334
R335
R336
R337
R338
R339
R340
R341
R342
R343
R344
R345
R346
R347
R348
R349
R350
R351
R352
R353
R354
R355
R356
R357
R358
R359
R360
R361
R362
R363
R364
R365
R366
R367
R368
R369
R370
R371
R372
R373
R374
R375
R376
R377
R378
R379
R380
R381
R382
R383
R384
R385
R386
R387
R388
R389

RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES

R390
R391
R392
R393
R394
R395
R396
R397
R398
R399
R400
R401
R402
R403
R404
R405
R406
R407
R408
R409
R410
R411
R412
R413
R414
R415
R416
R417
R418
R419
R420
R421
R422
R423
R424
R425
R426
R427
R428
R429
R430
R431
R432
R433
R434
R435
R436
R437
R438
R439
R440
R441
R442
R443
R444
R445
R446
R447
R448
R449
R450
R451
R452
R453
R454
R455
R456
R457
R458
R459
R460
R461
R462
R463
R464
R465
R466
R467
R468
R469
R470
R471
R472
R473
R474
R475
R476
R477
R478
R479
R480
R481
R482
R483
R484
R485
R486
R487
R488
R489
R490
R491
R492
R493
R494
R495
R496
R497
R498
R499

51B3
51B2
44D8
44D7
44D7
51B3
51A3
31C1
12A3
44D5
12D5
28C8
44D8
28C7
28C7
31C5
28C1
47B3
47B7
44D6
44B1
47B3
51C8
47B5
51A6
34D7
47B3
28A2
28B8
34D7
8B1
47B7
9A4
4B8
4A8
8A2
8B2
47B3
47B7
47C5
47C6
9A5
47B5
9A5
50C2
50D2
42B5
35B3
29D3
29D3
50A8
50B8
50A7
28A2
49B1
50A5
50C5
50B5
9C5
9D5
9D5
9C5
9A7
9C6
9A7
9A7
7C7
7C7
7C7
7B7
7A7
9C5
9C6
9A7
9C6
9C7
6C4
6C4
9C6
9C7
9C6
45B3
45B3
6C5
6C5
6C4
9C7
6C4
6C4
49C6
50D5
49B6
46D4
32A7
6C6
6C6
6C7
6C7
6C7
6C8
6C7
6C8
6C8
6C8
45C5
46D6
45B5
45B5
45B6
45B6

RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES

35C1
35C2
41B3
35C2
35C2
36B7
28A2
26A7
28A2
26B7
41C4
26B6
36B4
19B2
36D8
15C2
41D4
40C5
26A6
36D7
40B5
36C5
41C4
43B5
43B5
19A3
19A3
36C7
36C6
41D4
40B4
43B5
36C6
36B5
36C7
36C7
26A5
26B5
19A3
19A3
36B6
36C7
36C7
36B6
40C4
40C4
40B4
40B4
36C8
26B4
41A8
41D6
40C4
26A4
41C6
26B6
41C6
41D6
40B3
26A6
33B5
33B6
33C5
33C6
33D5
33D6
33B7
33B7
33C7
33C7
33D7
33D7
40B3
18B8
32C3
32C3
32C2
32C2
32C3
32C3
32B3
15C1
41C7
41D7
40C3
48B1
32B3
41B4
41B5
19A6
32B2
39B6
39C6
19A6
32A7
35B2
35B2
43A6
43B4
43B4
32B3
35B2
35B1
28A2
32B7
15B1
48C2
15C1
43A2
48C3

1
R500
R501
R502
R503
R504
R505
R506
R507
R508
R509
R510
R511
R512
R515
R517
R518
R519
R521
R522
R523
R524
R525
R526
R527
R528
R529
R531
R532
R533
R535
R537
R540
R541
R542
R543
R545
R546
R547
R548
R549
R550
R551
R552
R553
R554
R555
R556
R557
R558
R559
R560
R561
R562
R563
R564
R565
R566
R567
R568
R569
R570
R571
R572
R573
R574
R575
R576
R577
R578
R579
R580
R581
R582
R583
R584
R585
R586
R587
R588
R589
R590
R591
R592
R593
R594
R595
R596
R597
R598
R599
R600
R601
R602
R603
R604
R605
R606
R607
R608
R609
R610
R611
R612
R613
R614
R615
R616
R617
R618
R619

RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES

19C2
39C7
39D7
48B6
48C3
48C5
19A7
15B1
15B3
19A7
30B4
30A3
15C3
48B5
39C5
46B5
46A5
39C5
42B8
48C6
39B4
42B7
42B7
48B7
39C4
48C6
39C2
39C4
26D6
26D1
27A5
24A6
26A6
26B6
26B1
16A7
24A5
24A6
27A7
16A8
24A5
24A5
26C8
26D8
22C7
22C3
22C2
22C2
17B7
24B6
26C7
26D7
22C6
27A6
23C5
28D5
30D6
24B5
24B5
22B3
24B6
28D8
28D8
28C6
28C8
34C1
34C1
28C7
30B6
30A8
16B3
24B5
24C5
26D3
29D7
29D6
28D6
16B3
26C3
28A8
28D6
24C6
23A7
24C5
24D5
26D5
26D5
26C3
26D3
22A8
24D6
51B3
23A7
24D5
44A3
44A5
44A5
51A5
51A5
51A5
46B4
28A6
51A5
29A8
51A5
51A6
30D8
30D8
30C7
16D6

67

R620
R621
R622
R623
R624
R625
R626
R627
R628
R629
R630
R635
R636
R637
R640
R641
R645
R646
R647
R648
R649
R650
R651
R653
R654
R655
R656
R657
R658
R659
R660
R661
R664
R665
R666
R667
R668
R669
R670
R671
R672
R673
R676
R677
R678
R679
R680
R682
R683
R684
R685
R686
R687
R688
R689
R690
R691
R692
R693
R694
R697
R698
R699
R700
R701
R702
R705
R706
R707
R708
R709
R710
R711
R712
R713
R714
R716
R717
R718
R719
R720
R721
R722
R723
R724
R725
R726
R727
R728
R729
R730
R731
R732
R733
R734
R735
R736
R737
R738
R739
R740
R741
R742
R743
R744
R745
R746
R747
R749
R750

RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES

28D5
30C6
16C6
37D5
37A7
12B6
37D2
37D5
28D5
28D5
28D5
37D3
44B6
34B3
37A5
28D1
51B6
44C1
34B4
44B2
44C3
28A2
28A2
44B7
44A5
44B2
44A6
44C3
44C3
44C2
28A1
28C7
51B6
44C1
28A6
16D6
29C3
29C2
29C2
44C1
28A6
34B4
44B4
44C2
28C8
37A2
28A8
50D5
28A1
34C1
51B7
44A7
44A7
44C2
44C3
44D3
28B3
44A3
44D8
28B3
12A3
44A3
44D3
44D3
44D4
34C4
29B3
29C3
34D4
28C8
34C3
28A5
28A6
9A3
9A4
34B7
44B8
44C3
28B2
30D5
9D3
50C8
44C6
28B2
28C2
44B6
44B7
28C7
28B2
44C6
44C7
44B6
44C7
44B7
44B7
28C7
28B2
38C7
51B7
51C7
51A7
51A7
28B2
38C4
38C7
38C3
28B8
28B6
28B8
28B8

7
R751
R752
R753
R754
R755
R756
R757
R758
R759
R760
R761
R762
R763
R764
R765
R766
R767
R768
R769
R770
R772
R773
R774
R775
R776
R777
R779
R780
R781
R782
R783
R784
R785
R786
R787
R788
R789
R790
R791
R792
R793
R794
R795
R796
R797
R798
R799
R800
R801
R802
R803
R804
R805
R806
R807
R808
R809
R810
R811
R815
R825
R827
R832
R833
R840
R841
R842
R843
R844
R845
R846
R847
R848
R849
R850
R851
R852
R853
R854
R855
R856
R857
R858
R859
R860
R861
R862
R863
R864
R865
R866
R867
R868
R869
R870
R871
R872
R873
R874
R875
R876
R877
R878
R879
R880
R881
R882
R883
R884
R885

RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES

51A8
9A4
37C2
37D4
28D2
28D2
9A4
38C1
37D2
38C5
37C5
28B3
28B3
9B4
9A4
9A4
37D2
37D5
51D7
51D7
9A4
37D2
37D4
38C7
9A5
9A4
38C1
38C3
38C5
38C7
38C4
38C7
38C4
38A4
38B4
38A7
38B7
38B7
38B7
38B2
38B6
50C7
50A6
15A8
50A5
50A5
50B8
45C3
45C3
50B5
50B5
50B6
50A3
50C6
50B5
50C3
15A8
50A5
50C5
50B3
15A3
49B5
9D6
9B7
7C7
7C7
7B7
7A7
7A7
7B7
7B7
7B7
7D5
7B7
4C2
7B7
9B7
9B7
9B7
9D6
7C5
7B5
7C5
7C5
7B5
9A7
9B7
9D6
9D7
9D6
6C4
6C4
9D7
9D5
9C5
49C3
49C3
49C5
6C4
6C4
9D7
6C4
6C5
6C5
49C3
23D2
7B5
49B6
49C5
9D6

R886
R887
R888
R889
R890
R891
R892
R893
R894
R895
R896
R897
R898
R899
R900
R901
R902
R903
R904
R905
R906
R907
R908
R909
R910
R911
R912
R913
R914
R915
R916
R917
R918
R919
R920
R921
R922
R923
R924
R925
R926
R927
R928
R929
R930
R931
R932
R933
R934
R935
R936
R937
R939
R940
R941
R942
R943
R944
R945
R946
R947
R948
R949
R950
R951
R952
R953
R954
R955
R956
R957
R958
R959
R960
R961
R962
R963
R964
R965
R966
R967
R968
R969
R970
R971
R972
R973
R974
R975
R976
R977
R978
R979
R980
R981
R982
R983
R984
R985
R986
R987
R988
R989
R990
R991
R992
R993
R994
R995
R996

RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES

R997
R998
R999
R1000
R1001
R1002
R1003
R1004
R1005
R1006
R1007
R1008
R1009
R1010
R1011
R1012
R1013
R1014
R1015
R1016
R1017
R1018
R1019
R1020
R1021
R1022
R1023
R1024
R1025
R1026
R1027
R1028
R1029
R1401
R1402
R1403
R1404
R1405
R1406
R1407
R1408
R1409
R1410
R1411
R1412
R1413
R1414
R1415
R1416
R1417
R1418
R1503
R1504
R1505
R1506
R1507
R1508
R1509
R1510
R1511
R1512
R1513
R1514
R1515
R1516
R1517
R1518
R3001
R3002
R3501
R4201
R4202
R4203
R4301
R4302
R4303
R4304
R4305
R4401
R4501
R4502
R4503
R4504
R4505
R4506
R4507
R4508
R4509
R4701
R4702
R4703
R4704
R4705
R4706
R4707
R4708
R4709
R4710
R4801
R4802
R4803
R4901
R5001
R5002
R5003
R5101
R5301
RP1
RP2
RP3

9C6
6C5
49D5
6C5
9D7
4D6
9D7
9C7
9C7
4D2
45C5
45B5
45B5
45D6
45C5
4D3
7A3
7A3
7A3
7A3
7B3
7B3
45D6
7B5
7B5
7B5
7A5
7C3
7C3
7C3
7B3
7B3
7C3
7B3
7B3
7B5
7A5
7A5
7D5
7C5
7C3
46C5
45C5
45C5
46C5
45D7
45C7
45D7
45C8
45A5
45A5
8A4
8A4
8A4
37D1
22A7
37D2
37D2
46B7
23D2
23D2
31D4
31D4
31D3
31C2
22A7
22A7
22A6
22A6
22A6
22A6
46B5
46C5
23D2
23D1
23D1
23D1
23D1
27B5
27B4
27C5
27B4
27C4
27B4
27C4
27C3
27C2
27C2
27C2
27C2
27C2
27C2
27C2
27C2
42D6
42D6
42C4
42D4
42D3
43D5
43D5
43C2
43D2
23D2
23D2
23C1
23C1
23C1
23C1
23C1

RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RPAK4P
RPAK4P
RPAK4P

23C1
23C1
23C1
27B5
27C4
27B4
27B3
27B3
28C1
33D5
33D5
33C5
33C5
33B5
33B5
51B2
50D7
50C8
29B4
36D7
51C3
51C2
23C6
23C6
26A1
26C2
26C1
17A4
17A4
17C7
17C7
32A7
32A7
14B2
14A2
14D7
14C7
14C7
14C7
14C7
14C7
14C7
14C7
14B7
14B7
14B7
14B7
14B7
14B7
14B7
14A7
15C7
15C7
15C7
15C7
15C7
15C7
15C7
15B7
15B7
15B7
15B7
15B7
15B7
15B7
15A7
15A7
28A2
28A2
33A8
42B6
42C5
42B5
41A7
43A5
43A5
43A4
43A4
43C7
43B6
43A6
43A6
43B6
43A6
43A6
43C5
45B3
45C4
45B6
45B6
45B3
45B3
45B3
45D3
45D3
45C5
45B6
47B4
46C7
48B4
48C3
49B4
50B3
50A3
50A1
51B7
51C1
35C7
36C7
36B7

RP4
RP5
RP6
RP7
RP8
RP9
RP10
RP11
RP12
RP13
RP14
RP15
RP16
RP17
RP18
RP19
RP20
RP21
RP22
RP23
RP24
RP25
RP26
RP27
RP28
RP29
RP30
RP31
RP32
RP33
RP34
RP35
RP36
RP37
RP38
RP39
RP40
RP41
RP42
RP43
RP44
RP45
RP46
RP47
RP48
RP49
RP50
RP51
RP52
RP54
RP56
RP58
RP59
RP60
RP61
RP62
RP63
RP64
RP65
RP66
RP67
RP68
RP69
RP70
RP71
RP72
RP73
RP74
RP75
RP76
RP77
RP78
RP79
RP80
RP81
RP82
RP83
RP84
RP85
RP86
RP87
RP88
RP89
RP90
RP91
RP92
RP93
RP94
RP95
RP96
RP97
RP98
RP99
RP100
RP101
RP102
RP103
RP104
RP105
RP106
RP107
RP108
RP109
RP110
RP111
RP112
RP113
RP114
RP115
RP116

RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P

19B5 19C5
19B5
19B5
19B5
18A2 18A3
18C2 18C2
19C7
19B7
19B7
19B7
19C7
35B7 35B8
35A4
19C7
19D7
19D7
19D7
19D7
18F2 18F3
18E2 18E3
19C5
19C5 19D5
19C5
19D5
19D5
19D5
17D7
17C7
17D7
17B7
17C7
17B7
17A7
16B3 16C3
30B6
28D2
17D7
17C7
17D7
17C7
17C7
17B7
17B7
17A7
16B3
16B1 16B1
16B1
12C2
12B2
31B7
31B7
31C7
31C7
28C2
31B7
12C3
30B8
31B7
34C4
28A8
31B7
12D3
30B8
34C7
12C2 12D2
31C7
31C7
28A8
31C7
34C7
31C7
7A7
7A5 7C5
19B7
19B7
19B7 19C7
18B2 18B3
18B2 18B2
18B3 18C2
19B5
19B5
19C5
19C5
19C7
19C7 19D7
19C7
18E2 18E3
18F2 18F3
18F2 18F2
19C5
19D5
16B3 16C3
16C1
28A8
34B1
12C5
37B2 37C2
37B4 37B5
12B5
37B2
37B4 37B4
28A3 28B3
12A5
28A8
37C4 37C4
34C4
28B8
37A2 37B2
37A4 37A5
12B3

1
RP117
RP118
RP119
S1
S2
SP1
SP2
SP3
SP4
T1
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U18
U19
U20
U21
U22
U23
U25

RPAK4P
28C1 28C1 28D1 28D1
RPAK4P
37C2
RPAK4P
34C1
SWI_TACT_2P1 44B2
SWI_TACT 44A3
SPRING_CLIP_1P_EMI 10D2
SPRING_CLIP_1P_EMI 10D2
SPRING_CLIP_1P_EMI 10D1
SPRING_CLIP_1P_EMI 10D1
XFR_100BT_MDIX 35C3
SIL1162
27C3
SHNTREG_TLV431A 21A4
VREG_LP2951 36D7
FW802A
36C5
SDRAM_DDR_4MX32 21D6 21D7
OPAMP_TLV2362 40B3 40C3
SHNTREG_TLV431A 18B8
AMP_TPA6112A2 41D5
CLK_GEN_CY25811 22A7
NC7WZ08
42C7
UPD720101_FBGA 32C5
SDRAM_DDR_4MX32 20D6 20D7
OPAMP_TLV2362 43A3
VREG_LP2951 39D6
TAS3004
39C3
SHNTREG_TLV431A 20A5
CBTV4020 13D7
VREG_LT1962 28D7
VREG_LM1117 23A8
VDET_MC33465N_22ATR 44A4
CBTV4020 13B6
MAX6328
44A5
INTREPID 9D2 10D5 10D7 12D7 16D5 28C4 30D5
34C5 37D8
U26
M16C62
44C5
U27
CBTV4020 13D4
U28
VREG_TL431 44D8
U29
CBTV4020 13C2
U31
DCDC_SC2602 47B6
U33
LTC3707
50B6
U34
APOLLO_MPC7445_360 4C5 5D3 5D6
U35
TRA_SI4435DY 51D3
U36
SDRAM_DDR_4MX32 21D2 21D3
U37
TRANSCEIVER_BCM5221 35C5
U38
SN74AUC1G04 30B3
U39
NV18B
17D6 18G5 18G7 22D4 23D4
U40
DCDC_SC2602 48C6
U41
SDRAM_DDR_4MX32 20D2 20D3
U42
FEPR_1MX8 30C2
U45
DCDC_SC2602 49C5
U46
SN74LVC1G04 44D1
U47
LTC3707
45C6
U48
NC7WZ08
41A7 43C7
U49
AMP_SN0210045A 42D5
U3501 SWI_TPS2023 33A7
VR1
VREG_LM1117 39C7
VR2
VREG_MIC39102 46B6
VR3
VREG_EZ1582 51B4
VR4
VREG_MIC39102 46C5
XW1
SHORT
39B7
XW2
SHORT8L25_WITH_ALTS 48B2
XW4
SHORT
39B7
XW5
SHORT
39B7
XW6
SHORT8L25_WITH_ALTS 48B4
XW7
SHORT8L25_WITH_ALTS 48C7
XW12 SHORT8L25_WITH_ALTS 47B3
XW13 SHORT8L25_WITH_ALTS 47B4
XW14 SHORT8L25_WITH_ALTS 47C5
XW15 SHORT8L25_WITH_ALTS 47A6
XW16 SHORT8L25_WITH_ALTS 50A3
XW17 SHORT8L25_WITH_ALTS 50B8
XW18 SHORT8L25_WITH_ALTS 50A3
XW19 SHORT8L25_WITH_ALTS 50B2
XW20 SHORT8L25_WITH_ALTS 50B3
XW21 SHORT8L25_WITH_ALTS 50A6
XW22 SHORT8L25_WITH_ALTS 50B5
XW23 SHORT8L25_WITH_ALTS 49B2
XW24 SHORT8L25_WITH_ALTS 49C4
XW25 SHORT8L25_WITH_ALTS 49C4
XW26 SHORT8L25_WITH_ALTS 45C3
XW27 SHORT8L25_WITH_ALTS 45C3
XW28 SHORT8L25_WITH_ALTS 45B1
XW29 SHORT8L25_WITH_ALTS 45C6
XW30 SHORT8L25_WITH_ALTS 45A3
XW31 SHORT8L25_WITH_ALTS 45B3
XW32 SHORT
39B7
XW33 SHORT
41B7
XW34 SHORT
39A7
XW37 SHORT
39B7
XW38 SHORT
39A7
XW39 SHORT8L25_WITH_ALTS 48B5
XW41 SHORT8L25_WITH_ALTS 49B5
XW42 SHORT
28A5
XW43 SHORT
28A5
XW44 SHORT
28A5
XW45 SHORT
28A4
XW46 SHORT
28A4
XW47 SHORT
9A2
XW48 SHORT
16A5
XW49 SHORT
30B5
Y1
CRYSTAL
36C6
Y2
CRYSTAL_4PIN 22B3
Y3
CRYSTAL
44A6
Y4
CRYSTAL_4PIN 44B2
Y5
CRYSTAL
28A6
Y6
CRYSTAL
35B7
Y7
CRYSTAL
32D3
ZH3
MTGHOLE
39A7
ZH4
MTGHOLE
4B2
ZH5
SLOT
4B1

18B2
18C3 18C3

18G2 18G3

16C3

16C1

19C7
18B3
18B3
18C3

18F3

16C3

37C5

37B5

37C5 37C5

37B4 37B5

68

ZH6
ZH7
ZT1
ZT2
ZT3
ZT4
ZT5
ZT6
ZT7
ZT8
ZT9
ZT10
ZT11
ZT12
ZT13
ZT14
ZT15
ZT16
ZT17
ZT18
ZT19
ZT20
ZT21
ZT22
ZT23
ZT24
ZT25
ZT26
ZT27
ZT28
ZT29
ZT30
ZT31
ZT32
ZT33
ZT34
ZT35
ZT36
ZT37
ZT38
ZT39
ZT40
ZT41
ZT42
ZT43
ZT44
ZT45
ZT46
ZT47
ZT48
ZT49
ZT50
ZT51
ZT52
ZT53
ZT54
ZT55
ZT56
ZT57
ZT58
ZT59
ZT60
ZT61
ZT62
ZT63
ZT64
ZT65
ZT66
ZT67
ZT68

SLOT
MTGHOLE
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA

4B2
4B1
18C2
18C2
18C2
18A2
18C2
18C2
18A2
18C2
18B2
18B2
18B2
18B2
18B2
18B2
18B2
18B2
18B2
18B2
18A2
18G2
18E2
18F2
18F2
18F2
18F2
18F2
18E2
18D2
18G2
18F2
18F2
18E2
18E2
18F2
18E2
18E2
18F2
18E2
3B3
3B3
3B3
3B3
3A3
3A3
3A3
3B3
3B3
3B3
3B3
3A3
3A3
3A3
3B2
3B2
3B2
3B2
3A2
3A2
3B2
3B2
3B2
3B2
3A2
3B1
3B1
3B1
3B1
3A1

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6569

69

OF

A
69

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