D Flip Flop

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_FlipFlop IS PORT(D,CLK,RESET,PRESET:IN STD_LOGIC; Q,QBAR:INOUT STD_LOGIC); END D_FlipFlop; ARCHITECTURE D_BEHAV OF D_FlipFlop IS SIGNAL TEMP: STD_LOGIC; BEGIN ASSERT (RESET='0' AND PRESET='0') REPORT ("BOTH RESET='0' AND PRESET='0' IS HIGHLY INVALID") SEVERITY ERROR; PROCESS(CLK,D,RESET,PRESET) begin if(RESET='0')then Q<='0'; ELSIF(PRESET='0')THEN Q<='1'; ELSE IF(CLK='1' AND CLK'EVENT)THEN Q <= D; END IF; END IF; END PROCESS; TEMP<= NOT Q; QBAR <= TEMP; END D_BEHAV;

T Flip Flop LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY T_FLIPFLOP IS PORT(T,CLK,RESET,PRESET:IN STD_LOGIC; Q,QBAR:OUT STD_LOGIC); END T_FLIPFLOP; ARCHITECTURE T_STRUCTURE OF T_FLIPFLOP IS COMPONENT NAND2 PORT(X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END COMPONENT COMPONENT NAND3 PORT(W,X,Y:IN STD_LOGIC; Z:OUT STD_LOGIC); END COMPONENT SIGNAL Sig0,Sig1,Sig2,Sig3: STD_LOGIC; BEGIN ASSERT (RESET='0' AND PRESET='0') REPORT ("Both Reset and Preset Cannot be active") SEVERITY ERROR; Sig3<= NOT Sig2; IF(RESET='0') THEN Sig2<='0'; ELSIF(PRESET='0') THEN Sig2<='1'; ELSE IF(CLK='1' AND CLK'EVENT) THEN N3in1: NAND3 PORT MAP(T,CLK,Sig3,Sig0); N3in2: NAND3 PORT MAP(T,CLK,Sig2,Sig1);

N1: NAND2 PORT MAP(Sig0,Sig3,Sig2); N2: NAND2 PORT MAP(Sig1,Sig2,Sig3); END IF END IF Q<=Sig2; QBAR<=Sig3; END T_STRUCTURE;

SR Flip Flop LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY SR_FLIP_FLOP IS PORT(S1,R1:IN STD_LOGIC;Q1,Q1BAR:INOUT STD_LOGIC); END SR_FLIP_FLOP; ARCHITECTURE SR_STRUCTURE OF SR_FLIP_FLOP IS SIGNAL SIG1,SIG2: STD_LOGIC; COMPONENT NAND_GATE PORT(L,M:IN STD_LOGIC;Z:OUT STD_LOGIC); END COMPONENT; BEGIN N1:NAND_GATE PORT MAP(S1,S1,SIG1); N2:NAND_GATE PORT MAP(R1,R1,SIG2); N3:NAND_GATE PORT MAP(SIG1,Q1BAR,Q1); N4:NAND_GATE PORT MAP(SIG2,Q1,Q1BAR); END SR_STRUCTURE;

JK Flip Flop LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY jkff IS port(j,k,clk:in std_logic; q,qbar:out std_logic); END jkff; ARCHITECTURE jk_ff OF jkff IS signal jks:std_logic; BEGIN process(clk) variable jk:std_logic_vector(1 downto 0); constant delay:TIME:=450 ps; BEGIN if(clk='1' and clk'event)then jk:=j&k; case jk is when"00"=> jks <= jks after delay; when"01"=> jks <= '0' after delay; when"10"=> jks <= '1' after delay; when others=> jks <= not(jks) after delay; end case; end if; end process; END jk_ff;

Generic Priority Encoder LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY GENRIC_PRIORITY IS GENERIC(N:NATURAL :=4); PORT(I:IN STD_LOGIC_VECTOR(0 TO (N-1)); V:OUT STD_LOGIC; O: OUT STD_LOGIC_VECTOR(0 TO (N-1))); END GENRIC_PRIORITY; ARCHITECTURE PRIORITY_BEHAV OF GENRIC_PRIORITY IS BEGIN PROCESS (I) VARIABLE M:NATURAL; BEGIN M:= 0 ; FOR K IN 1 TO N LOOP IF(I(K-1)='1') THEN M:=K; END IF; END LOOP; IF(M = 0) THEN V<='0'; O<="0000"; ELSE V<='1'; O(M-1)<='1'; FOR J IN 0 TO (M-2) LOOP

O(J)<='0'; END LOOP; FOR J IN (M) TO (N-1) LOOP O(J)<='0'; END LOOP; END IF; END PROCESS; END PRIORITY_BEHAV;

Generic Comparator Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity generic_comparitor is generic (N: NATURAL := 2); port(IA,IB: in std_logic_vector(0 to N-1); OA,OB: out std_logic); end generic_comparitor; architecture generic_behave of generic_comparitor is begin process (IA,IB) begin if(IA>IB) then OA<='1'; OB<='0'; elsif(IA<IB)then OA<='0'; OB<='1'; else OA<='1'; OB<='1'; end if; end process; end generic_behave;

Pulse Counter

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_FlipFlop IS PORT(D,CLK,RESET,PRESET:IN STD_LOGIC; Q,QBAR:INOUT STD_LOGIC); END D_FlipFlop; ARCHITECTURE D_BEHAV OF D_FlipFlop IS SIGNAL TEMP: STD_LOGIC; BEGIN ASSERT (RESET='0' AND PRESET='0') REPORT ("BOTH RESET='0' AND PRESET='0' IS HIGHLY INVALID") SEVERITY ERROR; PROCESS(CLK,D,RESET,PRESET) begin if(RESET='0')then Q<='0'; ELSIF(PRESET='0')THEN Q<='1'; ELSE IF(CLK='1' AND CLK'EVENT)THEN Q <= D; END IF; END IF; END PROCESS; TEMP<= NOT Q; QBAR <= TEMP; END D_BEHAV;

Vending Machine Controller LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY VENDING_MACHINE IS PORT(CLK,CR,SEL:IN STD_LOGIC; C5,C10,C20: IN STD_LOGIC; CO,LA: OUT STD_LOGIC; BAL: OUT STD_LOGIC_VECTOR(0 TO 4)); END VENDING_MACHINE;

ARCHITECTURE VENDING_BEHAV OF VENDING_MACHINE IS TYPE S IS(S0,S5,S10,S15,S20,S25,S30,STEMP); SIGNAL PR_STATE,NXT_STATE:S; SIGNAL BAL_REG:STD_LOGIC_VECTOR(0 TO 4); BEGIN P1: PROCESS (CLK,CR) BEGIN IF(CR='0')THEN PR_STATE<=S0; ELSIF(CLK='1' AND CLK'EVENT) THEN PR_STATE<=NXT_STATE; END IF; END PROCESS P1; P2: PROCESS(C5,C10,C20,PR_STATE,SEL) BEGIN CASE PR_STATE IS WHEN S0 => CO<='0'; LA<='0';

IF(C5='1')THEN BAL_REG<="00101"; NXT_STATE<=S5; ELSIF(C10='1')THEN BAL_REG<="01010"; NXT_STATE<=S10; ELSIF(C20<='1')THEN BAL_REG<="10100"; NXT_STATE<=S20; ELSE BAL_REG<="00000"; END IF; BAL<= BAL_REG; WHEN S5 => CO<='0'; LA<='0'; IF(C5='1') THEN BAL_REG<="01010"; NXT_STATE<= S10; ELSIF(C10='1') THEN BAL_REG<="01111"; NXT_STATE<= S15; ELSIF(C20='1') THEN BAL_REG<="10100"; NXT_STATE<= S25; ELSE BAL_REG<="00101"; END IF; BAL<= BAL_REG;

WHEN S10 => CO<='0'; LA<='0'; IF(C5='1') THEN BAL_REG<="01111"; NXT_STATE<= S15; ELSIF(C10='1') THEN BAL_REG<="10100"; NXT_STATE<= S20; ELSIF(C20='1') THEN BAL_REG<="11110"; NXT_STATE<= S30; ELSE BAL_REG<="01010"; END IF; BAL<= BAL_REG; WHEN S15 => CO<='0'; LA<='1'; BAL_REG<="00000"; BAL<= BAL_REG; NXT_STATE<=S0; WHEN S20 => CO<='1'; LA<='0'; BAL_REG<="00000"; BAL<= BAL_REG; NXT_STATE<=S0; WHEN S25 =>

CO<='0'; LA<='0'; IF(SEL='0') THEN BAL_REG<="01010"; NXT_STATE<= S15; ELSE BAL_REG<="00101"; NXT_STATE<= S20; END IF; BAL<= BAL_REG; WHEN S30 => CO<='0'; LA<='0'; IF(SEL='0') THEN BAL_REG<="00101"; NXT_STATE<=STEMP; ELSE BAL_REG<="01010"; NXT_STATE<=S20; END IF; BAL<= BAL_REG; WHEN STEMP => CO<='0'; LA<='0'; BAL_REG<="01010"; NXT_STATE<=S15; BAL<= BAL_REG; END CASE; END PROCESS P2;

END VENDING_BEHAV;