2010 4 1 NEC

http://www.renesas.com

2010 4 1

http://www.renesas.com
http://japan.renesas.com/inquiry


1.

2.

3.

4.

5.

6.

7.

OA AV

8.

9.

10.

RoHS

11.

12.

1.

2.

OPENCAD V5.3
NEC ASICCAD
Design Compiler

A14353JJ3V0UM003
May 2000 NSCP(K)
NEC Corporation 1999

A14353JJ3V0UM00


117
221
327
437
565
681
A87
BDIF.dif89
C97
D 99
ENEC Design Ware103

A14353JJ3V0UM00

OPENCAD
Vdraw, V.sim, C.FGRADE
VerilogCadence Design Systems
Design CompilerSynopsys
ModelSimModel Technology
PrimeTime, VCSSynopsys
Mentor, Design ArchtectMentor Graphics
Verilog-XLCadence Design Systems

M7A98.8

A14353JJ3V0UM00

CB-C7CB-7
CB-C8CB-8
CB-C9CB-9
CB-C10CB-10EA-C9EA-9EA-C9HDEA-9HD
EA-C10EA-10

p.66

5. 2 2 b
CB-10

p.74

5. 10 2
IPOECO

A14353JJ3V0UM00

A14353JJ3V0UM00


OPENCAD

LSI

LSI
NEC ASIC

SynopsysDesign CompilerOPENCAD V5.3ASIC

SynopsysDesign CompilerNEC
Design Compiler

Design Compiler

2
5

A14353JJ3V0UM00

OPENCAD

1
OPENCAD
2
OPENCAD

3
.synopsys_dc.setup

4
NEC3MIN, TYP, MAX

NEC Design WareHDL

5
CTS, SCAN
HDL

6
NEC

A
BDIF.dif
C
D
ENEC Design Ware

A14353JJ3V0UM00

NEC ASICCAD NEC

OPENCAD

STA

A12866J

OPC_VSHELL

A14343J

A14344J

A14345J

TM

V.sim

A14346J
TM

ModelSim

Verilog
TM

VCS

TM

Vdraw

A14349J

A14351J
TM

PrimeTime

A14348J

A14350J

Tiara

A14347J

Design Compiler
TM

C.FGRADE

A14352J

A14354J

A14357J

OPENCAD

A14355J

NEC

A14353JJ3V0UM00

10

A14353JJ3V0UM00

117
1. 117
1. 1. 1VHDL18
1. 1. 2Verilog HDL19
1. 2Design Compiler20

221
2. 1OPENCAD21
2. 1. 121
2. 1. 221
2. 2Design Compiler23
2. 2. 1CTS23
2. 2. 223
2. 2. 323
2. 2. 4I/O24
2. 2. 5NEC Design Ware24
2. 2. 6MIN/MAX24
2. 3Verilog25
2. 3. 125
2. 3. 2MCOMROM25

327
3. 127
3. 1. 1NEC Design Ware28
3. 1. 228
3. 2Design Compiler29
3. 2. 1Synopsys29
3. 2. 230
3. 331
3. 3. 132
3. 3. 236

437
4. 137
4. 1. 137
4. 1. 239
4. 1. 339
4. 240
4. 2. 140

A14353JJ3V0UM00

11

4. 2. 243
4. 352
4. 3. 152
4. 3. 2CTS, SCAN53
4. 3. 3DPLLGTL53
4. 453
4. 4. 153
4. 4. 254
4. 5NEC Design Ware57
4. 5. 1NEC Design Ware57
4. 5. 2NEC Design Ware58
4. 5. 3HDL59
4. 5. 4moduleimplementation63
4. 6NEC Design Ware64

565
5. 165
5. 265
5. 366
5. 467
5. 567
5. 6NEC_SCAN68
5. 6. 168
5. 6. 269
5. 7BIST RAM71
5. 8CTS71
5. 8. 1CTS71
5. 8. 2CTS71
5. 8. 372
5. 9VHDL73
5. 10IPO74
5. 1175
5. 1275
5. 12. 1CB-8VX/VMCB-9VX/VMCB-10
CMOS-9HDEA-9HDEA-1075
5. 13F/FF/F80
5. 13. 1F/F80
5. 13. 2F/F80

681
6. 181
6. 281
6. 382
6. 482
6. 4. 1Verilog HDL82
6. 4. 2VHDL82
6. 582
12

A14353JJ3V0UM00

A87
BDIF.dif89
B. 189
B. 290
B. 2. 190
B. 2. 290
B. 391
B. 3. 1DIF91
B. 3. 2 91
B. 3. 391
B. 3. 494
B. 4DIF95
B. 5 96

C97
C. 197
C. 2PIASS97

D 99
ENEC Design Ware103
E. 1103
E. 2104
E. 3106
E. 3. 1NEC_SM01_ABSVAL106
E. 3. 2NEC_SM01_ADD108
E. 3. 3NEC_SM01_ADDSUB111
E. 3. 4NEC_SM01_ASH114
E. 3. 5NEC_SM01_BSH116
E. 3. 6NEC_SM01_CMP2118
E. 3. 7NEC_SM01_CMP6121
E. 3. 8NEC_SM01_DEC123
E. 3. 9NEC_SM01_DECODE126
E. 3. 10NEC_SM01_INC128
E. 3. 11NEC_SM01_INCDEC131
E. 3. 12NEC_SM01_SUB134
E. 3. 13NEC_SM02_MAC_TC137
E. 3. 14NEC_SM02_MAC_US139
E. 3. 15NEC_SM02_MULT_TC141
E. 3. 16NEC_SM02_MULT_US144
E. 3. 17NEC_SM02_SUM147
E. 3. 18NEC_SM03_BICTR_DECODE149
E. 3. 19NEC_SM03_BICTR_DCNTO152
E. 3. 20NEC_SM03_BICTR_SCNTO155
E. 3. 21NEC_SM03_CNTR_GRAY158

A14353JJ3V0UM00

13

E. 3. 22NEC_SM03_LFSR_DCNTO161
E. 3. 23NEC_SM03_LFSR_LOAD164
E. 3. 24NEC_SM03_LFSR_SCNTO167
E. 3. 25NEC_SM03_LFSR_UPDN170
E. 3. 26NEC_SM03_UPDN_CTR173
E. 3. 27NEC_SM04_FIFOCNTL_S_SF176
E. 3. 28NEC_SM04_FIFO_S_SF182
E. 3. 29NEC_SM04_STACK187
E. 3. 30NEC_SM05_ARBITER192
E. 3. 31NEC_SM05_PAR_GEN196

14

A14353JJ3V0UM00

11

VHDL18

12

Verilog HDL19

13

Design Compiler20

21

21

31

OPC_VSHELL29

32

Synopsys30

33

Configuration File30

41

41

42

CMOS-841

43

M65800_100area43

44

46

45

47

46

48

47

Synopsys49

48

Create Synopsys Timing Files50

49

Verilog52

51

ungroup-prefix67

52

69

53

70

54

70

55

CTS70

56

72

57

76

61

83

62

Convert Netlist Type83

63

84

64

Delete Floated Net84

65

Convert Netlist Type84

66

85

E1

8-bit LFSR104

E2

NEC_SM03_BICTR_DCNT154

E3

NEC_SM03_BICTR_SCNTO157

E4

NEC_SM04_FIFOCNTL_S_SF181

A14353JJ3V0UM00

15

31

Configuration File31

32

31

33

link_library, target_library33

34

33

35

CB-8VMlink_library, target_library34

36

symbol_library35

37

CB-8VMsymbol_library35

41

39

42

SDF43

43

44

44

44

45

Create Synopsys Timing Files51

46

NEC Design Ware57

51

77

61

81

A1

87

A2

87

B1

DIF90

B2

DIF90

B3

91

B4

PIA92

B5

EPIN92

B6

SPIN92

B7

CONDITION93

B8

UNV-PCI93

B9

PIN93

B10 94
B11 94
E1

8-bitLFSR105

E2

105

16

A14353JJ3V0UM00

1. 1
1112OPENCAD

Design Compiler

A14353JJ3V0UM00

17

1. 1. 1VHDL
11VHDL
MentorTMV8 I/F
Design ArchitectTM
Vdraw
siff

Vdraw

netlister

V.sim
netlist utility

VHDL

V.sim

PWC

EDIF

Synopsys I/F
VHDL_EXPAND.scr

Design Compiler

Set_load

VHDL

dc.sdf

back annotation

VSS I/F
VSS

G/A
galet floorplan

pdef

NEC_SRCHECK

def

scan buffer insertion

Sta.sdf

PWC.fix

nif

GateDRC

NEC_BSCHECK

set

NEC
nif

Sta.sdf

18

A14353JJ3V0UM00

1. 1. 2Verilog HDL
12Verilog HDL
Mentor V8 I/F
Design Architect
Vdraw
siff

Vdraw

netlister

V.sim
netlist utility

V.sim

PWC

Verilog HDL
Verilog I/F

Synopsys I/F

Verilog-XLTM
Design Compiler

set_load

dc.sdf

back annotation

G/A
galet floorplan

pdef

NEC_SRCHECK

def

scan buffer insertion

Sta.sdf

PWC.fix

nif

GateDRC

NEC_BSCHECK

set

NEC
nif

Sta.sdf

A14353JJ3V0UM00

19

1. 2Design Compiler
13Design Compiler

HDL

No

Yes

Gate DRC

No

Yes

No

Yes

No

20

Yes

A14353JJ3V0UM00

NEC

2. 1OPENCAD
2. 1. 1
OPENCAD V5.3115

VHDLVHDL

2. 1. 2
21

2$[]
164
=AZ09_
164

3$
132
=azAZ09_
132

A14353JJ3V0UM00

21

4$
1255
=azAZ09_$
1255

5Printable Character
ASCII0x210x7E
ASCII0x2C
1255
= 0x210x2B0x2D0x7E
1255

6Printable Character
ASCII0x210x7E
ASCII0x2C
1255
= 0x210x2B0x2D0x7E
1255

7$[]
1255
=azAZ09_$ []
1255

10

11

12OPENCAD
DBHIDBHODBHB
DBCLn+DBCLn-
DPPICONDPPOCONDPPBCON
DBCLAMP0DBCLAMP1

n19

22

A14353JJ3V0UM00

13ICIC

VDD, GND

Verilog HDL1415

14

15

1.$$2
$$1$50$888
$Y$N1$00A

2.5111
255

2. 2Design Compiler
2. 2. 1CTS
CTSGateDRC
GateDRCCTSDesign Compiler
Design Compiler
GateDRCCTS
Create Synopsys Timing Files
32SDFDesign Compiler
6 nsFCTS, FC44, FC843 nsFC42,
FC82CTS5. 8CTS

2. 2. 2
SynopsysNEC

F905, F906, F911, F912, F913, F914, F961, F962, F963, F964Lxxx, Yxxx, Sxxx

2. 2. 3

auto_wire_load_selection
falseOPENCAD.synopsys_dc.setup
false

A14353JJ3V0UM00

23

2. 2. 4I/O
CB-7CB-8I/O
GTLPLLDesign Compiler
io_pad
io_pad

dont_touch_network

2. 2. 5NEC Design Ware

1NEC Design Ware

2AC
3NEC Design WareOPENCAD.synopsys_dc.setup
4. 5. 2NEC Design Ware
4
Design Compiler V1997.01true
falseV1997.08

hdlin_make_dc_zero = true

hdlin_make_dc_zero = false
NEC_SM03_BICTRNEC_LFSR_SCNT0Count_to1/2

2. 2. 6MIN/MAX
Design Compiler 1998_02MINMAX
MIN/MAX

MIN/MAX

remove_min_max_pessimism = "true"

24

A14353JJ3V0UM00

2. 3Verilog
2. 3. 1
Verilog

NECNAME_RULE.scrVerilog
PWC

change_names_dont_change_bus_members = true
define_name_rules example-restricted"[]"-type net
define_name_rules example-restricted"[]"-type cell
change_names-rules example-hier-verbose

2. 3. 2MCOMROM
M_COMROMDesign Compiler3-State Function
ANDVerilogwand
PWCVerilogpwc
VerilogDesign Compilerwand

foreach(design_data, find(design, "*")){

current_design design_data;
foreach(wand_net, filter(find(net, "*") "@wired_and == true")[
remove_attribute wand_net wired_and;
}
}

A14353JJ3V0UM00

25

26

A14353JJ3V0UM00

3. 1
$OPC_PATH

lib

common designware dw_syn

NEC_SM0.sldb
nec_sm0

.mra
.syn

seriese

condition

synopsys

synopsys_
object

NEC Design Ware

analog
basic
primitive
special
clockdriver
iobuffer
mega

nec_scan
nec_bscan
oscillator
scan
script

memory
BUS_EXPAND_VHDL.scr
BUS_EXPAND_VHDL_MENTOR.scr
EDIF_WRITE.scr
NAME_RULE.scr
NEC_SCAN_USE.scr
VHDL_WRITE.scr
VHDL_WRITE_MENTOR.scr
CMOS_IOSYN.scr
CMOS_TTL_IOSYN.scr

wire_model

WIRE_.lib
WIRE_.db

Technology.map

A14353JJ3V0UM00

SIFFmap

27

3. 1. 1NEC Design Ware

NEC_DesignWare

$OPC_PATH/lib/common/designware/<DesignWareDir>

DesignWareDir

dw_1997.01, dw_1997.08, dw_1998.02, dw_1998.08

3. 1. 2

$OPC_PATH/lib/<series>/<condition>/synopsys

script/

wire_model/ wire_model
object/

Design Compiler

object
xx_MAX_xx.db
xx_TYP_xx, dbMIN, TYP, MAX
xx_MIN_xx.db
xx_SYMBOL_xx.sdb
XX_ATG_xx.db ATGMIN, TYP, MAX

28

A14353JJ3V0UM00

3. 2Design Compiler
OPENCADDesign Compiler

3. 2. 1Synopsys
1OPC_VSHELL
OPC_VSHELL

%OPC_VSHELL

CR

2OPC_VSHELL
1OPC_VSHELL31

31OPC_VSHELL

3Synopsys
31Logic Synthesissynopsys
Logic Synthesis

A14353JJ3V0UM00

29

4Synopsys
3SynopsysSynopsys32

32Synopsys

3. 2. 2
Synopsys

1Set Configuration
32SynopsysSet Configuration File

32Exit

2Configuration File
1Set Configuration FileConfiguration File33

33Configuration File

30

A14353JJ3V0UM00

31Configuration File

Select Synopsys Version

OPENCADDesign Analyzer

OPENCAD V5.3 OPENCADA14355J

Delay Type

Synopsys .cshrc

Synopsys Root Directory

$SYNOPSYS

Use Design Ware

NEC Design Ware

NEC Design Ware
NEC Design Ware2

Use Complied modules

MCOM

Execute/Close

Execute
Close

Configuration File

3. 3
33Configuration File.synopsys_dc.setup

32

32

Search_path

link_library

target_library

Symbol_library

Synthetic_library

NEC_SM0.sldb

Define_design_library

NEC_SM0-path synlib_root

+dw.syn_/nec_sm0
auto_wire_load_selection

false

auto_link_disable

false

Vhdlout_use_packages

IEEE.STD_LOGIC_1164

A
B

1.32
2.NEC Design Ware
hdlin_make_dc_zero2

A14353JJ3V0UM00

31

3. 3. 1
1search_path
ab
NEC Design Ware

SynopsysGtech

<OPENCAD>/synopsys/object

<OPENCAD>/synopsys/wire_model

<Module Path>/lib/<series>/<condition>

NEC Design Ware

4. 5NEC Design Ware

5. 4

2link_library, target_library
3334

link_library
NEC_SCANnec_scan

alink_library
33
33

search_path
NEC Design Ware
4. 5NEC Design Ware

32

A14353JJ3V0UM00

btarget_library
target_library
33
33

33link_library, target_library

Basic

Primitive

Special

Analog

Clockdriver

FCxx

CTS

Iobuffer

I/F

I/F

Mega

nec_scan

NEC_SCAN

DFTNEC_SCAN

nec_bscan

DFTNEC_BSCAN

Oscillator

Scan

MUX

NEC_SCAN

Memory

BASIC RAM,

BASIC RAM, ROM

ROM

IC

5. 4

34

TA

VDD

MIN

TYP

typical

MAX

A14353JJ3V0UM00

33

cCB-8VM
CB-8VM35

35CB-8VMlink_library, target_library

object/basic

CBC8VM_CMOS_33V_MAX_BASIC.db
CBC8VM_CMOS_33V_TYP_BASIC.db
CBC8VM_CMOS_33V_MIN_BASIC.db

object/primitive

CBC8VM_CMOS_33V_MAX_PRIM.db
CBC8VM_CMOS_33V_TYP_PRIM.db
CBC8VM_CMOS_33V_MIN_PRIM.db

object/analog

CBC8VM_CMOS_33V_ANALOG.db

object/clockdriver

CBC8VM_CMOS_33V_MAX_DRIVE.db
CBC8VM_CMOS_33V_TYP_DRIVE.db
CBC8VM_CMOS_33V_MIN_DRIVE.db

object/iobuffer

CBC8VM_CMOS_33V_ATG_IO.db
CBC8VM_CMOS_33V_MAX_IO.db
CBC8VM_CMOS_33V_TYP_IO.db
CBC8VM_CMOS_33V_MIN_IO.db

object/mega

CBC8VM_CMOS_33V_MEGA.db

object/nec_scan

CBC8VM_CMOS_33V_MAX_NSCAN.db
CBC8VM_CMOS_33V_TYP_NSCAN.db
CBC8VM_CMOS_33V_MIN_NSCAN.db

object/oscillator

CBC8VM_CMOS_33V_MAX_OSC.db
CBC8VM_CMOS_33V_TYP_OSC.db
CBC8VM_CMOS_33V_MIN_OSC.db

object/scan

CBC8VM_CMOS_33V_MAX_SCAN.db
CBC8VM_CMOS_33V_TYP_SCAN.db
CBC8VM_CMOS_33V_MIN_SCAN.db

object/special

CBC8VM_CMOS_33V_MAX_SPECIAL.db
CBC8VM_CMOS_33V_TYP_SPECIAL.db
CBC8VM_CMOS_33V_MIN_SPECIAL.db

NEC

34

A14353JJ3V0UM00

3symbol_library
link_library, target_library
36

36symbol_library

Basic

Primitive

Special

Clockdriver

FCKx

CTS

Iobuffer

I/F

I/F

nec_scan

NEC_SCAN

DFTNEC_SCAN

nec_bscan

DFTNEC_BSCAN

Oscillator

Scan

MUX

NEC_SCAN

Memory

BASIC RAM,

BASIC RAM, ROM

ROM

IC

37CB-8VM

37CB-8VMsymbol_library

object/basic

CBC8VM_CMOS_33V_SYMBOL_BASIC.sdb

object/primitive

CBC8VM_CMOS_33V_SYMBOL_PRIM.sdb

object/clockdriver

CBC8VM_CMOS_33V_SYMBOL_DRIVE.sdb

object/iobuffer

CBC8VM_CMOS_33V_SYMBOL_IO.sdb

object/nec_scan

CBC8VM_CMOS_33V_SYMBOL_NSCAN.sdb

object/oscillator

CBC8VM_CMOS_33V_SYMBOL_OSC.sdb

object/scan

CBC8VM_CMOS_33V_SYMBOL_SCAN.sdb

object/special

CBC8VM_CMOS_33V_SYMBOL_SPECIAL.sdb

4synthetic_library
NEC Design Ware
NEC Design WareOPC_VSHELL

4. 5NEC Design Ware

A14353JJ3V0UM00

35

5define_design_library
NEC Design Ware
NEC Design WareOPC_VSHELL

4. 5NEC Design Ware

6vhdlout_use_package
VHDLModelSim
OPENCAD V5.3 ModelSim
A14347J

3. 3. 2
NEC

1auto_wire_load_selection
true
NEC

false

true
4. 2. 1

2auto_link_disable
trueset_load

link
set_load
false
4. 2. 2

36

A14353JJ3V0UM00

4. 1
4. 1. 1
NECMINBESTTYP, MAXWORST3

MIN MIN.db
TYP TYP.db
MAX MAX.db

local_link_library
local_link_libraryset_local_link_library
2

link_library, target_librarylocal_link_library
link

set_loacl_link_library
link_library =
target_library =
link

A14353JJ3V0UM00

37

CMOS-8
set_loacl_link_library{
CMOS8_CMOS_5V_MAX_BASIC.db
CMOS8_CMOS_5V_MAX_DRIVE.db
CMOS8_CMOS_5V_MAX_IO.db
CMOS8_CMOS_5V_MEGA.db
CMOS8_CMOS_5V_MAX_MEM.db
CMOS8_CMOS_5V_MAX_BSCAN.db
CMOS8_CMOS_5V_MAX_NSCAN.db
CMOS8_CMOS_5V_MAX_OSC.db
CMOS8_CMOS_5V_MAX_PRIM.db
CMOS8_CMOS_5V_MAX_SCAN.db
CMOS8_CMOS_5V_MAX_SPECIAL.db
NEC_SM01.sldb
NEC_SM02.sldb
NEC_SM03.sldb
NEC_SM04.sldb
NEC_SM05.sldb};
link_library = {"*"
CMOS8_CMOS_5V_MAX_BASIC.db
CMOS8_CMOS_5V_MAX_DRIVE.db
CMOS8_CMOS_5V_MAX_IO.db
CMOS8_CMOS_5V_MEGA.db
CMOS8_CMOS_5V_MAX_MEM.db
CMOS8_CMOS_5V_MAX_BSCAN.db
CMOS8_CMOS_5V_MAX_NSCAN.db
CMOS8_CMOS_5V_MAX_OSC.db
CMOS8_CMOS_5V_MAX_PRIM.db
CMOS8_CMOS_5V_MAX_SCAN.db
CMOS8_CMOS_5V_MAX_SPECIAL.db
NEC_SM01.sldb
NEC_SM02.sldb
NEC_SM03.sldb
NEC_SM04.sldb
NEC_SM05.sldb};
target_library = {"*"
CMOS8_CMOS_5V_MAX_BASIC.db
CMOS8_CMOS_5V_MAX_DRIVE.db
CMOS8_CMOS_5V_MAX_IO.db
CMOS8_CMOS_5V_MEGA.db
CMOS8_CMOS_5V_MAX_MEM.db
CMOS8_CMOS_5V_MAX_BSCAN.db
CMOS8_CMOS_5V_MAX_NSCAN.db
CMOS8_CMOS_5V_MAX_OSC.db
CMOS8_CMOS_5V_MAX_PRIM.db
CMOS8_CMOS_5V_MAX_SCAN.db
CMOS8_CMOS_5V_MAX_SPECIAL.db}
link

38

A14353JJ3V0UM00

4. 1. 2
41

41
Design Compiler

TYP

HDL
report-cell

MAX

wire_load

max_delay, CLK

MAX

incrimental_mapping

dont_touch

MIN

wire_load

min_delay, CLK
MIN

prioritize_min_paths

MIN/MAX

Synopsys

4 KB

4. 1. 3
Design Compiler

HDL
CTS
dont_touch

A14353JJ3V0UM00

39

4. 2
2
4. 2. 1
4. 2. 2

4. 2. 1
2
NEC
floorplan_manager

1NEC

a
NEC

2libdb

i
set_wire_load
libdb-mode_enclosed

T
T65800-mode_enclosed

ii

M_

40

M65800_10000

lib

M65800_10000-library WIRE_65800

db

A14353JJ3V0UM00

4141lib

41

dc_shell>set_wire_load "T65800"-mode_enclosed

TOP

dc_shell>current_design = A
dc_shell>set_wire_load "M65800_10000"

dc_shell>current_design = B
dc_shell>set_wire_load "M65800_10000"
dc_shell>current_design = TOP

b
CMOS-8

42CMOS-8

CMOS-8

TOP
CC

IO0

IO4
TOP

IO1

AA
8530
BB100

BB
100

AA
IO5

IO2

BB

CC

IO6
IO3

auto_wire_load_selection = "false"

dc_shell>current_design =
dc_shell>link
dc_shell>update_lib <> -overwrite WIRE_.lib

lib

db

read WIRE_.db

1
CMOS-8

A14353JJ3V0UM00

41

dc_shell>current_design = TOP
lib

dc_shell>link

dc_shell>update_lib CMOS8_CMOS_5V_MAX_BASIC -overwrite WIRE_65800.lib

db

read WIRE_65800.db

dc_shell>set_wire_load "T65800" mode enclosed

dc_shell>current_design = AA
lib

dc_shell>set_wire_load "M65800_9000"
set_wire_load M65800_9000-library WIRE_65800

db

AA8530
9000

AAAA
BB
BBAA

ICgrid

carea
area
Design Compiler

i
Design Compiler
Combinational/Noncombinational areaTotal area
area

iiarea
A, B
A, B
o =i1i2i3
areaB

42

A14353JJ3V0UM00

areafanout_lengh
area1area
M65800_100fanout_lengh = 0.525483area = 0.000001

Aarea fanout_lengtharea = 0.5254830.0000015 = 0.000003

Barea fanout_lengtharea = 0.5254830.0000014 = 0.000002

43M65800_100area
B

A
I1
I1
I2
I2

L312 2

I3

I3

L421 3

L202 1

area = 210.000003area = 30.000002

= 3.000003

= 3.000002

areaB

2floorplan_manager
PDEFfloorplan_manager

SynopsysFloorplan Manager

4. 2. 2
1Design Compiler

aDesign Compiler
Design Compiler
SDFNIF242

42SDF

SDF

report
compileSDF

IPOIn Place Optimization

Design Compiler
SDF
NIFset_load

A14353JJ3V0UM00

43

43
4. 2. 224. 2. 23

43

IPO

set_load

set_load

SDF

set_load

set_load

SDF

set_loadIPO-in_place
IPOwire_model

44

SDF

IOPATH

SDFset_load

SDF
IOPATHSDFINTERCONNECT

SDFset_load

IPO

IPO

max_capacitance

2
SDFset_load

aSDF
SDFDesign Compiler

44

A14353JJ3V0UM00

iV1997.01, V1997.08

MAX
sdfin_rise_cell_delay_type = "maximum"
sdfin_fall_cell_delay_type = "maximum"

MIN
sdfin_rise_cell_delay_type = "minimum"
sdfin_fall_cell_delay_type = "minimum"

SDF
read_timing-format sdf sdf

iiV1998.02, V1998.08

MAX
SDF
read_timing-max_triplet format sdf sdf

MIN
SDF
read_timing-min_triplet minimum max_triplet none -format sdf sdf

bset_load
set_loadinclude
include *.scr

set_load

include -quiet*.scr

falsetrue1/3
auto_link_disable = "true"

includetruefalse

nifset_load

A14353JJ3V0UM00

45

3
NEC
OPC_VSHELLSDFset_load

a
NEC 44

45

46

44

DIF

Create Synopsys Timing Files

OPC_NETDELAY

NIF

.static.sdf
.ringN.static.sdf

opc_nif2syn

OPC_SDF2SDF

XXX.set_load.scr

XXX.DC.sdf
XXX.Static.sdf

Design Compiler

46

A14353JJ3V0UM00

45

DIF

.dc_fp.es.nif

.fp.es.Universal.sdf
.ringN.fp.es.Universal.sdf
Create Synopsys Timing Files

opc_nif2syn

OPC_SDF2SDF

XXX.set_load.scr

XXX.DC.sdf
XXX.Static.sdf

Design Compiler

A14353JJ3V0UM00

47

46

DIF

.dc_hier.pr.nif

.hier.pr.Universal.sdf
.ringN.hier.pr.Universal.sdf
Create Synopsys Timing Files

opc_nif2syn

OPC_SDF2SDF

XXX.set_load.scr

XXX.DC.sdf
XXX.Static.sdf

Design Compiler

48

A14353JJ3V0UM00

iSynopsys47Create Synopsys Timing Files

47Synopsys

A14353JJ3V0UM00

49

iiCreate Synopsys Timing Files

iCreate Synopsys Timing Files48
48sdfset_load

48Create Synopsys Timing File

50

A14353JJ3V0UM00

45Create Synopsys Timing Files

Netlist Type

PWS, EDIF, Verilog HDL, VHDL

Netlist File Name

Create New SDF File & NIF File

SDFSet_load Script
Create New SDF File & NIF File

SDF
Create New SDF File & NIF File

DIF File Name & DIF Condition

DIF

NIF File Name

NIF

SDF File Name

Complete SDFIO Ring SDF

Complete, IO Ring

1Complete SDF

Set_load Delay Type

DIF3MINTYPMAX
MINMAX
Set_load Script File Name

Set_load Script File Name

Set_load ScriptDesign Compiler

Execute/Close

Execute
Close

Create Synopsys Timing Files

Design Compiler

4VHDL
SDFVHDLPWC

Design CompilerVHDLSDF
SDF

atr
tr'[a-z]''[A-Z]'<>

bPWCVHDL
VHDLPWCVHDL

A14353JJ3V0UM00

51

4. 3
NEC

CTS, SCAN
DPLLGTL

4. 3. 1
CPURAM

Verilog

49Verilog

ab

Verilog
MEGAMACRO1

DI30

52

MEGAMACRO1

DO30

A14353JJ3V0UM00

DI3

DO3

DI2

DO2

DI1

DO1

DI0

DO0

49

module TOP(X, X,..DI, DO,.......)

input X, X, X,,....;
input [3:0] DI;
output X, X, X, t,....;
output [3:0] DO;

MEGAMACRO1 iotop1(DI0(DI[0]), DI1(DI[1]), DI2(DI[2]), DI3(DI[3]),

DO0(DO[0]), DO1(DO[1]), DO2(DO[2]), DO3(DO[3])),

end_module

4. 3. 2CTS, SCAN
CTS, SCAN

4. 3. 3DPLLGTL
DPLLGTL

4. 4
4. 4. 1
1
OPENCADDesign CompilerI/O
2

DRC
NECI/F

A14353JJ3V0UM00

53

4. 4. 2
1
dont_useOPENCAD
CMOS_IOSYN.scrCMOSCMOSTTL_IOSYN.scrCMOS&TTLTTL_IOSYN.scrTTL
dont_use

CMOS
include CMOS_IOSYN.scr

CMOS&TTL
include CMOS_TTL_IOSYN.scr

TTL
include TTL_IOSYN.scr

CMOS_IOSYN.scr, CMOS_TTL_IOSYN.scr, TTL_IOSYN.scr

UNIX

CMOS-8
% sed 's/_MIN/_MAX/g' CMOS_IOSYN.scr>CMOS_IOSYN_MAX.scr

2
dc_shelldesign_analyzercommand_window

aTOPport_is_pad
current_design = TOPTOP
set_port_is_pad TOP or port_list

b
set_pad_type exact xxxxport_list

c
insert_pads

synopsysDesign Compiler

54

A14353JJ3V0UM00

3HDL
Verilog HDLVHDL
TOPport_is_pad

insert_pads
set_pad_type exact

synopsys
Verilog HDLVHDL

aVerilog HDL

module decoder(a, b);

input [3:0]a;
output[3:0]b;

//synopsys dc_script begin

//set_port_is_pad a
//set_port_is_pad b
//set_pad_type -exact FI01 a

HDL

//set_pad_type -exact FO01 b

//synopsys dc_script_end

assign b [3] = (a == 4'a3) ;

assign b [2] = (a == 4'a2) ;
assign b [1] = (a == 4'a1) ;
assign b [0] = (a == 4'a0) ;

endmodule

A14353JJ3V0UM00

55

bVHDL

-- decoder, vhd
library IEEE;
use IEEE.std_logic_1164.all;

entity decoder is
port (
decimal:out STD_LOGIC_VECTOR(9 downto 0) ;
BCD

:in STD_LOGIC_VECTOR(3 downto 0)

);
end decoder;

architecture STRUCT_decoder of decoder is

-- pragma dc_script_begin
-- set_port_is_pad decimal
-- set_port_is_pad BCD
-- set_pad_type -exact FO01 decimal

VHDL

-- set_pad_type -exact FI01 BCD

-- pragma dc_script_end

begin
P:process(BCD)
begin
case BCD(3 downto 0)is
when "0000" => decimal <= "0000000001" ;
when "0001" => decimal <= "0000000010" ;
when "0010" => decimal <= "0000000100" ;
when "0011" => decimal <= "0000001000" ;
when "0100" => decimal <= "0000010000" ;
when "0101" => decimal <= "0000100000" ;
when "0110" => decimal <= "0001000000" ;
when "0111" => decimal <= "0010000000" ;
when "1000" => decimal <= "0100000000" ;
when "1001" => decimal <= "1000000000" ;
when others => decimal <= "0000000000" ;
end case;
end process P;
end STRUCT_decoder;

56

A14353JJ3V0UM00

4. 5NEC Design Ware

4. 5. 1NEC Design Ware
NEC Design Ware
OPENCAD V5.3

OPENCADA14355J

NEC Design WareNECSynopsys

Design Ware

46NEC Design Ware1/2

NEC_SM01

NEC_SM02
Advanced

Absolute Value

RPL, CLA, BLC

Adder

RPL, CLA, BLC

Subtractor

RPL, CLA, BLC

Adder-Substractor

RPL, CLA, BLC

Incrementor

RPL, CLA, BLC

Decrementor

RPL, CLA, BLC

Incrementer-Decrementor

RPL, CLA, BLC

2-Function Comparator

6-Function Comparator

Decoder

Arthmetic Shiffer

Barrael Shiffer

Multiplier2s complement

CSA, WALL

Multiplierunsigned

CSA, WALL

Multiplier-Accumulator2s complement

CSA, WALL

Multiplier-Accumulatorunsigned

CSA, WALL

Vector Adder
NEC_SM03
Counter

RPL, CSA, WALL

Up/Down Binary Counter with Dynamic Count-to Flag

Up/Down Binary Counter with Static Count-to Flag

Up/Down Binary Counter with Output Decode

Gray Code Counter

LFSR Counter with Dynamic Count-to Flag

LFSR Counter with Static Count-to Flag

LFSR Counter with Output Decode

LFSR Up/Down Counter

Up/Down Counter

RPL, CLA, BLC

A14353JJ3V0UM00

57

46NEC Design Ware2/2

NEC_SM04

NEC_SM05

Syncronous FIFO with Static Flag Logic

Syncronous FIFO Controller with Static Flag Logic

Syncronous Stack

Parity Generator and Checker

Round Robin Arbiter

OPENCADA14355J

4. 5. 2NEC Design Ware

NEC Design Ware14
synopsys_root, library_root, synlib_root, library
OPC_VSHELL

synopsys_root Design Compiler

OPC_PATH

OPENCAD

1
search_path = {.
<OPC_PATH>lib/common/designware/dw_syn<Synopsys>};
/usr/nec/ss2/lib/common/designware/dw_syn3.5a

2
link_library = {};

3
synthetic_library = {NEC_SM01.sldb};
synthetic_library = {NEC_SM02.sldb};

4
define_design_lib NEC_SM01 path synlib_root+"/dw_syn<Synopsys>"+"/nec_sm01"
define_design_lib NEC_SM02 path synlib_root+"/dw_syn<Synopsys>"+"/nec_sm02"

58

A14353JJ3V0UM00

4. 5. 3HDL
HDLanalyzeelaborate
read

analyze

analyze format

elaborate

elaborate

HDL2

Operator Inferencing
Component Instantiation

12

1Operator Inferencing
HDLHDL Operator
HDL Operatordecorder
HDL OperatorADDER

Verilog HDLsignedOperator Inferencing

Component Instantiation
Multiplier2s complement
Multiplier-Accumulator2s complement

A14353JJ3V0UM00

59

aVHDL
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity ADDER is
port(in1, in2 :in_std_logic_vector(7 downto 0);
sum

:out std_logic_vector(7 downto 0);

end ADDER;

architecture impl of ADDER is

signal in1_signed, in2_signed, sum_signed:SIGNED(7 downto 0);

begin
in1_signed <= SIGNED (in1) ;
in2_signed <= SIGNED (in2) ;

--infer the addtion operator(+)

sum_signed <= in1_signed+in2_signed;

sum <= STD_LOGIC_VECTOR(sum_signed)

end impl;

bVerilog
module adder(in1, in2, sum);
input[7:0]in1, in2;
output[7:0]sum;

//infer the addition operator(+)

assign sum = in1+in2;
endmodule

60

A14353JJ3V0UM00

2Component Instantiation
HDLNEC_SM01_ADD

aVHDL
library IEEE;
use IEEE.std_logic_1164.all;

entity ADDER is
port(in1, in2 :in std_logic_vector(7 downto 0);
carry_in :in std_logic;
sum

:out std_logic_vector(7 downto 0);

carry_out :out std_logic);

end ADDER;

architecture impl of ADDER is

--declare the component NEC_SM01_ADD
component NEC_SM01_ADD
generic(Width:Integer)
port(A, B :in std_logic_vector(Width-1 downto 0);
CI

:in std_logic;

SUM :out std_logic_vector(Width-1 downto 0);

CO

:out std_logic);

end component;
begin
--instantiate NEC_SM01_ADD
U1:NEC_SM01_ADD
generic map(Width => 8)
port map(A => in1, B => in2, CI => carry_in, SUM => sum,
CO => carry_out);
end impl;

bVHDL
VHDL

NEC_SM01_COMPONENTS
VHDLuse

A14353JJ3V0UM00

61

library IEEE, NEC_SM01;

use IEEE.std_logic_1164.all;
use NEC_SM01.NEC_SM01_COMPONENTS.all;

entity ADDER is
port(in1, in2 :in std_logic_vector(7 downto 0);
carry_in :in std_logic;
sum

:out std_logic_vector(7 downto 0);

carry_out :out std_logic);

end ADDER;

architecture impl of ADDER is

begin
--instantiate NEC_SM01_ADD
U1:NEC_SM01_ADD
generic map(Width => 8)
port map(A => in1, B => in2, CI => carry_in, SUM => sum,
CO => carry_out);
end impl;

cVerilog
module adder(in1, in2, carry_in, sum, carry_out);
parameter wordlength = 8;
input[wordlength-1:0]in1, in2;
input carry_in;
output[wordlengh-1:0]sum;
output carry_out;

//instantiate NEC_SM01_ADD
NEC_SM01_ADD # (wordlength)U1(in1, in2, carry_in, sum, carry_out);

endmodule

62

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4. 5. 4moduleimplementation
moduleimplementationHDL

CLA implementationab

aVHDL
library IEEE, NEC_SM01, synopsys;
use IEEE.std_logic_1164.all;
use synopsys.attributes.all;
use NEC_SM01.NEC_SM01_COMPONENTS.all;

entity ADDER is
port(in1, in2 :in std_logic_vector(7 downto 0);
carry_in :in std_logic;
sum

:out std_logic_vector(7 downto 0);

carry_out :out std_logic);

end ADDER;

architecture impl of ADDER is

attribute inplementation of U1:label is "CLA";
begin
--instantiate NEC_SM01_ADD
U1:NEC_SM01_ADD
generic map(Width => 8)
port map(A => in1, B => in2, CI => carry_in, SUM => sum,
CO => carry_out);
end impl;

A14353JJ3V0UM00

63

bVerilog
module adder(in1, in2 carry_in, sum, carry_out);
parameter wordlengh = 8;
input[wordlengh-1:0]in1, in2;
input carry_in;
output[wordlengh-1:0]sum;
output carry_out;

/* synopsys dc_script_begin
set_implementation CLA U1
*/

//instantiate NEC_SM01_ADD
NEC_SM01_ADD # (wordlengh)U1(in1, in2, carry_in, sum, carry_out);

endmodule

4. 6NEC Design Ware

1Arithmetic ShifterNEC_SM01_ASH
Arithmetic ShifterSH_Widthlog2bit

16 bitSH_Width
SH_Width = log216 = 4
2NEC Design Ware
DecoderNEC_SM01_DECODE
8-bit
SM03, SM04bit

NEC_SM03_BICTR_DECODE

Width = 8

NEC_SM03_BICTR_SCNTO

Width = 16

NEC_SM03_CNTR_GRAY

Width = 8

NEC_SM03_LFSR_SCNTO

Width = 16

NEC_SM04_FIFO_S_SF

Width = 9, Depth = 15

NEC_SM04_STACK

Width =16, Depth = 15

64

A14353JJ3V0UM00

5. 1
Design Analyzer2

Design Analzer
OPC_VSHELL SynopsysExcute Design Analyzer
dc_shell
OPC_VSHELL SynopsysExcute Design Compiler

5. 2
1
Design CompilerpF
pF
A

aCMOS-N5, CMOS-6/8/8L/8LHD/9EA-9QB-8
set_max_fanout

bCMOS-9HDEA-9HDEA-10CB-8VX/VMCB-9
VX/VMCB-10
set_max_capacitance

2
CMOS-9HDEA-10

1L101 get_attribute

L1011.0

aCMOS-N5, CMOS-6/8/8L/8LHD/9EA-9QB-8
CMOS-8

dc_shell>get_attribute CMOS8_CMOS_5V_MAX_BASIC/L101/H01 fanout_load

A14353JJ3V0UM00

65

10set_max_fanout

dc_shell>set_max_fanoutget_attribute*10

bCMOS-9HDEA-9HDEA-10CB-8VX/VMCB-9
VX/VMCB-10
CB-8VX

dc_shell>get_attribute CBC8VX_CMOS_33_V_MAX_BASIC/L101/H01 capacitance

10set_max_capacitance

dc_shell>set_max_capacitanceget_attribute*10

5. 3
1uniquify
NECuniquify
uniquify-forcedont_touch

2ungroup
compile-ungroup_all
ungrouptrue
Design Compilerungroup
/
VHDL//
VHDL
ungroup-prefix
/

66

A14353JJ3V0UM00

51ungroup-prefix
TOP

TOP

AAA

AAA

AAA/B

AAA_B
ungroup B-prefixAAA_

5. 4
NECDesign Compilerdb
.db
search_path
object/memory
dont_touchungroup, uniquify

RAM

RAMBIST
RAM

RJxx RKxx RBxx

BIST

RUxx

xx

5. 5
NECFCK

LSI
1dont_touch

A14353JJ3V0UM00

67

5. 6NEC_SCAN
NECNEC_SCANFULLSCAN
Design Compiler
A14357JNEC_SCAN

NEC_SCAN

5. 6. 1
1dont_use
OPENCAD1SCAN_USE.scr
NEC_SCANF/Fdont_useF/F
NEC_SCAN3dont_use

SCAN_USE.scrCompile

SCAN_USE.scr
UNIX

CMOS-8
% sed 's/_MIN/_MAX/g' SCAN_USE.scr>SCAN_USE_MAX.scr

sbinsNEC

NEC
sbinsSCAN

68

A14353JJ3V0UM00

4Design CompilerDRCSCAN

5. 6. 2
NEC_SCAN

52

A14353JJ3V0UM00

69

53

54

SCD1

Y
Z

sbins

3CTSSCAN
CTSSCAN2F/F
CTS55

55CTS

CTS

SCD1

Y
Z

sbins

2CTS
Design CompilerF/F

70

A14353JJ3V0UM00

CTSdont_touch_network

5. 7BIST RAM
NECBIST RAMRAM BISTRAMBIST

Design CompilerBISTBISTRAM

5. 8CTS
CTS
F/F

CTS

5. 8. 1CTS
CTS
dont_useCTS
CTS
CTS

CTS
dont_touch_network

5. 8. 2CTS
CTS

FC42, FC82

3 ns

FCTS, FC44, FC84 6 ns

2CTS
0.4 ns

3CTS
0 ns

A14353JJ3V0UM00

71

4
3

Design Compiler

aset_clock_skew uncertainlyobject_list
bset_clock_skew plus_uncertainlyobject_list
cset_clock_skew minus_uncertainlyobject_list

report_timingpropagated
SYNOPSYS
NEC

5. 8. 3
FI08, FCK1Design Compiler56
1

56

bDesign Compiler

D/5
D/5
D/5
D/5

D/5

D/5

single_out

72

A14353JJ3V0UM00

5. 9VHDL
VHDL

1
VHDL
VHDLSynopsysIEEE.STD_LOGIC_1164mvl9

avhdlout_bit_type = "STD_LOGIC";
bvhdlout_bit_vector_type = "STD_LOGIC_VECTOR";
cvhdlout_use_packages = {"IEEE.STD_LOGIC_1164"};

2
VHDL Design Compiler VHDL
Synopsys
VHDLDesign Compiler

3VHDL
VHDLOPC_VITAL

BUS_EXPAD_VHDL.scr VHDL
OPC_VITAL
OPC_VITAL

BUS_EXPAD_VHDL.scr

vhdlout_use_packages = {"IEEE.STD_LOGIC_1164;library OPC_VITAL;use OPC_VITAL.all"};

VHDL

Library IEEE;
use IEEE.std_logic_1164.all;library OPC_VITAL;use OPC_VITAL.all;

A14353JJ3V0UM00

73

5. 10IPO
1IPO
IPODesign Compiler1
compile-in_place
IPO

IPO

IPOECO TAT

IPOSynopsyssdf
psd4. 2. 2

ECO

IPO

2
IPO

compile_no_new_cells_at_top_level = "false"
compile_ignore_area_during_inplace_opt = "true";
compile_ignore_footprint_during_inplace_opt = "true";
compile_ok_to_buffer_during_inplace_opt = "true";
compile_disable_area_opt_during_inplace_opt = "false";
compile_update_annotated_delays_during_inplace_opt = "true";
compile_dont_touch_annotated_cell_during_inplace_opt = "false";

IPOSynopsys

a
b
c
d

ECOTAT
ECOIPONEC

IPO

reoptimize_design_changed_list_file_name = in_place.rep

74

A14353JJ3V0UM00

5. 11
NECANDORF4XX, L4XX

NEC

5. 12
5. 12. 1CB-8VX/VMCB-9VX/VMCB-10
CMOS-9HDEA-9HDEA-10

Synopsys

Design Compiler

A14353JJ3V0UM00

75

57

1
NG

OK

Yes

No

OK

Gate DRC

NG

NG

OK
NEC

76

A14353JJ3V0UM00

51

synopsys_dc.setup

HDL

NEC

Gate DRC

NG

1
NIF

NIF

a
4. 2. 2

NEC

Design CompilerNIF

b
Design Compiler
4. 2. 2

A14353JJ3V0UM00

77

creport_constraint
report_constraintNG
_cWIRE_LOAD
_cdont_touch

include3
IPOIPO5. 10
IPO

aIPO
IPO
Synopsys
compile_no_new_cells_at_top_level = "false";
compile_ignore_area_during_inplace_opt = "true";
compile_ignore_footprint_during_inplace_opt = "true";
compile_ok_to_buffer_during_inplace_opt = "true";
compile_disable_area_opt_during_inplace_opt = "false";
compile_update_annotated_delays_during_inplace_opt = "true";
compile_dont_touch_annotated_cell_during_inplace_opt = "false";

IPO

IPOinclude

bIPO
IPO

compile_inplace_changed_list_file_name = in_place.rep

cIPO

compile-in_place

78

A14353JJ3V0UM00

5
14
NEC

Design Compiler

set_capacitance

IPO

IPO

1
IPO

aNIF
b
% current_design

cWIRE

% set_wire_load "Mxxx"-library ""

ddont_touch

% set_max_capacitance 10.0 ""

% set_dont_touch find(net, "*")

edont_touch
% set_dont_touch find(net, "")false

f-only_design_rulecompile
% compile -only_design_rule

NEC
IPO

WIRE_LOAD1

A14353JJ3V0UM00

79

5. 13F/FF/F

F/F
F/FDesign Compiler

5. 13. 1F/F
F/F

VerilogCLK_NEGAF/F
F637

read -f verilog/

create_clock -p 20 {CLK_POSE,CLK_NEGA}/

neg_ff = all_fanout(-from CLK_NEGA -only_cell)

foreach(regs,neg_ff) {
set_register_type -flip_flop F637 -exact reg
}
compile

5. 13. 2F/F
Design Compiler

F/F
F/F

F617 - F637

Design Compiler
F/F
F/Fdont_use

80

A14353JJ3V0UM00

6. 1
OPENCAD

NEC
OPENCAD2

61

64

32

255

255

ASCII0x210x7E

255

0x2C

6. 2
1
2

define_name_rules"OpenCAD"-max_length"255"-allowed"a-zA-Z0-9_!@#$%^&*()-+=|~'{}[];
:'<>,.?/"-type cell
define_name_rules"OpenCAD"-max_length"255"-allowed"a-zA-Z0-9_!@#$%^&*()-+=|~'{}[];
:'<>,.?/"-type net
define_name_rules"OpenCAD"-max_length"255"-allowed"a-zA-Z0-9_[]"-type port

define_name_rules"OpenCAD"-case_insensitive

VHDLEDIF

3report_names -rulesOpenCAD
CRT

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81

6. 3

dc_shell>change_names -rules OpenCAD -h

6. 4
NEC
Verilog HDLVerilog HDL
EDIFEDIF
BUS

6. 4. 1Verilog HDL
Verilog HDL

write -f verilog-h -o

6. 4. 2VHDL
VHDLEDIF
SynopsysBUS_EXPAND_VHDL.scr
VHDLSYNOPSYS db
EDIF

scriptBUS_EXPAND_VHDL.scr
DESIGN_FILE_NAME
DESIGN_TOP_NAME
dc_shell -f BUS_EXPAND_VHDL.scr
DESIGN_FILE_NAME.edif

6. 5
Design Compiler
Design Compiler61
check_design
OPENCAD

82

A14353JJ3V0UM00

61

i1
i2
i3

o1
A

o2

A'
F101

o3

F101

F101

o4

F101

A'

1edif
UNIXOPC_VSHELLNetlist UtilitiesConvert Nettlist type
edifpwc

62Convert Netlist Type

Source Netlist TypeType

Destination Netlist TypeTypePWC
62OK63

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83

63

Input EDIF File Name

Output PWC File Name
PWCYESNO

2Netlist UtilitiesDelete Floated Net

64Delete Floated Net

Input PWC File Name

Output PWC File Name

3Netlist UtilitiesConvert Nettlist typepwcedif

65Convert Netlist Type

84

A14353JJ3V0UM00

Source Netlist TypeType

Destination Netlist TypeTypeEDIF
65OK66

66

Input PWC File Name

Output EDIF File Name

A14353JJ3V0UM00

85

86

A14353JJ3V0UM00

A1

A1

CMOS-N5

fan-in0.122

fan-out0.122

t1/0.122

CMOS-6

fan-in0.251

fan-out0.101

t1/0.251

CMOS-8

fan-in0.051

fan-out0.051

t1/0.051

CMOS-8L/8LH/8LHD

fan-in0.041

fan-out0.041

t1/0.041

CMOS-9

fan-in0.028

fan-out0.028

t1/0.028

CMOS-9HD

fan-in0.034

fan-out0.034

t1/0.034

EA-9HD

fan-in0.034

fan-out0.034

t1/0.034

EA-9

fan-in0.028

fan-out0.028

t1/0.028

EA-10

Cin

Cmax

ExtrinsicA
ExtrinsicB

QB-8

fan-in0.034

fan-out0.034

t1/0.034

CB-8

Cin

Cmax

ExtrinsicA
ExtrinsicB

CB-9

Cin

Cmax

ExtrinsicA
ExtrinsicB

CB-10

Cin

Cmax

ExtrinsicA
ExtrinsicB

A2

A2

CMOS-9HD, EA-9HD, EA-10, CB-8, CB-9, CB-10

set_load

set_max_capacitance

set_fanout_load

set_max_fanout

OPENCAD V5.3

OPENCADA14355J

A14353JJ3V0UM00

87

88

A14353JJ3V0UM00

BDIF.dif

B. 1
DIF

UNV-PCI

OPENCAD V5

1
DIF2
1C
MIN,TYP, MAX3MIN, TYP, MAX
3MIN, TYP, MAX

2
DIF
15 pF

33
DIF3MIN, TYP, MAX
DIF3

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89

BDIF.dif

B. 2
B. 2. 1
1512

B. 2. 2

B1

B1DIF

B2

B2DIF

90

103

106

109

1012

A14353JJ3V0UM00

BDIF.dif

B. 3
B. 3. 1DIF
DIF3

B. 3. 2

DIF

1Designer_NameCreate_Date
Designer_NameCreate_Date

B. 3. 3
B3
/DESIGN/END DESIGN

B3

/DESIGN

TECHNOLOGY =

CONDITION =

MASTER =

PACKAGE =

PINS =

CODE =

LAYER =

CONDITION

2CONDITION
3PIN

PIN

1PIA

/END DESIGN

PINCONDITION
PINCONDITION
CONDITION1

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91

BDIF.dif

1PIA

/PIA/END PIA
B4

B4PIA

/PIA
aEPINbSPIN
/END PIA

aEPIN

/EPIN/END EPIN
B5

B5EPIN

/EPIN

PAD =

/END EPIN

bSPIN
SPIN
SPIN
/SPIN/END SPIN
B6

B6SPIN

SPIN

/SPIN

PAD =

/END SPIN

SPIN

SPIN

92

A14353JJ3V0UM00

BDIF.dif

2CONDITION

/CONDITION/END CONDITION
CONDITION1

B7

B7CONDITION

PIN

3PIN

UNV-PCI

aUNV-PCI

/CONDITION

/END CONDITION

aUNV-PCI
UNV-PCIUNV-PCI

/UNV-PCI/END UNV-PCI
B8

B8UNV-PCI

UPCI

/UNV-PCI

UPCIUPCI

/END UNV-PCI

UPCI

3PIN
PIN
/PIN/END PIN
B9

B9PIN

/PIN

/END PIN

1.
1
2.1
B10

A14353JJ3V0UM00

93

BDIF.dif

B10
3

CMIN

CTYP

CMAX

rise

TRMIN

TRTYP

TRMAX

fall

TFMIN

TFTYP

TFMAX

3MIN, TYP, MAX

MIN, TYP3

OPENCAD V5.23

CMIN = 15 CTYP = 20 CMAX = 30

C = 15 CMAX = 30pF
CMIN = 15pF
C = 15pF

B. 3. 4
DIF

B11

94

END

A14353JJ3V0UM00

BDIF.dif

B. 4DIF
1
1CONDITION
NEC_PIN
CONDITIONDIF Merge

23
DIF
3MIN, TYP, MAX

3SCAN
SCANSMCSINSOT
SCANPIN

Terminal name SIN is not found in netlist at 6 pin

Terminal name SMC is not found in netlist at 5 pin.
Terminal name SOT is not found in netlist at 7 pin.

4
NEC_PINI/F

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95

BDIF.dif

B. 5

*DIF quest14 1998.10.13120351

/DESIGN SAMPLE
TECHNOLOGY = CMOS8 ;
CONDITION = cmos_5V ;
MASTER = 65801 ;
PACKAGE = QFPCGD ;
PINS = 208 ;
CODE = 000 ;
/PIA
/EPIN DUT
IN1
PAD = 3 ;
IN2
PAD = 4 ;

OUT1
EPIN
PAD = 5 ;
OUT2
PAD = 6 ;
/END EPIN
/SPIN DUT
**G1
PAD = 2 26 51 79 106 131 155 182 ;
**G3
PAD = 1 52 105 156 ;
**V1
SPIN
PAD = 27 78 130 183 ;
**V3
PAD = 53 104 157 208 ;
/END SPIN
/END PIA
/CONDITION 1
/PIN

IN1
DIR = INPUT
TRMIN = 3.0 TRTYP = 3.5 TRMAX = 3.0 ;
TFMIN = 4.0 TFTYP = 4.5 TFMAX = 4.0 ;

IN2
DIR = INPUT
TRMIN = 2.0 TRTYP = 2.0 TRMAX = 2.5 ;
TFMIN = 3.0 TFTYP = 4.0 TFMAX = 3.5 ;

OUT1
DIR = OUTPUT
CMIN = 18 CTYP = 15 CMAX = 60 ;

OUT2
DIR = OUTPUT
CMIN = 50 CTYP = 50 CMAX = 50 ;
/END PIN
/END CONDITION
/CONDITION 2
/PIN

IN1
DIR = INPUT
TRMIN = 1.0 TRTYP = 1.5 TRMAX = 2.0 ;
TFMIN = 3.0 TFTYP = 3.5 TFMAX = 4.0 ;

IN2
DIR = INPUT
TRMIN = 4.0 TRTYP = 4.0 TRMAX = 4.0 ;
TFMIN = 6.0 TFTYP = 6.0 TFMAX = 6.0 ;

OUT1
DIR = OUTPUT
CMIN = 100 CTYP = 100 CMAX = 100 ;

OUT2
DIR = OUTPUT
CMIN = 20 CTYP = 18 CMAX = 30 ;
/END PIN
/END CONDITION
/END DESIGN
*END

96

A14353JJ3V0UM00

PIA

C. 1
*ALBATROSS;
*TIMING;
PERIOD;
MODULATION:;
CLOCK TYPE = :12:;
*END_OF_TIMING;
*END;
1.MODULATION
2.CLOCK
3.MODULATIONCLOCK

*ALBATROSS HONMA;
*TIMING;
PERIOD 200 NS;
MODULATION 20 NS:D0;
MODULATION 20 NS:D1;

CLOCK TYPE = P:10 NS 40 NS:CK

CLOCK TYPE = N:10 NS 40 NS:CK1
*END_OF_TIMING;
*END

C. 2PIASS
PIASSPIASS

0
15 pF
PIASS
nec_pin

A14353JJ3V0UM00

97

1
PIASS

/NAME

/PIN

1-

-***COMMENT****

/END

15 pF

0
pF
15 pF

1-

3
PIASS HORIKOSHI 92/09/03 21:03:03
/NAME 65800000
/PIN
SET1CLK

ENB1

STATEEB3

CMPOUT00

0 20

ABCDEFGH

0 20

ABCDEF

0 30

ABCDE

0 30

AB

ENB2

D0000

RSTB

CLK

50

/END

98

A14353JJ3V0UM00

CB-8VMSynopsys

/**/

3. 3
4. 1

search_path = {./susr/synopsys/V3.5a/libraries/syn \
/OPENCAD/V5.2.0/ss2/lib/CBC8_VM/cmos_3.3V/synopsys/object/basic \
/OPENCAD/V5.2.0/ss2/lib/CBC8_VM/cmos_3.3V/synopsys/object/iobuffer \
/OPENCAD/V5.2.0/ss2/lib/CBC8_VM/cmos_3.3V/synopsys/object/primitive \
/OPENCAD/V5.2.0/ss2/lib/CBC8_VM/cmos_3.3V/synopsys/object/special \
/OPENCAD/V5.2.0/ss2/lib/CBC8_VM/cmos_3.3V/synopsys/wire_model};
link_library = {\
CBC8VM_CMOS_33V_MAX_BASIC.db \
CBC8VM_CMOS_33V_MAX_IO.db \
CBC8VM_CMOS_33V_MAX_PRIM.db \
CBC8VM_CMOS_33V_MAX_SPECIAL.db};
target_library = {\
CBC8VM_CMOS_33V_MAX_BASIC.db \
CBC8VM_CMOS_33V_MAX_IO.db \
CBC8VM_CMOS_33V_MAX_PRIM.db \
CBC8VM_CMOS_33V_MAX_SPECIAL.db}
symbol_library = {\
CBC8VM_CMOS_33V_SYMBOL_BASIC.sdb \
CBC8VM_CMOS_33V_SYMBOL_IO.sdb \
CBC8VM_CMOS_33V_SYMBOL_PRIM.sdb \
CBC8VM_CMOS_33V_SYMBOL_SPECIAL.sdb}

auto_wire_load_selection = "false";
edifout_netlist_only = "true";
edifout_no_array = "true";
edifout_power_and_ground_representation = "cell";

verilogout_no_tri = "true";

/**/

read -f verilog cf191.v

/*

VerilogHDL

read -f verilog F191.v

/*

VerilogHDL

*/

*/

A14353JJ3V0UM00

99

/*

*/

current_design = F191

read{CBC8VM_CMOS_33V_MAX_BASIC.db \
CBC8VM_CMOS_33V_MAX_PRIM.db \
CBC8VM_CMOS_33V_MAX_SPECIAL.db};

/*

*/

4. 2. 1

link
update_lib CBC8VM_CMOS_33V_MAX_BASIC.db -overwrite WIRE_B18.lib

/*

*/

/*

F101F101

CB-8CB-9set_max_capacitanceset_max_fanout

*/

5. 2A
set_max_capacitance 0.053 all_inputs()
set_drive 0.75 all_inputs()

create_clock "CLK" -period 20 -waveform{0 10}

set_wire load MB18_500

/*

MAX*/

compile -map_effort low

4. 1

/*

MIN*/

/*

MAXlocal_link_library

*/

set_local_link_library{\
CBC8VM_CMOS_33V_MIN_BASIC.db \
CBC8VM_CMOS_33V_MIN_PRIM.db \
CBC8VM_CMOS_33V_MIN_SPECIAL.db};

link_library = {\
CBC8VM_CMOS_33V_MIN_BASIC.db \
CBC8VM_CMOS_33V_MIN_PRIM.db \
CBC8VM_CMOS_33V_MIN_SPECIAL.db};

100

A14353JJ3V0UM00

target_library = {\
CBC8VM_CMOS_33V_MIN_BASIC.db \
CBC8VM_CMOS_33V_MIN_PRIM.db \
CBC8VM_CMOS_33V_MIN_SPECIAL.db};
link

update_lib CBC8VM_CMOS_33V_MIN_BASIC -overwrite WIRE_B18.lib

set_wire load MB18_500

compile -prioritize_min_path -only_design_rule

remove_design {CBC8VM_CMOS_33V_MIN_BASIC.db \

2Compile
-only_design_rule

CBC8VM_CMOS_33V_MIN_PRIM.db \
CBC8VM_CMOS_33V_MIN_SPECIAL.db};
/*

*/

current_design = cf191

/*

MAX

*/

set_local_link_library{\
CBC8VM_CMOS_33V_MAX_BASIC.db \
CBC8VM_CMOS_33V_MAX_PRIM.db \
CBC8VM_CMOS_33V_MAX_SPECIAL.db};

link_library = {\
CBC8VM_CMOS_33V_MAX_BASIC.db \
CBC8VM_CMOS_33V_MAX_PRIM.db \
CBC8VM_CMOS_33V_MAX_SPECIAL.db};
target_library = {\
CBC8VM_CMOS_33V_MAX_BASIC.db \
CBC8VM_CMOS_33V_MAX_PRIM.db \
CBC8VM_CMOS_33V_MAX_SPECIAL.db};

link

update_lib CBC8VM_CMOS_33V_MAX_BASIC -overwrite WIRE_B18.lib

set_wire_load TB18 -mode enclosed

enclosed

create_clock "CLK" -period20 -waveform{0 10}

A14353JJ3V0UM00

101

compile -map_effort low -only_design_rule

remove_design {CBC8VM_CMOS_33V_MAX_BASIC.db \
CBC8VM_CMOS_33V_MAX_PRIM.db \
CBC8VM_CMOS_33V_MAX_SPECIAL.db};

/*

MIN

*/

set_local_link_library{\
CBC8VM_CMOS_33V_MIN_BASIC.db \
CBC8VM_CMOS_33V_MIN_PRIM.db \
CBC8VM_CMOS_33V_MIN_IO.db \
CBC8VM_CMOS_33V_MIN_SPECIAL.db};

link_library = {\
CBC8VM_CMOS_33V_MIN_BASIC.db \
CBC8VM_CMOS_33V_MIN_PRIM.db \
CMC8VM_CMOS-33V_MIN_IO.db \
CBC8VM_CMOS_33V_MIN_SPECIAL.db};

target_library = {\
CBC8VM_CMOS_33V_MIN_BASIC.db \
CBC8VM_CMOS_33V_MIN_PRIM.db \
CBC8VM_CMOS_33V_MIN_IO.db \
CBC8VM_CMOS_33V_MIN_SPECIAL.db};

link

update_lib CBC8VM_CMOS_33V_MIN_BASIC -overwrite WIRE_B18.lib

set_wire_load TB18 -mode enclosed

compile -prioritize_min_path -only_design_rule

remove_design {CBC8VM_CMOS_33V_MIN_BASIC.db \
CBC8VM_CMOS_33V_MIN_PRIM.db \
CBC8VM_CMOS_33V_MIN_IO.db \
CBC8VM_CMOS_33V_MIN_SPECIAL.db};

/*

6. 26. 3

*/

current_design = cf91
define_name_rules "OpenCAD" -max_length "255" -allowed "a-zA-Z0-9_$" -type cell
define_name_rules "OpenCAD" -max_length "255" -allowed "a-zA-Z0-9_$[]" -type net
define_name_rules "OpenCAD" -max_length "255" -allowed "a-zA-Z0-9_[]" -type port

report_names -rules "OpenCAD"

change_names -rules OpenCAD -h

102

A14353JJ3V0UM00

ENEC Design Ware

E. 1
Block Type

Function

NEC_SM01_ADD

SSI Family

Adder

Logic Diagram

A
SUM
B
CO
CI

Functional Description

Pin Description
Pin Name

Size

Type

Function

CI

SUM

CO

Width

Input

Input data

A+B

Carry-out

Width

Input

Input data

A+B+1

Carry-out

CI

Input

Carry-in

SUM

Width

Output

Sum of A+B

CO

Output

Carry-out

Implementation
Implementation

HDL

Implementations
Function

Im ple m e n tatio n N a m e
RPL

Ripple Carry

Parameter Description

CLA

Carry Look-ahead

BLC

Binary Look-ahead Carry

Parameter
Width

Function

Legal Range

Width
1024
W ord Length of A, B and SUM 1

Access
Com ponent Instantiation Operator Inferencing

Component Instatication

Operator

Operator Inferencing
operator

Operator Inferencing

A14353JJ3V0UM00

103

ENEC Design Ware

E. 2
E. 3. 18
NEC_SM03_BICTR_DECODE, E. 3. 19
NEC_SM03_BICTR_DCNTO,
E. 3. 20
NEC_SM03_BICTR_SCNTO, E. 3. 21
NEC_SM03_CNTR_GRAY, E. 3. 22
NEC_SM03_LFSR_DCNTO,
E. 3. 23
NEC_SM03_LFSR_LOAD, E. 3. 24
NEC_SM03_LFSR_SCNTO, E. 3. 25
NEC_SM03_LFSR_UPDN,
E. 3. 26
NEC_SM03_UPDN_CTR

NEC Design Ware

LFSR3

LFSRCount-to

Count-toDynamicStatic2
Dynamic Count-to
Static Count-to
Static Count-to

Linear Feedback Shift RegisterLFSRN-bitLFSR

N

2 12NLFSR
XOR

NN10
LFSRCount-toN
Count-toCount-toE2
8

fx= x8x6x5x1

LFSR0NEC Design Ware

LFSRmodulo2XOR
1
8LFSR

E18-bit LFSR

X7

X6

X5

X4

X3

X2

X1

E1MSB

count7= notcount6xor count5xor count1xor count0

104

A14353JJ3V0UM00

X0

ENEC Design Ware

8-bitLFSR

E18-bitLFSR
Binary Count

X7

X6

X5

X4

X3

X2

X1

X0

00000

00011

00102

00113

01004

01015

01106

01117

10008

10019

1010A

9Count-to1000010185h

E2

27

28

29

30

16

31

32

28

33

13

34

15

35

36

11

37

12

38

39

40

21

41

42

23

43

44

27

45

46

21

47

48

28

49

50

27

x x x x1

27

x x x x1

28

x x 1

29

x x 1

x1

x x1

x x1

x x1

x x 1

x x1

x x1

x x x x1

x x 1

15

30

x x x x1

31

x x 1

32

x x x x1

33

x x 1

34

x x x x1

27

14

10

35

x x 1

11

36

x x 1

12

37

x x x x 1

13

38

x x x x1

14

12

39

x x 1

40

x x x x 1

x x 1

11

x x 1

12

x x x x 1

13

x x x x1

14

x x x x1

15

x x1

16

26

26

10

11

15

10

19

16

41

x x 1

17

42

x x x x1

18

43

x x x x1

19

x x x x 1

22

17

x x 1

18

x x 1

19

x x x x1

44

x x x x1

20

x x 1

45

x x x x1

21

21

x x 1

22

x X1

23

x x 1

24

x x x x1

25

x x 1

22

23

24

25

26

20

46

x x x x1

47

x x 1

48

x x x x1

49

x x 1

50

x x x x1

A14353JJ3V0UM00

27

26

105

ENEC Design Ware

E. 3
E. 3. 1NEC_SM01_ABSVAL
Block Type

Function

NEC_SM01_ABSVAL

SSI Family

Absolute Value

Logic Diagram

ABSVAL

Truth TableWidth = 3
2
0

Value of A

000
001
010
011
100
101
110
111

0
1
2
3
4
3
2
1

Pin Description

2
0
Value of ABSV AL
ABSV AL
0
1
2
3
4
3
2
1

000
001
010
011
100
011
010
001

Pin Name

Size

Type

Width

Input

ABSVAL

Width

Output

Function
Input data
Absolute value of A

Implementations
Function

Im ple m e n tatio n N a m e
RPL

Ripple Carry

Parameter Description

CLA

Carry Look-ahead

BLC

Binary Look-ahead Carry

Parameter

Function

Legal Range

Width

W ord Length of A and ABSVAL

Width
2

Access
Com ponent Instantiation Operator Inferencing

106

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01
NEC-SM-LCS

ENEC Design Ware

NEC_SM01_ABSVALAABSVAL

1Implementation

RPL

CLA
BLC

RPL
CLA
BLCCLA

2
Component Instantiation

A14353JJ3V0UM00

107

ENEC Design Ware

E. 3. 2NEC_SM01_ADD
Block Type

Function

NEC_SM01_ADD

SSI Family

Adder

Logic Diagram

A
SUM
B
CO
CI

Functional Description

Pin Description
Pin Name

Size

Type

Function

CI

SUM

CO

Width

Input

Input data

A+B

Carry-out

Width

Input

Input data

A+B+1

Carry-out

CI

Input

Carry-in

SUM

Width

Output

Sum of A+B

CO

Output

Carry-out

Implementations
Function

Im ple m e n tatio n N a m e
RPL

Ripple Carry

Parameter Description

CLA

Carry Look-ahead

BLC

Binary Look-ahead Carry

Parameter
Width

Function

Legal Range

Width
1024
W ord Length of A, B and SUM 1

Access
Com ponent Instantiation Operator Inferencing

108

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01
NEC-SM-LCS

ENEC Design Ware

NEC_SM01_ADD2A, BCISUM
CO

1Implementation

RPL

CLA
BLC

RPL
CLA
BLCCLA

2
Component InstantiationOperator Inferencing2Operator InferencingOperator

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109

ENEC Design Ware

3
Component Instantiation
4. 5NEC Design Ware
Operator Inferencing
ImplementationBLC

VHDL
library IEEE, synopsys;
use synopsys.attributes.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity ADDER is
generic(width : Integer)
port(IN1, IN2 : in std_logic_vector(width-1 downto 0);
SUM
: out std_logic_vector(width-1 downto 0));
end ADDER;
architecture imp1 of ADDER is
signal in1_signed, in2_signed, sum_signed : SIGNED(width-1 downto 0);
begin
in1_signed <= SIGNED(IN1);
in2_signed <= SIGNED(IN2);
process(in1_signed, in2_signed);
constant r0:resource := 0;
attribute map_to_module of r0 : constant is "NEC_SM01_ADD";
attribute implementation of r0 : constant is "BLC";
attribute ops
of r0 : constant is "A1";
begin
sum_signed <= in1_signed + in2_signed;
end process;

-- pragma label A1

SUM <= STD_LOGIC_VECTOR(sum_signed);

end impl;

Verilog
module adder(IN1, IN2, SUM);
parameter wordlength = 8;
input [wordlength-1:0]IN1, IN2;
output [wordlength-1:0]SUM;
reg
[wordlength-1:0]SUM;
always @(IN1 or IN2)
begin : b1
/* synopsys resource r0:
map_to_module = "NEC_SM01_ADD",
implementation = "BLC",
ops
= "A1";
*/
SUM = IN1 + IN2; // synopsys label A1
end
endmodule

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E. 3. 3NEC_SM01_ADDSUB
Block Type

Function

NEC_SM01_ADDSUB

SSI Family

Adder-Subtractor

Logic Diagram

A
SUM
B

CI
CO
ADD_SUB

Functional Description

Pin Description
Pin Name

Size

Type

Function

ADD_SUB

CI

SUM

CO

Width

Input

Input data

A+B

Carry-out

Width

Input

Input data

A+B+1

Carry-out

CI

Input

Carry/borrow in

A-B

Carry-out

ADD_SUB

Input

ADD_SUB = 0
or
Addition

A-B-1

Carry-out

Subtraction
ADD_SUB = 1
SUM

Width

Output

Sum/difference

CO

Output

Carry/borrow out

Implementations
Function

Im ple m e n tatio n N a m e
RPL

Ripple Carry

Parameter Description

CLA

Carry Look-ahead

BLC

Binary Look-ahead Carry

Parameter

Function

Legal Range

Width

W ord Length of A, B and SUM

Width
1

Access
Com ponent Instantiation Operator Inferencing

Operator

Library
Required License

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NEC_SM01
NEC-SM-LCS

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NEC_SM01_ADDSUB2A, BCI
SUMCOADD_SUBADD_SUB

1Implementation

RPL

CLA
BLC

RPL
CLA
BLCCLA

2
Component InstantiationOperator Inferencing2Operator InferencingOperator

112

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4. 5NEC Design Ware
Operator Inferencing
ImplementationBLC

VHDL
library IEEE, synopsys;
use synopsys.attributes.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity ADDER_SUBTRACTOR is
generic(width : Integer)
port(IN1, IN2 : in std_logic_vector(width-1 downto 0);
CTL
: in std_logic;
SUM
: out std_logic_vector(width-1 downto 0));
end ADDER_SUBTRACTOR;
architecture imp1 of ADDER_SUBTRACTOR is
signal in1_signed, in2_signed, sum_signed : SIGNED(width-1 downto 0);
begin
in1_signed <= SIGNED(IN1);
in2_signed <= SIGNED(IN2);
process(in1_signed, in2_signed, CTL);
constant r0 : resource := 0;
attribute map_to_module of r0 : constant is "NEC_SM01_ADDSUB";
attribute implementation of r0 : constant is "BLC";
attribute ops
of r0 : constant is "A1";
begin
if(CTL = '0')then
sum_signed <= in1_signed + in2_signed;
else
sum_signed <= in1_signed in2_signed;
end if;
end process;

-- pragma label A1
-- pragma label A1

SUM <= STD_LOGIC_VECTOR(sum_signed);

end impl;

Verilog
module adder_subtractor(IN1, IN2, CTL, SUM);
parameter wordlength = 8;
input [wordlength-1:0]IN1, IN2;
input CTL;
output [wordlength-1:0]SUM;
reg
[wordlength-1:0]SUM;
always @(IN1 or IN2 or CTL)
begin : b1
/* synopsys resource r0:
map_to_module = "NEC_SM01_ADDSUB",
implementation = "BLC",
ops
= "A1";
*/
if(CTL = 0)
SUM = IN1 + IN2; // synopsys label A1
else
SUM = IN1 IN2; // synopsys label A1
end
endmodule

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E. 3. 4NEC_SM01_ASH
Block Type

Function

NEC_SM01_ASH

SSI Family

Arithmetic Shifter

Logic Diagram

DATA_TC
B
SH

SH_TC

Truth Table

Pin Description

Pin Name

Size

Type

Function

A_Width

Input

Input data

DATA_TC

Input

Data twos com plement control

SH

SH_Width

Input

Shift control

SH_TC

Input

Shift twos com plement control

A_Width

Output

Output data

Implementations
Function

Im ple m e n tatio n N a m e
STR

Synthesis model

Parameter Description
Parameter

Function

Legal Range

A_Width Word length of A and B

SH_Width Word length of SH

A_Width
1
SH_Width
1

Access
Com ponent Instantiation Operator Inferencing

114

Operator

Library
Required License

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NEC_SM01
NEC-SM-LCS

ENEC Design Ware

Truth TableSH_Width = 3
2
0
SH_TC
SH

7
B
6
B
5
B
4
B
3
B
2
B
1
B
0

DATA_TC B

000

A7

A6

A5

A4

A3

A2

A1

A0

001

A6

A5

A4

A3

A2

A1

A0

010

A5

A4

A3

A2

A1

A0

011

A4

A3

A2

A1

A0

100

A3

A2

A1

A0

101

A2

A1

A0

110

A1

A0

111

A0

000

A7

A6

A5

A4

A3

A2

A1

A0

001

A6

A5

A4

A3

A2

A1

A0

010

A5

A4

A3

A2

A1

A0

011

A4

A3

A2

A1

A0

100

A7

A6

A5

A4

101

A7

A6

A5

A4

A3

110

A7

A6

A5

A4

A3

A2

111

A7

A6

A5

A4

A3

A2

A1

100

A7

A7

A7

A7

A7

A6

A5

A4

101

A7

A7

A7

A7

A6

A5

A4

A3

110

A7

A7

A7

A6

A5

A4

A3

A2

A6

A5

A4

A3

A2

A1

111

A7

A7

NEC_SM01_ASHASH

SH_TCSHunsigned
SH_TCSH2

DATA_TCAunsigned2
unsigned0
2

1
Component Instantiation

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E. 3. 5NEC_SM01_BSH
Block Type

Function

NEC_SM01_BSH

SSI Family

Barrel Shifter

Logic Diagram

SH

Truth TableWidth = 3

Pin Description

2
0
B
SH
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0

000
001
010
011
100
101
110
111

A7 A6 A5 A4 A3 A2 A1 A0
A6 A5 A4 A3 A2 A1 A0 A7
A5 A4 A3 A2 A1 A0 A7 A6
A4 A3 A2 A1 A0 A7 A6 A5
A3 A2 A1 A0 A7 A6 A5 A4
A2 A1 A0 A7 A6 A5 A4 A3
A1 A0 A7 A6 A5 A4 A3 A2
A0 A7 A6 A5 A4 A3 A2 A1

Pin Name

Size

Type

Function

A_Width

Input

Input data

SH

SH_Width

Input

Shift control

A_Width

Output

Shifted data out

Implementations
Function

Im ple m e n tatio n N a m e
STR

Synthesis model

Parameter Description
Parameter

Function

A_Width W ord length of A and B

Legal Range
1
A_Width

SH_Width Word length of SH 1

SH_Width
log 2A_Width

Access
Com ponent Instantiation Operator Inferencing

116

Operator

Library
Required License

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NEC_SM01
NEC-SM-LCS

ENEC Design Ware

NEC_SM01_BSHASH
MSBLSBSHunsigned
SH_Widthlog2A_Width

1
Component Instantiation

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E. 3. 6NEC_SM01_CMP2
Block Type

Function

NEC_SM01_CMP2

SSI Family

2-Function Comparator

Logic Diagram

A
LT_LE
B

LEQ
GE_GT
TC

Functional Description

Pin Description

LEQ

Condition

LT_LE

GE_GT

AB

AB

AB

AB

TC

for A and B

Numeric Data Type

Unsigned numbers

Twos-complement numbers

Pin Name

Size

Type

Width

Input

Input data

Width

Input

Input data

LEQ

Input

O utput condition control

TC

Input

Twos com plem ent control

LT_LE

Output

Output condition

GE_GT

Output

Output condition

Implementations

STR

Parameter Description

Function

Im ple m e n tatio n N a m e

Function

Synthesis model

Parameter

Function

Legal Range

Width

Word Length of A and B

Width
1

Access
Com ponent Instantiation Operator Inferencing

118

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01
NEC-SM-LCS

ENEC Design Ware

NEC_SM01_CMP2signedunsigned2A, BLE_LT,
GT_GE2LEQTC2signed
TCunsignedTC

1
Component InstantiationOperator Inferencing2Operator InferencingOperator

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4. 5NEC Design Ware
Operator Inferencing

VHDL
library IEEE, synopsys;
use synopsys.attributes.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity COMPARE2 is
generic(width :
port(IN1, IN2 :
COND
:
COMP2
:
end COMPARE2;

Integer)
in std_logic_vector(width-1 downto 0);
in std_logic;
out boolean);

architecture imp1 of COMPARE2 is

signal in_signed1, in_signed2, sum_signed : SIGNED(width-1 downto 0);
begin
in_signed1 <= SIGNED(IN1);
in_signed2 <= SIGNED(IN2);
process(in_signed1, in_signed2, COND);
constant r0 : resource := 0;
attribute map_to_module of r0 : constant is "NEC_SM01_CMP2";
attribute implementation of r0 : constant is "STR";
attribute ops
of r0 : constant is "A1";
begin
if(COND = '0')then
COMP2 <= in1_signed > in2_signed; -- pragma label A1
else
COMP2 <= in1_signed >= in2_signed; -- pragma label A1
end if;
end process;
end impl;

Verilog
module compare2(IN1, IN2, COND, COMP2);
parameter wordlength = 8;
input [wordlength-1:0] IN1, IN2;
input COND;
output COMP2;
reg
COMP2;
always @(IN1 or IN2 or COND)
begin : b1
/* synopsys resource r0:
map_to_module = "NEC_SM01_CMP2",
implementation = "STR",
ops
= "A1";
*/
if(COND = 0)
COMP2 = (IN1 > IN2); // synopsys label A1
else
COMP2 = (IN1 >= IN2); // synopsys label A1
end
endmodule

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E. 3. 7NEC_SM01_CMP6
Block Type

Function

NEC_SM01_CMP6

SSI Family

6-Function Comparator

Logic Diagram

GT

LT
EQ
B
LE
GE
TC

NE

Functional Description

Pin Description
Pin Name

Size

Type

Function

Condition

GT

LT

EQ

LE

GE

NE

Width

Input

Input data

AB

Width

Input

Input data

AB

TC

Input

Tw os com plem ent control

A=B

GT

Output Greater-than output condition

LT

Output Less-than output condition

TC

for A and B

Numeric Data Type

EQ

Output Equal output condition

Unsigned numbers

LE

Output Less-than-or-equal output condition

Twos-complement numbers

GE

Output Greater-than-or-equal output condition

NE

Output Not equal output condition

Implementations
Function

Im ple m e n tatio n N a m e
STR

Parameter Description

Synthesis model

Parameter

Function

Legal Range

Width

Word Length of A and B

Width
1

Access
Com ponent Instantiation Operator Inferencing

Operator

Library

=,,,,,

Required License

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NEC_SM01
NEC-SM-LCS

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NEC_SM01_CMP6signedunsigned2A, B6greater-than
GTless-thanLTequalEQless-than-or-equalLEgreater-than-or-equalGEnot equal
NETC2signedTCunsigned
TC

1
Component InstantiationOperator Inferencing2Operator InferencingOperator
=

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E. 3. 8NEC_SM01_DEC
Block Type

Function

NEC_SM01_DEC

SSI Family

Decrementer

Logic Diagram

SUM

Functional Description

Pin Description
Pin Name

Size

Type

SUM

Width

Input

AWidth-10

AWidth-10- 00...01

SUM

Width

Output

Function
Input data
Decremented output data

Implementations
Function

Im ple m e n tatio n N a m e
RPL

Ripple Carry

Parameter Description

CLA

Carry Look-ahead

BLC

Binary Look-ahead Carry

Parameter

Function

Legal Range

Width

W ord Length of A and S U M

Width
1

Access
Com ponent Instantiation Operator Inferencing

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01
NEC-SM-LCS

123

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NEC_SM01_DECA1SUM

1Implementation

RPL

CLA
BLC

RPL
CLA
BLCCLA

2
Component InstantiationOperator Inferencing2Operator InferencingOperator

124

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3
Component Instantiation
4. 5NEC Design Ware
Operator Inferencing
ImplementationBLC

VHDL
library IEEE, synopsys;
use synopsys.attributes.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity DECREMENTER is
generic(width : Integer)
port(IN1 : in std_logic_vector(width-1 downto 0);
SUM : out std_logic_vector(width-1 downto 0));
end DECREMENTER;
architecture imp1 of DECREMENTER is
signal in_signed, sum_signed : SIGNED(width-1 downto 0);
begin
in_signed <= SIGNED(IN1);
process(in_signed);
constant r0 : resource := 0;
attribute map_to_module of r0 : constant is "NEC_SM01_DEC";
attribute implementation of r0 : constant is "BLC";
attribute ops
of r0 : constant is "A1";
begin
SUM_signed <= in_signed - 1;
end process;

-- pragma label A1

SUM <= STD_LOGIC_VECTOR(sum_signed);

end imp1;

Verilog
module decrementer(IN1, SUM);
parameter wordlength = 8;
input [wordlength-1:0]IN1;
output [wordlength-1:0]SUM;
reg
[wordlength-1:0]SUM;
always @(IN1)
begin : b1
/* synopsys resource r0:
map_to_module = "NEC_SM01_DEC",
implementation = "BLC",
ops
= "A1";
*/
SUM = IN1 1;
end
endmodule

// synopsys label A1

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E. 3. 9NEC_SM01_DECODE
Block Type

Function

NEC_SM01_DECODE

SSI Family

Decoder

Logic Diagram

Truth TableWidth = 3

Pin Description

2
0
B
A
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0

0
0
0
0
0
0
0
1

000
001
010
011
100
101
110
111

0
0
0
0
0
0
1
0

0
0
0
0
0
1
0
0

0
0
0
0
1
0
0
0

0
0
0
1
0
0
0
0

0
0
1
0
0
0
0
0

0
1
0
0
0
0
0
0

1
0
0
0
0
0
0
0

Pin Name

Size

Type

Width

Input

Width

Output

Function
Binary input data
D ecoded output data

Implementations
Function

Im ple m e n tatio n N a m e
STR

Synthesis model

Parameter Description
Parameter

Function

Legal Range

Width

W ord length of input A is Width.

W ord length of output B is 2

Width
1

Width

Access
Com ponent Instantiation Operator Inferencing

126

Operator

Library
Required License

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NEC_SM01
NEC-SM-LCS

ENEC Design Ware

NEC_SM01_DECODEAB1

1
Component Instantiation

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E. 3. 10NEC_SM01_INC
Block Type

Function

NEC_SM01_INC

SSI Family

Incrementer

Logic Diagram

SUM

Functional Description

Pin Description
Pin Name

Size

Type

SUM

Width

Input

AWidth-10

AWidth-10+ 00...01

SUM

Width

Output

Function
Input data
Incremented output data

Implementations
Function

Im ple m e n tatio n N a m e
RPL

Ripple Carry

Parameter Description

CLA

Carry Look-ahead

BLC

Binary Look-ahead Carry

Parameter

Function

Legal Range

Width

W ord Length of A and S U M

Width
1

Access
Com ponent Instantiation Operator Inferencing

128

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01
NEC-SM-LCS

ENEC Design Ware

NEC_SM01_INCA1SUM

1Implementation

RPL

CLA
BLC

RPL
CLA
BLCCLA

2
Component InstantiationOperator Inferencing2Operator InferencingOperator

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3
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4. 5NEC Design Ware
Operator Inferencing
ImplementationBLC

VHDL
library IEEE, synopsys;
use synopsys.attributes.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity INCREMENTER is
generic(width : Integer)
port(IN1 : in std_logic_vector(width-1 downto 0);
SUM : out std_logic_vector(width-1 downto 0));
end INCREMENTER;
architecture imp1 of INCREMENTER is
signal in_signed, sum_signed : SIGNED(width-1 downto 0);
begin
in_signed <= SIGNED(IN1);
process(in_signed);
constant r0 : resource := 0;
attribute map_to_module of r0 : constant is "NEC_SM01_INC";
attribute implementation of r0 : constant is "BLC";
attribute ops
of r0 : constant is "A1";
begin
SUM_signed <= in_signed + 1;
end process;

-- pragma label A1

SUM <= STD_LOGIC_VECTOR(sum_signed);

end imp1;

Verilog
module incrementer(IN1, SUM);
parameter wordlength = 8;
input [wordlength-1:0]IN1;
output [wordlength-1:0]SUM;
reg
[wordlength-1:0]SUM;
always @(IN1)
begin : b1
/* synopsys resource r0:
map_to_module = "NEC_SM01_INC",
implementation = "BLC",
ops
= "A1";
*/
SUM = IN1 + 1;
end
endmodule

130

// synopsys label A1

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E. 3. 11NEC_SM01_INCDEC
Block Type

Function

NEC_SM01_INCDEC

SSI Family

Incrementer-Decrementer

Logic Diagram

SUM

INC_DEC

Functional Description

Pin Description
P in N a m e

Size

Type

Function

IN C _D E C

SUM

Width

Input

Input data

AWidth-10

AWidth-10+ 00...01

INC_DEC

Input

IN C _ D E C = 0

Incre m e nt

AWidth-10

AWidth-10- 00...01

IN C _ D E C = 1

or D ecre m e nt
SUM

Width

Output Incremented or decremented

output data

Implementations
Function

Im ple m e n tatio n N a m e
RPL

Ripple Carry

Parameter Description

CLA

Carry Look-ahead

BLC

Binary Look-ahead Carry

Parameter

Function

Legal Range

Width

W ord Length of A and S U M

Width
1

Access
Com ponent Instantiation Operator Inferencing

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01
NEC-SM-LCS

131

ENEC Design Ware

NEC_SM01_INCDEC-A1A1
SUM1INC_DECINC_DEC
11

1Implementation

RPL

CLA
BLC

RPL
CLA
BLCCLA

2
Component InstantiationOperator Inferencing2Operator InferencingOperator

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3
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4. 5NEC Design Ware
Operator Inferencing
ImplementationBLC

VHDL
library IEEE, synopsys;
use synopsys.attributes.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity INCREMENTER_DECREMENTER is
generic(width : Integer)
port(IN1 : in std_logic_vector(width-1 downto 0);
CTL : in std_logic;
SUM : out std_logic_vector(width-1 downto 0));
end INCREMENTER_DECREMENTER;
architecture imp1 of INCREMENTER_DECREMENTER is
signal in_signed, sum_signed : SIGNED(width-1 downto 0);
begin
in_signed <= SIGNED(IN1);
process(in_signed, CTL);
constant r0 : resource := 0;
attribute map_to_module of r0:constant is "NEC_SM01_INCDEC";
attribute implementation of r0:constant is "BLC";
attribute ops
of r0:constant is "A1";
begin
if(CTL = '0')then
sum_signed <= in_signed + 1;
else
sum_signed <= in_signed - 1;
end if;
end process;

-- pragma label A1
-- pragma label A1

SUM <= STD_LOGIC_VECTOR(sum_signed);

end imp1;

Verilog
module incrementer_decrementer(IN1, CTL, SUM);
parameter wordlength = 8;
input [wordlength-1:0]IN1;
input CTL;
output [wordlength-1:0]SUM;
reg
[wordlength-1:0]SUM;
always @(IN1 or CTL)
begin : b1
/* synopsys resource r0:
map_to_module = "NEC_SM01_INCDEC",
implementation = "BLC",
ops
= "A1";
*/
if(CTL = 0)
SUM = IN1 + 1;
else
SUM = IN1 - 1;
end
endmodule

// synopsys label A1
// synopsys label A1

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E. 3. 12NEC_SM01_SUB
Block Type

Function

NEC_SM01_SUB

SSI Family

Subtractor

Logic Diagram

A
DIFF
B
CO
CI

Functional Description

Pin Description
Pin Name

Size

Type

Function

CI

DIFF

CO

Width

Input

Input data

A-B

Carry-out

Width

Input

Input data

A-B-1

Carry-out

CI

Input

Carry-in

DIFF

Width

Output

Difference of A-B

CO

Output

Carry-out

Implementations
Function

Im ple m e n tatio n N a m e

Parameter Description

RPL

Ripple Carry

CLA

Carry Look-ahead

BLC

Binary Look-ahead Carry

Parameter

Function

Legal Range

Width

W ord Length of A, B and DIFF

Width
1

Access
Com ponent Instantiation Operator Inferencing

134

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01
NEC-SM-LCS

ENEC Design Ware

NEC_SM01_SUB2A, BCIDIFF
CO

1Implementation

RPL

CLA
BLC

RPL
CLA
BLCCLA

2
Component InstantiationOperator Inferencing2Operator InferencingOperator

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3
Component Instantiation
4. 5NEC Design Ware
Operator Inferencing
ImplementationBLC

VHDL
library IEEE, synopsys;
use synopsys.attributes.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity SUBTRACTOR is
generic(width : Integer)
port(IN1, IN2 : in std_logic_vector(width-1 downto 0);
DIFF
: out std_logic_vector(width-1 downto 0));
end SUBTRACTOR;
architecture imp1 of SUBTRACTOR is
signal in1_signed, in2_signed, sum_signed : SIGNED(width-1 downto 0);
begin
in1_signed <= SIGNED(IN1);
in2_signed <= SIGNED(IN2);
process(in1_signed, in2_signed);
constant r0:resource := 0;
attribute map_to_module of r0:constant is "NEC_SM01_SUB";
attribute implementation of r0:constant is "BLC";
attribute ops
of r0:constant is "A1";
begin
diff_signed <= in1_signed - in2_signed;
end process;

-- pragma label A1

DIFF <= STD_LOGIC_VECTOR(diff_signed);

end impl;

Verilog
module subtractor(IN1, IN2, DIFF);
parameter wordlength = 8;
input [wordlength-1:0]IN1, IN2;
output [wordlength-1:0]DIFF;
reg
[wordlength-1:0]DIFF;
always @(IN1 or IN2)
begin : b1
/* synopsys resource r0:
map_to_module = "NEC_SM01_SUB",
implementation = "BLC",
ops
= "A1";
*/
DIFF = IN1 - IN2; // synopsys label A1
end
endmodule

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E. 3. 13NEC_SM02_MAC_TC
Block Type

Function

NEC_SM02_MAC_TC

SSI Family

Multiplier-Accumulator
2s complment data

Logic Diagram

MAC

Functional Description

Pin Description
P in N a m e

Size

Type

Function

MAC

A_Width

Input

2s com plm ent

Multiplier

AB+C

B_Width

Input

2s complment

Multiplicand

A_Width+B_Width

Input

2s com plm ent

Addition Data

2s complement 2s complement 2s complement

MAC

B+C
2s complment

A_Width+B_Width Output Result A

Implementations
Function

Parameter

Function

Legal Range

Carry Save Array

A_Width

Word Length of A

A_ Width
1024
2

Wallace Tree

B_Width

Word Length of B

B_ Width
1024
2

Im ple m e n tatio n N a m e
CSA
WALL

Parameter Description

Access
Com ponent Instantiation Operator Inferencing

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01, NEC_SM02
NEC-SM-LCS

137

ENEC Design Ware

NEC_SM02_MAC_TCA, BCMAC
signed2s complement

1Implementation

CSA

WALL

CSA
WALL Wallace-Tree

2
Component Instantiation

138

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E. 3. 14NEC_SM02_MAC_US
Block Type

Function

NEC_SM02_MAC_US

SSI Family

Multiplier-Accumulator
Unsigned

Logic Diagram

MAC

Functional Description

Pin Description
P in N a m e

Size

Type

Function

MAC

A_Width

Input

Unsigned

M ultiplier

AB+C

B_Width

Input

Unsigned

M ultiplicand

Unsigned

Unsigned

Unsigned

A_Width+B_Width

Input

Unsigned

Addition Data

MAC

B+C
Unsigned

A_Width+B_Width Output Result A

Implementations
Function

Parameter

Function

Legal Range

Carry Save Array

A_Width

Word Length of A

A_ Width
1024
2

Wallace Tree

B_Width

Word Length of B

B_ Width
1024
2

Im ple m e n tatio n N a m e
CSA
WALL

Parameter Description

Access
Com ponent Instantiation Operator Inferencing

Operator

Library
Required License

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NEC_SM01, NEC_SM02
NEC-SM-LCS

139

ENEC Design Ware

NEC_SM02_MAC_USA, BCMAC
unsigned

1Implementation

CSA

WALL

CSA
WALL Wallace-Tree

2
Component Instantiation

140

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E. 3. 15NEC_SM02_MULT_TC
Block Type

Function

NEC_SM02_MULT_TC

SSI Family

Multiplier
2s complement data

Logic Diagram

PRODUCT

Functional Description

Pin Description
P in N a m e

Size

Type

Function

PRODUCT

A_Width

Input

2s com plem ent

M ultiplier

AB

B_Width

Input

2s com plem ent

M ultiplicand

2s complement 2s complement 2s complement

B
2s complement

PRODUCT A_Width+B_Width Output Product A

Implementations

Parameter Description

Function

Parameter

Function

Legal Range

Carry Save Array

A_Width

Word Length of A

A_ Width
1024
2

Wallace Tree

B_Width

Word Length of B

B_ Width
1024
2

Im ple m e n tatio n N a m e
CSA
WALL

Access
Com ponent Instantiation Operator Inferencing

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01, NEC_SM02
NEC-SM-LCS

141

ENEC Design Ware

NEC_SM02_MULT_TC2A, BPRODUCT
signed2s complement

1Implementation

CSA

WALL

CSA
WALL Wallace-Tree

2
Component InstantiationOperator Inferencing2Operator InferencingOperator
VerilogComponent Instantiation

142

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3
Component Instantiation
4. 5NEC Design Ware
Operator Inferencing
ImplementationCSA

VHDL
library IEEE, synopsys;
use synopsys.attributes.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity MULTIPLIER is
generic(Xbit, Ybit : Integer)
port(IN1 : in std_logic_vector(Xbit-1 downto 0);
IN2 : in std_logic_vector(Ybit-1 downto 0);
OUT : out std_logic_vector(Xbit+Ybit-1 downto 0));
end MULTIPLIER;
architecture imp1 of MULTIPLIER is
signal in1_signed : SIGNED(Xbit-1 downto 0);
signal in2_signed : SIGNED(Ybit-1 downto 0);
signal out_signed : SIGNED(Xbit+Ybit-1 downto 0);
begin
in1_signed <= SIGNED(IN1);
in2_signed <= SIGNED(IN2);
process(in1_signed, in2_signed);
constant r0:resource := 0;
attribute map_to_module of r0:constant is "NEC_SM02_MULT_TC";
attribute implementation of r0:constant is "CSA";
attribute ops
of r0:constant is "A1";
begin
out_signed <= in1_signed * in2_signed;
end process;

-- pragma label A1

OUT <= STD_LOGIC_VECTOR(out_signed);

end imp1;

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E. 3. 16NEC_SM02_MULT_US
Block Type

Function

NEC_SM02_MULT_US

SSI Family

Multiplier
Unsigned data

Logic Diagram

PRODUCT

Functional Description

Pin Description
P in N a m e

Size

Type

Function

PRODUCT

A_Width

Input

U nsigned

M ultiplier

AB

B_Width

Input

Unsigned

M ultiplicand

unsigned

unsigned

unsigned

B
Unsigned

PRODUCT A_Width+B_Width Output Product A

Implementations
Function

Parameter

Function

Legal Range

Carry Save Array

A_Width

Word Length of A

A_ Width
1024
2

Wallace Tree

B_Width

Word Length of B

B_ Width
1024
2

Im ple m e n tatio n N a m e
CSA
WALL

Parameter Description

Access
Com ponent Instantiation Operator Inferencing

144

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01, NEC_SM02
NEC-SM-LCS

ENEC Design Ware

NEC_SM02_MULT_US2A, BPRODUCT
unsigned

1Implementation

CSA

WALL

CSA
WALL Wallace-Tree

2
Component InstantiationOperator Inferencing2Operator InferencingOperator

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145

ENEC Design Ware

3
Component Instantiation
4. 5NEC Design Ware
Operator Inferencing
ImplementationCSA

VHDL
library IEEE, synopsys;
use synopsys.attributes.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity MULTIPLIER is
generic(Xbit, Ybit : Integer)
port(IN1 : in std_logic_vector(Xbit-1 downto 0);
IN2 : in std_logic_vector(Ybit-1 downto 0);
OUT : out std_logic_vector(Xbit+Ybit-1 downto 0));
end MULTIPLIER;
architecture imp1 of MULTIPLIER is
signal in1_unsigned : UNSIGNED(Xbit-1 downto 0);
signal in2_unsigned : UNSIGNED(Ybit-1 downto 0);
signal out_unsigned : UNSIGNED(Xbit+Ybit-1 downto 0);
begin
in1_unsigned <= UNSIGNED(IN1);
in2_unsigned <= UNSIGNED(IN2);
process(in1_unsigned, in2_unsigned);
constant r0:resource := 0;
attribute map_to_module of r0:constant is "NEC_SM02_MULT_US";
attribute implementation of r0:constant is "CSA";
attribute ops
of r0:constant is "A1";
begin
out_unsigned <= in1_unsigned * in2_unsigned;
end process;

-- pragma label A1

OUT <= STD_LOGIC_VECTOR(out_unsigned);

end imp1;

Verilog
module multiplier(IN1, IN2, OUT);
parameter xbit = 8, ybit = 8;
input [xbit-1:0]IN1;
input [ybit-1:0]IN2;
output [xbit+ybit-1:0]OUT;
reg
[15:0]OUT;
always @(IN1 or IN2)
begin : b1
/* synopsys resource r0:
map_to_module = "NEC_SM02_MULT_US";
implementation = "CSA";
ops
= "A1";
*/
OUT = IN1 * IN2;
end
endmodule

146

// synopsys label A1

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E. 3. 17NEC_SM02_SUM
Block Type

Function

NEC_SM02_SUM

SSI Family

Vector Adder

Logic Diagram

INPUT

SUM

Functional Description

Pin Description
Size

P in N a m e
INPUT
A

SUM

Type

INPUT N u m _Inputs
Input

A[Input_W idth-1:0]+A[2 Input_W idth-1:Input_W idth]+

A[3 Input_W idth-1:2 Input_W idth]+...+

Function
C oncatenated input data

Input_ W idth
SUM

Input_Width Output D ata su m m ation

A[Num _Inputs Input_W idth-1:(Num _Inputs-1) Input_W idth]

Implementations
Function

Im ple m e n tatio n N a m e
RPL

Ripple Carry

CSA

Carry Save Array

WALL

Parameter Description
Parameter

Function

Legal Range

N u m _Inputs

Number of inputs

N u m _Inp uts
1024
1

Input_ Width

Input word length

Input_ W idth
1024
1

Wallace Tree

Access
Com ponent Instantiation Operator Inferencing

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01, NEC_SM02
NEC-SM-LCS

147

ENEC Design Ware

NEC_SM02_SUMINPUT1SUM

n1

SUMm10=

Aj1m1jm

j=0

1Num_InputsInput_Width1
1INPUT

1Implementation

RPL

CSA

WALL

RPL

CSA
WALL Wallace-Tree

2
Component Instantiation

148

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E. 3. 18NEC_SM03_BICTR_DECODE
Block Type

Function

NEC_SM03_BICTR_DECODE

Up/Down Binary Counter with Output Decode

Logic Diagram

DATA
UP_DN

COUNT_DEC

LOAD
CEN
CLK

TERCNT

RESET

Truth Table

Pin Description
Pin Name

Size

Type

Function

RESET

LOAD

CEN

UP_DN

Operation

DATA

Width

Input

Counter load input

Reset

UP_DN

Input

High for count up and low for

Load

Standby

Count down

Count up

count down
LOAD

CEN

Input

Count enable, active high

CLK

Input

C loc k

Input

Counter reset, active low

COUNT_DEC
TERCNT

1
2

Width

Output Binary decoded count value

Output Terminal count flag, active high

Implementations

STR

Enable data load to counter,

active low

RESET

Parameter Description

Function

Im ple m e n tatio n N a m e

Input

Synthesis model

Parameter

Function

Legal Range

Width

Width of data input bus

Width
1

Access
Com ponent Instantiation Operator Inferencing

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01, NEC_SM03
NEC-SM-LCS

149

ENEC Design Ware

Block Type

Function

NEC_SM03_BICTR_DECODE

Up/Down Binary Counter with Output Decode

Functional Operation
Reset, Load and Count SequenceWidth = 4

CLK

DATA

0000

LOAD

CEN

UP_DN

RESET

COUNT_DEC
TERCNT

0001h

0002h 0004h 0008h 0010h 0020h 0040h 0080h 0100h 0200h 0400h 0800h 1000h

Up and Down Counting and Count-to SequenceWidth = 4

CLK

DATA

0000

LOAD

CEN

UP_DN

RESET

COUNT_DEC

2000h 4000h 8000h 0001h 0002h 0004h 0008h 0010h 0020h 0010h 0008h 0004h 0002h 0001h 8000h 4000h 2000h 1000h 0800h

TERCNT

150

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ENEC Design Ware

NEC_SM03_BICTR_DECODEUP/DOWN
Width000...0COUNT_DEC00...01111...1COUNT_DEC
10...002

Width

CLK

RESET000...0COUNT_DEC00...01
RESET1RESET

UP_DNCLKUP_DN
UP_DN
DATALOADDATACLK

CENCEN

COUNT_DEC000...012Width110...00
TERCNTCOUNT_DEC = 10...00
COUNT_DEC = 00...01

1
Component Instantiation

A14353JJ3V0UM00

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ENEC Design Ware

E. 3. 19NEC_SM03_BICTR_DCNTO
Block Type

Function

NEC_SM03_BICTR_DCNTO

Up/Down Binary Counter with Dynamic Count-to Flag

Logic Diagram

DATA
COUNT_TO
COUNT
UP_DN
LOAD
CEN

TERCNT

CLK
RESET

Truth Table

Pin Description
Pin Name

Size

Type

Function

RESET

LOAD

CEN

UP_DN

Operation

DATA

Width

Input

Counter load input

Reset

COUNT_TO

Width

Input

Count compare input

Load

UP_DN

Input

High for count up and low for

Standby

Count down

Count up

count down
LOAD

STR

Enable data load to counter,

active low

CEN

Input

Count enable, active high

CLK

Input

C loc k

RESET

Input

Counter reset, active low

COUNT

Width

TERCNT

Implementations

Output Output count bus

Output Terminal count flag, active high

Parameter Description

Function

Im ple m e n tatio n N a m e

Input

Synthesis model

Parameter

Function

Legal Range

Width

Width of data input bus

Width
1

Access
Com ponent Instantiation Operator Inferencing

152

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01, NEC_SM03
NEC-SM-LCS

ENEC Design Ware

Block Type

Function

NEC_SM03_BICTR_DCNTO

Up/Down Binary Counter with Dynamic Count-to Flag

Functional Operation
Reset, Load, and Count_to SequenceWidth = 4

CLK

DATA

LOAD

CEN

UP_DN

RESET

COUNT_TO

0h

4h

COUNT

TERCNT

0h

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

3h

2h

1h

0h

Fh

Eh

Dh

Ch

Bh

Up and Down Counting and Count-to SequenceWidth = 4

CLK

DATA

LOAD

CEN

UP_DN

RESET

COUNT_TO

0h

COUNT

TERCNT

4h
Dh

Eh

Fh

0h

1h

2h

3h

4h

5h

4h

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ENEC Design Ware

NEC_SM03_BICTR_DCNTODynamic Count-toUP/DOWN
COUNT_TOTERCNTterminal count
TERCNTLOAD
DATA
Width

Width000...0111...12

CLK

RESET000...0RESET1
RESET
COUNT_TOWidthCOUNTCOUNT_TOTERCNT
1
UP_DNCLKUP_DN
UP_DN
DATALOADDATACLK

CENCEN

1
Component Instantiation

2
NEC_SM03_BICTR_DCNTO020
TERCNTLOADE2DATA
00000COUNT_TO10100

E2NEC_SM03_BICTR_DCNT

Counter ApplicationWidth = 5

00000

DATA

10100

COUNT_TO
COUNT
UP_DN
LOAD
CEN

TERCNT

CLK
RESET

154

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E. 3. 20NEC_SM03_BICTR_SCNTO
Block Type

Function

NEC_SM03_BICTR_SCNTO

Up/Down Binary Counter with Static Count-to Flag

Logic Diagram

DATA
UP_DN

COUNT

LOAD
CEN
CLK

TERCNT

RESET

Truth Table

Pin Description
Pin Name

Size

Type

Function

RESET

LOAD

CEN

UP_DN

Operation

DATA

Width

Input

Counter load input

Reset

UP_DN

Input

High for count up and low for

Load

Standby

Count down

Count up

count down
LOAD

STR

Enable data load to counter,

active low

CEN

Input

Count enable, active high

CLK

Input

C loc k

Input

Counter reset, active low

RESET

COUNT

Width

TERCNT

Implementations

Output Output count bus

Output Terminal count flag, active high

Parameter Description

Function

Im ple m e n tatio n N a m e

Input

Synthesis model

Parameter

Function

Legal Range

Width

Width of data input bus

Count_To

Count-to Value

Width
1
2

Width

Count_To
1
-1

Access
Com ponent Instantiation Operator Inferencing

Operator

Library
Required License

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NEC_SM01, NEC_SM03
NEC-SM-LCS

155

ENEC Design Ware

Block Type

Function

NEC_SM03_BICTR_SCNTO

Up/Down Binary Counter with Static Count-to Flag

Functional Operation
Reset, Load and Count-to SequenceWidth = 4, Count_To = 3h

CLK

0h

0h

DATA

LOAD

CEN

UP_DN

RESET

COUNT
TERCNT

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Fh

Eh

Dh

Ch

Bh

Up and Down Counting and Count-to SequenceWidth = 4, Count_To = 3h

CLK

0h

DATA

LOAD

CEN

UP_DN

RESET

COUNT

Dh

Eh

Fh

0h

1h

2h

3h

4h

5h

4h

3h

2h

TERCNT

156

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1h

0h

ENEC Design Ware

NEC_SM03_BICTR_SCNTOStatic Count-toUP/DOWN
COUNT_TOTERCNTterminal countTERCNT
LOADDATA

Width000...0111...12

Width

CLK

RESET000...0RESET1
RESET
COUNT_TO12Width1COUNTCOUNT_TO
TERCNT1
UP_DNCLKUP_DN
UP_DN
DATALOADDATACLK

CENCEN

1
Component Instantiation

2
NEC_SM03_BICTR_SCNTO020
TERCNTLOADE3DATA
00000COUNT_TO10100

E3NEC_SM03_BICTR_SCNTO

Counter ApplicationWidth = 5, Count_To = 10100

00000

DATA
UP_DN

COUNT

LOAD
CEN
CLK

TERCNT

RESET

A14353JJ3V0UM00

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ENEC Design Ware

E. 3. 21NEC_SM03_CNTR__GRAY
Block Type

Function

NEC_SM03_CNTR_GRAY

Gray Code Counter

Logic Diagram

CEN
COUNT

CLK
COUNT_DEC
RESET

Truth Table

Pin Description
Pin Name

Size

Type

Function

RESET

CEN

Operation

CEN

Input

Counter enable, active high

Reset

CLK

Input

Clock

Standby

RESET

Input

Counter reset, active low

Count

COUNT

Width

COUNT_DEC

Width

Implementations

STR

Output Bit decode of current count

Parameter Description

Function

Im ple m e n tatio n N a m e

Output Gray coded counter output

Synthesis model

Parameter

Function

Legal Range

Width

Word length of counter

Width
1

Access
Com ponent Instantiation Operator Inferencing

158

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01, NEC_SM03
NEC-SM-LCS

ENEC Design Ware

Block Type
NEC_SM03_CNTR_GRAY

Function
Gray Code Counter

Functional Operation
Reset, Cen and Count SequenceWidth = 4

CLK

CEN

RESET

0000

0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000

0001h

0002h 0004h 0008h 0010h 0020h 0040h 0080h 0100h 0200h 0400h 0800h 1000h 2000h 4000h 8000h

COUNT

COUNT_DEC

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ENEC Design Ware

NEC_SM03_CNTR_GRAY
Width2

Width

CLK

RESET000...0RESET1
RESET
CENCEN

1
Component Instantiation

160

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ENEC Design Ware

E. 3. 22NEC_SM03_LFSR_DCNTO
Block Type

Function

NEC_SM03_LFSR_DCNTO

LFSR Counter with Dynamic Count-to Flag

Logic Diagram

DATA
COUNT_TO

COUNT

LOAD
CEN
CLK

TERCNT

RESET

Truth Table

Pin Description
Pin Name

Size

Type

Function

RESET

LOAD

CEN

Operation

DATA

Width

Input

Counter load input

Reset

COUNT_TO

Width

Input

Count compare input

Load

LOAD

Input

Enable data load to counter,

Standby

Count

active low
CEN

Input

Count enable, active high

CLK

Input

Clock

RESET

Input

Count reset, active low

COUNT

Width

TERCNT

Implementations

STR

Output Terminal count flag, active high

Parameter Description

Function

Im ple m e n tatio n N a m e

Output Output count bus

Synthesis model

Parameter

Function

Legal Range

Width

Word length of counter

50
Width
1

Access
Com ponent Instantiation Operator Inferencing

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01, NEC_SM03
NEC-SM-LCS

161

ENEC Design Ware

Block Type

Function

NEC_SM03_LFSR_DCNTO

LFSR Counter with Dynamic Count-to Flag

Functional Operation
Reset, Load, Cen, and Count_to SequenceWidth = 4

CLK

DATA

LOAD

CEN

RESET

COUNT_TO

7h

COUNT

TERCNT

162

0h

0h

8h

Ch

Eh

7h

Bh

Dh

A14353JJ3V0UM00

6h

3h

9h

4h

Ah

ENEC Design Ware

NEC_SM03_LFSR_DCNTODynamic Count-to
LFSRLinear Feedback Shift Register
2

LFSR
Width150
DATALOADDATACLK

CENCEN

RESET000...0
COUNT2Width111...11

COUNT_TOTERCNTterminal count
VLSIbuilt-in

1
Component Instantiation

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ENEC Design Ware

E. 3. 23NEC_SM03_LFSR_LOAD
Block Type

Function

NEC_SM03_LFSR_LOAD

LFSR Counter with Loadable Data Input

Logic Diagram

DATA
LOAD
CEN

COUNT

CLK
RESET

Truth Table

Pin Description
Pin Name

Size

Type

Function

RESET

LOAD

CEN

Operation

DATA

Width

Input

Counter load input

Reset

LOAD

Input

Enable data load to counter,

data is XOR with count

Standby

CEN

Input

C o u nt enable, active high

Count

CLK

Input

C loc k

RESET

Input

Counter reset, active low

COUNT

Width

active low

Implementations

STR

Parameter Description

Function

Im ple m e n tatio n N a m e

Output Output count bus

Synthesis model

Parameter

Function

Legal Range

Width

Word length of counter

50
Width
1

Access
Com ponent Instantiation Operator Inferencing

164

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01, NEC_SM03
NEC-SM-LCS

ENEC Design Ware

Block Type

Function

NEC_SM03_LFSR_LOAD

LFSR Counter with Loadable Data Input

Functional Operation
Reset, Count, and Cen SequenceWidth = 4

CLK

DATA

0h

LOAD

CEN

RESET

COUNT

0h

8h

Ch

Eh

7h

Bh

Dh

6h

3h

1h

4h

Eh

9h

4h

Ah

5h

2h

1h

9h

4h

Ah

5h

2h

Load and Count SequenceWidth = 4

CLK

4h

DATA

LOAD

CEN

RESET

COUNT

Bh

Dh

6h

3h

9h

4h

Ah

3h

Dh

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6h

3h

165

ENEC Design Ware

NEC_SM03_LFSR_LOAD
LFSRLinear Feedback Shift Register
2

LFSR
Width150
DATALOADDATACOUNTXOR
LOADLFSR
CENCEN

RESET000...0
COUNT2Width111...11

VLSIbuilt-in

1
Component Instantiation

166

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ENEC Design Ware

E. 3. 24NEC_SM03_LFSR_SCNTO
Block Type

Function

NEC_SM03_LFSR_SCNTO

LFSR Counter with Static Count-to Flag

Logic Diagram

DATA
LOAD

COUNT

CEN
CLK

TERCNT

RESET

Truth Table

Pin Description
Pin Name

Size

Type

Function

RESET

LOAD

CEN

Operation

DATA

Width

Input

Counter load input

Reset

LOAD

Input

Enable data load to counter,

Load

Standby

CEN

Input

Count enable, active high

Count

CLK

Input

Clock

RESET

Input

Counter reset, active low

COUNT

Width

TERCNT

active low

Implementations

STR

Output Terminal count flag, active high

Parameter Description

Function

Im ple m e n tatio n N a m e

Output Output count bus

Synthesis model

Parameter

Function

Width

Word length of counter

Count_To

Count-to Value

Legal Range
50
Width
1
2

Width

2
Count_To
1

Access
Com ponent Instantiation Operator Inferencing

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01, NEC_SM03
NEC-SM-LCS

167

ENEC Design Ware

Block Type

Function

NEC_SM03_LFSR_SCNTO

LFSR Counter with Static Count-to Flag

Functional Operation
Reset, Load, Cen, and Count_to SequenceWidth = 4, Count_To = 7h

CLK

DATA

0h

LOAD

CEN

RESET

COUNT
TERCNT

168

0h

8h

Ch

Eh

7h

Bh

Dh

A14353JJ3V0UM00

6h

3h

9h

4h

Ah

ENEC Design Ware

NEC_SM03_LFSR_SCNTOStatic Count-to
LFSRLinear Feedback Shift Register
2

LFSR
Width150
DATALOADDATACLK

CENCEN

RESET000...0
COUNT2Width111...11

COUNT_TOTERCNTterminal count
VLSIbuilt-in

1
Component Instantiation

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ENEC Design Ware

E. 3. 25NEC_SM03_LFSR_UPDN
Block Type

Function

NEC_SM03_LFSR_UPDN

LFSR Up/Down Counter

Logic Diagram

UP_DN
COUNT
CEN

CLK
TERCNT
RESET

Truth Table

Pin Description
Pin Name

Size

Type

Function

UP_DN

Input

High for count up and low for

RESET

LOAD

CEN

Operation

Reset

Standby

CEN

Input

Count enable, active high

Count down

CLK

Input

Clock

Count up

RESET

Input

Counter reset, active low

COUNT

Width

TERCNT

count down

Implementations

STR

Output Terminal count flag, active high

Parameter Description

Function

Im ple m e n tatio n N a m e

Output Output count bus

Synthesis model

Parameter

Function

Legal Range

Width

Word length of counter

50
Width
1

Access
Com ponent Instantiation Operator Inferencing

170

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01, NEC_SM03
NEC-SM-LCS

ENEC Design Ware

Block Type

Function

NEC_SM03_LFSR_UPDN

LFSR Up/Down Counter

Functional Operation
Reset, Cen, Count SequenceWidth = 4

CLK

CEN

UP_DN

RESET

COUNT
TERCNT

0h

8h

Ch

Eh

7h

Bh

Dh

6h

3h

9h

4h

Ah

5h

1h

2h

5h

Ah

4h

9h

Up and Down Counting and Count-to SequenceWidth = 4

CLK

CEN

UP_DN

RESET

COUNT

2h

1h

0h

8h

Ch

Eh

7h

Bh

7h

Eh

Ch

8h

0h

TERCNT

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ENEC Design Ware

NEC_SM03_LFSR_UPDN
LFSRLinear Feedback Shift Register2

LFSR
UP_DNUP_DN

CENCEN

RESET000...0
COUNT2Width111...11

TERCNT000...001UP_DN
10...00UP_DN00...01

Built-in self-testBIST

1
Component Instantiation

172

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ENEC Design Ware

E. 3. 26NEC_SM03_UPDN_CTR
Block Type

Function

NEC_SM03_UPDN_CTR

Up/Down Counter

Logic Diagram

DATA
UP_DN

COUNT

LOAD
CEN
CLK

TERCNT

RESET

Truth Table

Pin Description
Pin Name

Size

Type

Function

RESET

LOAD

CEN

UP_DN

Operation

DATA

Width

Input

Counter load input

Reset

UP_DN

Input

High for count up and low for

Load

Standby

Count down

Count up

Implementations

count down
LOAD

Input

Enable data load to counter,

active low

CEN

Input

Count enable, active high

CLK

Input

Clock

Input

Counter reset, active low

RESET

COUNT

Width

TERCNT

Output Output count bus

Output Terminal count flag, active high

Function

Im ple m e n tatio n N a m e

Parameter Description

RPL

Synthesis model

CLA

Synthesis model

Parameter

Function

Legal Range

BLC

Synthesis model

Width

Width of data input bus

Width
1

Access
Com ponent Instantiation Operator Inferencing

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM01, NEC_SM03
NEC-SM-LCS

173

ENEC Design Ware

Block Type

Function

NEC_SM03_UPDN_CTR

Up/Down Counter

Functional Operation
Reset, Load and Count SequenceWidth = 4

CLK

0h

0h

DATA

LOAD

CEN

UP_DN

RESET

COUNT
TERCNT

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

2h

1h

0h

Fh

Eh

Dh

Ch

Bh

Up and Down Counting and Count-to SequenceWidth = 4

CLK

0h

DATA

LOAD

CEN

UP_DN

RESET

COUNT

Dh

Eh

Fh

0h

1h

2h

3h

4h

5h

4h

3h

TERCNT

174

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ENEC Design Ware

NEC_SM03_UPDN_CTRUP/DOWN
Width000...0111...12

Width

CLK

RESET000...0RESET1
RESET
UP_DNCLKUP_DN
UP_DN
DATALOADDATACLK

CENCEN

TERCNTUP_DN11...11UP_DN
00...00

1Implementation

RPL

CLA
BLC

RPL
CLA
BLCCLA

2
Component Instantiation

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ENEC Design Ware

E. 3. 27NEC_SM04_FIFOCNTL_S_SF
Block Type

Function

NEC_SM04_FIFOCNTL_S_SF

Synchronous FIFO Controller with Static Flag Logic

Logic Diagram

FULL

WRQB

EMPTY
RRQB
THRESHOLD
CLK

R_ADDR
W_ADDR

RESET

WEB

Truth Table

Pin Description
Pin Name

Size

Type

Function

RESET

WRQB

RRQB

Operation

WRQB

Input

Input write request, active low

Reset

RRQB

Input

Input read request, active low

Write

CLK

Input

Clock

Read

RESET

Input

FIFO reset, active low

Hold

FULL

Output Output full, active high

EMPTY

Output O utput em pty, active high

THRESHOLD

Output Alm ost-full flag, active high

R_ADDR Bit_width
W _ AD D R Bit_width
WEB

Output Address output to read

Output Address output to write

Output Write enable

Bit_width = ceilinglog2Depth
Implementations
Function

Im ple m e n tatio n N a m e
STR

Parameter Description
Parameter

Synthesis model

Function

Depth

Word depth of FIFO

Level

Offset from full value.Used to

Legal Range
Depth
2
Le vel
D e pth
1

determine when threshold is asserted.

Access
Com ponent Instantiation Operator Inferencing

176

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM04
NEC-SM-LCS

ENEC Design Ware

Block Type

Function

NEC_SM04_FIFOCNTL_S_SF

Synchronous FIFO Controller with Static Flag Logic

Timing Waveforms1/2
Reset cycle
tcp

CLK

trpq

RESET

WRQB

RRQB

FULL
EMPTY

THRESHOLD

Write and read cycle

CLK

tws

twh

WRQB

twaddr

W_ADDR

twe

WEB

trs

trh

RRQB

traddr

R_ADDR

Timing diagram for full FIFO Controller

CLK

WRQB

tws

twh

RRQB

FULL

trs
tfup

trh
tfdn

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Block Type

Function

NEC_SM04_FIFOCNTL_S_SF

Synchronous FIFO Controller with Static Flag Logic

Timing Waveforms2/2
Timing diagram for empty FIFO Controller
CLK
RRQB

trs

trh

WRQB

EMPTY

tws
teup

twh
tedn

Timing diagram foralmost fullFIFO Controller

CLK

tws

twh

WRQB

RRQB

trs
ttup

trh
ttdn

FULL

178

A14353JJ3V0UM00

ENEC Design Ware

Block Type

Function

NEC_SM04_FIFOCNTL_S_SF

Synchronous FIFO Controller with Static Flag Logic

Functional Operation
Write and Read SequenceWidth = 4, Depth = 4, Level =2
CLK

WRQB

RRQB

RESET

W_ADDR

0h

1h

2h

3h

0h

1h

2h

3h

WEB

R_ADDR

FULL
EMPTY

THRESHOLD

3h

0h

1h

2h

3h

A14353JJ3V0UM00

0h

1h

2h

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ENEC Design Ware

NEC_SM04_FIFOCNTL_S_SFStatic FlagFIFO
WRQBCLKW_ADDR
FIFOFULL
RRQBCLKR_ADDR
FIFOEMPTY
FIFOFULL
FIFOEMPTY

RESET
FULL

EMPTY

THRESHOLDLevel

W_ADDRbit_widthDepth
R_ADDRbit_widthDepth
WEB

1
Component Instantiation

180

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2
NEC_SM04_FIFOCNTL_S_SFDual-Port RAMFIFO

E4NEC_SM04_FIFOCNTL_S_SF

FULL
FULL
WRQB

EMPTY
WRQB

EMPTY

RRQB

THRESHOLD

THRESHOLD

RRQB
CLK
CLK

R_ADDR

RESET

W_ADDR

RESET

WEB
NEC_SM04_FIFOCNTL_S_SF

DATAIN
DATAIN
RADDR
WADDR

DATAOUT
DATAOUT

RDB
WRB
CLK
Synchronous Dual-Port RAM

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E. 3. 28NEC_SM04_FIFO_S_SF
Block Type

Function

NEC_SM04_FIFO_S_SF

Synchronous FIFO with Static Flag Logic

Logic Diagram

FIFIN
FIFOUT
WRQB
FULL
RRQB
EMPTY
CLK
THRESHOLD
RESET

Truth Table

Pin Description
Pin Name

Size

Type

Function

RESET

WRQB

RRQB

Operation

FIFIN

Width

Input

Input FIFO bus

Reset

WRQB

Input

Input write request, active low

Write

RRQB

Input

Input read request, active low

Read

CLK

Input

Clock

Hold

RESET

Input

FIFO reset, active low

FIFOUT

Width

FULL

Output Output full, active high

EMPTY

Output O utput em pty, active high

THRESHOLD

Output Alm ost-full flag, active high

Implementations

STR

Parameter Description

Function

Im ple m e n tatio n N a m e

Output Output FIFO data bus

Synthesis model

Parameter

Function

Legal Range

Width

Width of data input bus

Width
1

Depth

Word depth of FIFO

Depth
2

Level

Offset from full value.Used to

Le vel
D e pth
1

determine when threshold is asserted.

Access
Com ponent Instantiation Operator Inferencing

182

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM04
NEC-SM-LCS

ENEC Design Ware

Block Type

Function

NEC_SM04_FIFO_S_SF

Synchronous FIFO with Static Flag Logic

Timing Waveforms1/2
Reset cycle
tcp

CLK

trpq

RESET

WRQB

RRQB

FULL
EMPTY

THRESHOLD

FIFOUT

all 0

Write and read cycle

CLK

tws

twh

WRQB

FIFIN

tds
X

tdh

datain

X
trs

trh

RRQB

tfd

FIFOUT

dataout

Timing diagram for full FIFO

CLK

WRQB

tws

twh

RRQB

FULL

trs
tfup

trh
tfdn

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ENEC Design Ware

Block Type

Function

NEC_SM04_FIFO_S_SF

Synchronous FIFO with Static Flag Logic

Timing Waveforms2/2
Timing diagram for empty FIFO
CLK

RRQB

trs

trh

WRQB

EMPTY

tws
teup

twh
tedn

Timing diagram for almost fullFIFO

CLK

WRQB

twh

RRQB

FULL

184

tws

trs
ttup

trh
ttdn

A14353JJ3V0UM00

ENEC Design Ware

Block Type

Function

NEC_SM04_FIFO_S_SF

Synchronous FIFO with Static Flag Logic

Functional Operation
Write and Read SequenceWidth = 4, Depth = 4, Level = 2
CLK

FIFIN

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

0h

WRQB

RRQB

RESET

FIFOUT
FULL
EMPTY

THRESHOLD

0h

1h

2h

3h

4h

A14353JJ3V0UM00

5h

Ah

Fh

185

ENEC Design Ware

NEC_SM04_FIFO_S_SFStatic FlagFIFOWidthDepth

WRQBCLKFIFINFIFOFULL

RRQBCLKFIFOUTFIFOEMPTY

FIFOFULL
FIFOEMPTY

FIFINWidth
FIFOUTWidth
RESETFIFOUT0
FULL

EMPTY

THRESHOLDLevel

1
Component Instantiation

186

A14353JJ3V0UM00

ENEC Design Ware

E. 3. 29NEC_SM04_STACK
Block Type

Function

NEC_SM04_STACK

Synchronous Stack

Logic Diagram

STIN
STOUT
PUSH
FULL
POP
EMPTY
CLK
RESET

Truth Table

Pin Description
Pin Name

Size

Type

Function

RESET

PUSH

POP

Operation

STIN

Width

Input

Input stack bus

Reset

PUSH

Input

Input push, active high

Hold

POP

Input

Input pop, active high

Write

CLK

Input

Clock

Read

RESET

Input

Input reset, active low

Hold

STOUT

Width

Output Output stack data bus

FULL

Output Output full, active high

EMPTY

Output O utput em pty, active high

Implementations
Function

Im ple m e n tatio n N a m e
STR

Parameter Description

Synthesis model

Parameter

Function

Legal Range

Width

Width of data input bus

Width
1

Depth

Word depth of stack

Depth
2

Access
Com ponent Instantiation Operator Inferencing

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM04
NEC-SM-LCS

187

ENEC Design Ware

Block Type

Function

NEC_SM04_STACK

Synchronous Stack

Timing Waveforms1/2
Reset cycle
tcp

CLK

trpq

RESET

PUSH

POP

FULL
EMPTY

STOUT

all 0

Write and read cycle

CLK

tpus

tpuh

PUSH

STIN

tds
X

tdh

datain

X
tpos

tpoh

RRQB

tfd

STOUT

dataout

Timing diagram for full STACK

CLK
PUSH

POP

tpuh

FULL

188

tpus

tpos
tfup

tpoh
tfdn

A14353JJ3V0UM00

ENEC Design Ware

Block Type

Function

NEC_SM04_STACK

Synchronous Stack

Timing Waveforms2/2
Timing diagram for empty STACK
CLK
POP

tpos

tpoh

PUSH

EMPTY

tpus
teup

tpuh
tedn

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ENEC Design Ware

Block Type

Function

NEC_SM04_STACK

Synchronous Stack

Functional Operation
Write and Read SequenceWidth = 4, Depth = 4

CLK

STIN

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

PUSH

POP

RESET

STOUT
FULL
EMPTY

190

0h

6h

5h

A14353JJ3V0UM00

4h

3h

0h

ENEC Design Ware

NEC_SM04_STACKSTACKWidthDepth
PUSHCLKSTINSTACKFULL

POPCLKSTOUTSTACKEMPTY

STINWidth
STOUTWidth
RESETSTOUT0
FULL

EMPTY

1
Component Instantiation

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ENEC Design Ware

E. 3. 30NEC_SM05_ARBITER
Block Type

Function

NEC_SM05_ARBITER

Round Robin Arbiter

Logic Diagram

REQ
DONE
GNT
CLK
RESET

Truth Table

Pin Description
Pin Name

Size

Type

Function

state

R ESET

REQ

DONE

next state

REQ

Nport

Input

Requests for resource

wait request

DONE

Input

Indicates that a

w ait request

any request

change priority

transfer is finished

change priority

evaluate request

CLK

Input

Clock

evaluate request

any request

change priority

RESET

Input

Reset

evaluate request

any request

wait request

GNT

Nport

Implementations

Output Indicates resource granted

Parameter Description

Im ple m e n tatio n N a m e

Function

Parameter

JUST

Single clock cycle priority resolution.

Nport

JUST2

Tw o clock cycle priority resolutio n.

Function
Number of ports

Legal Range
Nport
2

accessing resource

Access
Com ponent Instantiation Operator Inferencing

192

Operator

Library

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NEC_SM05

ENEC Design Ware

Block Type

Function

NEC_SM05_ARBITER

Round Robin Arbiter

Timing Waveforms
tcp

CLK

trpw

RESET

REQ

tsreq

threq

Request
tsdone

thdone

DONE

tdgnth

tdgntl
Granted

GNT

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Block Type
NEC_SM05_ARBITER

Function
Round Robin Arbiter

Functional Operation
Write and Read SequenceNport = 4

CLK

REQ0

REQ1

REQ2

REQ3

DONE

GNT0

GNT1

GNT2

GNT3

194

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ENEC Design Ware

NEC_SM05_ARBITERRound Robin Arbiter

NportREQRound Robin Arbiter

GNT
DONE
GNTREQ1
RESET

reqn

req0

req2

req1

req1

req1

reqn1

req2

req0

reqn1

reqn

1Implementation
JUST

JUST2 2

2
Component Instantiation

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ENEC Design Ware

E. 3. 31NEC_SM05_PAR_GEN
Block Type

Function

NEC_SM05_PAR_GEN

Parity Generator and Checker

Logic Diagram

DATAIN

PARITY

Functional Description

Pin Description
Pin Name

Size

Type
Input

DATAIN

Par_type

PARITY

DATAIN

Width

even#1s

PARITY

odd#1s

even#1s

odd#1s

Implementations

STR

Input data

Output Generated parity

Parameter Description

Function

Im ple m e n tatio n N a m e

Function

Synthesis model

Parameter

Function

Legal Range

Width

Defines the width of the input bus

1
Width

Par_type D efines the type of parity Par_type = 0 or 1

Access
Com ponent Instantiation Operator Inferencing

196

Operator

Library
Required License

A14353JJ3V0UM00

NEC_SM05
NEC-SM-LCS

ENEC Design Ware

NEC_SM05_PAR_GENDATAIN
PARITY
oddeven

1
Component Instantiation

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FAX
E-mail

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