RETARDO INERCIAL

RETARDO DE TRANSPORTE

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%5 PROGRAMA DE COMPARACIN VARIABLES Y SEALES :: DENTRO DE UN PROCESO, SOLAMENTE LAS VARIABLES SE ACTUALIZAN CORRECTAMENTE, LAS SEALES NO.. entity trece is Port ( d1 : in STD_LOGIC; d2 : in STD_LOGIC; d3 : in STD_LOGIC; res1 : out STD_LOGIC; res2 : out STD_LOGIC); end trece;

architecture Behavioral of trece is signal sig_s1: std_logic; begin

proc1: process(d1,d2,d3) variable var_s1: std_logic; begin var_s1 := d1 and d2; res1 <= var_s1 xor d3; end process; proc2: process(d1,d2,d3) begin sig_s1 <= d1 and d2; res2 <= sig_s1 xor d3; end process end behavioral; &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& SUMADOR DE N BITS USANDO OPERACIONES MATEMTICAS + entity ADDER is generic(n: natural :=2); port( A: in std_logic_vector(n-1 downto 0); B: in std_logic_vector(n-1 downto 0); carry: out std_logic; sum: out std_logic_vector(n-1 downto 0) ); end ADDER; -------------------------------------------------------architecture behv of ADDER is -- define a temparary signal to store the result signal result: std_logic_vector(n downto 0); begin -- the 3rd bit should be carry result <= ('0' & A)+('0' & B); sum <= result(n-1 downto 0); carry <= result(n); end behv;

+++++++++++++++++++++++++++++++++++++++++++++++++++++++= ALU
entity ALU is port( A: B: Sel: in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0);

Res:

out std_logic_vector(1 downto 0)

);

end ALU; --------------------------------------------------architecture behv of ALU is begin process(A,B,Sel) begin -- use case statement to achieve -- different operations of ALU case Sel is when "00" => Res <= A + B; when "01" => Res <= A + (not B) + 1; when "10" => Res <= A and B; when "11" => Res <= A or B; when others => Res <= "XX"; end case; end process; end behv;

+++===================================================== MULTIPLICADOR
-- two 4-bit inputs and one 8-bit outputs entity multiplier is port( num1, num2: in std_logic_vector(1 downto 0); product: out std_logic_vector(3 downto 0) ); end multiplier; architecture behv of multiplier is begin process(num1, num2) variable num1_reg: std_logic_vector(2 downto 0); variable product_reg: std_logic_vector(5 downto 0); begin num1_reg := '0' & num1; product_reg := "0000" & num2; -- use variables doing computation -- algorithm is to repeat shifting/adding for i in 1 to 3 loop if product_reg(0)='1' then product_reg(5 downto 3) := product_reg(5 downto 3) + num1_reg(2 downto 0); end if; product_reg(5 downto 0) := '0' & product_reg(5 downto 1); end loop;

-- assign the result of computation back to output signal product <= product_reg(3 downto 0); end process; end behv;

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ FLIP FLOP TIPO D

entity dff is port( data_in: clock: data_out: ); end dff; in std_logic; in std_logic; out std_logic

---------------------------------------------architecture behv of dff is begin process(data_in, clock) begin -- clock rising edge if (clock='1' and clock'event) then data_out <= data_in; end if; end process; end behv;

++++++++===++++++++++++++++++++++++++++++++++++++++++ FLIP FLIO TIPO J-K

---------------------------------------------entity JK_FF is port ( clock: J, K: reset: Q, Qbar: ); end JK_FF; in std_logic; in std_logic; in std_logic; out std_logic

----------------------------------------------architecture behv of JK_FF is -- define the useful signals here signal state: std_logic; signal input: std_logic_vector(1 downto 0); begin -- combine inputs into vector

input <= J & K; p: process(clock, reset) is begin if (reset='1') then state <= '0'; elsif (rising_edge(clock)) then -- compare to the truth table case (input) is when "11" => state <= not state; when "10" => state <= '1'; when "01" => state <= '0'; when others => null; --NULL: NO HACE NADA, PASA A LA SIGUIENTE LINEA end case; end if; end process; -- concurrent statements Q <= state; Qbar <= not state; end behv;

++++++++===++++++++++++++++++++++++++++++++++++++++++ REGISTRO PIPO entity reg is generic(n: natural :=2); port( I: in std_logic_vector(n-1 downto 0); clock: in std_logic; load: in std_logic; clear: in std_logic; Q: out std_logic_vector(n-1 downto 0) ); end reg; ---------------------------------------------------architecture behv of reg is signal Q_tmp: std_logic_vector(n-1 downto 0); begin process(I, clock, load, clear) begin if clear = '0' then -- use 'range in signal assigment Q_tmp <= 0; elsif (clock='1' and clock'event) then if load = '1' then Q_tmp <= I; end if; end if; end process; -- concurrent statement Q <= Q_tmp; end behv;

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ CONTADOR CON DIVISOR DE FRECUENCIA

entity counter is

port (

clk : in std_logic; reset : in std_logic; pause : in std_logic; count_out : out std_logic_vector(3 downto 0)); end counter; architecture Behavioral of counter is signal temp_count : std_logic_vector(3 downto 0) := x"0"; signal slow_clk : std_logic; -- Clock divider can be changed to suit application. -- Clock (clk) is normally 50 MHz, so each clock cycle -- is 20 ns. A clock divider of 'n' bits will make 1 -- slow_clk cycle equal 2^n clk cycles. signal clk_divider : std_logic_vector(23 downto 0) := x"000000"; begin -- Process that makes slow clock go high only when MSB of -- clk_divider goes high. clk_division : process (clk, clk_divider) begin if (clk = '1' and clk'event) then clk_divider <= clk_divider + 1; end if; slow_clk <= clk_divider(23); end process; counting : process(reset, pause, slow_clk, temp_count) begin if reset = '1' then temp_count <= "0000"; -- Asynchronous reset. elsif pause = '1' then temp_count <= temp_count; -- Asynchronous count pause. else if slow_clk'event and slow_clk ='1' then -- Counting state if temp_count < 9 then temp_count <= temp_count + 1; -- Counter increase else temp_count <= "0000"; zero end if; end if; end if; count_out <= temp_count; end process; end Behavioral; -- Output -- Rollover to

**********************************************************************

FLIP FLOP TIPO D

entity domingo is Port ( d, clk, rst : in STD_LOGIC; q : out STD_LOGIC); end domingo; architecture Behavioral of domingo is begin process (rst, clk) begin if (rst='1') then q<='0'; elsif (clk'event and clk='1') then q<=d; end if; end process;

end Behavioral; &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&

-- Conversion de Funciones -- Decodificador 7 segmentos -- Multiplexor 8 a 1 -- Decodificador 3 a 8 -- ALU -- Comparador -- Multiplexor 4 a 1 -- Generador de Paridad -- Desplazador -- Divisor de frecuencia -- Mealy -- Moore - Otros ejemplos

-- MAX+plus II VHDL Ejemplo -- Conversion de Funciones LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY adder IS PORT (op1, op2 : IN UNSIGNED(7 downto 0); result : OUT INTEGER); END adder; ARCHITECTURE maxpld OF adder IS BEGIN

result <= CONV_INTEGER(op1 + op2); END maxpld;

-- MAX+plus II VHDL Ejemplo -- DECODIFICADOR HEXADECIMAL A 7 SEGMENTOS ENTITY hex7seg IS PORT( aa,bb,cc,dd : IN BIT; a,b,c,d,e,f,g : OUT BIT); END hex7seg; ARCHITECTURE comportamental OF hex7seg IS SIGNAL pepe : BIT_VECTOR(3 DOWNTO 0); SIGNAL SAL : BIT_VECTOR(6 DOWNTO 0); BEGIN PROCESS BEGIN pepe <= aa & bb & cc & dd; CASE pepe IS WHEN "0000" => SAL <="0000000"; WHEN "0001" => SAL <="1100000"; WHEN "0010" => SAL <="1011011"; WHEN "0011" => SAL <="1110011"; WHEN "0100" => SAL <="1100101"; WHEN "0101" => SAL <="1011011"; WHEN "0110" => SAL <="0111111"; WHEN "0111" => SAL <="1100010"; WHEN "1000" => SAL <="1111111"; WHEN "1001" => SAL <="1100111"; WHEN "1010" => SAL <="1101111"; WHEN "1011" => SAL <="0111101"; WHEN "1100" => SAL <="0011110"; WHEN "1101" => SAL <="1111001"; WHEN "1110" => SAL <="0011111"; WHEN "1111" => SAL <="0001111"; WHEN OTHERS => SAL <="0000000"; END CASE; END PROCESS; a <= sal(6); b <= sal(5); c <= sal(4); d <= sal(3); e <= sal(2); f <= sal(1); g <= sal(0); END comportamental;

-- MAX+plus II VHDL Ejemplo -- Multiplexor 8 a 1 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity A_81MUX is port (A, B, C, GN : in std_logic; D0, D1, D2, D3, D4, D5, D6, D7 : in std_logic; Y, WN : out std_logic); end A_81MUX; architecture BEHAVIOR of A_81MUX is begin process(A, B, C, GN, D0, D1, D2, D3, D4, D5, D6, D7) variable sel : integer range 0 to 7; begin sel := 0; if GN = '1' then Y <= '0'; WN <= '1'; else if (A = '1') then sel := sel + 1; end if; if (B = '1') then sel := sel + 2; end if; if (C = '1') then sel := sel + 4; end if; case sel is when 0 => Y <= D0; WN <= not D0; when 1 => Y <= D1; WN <= not D1; when 2 => Y <= D2; WN <= not D2; when 3 => Y <= D3; WN <= not D3; when 4 => Y <= D4; WN <= not D4; when 5 => Y <= D5; WN <= not D5; when 6 => Y <= D6; WN <= not D6; when 7 =>

Y <= D7; WN <= not D7; end case; end if; end process; end BEHAVIOR;

-- MAX+plus II VHDL Ejemplo -- decoder 3 a 8 library ieee; use ieee.std_logic_1164.all; entity decoder is port ( inp: in std_logic_vector(2 downto 0); outp: out std_logic_vector(7 downto 0)); end decoder; architecture behave of decoder is begin outp(0) <= '1' when inp = "000" else '0'; outp(1) <= '1' when inp = "001" else '0'; outp(2) <= '1' when inp = "010" else '0'; outp(3) <= '1' when inp = "011" else '0'; outp(4) <= '1' when inp = "100" else '0'; outp(5) <= '1' when inp = "101" else '0'; outp(6) <= '1' when inp = "110" else '0'; outp(7) <= '1' when inp = "111" else '0'; end behave;

-- ALU library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity alu is port ( a, b : in std_logic_vector(7 downto 0); opcode: in std_logic_vector(1 downto 0); clk: in std_logic; result: out std_logic_vector(7 downto 0) ); end alu; architecture behave of alu is constant plus: std_logic_vector(1 downto 0) := b"00"; constant minus: std_logic_vector(1 downto 0) := b"01"; constant equal: std_logic_vector(1 downto 0) := b"10";

constant not_equal: std_logic_vector(1 downto 0) := b"11"; begin process (opcode) begin case opcode is when plus => result <= a + b; -- add when minus => result <= a - b; -- subtract when equal => -- equal if (a = b) then result <= X"01"; else result <= X"00"; end if; when not_equal => -- not equal if (a /= b) then result <= X"01"; else result <= X"00"; end if; end case; end process; end behave;

-- Comparador library ieee; use ieee.std_logic_1164.all; entity compare is port ( a, b : in std_logic_vector (7 downto 0); equal: out std_logic); end compare; architecture behave of compare is begin equal <= '1' when a = b else '0'; end behave ;

--MUX 4 a 1 library ieee; use ieee.std_logic_1164.all; entity mux is port (output_signal:

out std_logic;

in1, in2, in3, in4: in std_logic; sel: in std_logic_vector( 1 downto 0) ); end mux; architecture behave of mux is begin process (in1, in2, in3, in4, sel) begin case sel is when "00" => output_signal <= in1; when "01" => output_signal <= in2; when "10" => output_signal <= in3; when "11" => output_signal <= in4; when others => output_signal <= 'X'; end case; end process; end behave;

-- GENERADOR DE PARIDAD library ieee; use ieee.std_logic_1164.all; entity parity is generic ( bus_size : integer := 8 ); port ( input_bus : in std_logic_vector (bus_size-1 downto 0); even_numbits, odd_numbits : out std_logic ) ; end parity ; architecture behave of parity is begin process (input_bus) variable temp: std_logic; begin temp := '0'; for i in input_bus'low to input_bus'high loop temp := temp xor input_bus(i) ; end loop ; odd_numbits <= temp ; even_numbits <= not temp; end process; end behave;

-- Desplazador -- 8 bit shift register IZQ-DER y CARGA -- Reset sincroono. library ieee; use ieee.std_logic_1164.all; entity shifter is port (data : in std_logic_vector (7 downto 0); shift_left, shift_right, clk, reset : in std_logic; mode : in std_logic_vector (1 downto 0); qout : buffer std_logic_vector (7 downto 0) ); end shifter; architecture behave of shifter is signal enable: std_logic; begin process begin wait until (rising_edge(clk) ); if (reset = '1') then qout <= "00000000"; else case mode is when "01" => qout <= shift_right & qout(7 downto 1); -- shift right when "10" => qout <= qout(6 downto 0) & shift_left; -- shift left when "11" => qout <= data; -- parallel load when others => null; -- null means do nothing end case; end if; end process; end behave;

-- DIVISOR DE FRECUENCIA ENTITY divisor IS PORT (CLK,EN : IN BIT; CUENTA : OUT BIT; NUMERO : OUT INTEGER RANGE 0 TO 500); END divisor;

ARCHITECTURE pp OF divisor IS SIGNAL VALOR : INTEGER RANGE 0 TO 1000; BEGIN PROCESS (CLK,EN) BEGIN IF (CLK'EVENT AND CLK = '1') THEN IF (EN='1') THEN IF VALOR = 256 THEN CUENTA <= '1'; VALOR <= 0; ELSE VALOR <= VALOR +1 ; CUENTA <= '0'; END IF; END IF; END IF; END PROCESS; NUMERO<= VALOR; END PP;

--MAQUINAAS ESTADO FiNITO, LA CODIFICACIN DE ESTADO NO AFECTA --SIGNIFICATIVAMENTE AL COMPORTAMIENTO DE LA MAQUINA ENTITY mealy IS PORT( clk, input, reset : in BIT; output : out BIT_VECTOR (3 downto 0)); END mealy; ARCHITECTURE maquina OF mealy IS TYPE tipo_de_estado IS (S0,S1,S2,S3); SIGNAL estado : tipo_de_estado; BEGIN PROCESS(clk,reset) BEGIN IF reset = '1' THEN estado <= S0; ELSIF (clk'event AND clk='1') THEN CASE estado IS WHEN S0 => IF input='1' THEN estado <= S1; END IF; WHEN S1 => IF input='0' THEN estado <= S2; END IF; WHEN S2 => IF input='1' THEN estado <= S3; END IF;

WHEN S3 => IF input='0' THEN estado <= S0; END IF; END CASE; END IF; END PROCESS; PROCESS(input,estado) BEGIN CASE estado IS WHEN S0 => IF input='0' THEN output <= "0000"; ELSE output <= "1001"; END IF; WHEN S1 => IF input='1' THEN output <= "1001"; ELSE output <= "1100"; END IF; WHEN S2 => IF input='0' THEN output <= "1100"; ELSE output <= "1111"; END IF; WHEN S3 => IF input='1' THEN output <= "1111"; ELSE output <= "0000"; END IF; END CASE; END PROCESS; END maquina;

-- MAQUINA DE MOORE LA CODIFICACIN DE ESTADO NO AFECTA --SIGNIFICATIVAMENTE AL COMPORTAMIENTO DE LA MAQUINA ENTITY moore IS PORT( clk : IN BIT; input : IN BIT; reset : IN BIT; output : OUT BIT_VECTOR (3 downto 0)); END moore; ARCHITECTURE maquina OF moore IS TYPE tipo_de_estado IS (S0,S1,S2,S3); SIGNAL estado : tipo_de_estado;

BEGIN PROCESS(clk,reset) BEGIN IF reset = '1' THEN estado <= S0; ELSIF clk'event AND clk='1' THEN CASE estado IS WHEN S0 => IF input='1' THEN estado <= S1; END IF; WHEN S1 => IF input='0' THEN estado <= S2; END IF; WHEN S2 => IF input='1' THEN estado <= S3; END IF; WHEN S3 => IF input='0' THEN estado <= S0; END IF; END CASE; END IF; END PROCESS; PROCESS(estado) BEGIN CASE estado IS WHEN S0 => output <= "0000"; WHEN S1 => output <= "1001"; WHEN S2 => output <= "1100"; WHEN S3 => output <= "1111"; END CASE; END PROCESS; END maquina;

LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY FullAdder IS PORT( X, Y, CIN : IN STD_LOGIC; S, COUT : OUT STD_LOGIC); END FullAdder; ARCHITECTURE a OF FullAdder IS BEGIN S <= X XOR Y XOR CIN; COUT <= (X AND Y) OR (X AND CIN) OR (Y AND CIN); END a;

LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY RippleAdder IS PORT( X, Y : IN STD_LOGIC_VECTOR(0 to 3); CIN : IN STD_LOGIC; S : OUT STD_LOGIC_VECTOR( 0 TO 3); COUT : OUT STD_LOGIC); END RippleAdder; ARCHITECTURE b OF RippleAdder IS component FullAdder --component declaration PORT( --the port names here must X, Y, CIN : IN STD_LOGIC; --be the same as in the S, COUT : OUT STD_LOGIC); --entity declaration END component; signal C1, C2, C3 : STD_LOGIC; BEGIN U1: FullAdder port map (X(0), Y(0), CIN, S(0), C1); U2: FullAdder port map (X(1), Y(1), C1, S(1), C2); U3: FullAdder port map (X(2), Y(2), C2, S(2), C3); U4: FullAdder port map (X(3), Y(3), C3, S(3), COUT); END b;

LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY RippleAdder16 IS PORT( X, Y : IN STD_LOGIC_VECTOR(0 to 15); CIN : IN STD_LOGIC; S : OUT STD_LOGIC_VECTOR( 0 TO 15); COUT : OUT STD_LOGIC); END RippleAdder16; ARCHITECTURE b OF RippleAdder16 IS component FullAdder --component declaration PORT( X, Y, CIN : IN STD_LOGIC; S, COUT : OUT STD_LOGIC); END component;

signal C : STD_LOGIC_VECTOR(0 TO 16); BEGIN C(0) <= CIN; g1: for i in 0 to 15 generate U1: FullAdder port map (X(i), Y(i), C(i), S(i), C(i+1)); end generate; COUT <= C(16); END b;

LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY prime9 IS PORT( N : IN STD_LOGIC_VECTOR (15 DOWNTO 0) ; F : OUT STD_LOGIC); END prime9; ARCHITECTURE prime9_arch OF prime9 IS BEGIN process(N) variable NI, i : INTEGER; variable prime: boolean; begin NI:=CONV_INTEGER(N); prime := true; i := 2; if NI=1 or NI=2 then null; else while i<=253 and prime loop if NI mod i = 0 then prime := false; end if; i:=1+1; end loop; end if; if prime then F <='1';else F <= '0';end if; end process; END prime9_arch;

LED_MSD_DISPLAY: WITH MSD SELECT MSD_7SEG <= "1111110" WHEN "0000", "0110000" WHEN "0001",

"1101101" WHEN "0010", "1111001" WHEN "0011", "0110011" WHEN "0100", "1011011" WHEN "0101", "1011111" WHEN "0110", "1110000" WHEN "0111", "1111111" WHEN "1000", "1111011" WHEN "1001", "0111110" WHEN OTHERS;

LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY statemachine IS PORT( clk,reset,Y : IN STD_LOGIC; X : OUT STD_LOGIC); END statemachine; ARCHITECTURE st_mach_arch OF statemachine IS TYPE STATE_TYPE IS (state_A, state_B); SIGNAL state: STATE_TYPE; BEGIN process(reset,clk) BEGIN IF reset='1' THEN state <= state_A; ELSIF CLK `EVENT AND clk='1' THEN CASE state IS WHEN state_A => IF Y='0' THEN state <= state_B; END IF; WHEN state_B => IF Y='1' THEN state <= state_A; END IF; END CASE; END IF; END PROCESS; WITH state SELECT X <= `0' WHEN state_A, `1' WHEN state_B; END st_mach_arch;

LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_unsigned.all; ENTITY alu IS PORT( Op_code : IN STD_LOGIC_VECTOR(4 DOWNTO 0); A_input, B_input : IN STD_LOGIC_VECTOR(11 DOWNTO 0); Y : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); END alu; ARCHITECTURE alu_arch OF alu IS SIGNAL Temp_output : STD_LOGIC_VECTOR(11 DOWNTO 0); BEGIN PROCESS (Op_code, A_input, B_input) BEGIN CASE Op_code(4 DOWNTO 2) IS WHEN "000" => Temp_output <= A_input; WHEN "001" => Temp_output <= A_input + B_input; WHEN "010" => Temp_output <= A_input - B_input; WHEN "011" => Temp_output <= A_input AND B_input; WHEN "100" => Temp_output <= A_input OR B_input; WHEN "101" => Temp_output <= A_input + 1; WHEN "110" => Temp_output <= A_input - 1; WHEN "111" => Temp_output <= B_input; WHEN OTHERS => Temp_output <= "000000000000"; END CASE; CASE Op_code(1 DOWNTO 0) IS WHEN "00" => Y <= Temp_output; WHEN "01" => Y <= Temp_output(10 DOWNTO 0) & '0'; WHEN "10" => Y <= '0' & Temp_output(11 DOWNTO 1); WHEN OTHERS => Y <= "000000000000"; END CASE; END PROCESS; END alu_arch;
entity cargar is generic(lim_max:integer:=2500000); Port ( clock : in STD_LOGIC;

reset : in STD_LOGIC; indata : in STD_LOGIC_VECTOR (3 downto 0); outdata : out STD_LOGIC_VECTOR (3 downto 0); load : in STD_LOGIC); end cargar; architecture Behavioral of cargar is signal clock_hz: std_logic; signal temp: std_logic_vector (3 downto 0):=x"0"; begin uno: process(clock) variable contador: integer range 0 to 2500000; begin if clock'event and clock='1' then contador:=contador+1; if contador = lim_max then contador:=0; clock_hz<= not clock_hz; end if; end if; end process uno; dos: PROCESS(CLock_hz, Reset, Load) BEGIN IF (Reset ='1') THEN temp <= (OTHERS =>'0'); -- Uso de la MACRO rising_edge ELSIF (Load = '1') THEN temp <= indata; else if CLock_hz'event and clock_hz = '1' THEN temp <= temp+1; END IF; END IF; outdata<=temp; END PROCESS dos;

Uso de PAQUETES, LIBRERIAS

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.comp_or.all; use work.comp_and.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity principal is Port ( r : in STD_LOGIC; s : in STD_LOGIC; t : in STD_LOGIC; p : in STD_LOGIC; y : out STD_LOGIC); end principal; architecture Behavioral of principal is signal v1: std_logic_vector (2 downto 0); signal v2: std_logic_vector (1 downto 0); signal v3: std_logic_vector (2 downto 0); signal v4: std_logic_vector (2 downto 0); signal uno,dos,tres:std_logic; begin v1<=r&s&t; v2<=r&p; v3<=r&s&p; v4<=uno&dos&tres; u0: and_3 port map (v1,uno); u1: or_n generic map(2) port map (v2,dos); u2: or_n generic map(3) port map (v3,tres); u3: or_n generic map(3) port map (v4,y); end Behavioral; ********* or_pck *************** library IEEE; use IEEE.STD_LOGIC_1164.all; package comp_or is component or_n generic (n: integer); port (x: in std_logic_vector(n-1 downto 0); y: out std_logic); end component;

end comp_or;

library IEEE; use IEEE.STD_LOGIC_1164.all; entity or_n is generic (n: integer:= 2); port (x: in std_logic_vector(n-1 downto 0); y: out std_logic); end or_n; architecture Behavioral of or_n is begin process (x) variable parcial: std_logic; begin parcial:='0'; for i in 0 to n-1 loop parcial:=parcial or x(i) ; end loop; Y<=parcial ; end process; end Behavioral; **************and_pck ***************** library IEEE; use IEEE.STD_LOGIC_1164.all; package comp_and is component and_3 port downto 0); end component; end comp_and; library IEEE; use IEEE.STD_LOGIC_1164.all; entity and_3 is port (x: in std_logic_vector(2 downto 0); y: out std_logic); end and_3; architecture Behavioral of and_3 is begin Y<=x(0)and x(1) and x(2) ; end Behavioral;

(x:

in

std_logic_vector(2 y: out std_logic);

USO DE IPCORE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity twofreqledblink is Port ( --boardInputClkN : in STD_LOGIC; boardInputClkP : in STD_LOGIC; extResetH : in STD_LOGIC; LedClk6_25 : out STD_LOGIC; LedClk12_5 : out STD_LOGIC); end twofreqledblink; architecture Behavioral of twofreqledblink is COMPONENT gen PORT( CLKIN_IN : IN std_logic; RST_IN : IN std_logic; CLKDV_OUT : OUT std_logic; CLKIN_IBUFG_OUT : OUT std_logic; CLK0_OUT : OUT std_logic; LOCKED_OUT : OUT std_logic ); END COMPONENT; COMPONENT prescaler is Port ( clk : in STD_LOGIC; reset_0 : in STD_LOGIC; clkPrescaled : out STD_LOGIC); END COMPONENT; signal clk250MHz: std_logic; signal clk125MHz: std_logic; signal clkInBuffer: std_logic; signal dcmLock: std_logic; begin Inst_gen: gen PORT MAP( CLKIN_IN => boardInputClkP, RST_IN =>extResetH , CLKDV_OUT =>clk125MHz , CLKIN_IBUFG_OUT => clkInBuffer, CLK0_OUT => clk250MHz, LOCKED_OUT => dcmLock );

Inst_prescaler6_25Hz: prescaler PORT MAP( clk=>clk125MHz, reset_0=>extResetH, clkPrescaled=>ledClk6_25 --1,24hz ); Inst_prescaler12_5Hz: prescaler PORT MAP( clk=>clk250MHz, reset_0=>extResetH, clkPrescaled=>ledClk12_5 --2.5hz ); end Behavioral; ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity prescaler is Port ( clk : in STD_LOGIC; reset_0 : in STD_LOGIC; clkPrescaled : out STD_LOGIC); end prescaler; architecture Behavioral of prescaler is signal counter: std_logic_vector(23 downto 0); signal outClk: std_logic; begin clkPrescaled<=outClk; scale: process(clk,reset_0) begin if rising_edge (clk) then if reset_0='1' then counter<=(others=>'0'); outClk<='0'; else counter<=counter+1; if counter=10000000 then counter<=(others=>'0'); outClk<=not outClk; end if; end if; end if; end process scale; end Behavioral;