Yonah / Calistoga / ICH7-M

1
DW1 BLOCK DIAGRAM

Yonah / Calistoga / ICH7-M
A
CPU THERMAL
SENSOR
CPU Yonah/Merom
14.318MHz
MAX6657
PG 5
SYSTEM POWER MAX8743
CPUCLK, CPUCLK#
478P (uPGA)
PG 39
CLOCK GEN
PG 5,6
ICS954206AG
56pins
CPU CORE MAX8771
CLK_MCH_BCLK, CLK_MCH_BCLK#
DREFCLK, DREFCLK#
DVI Bridge
CH7307
PG 13
S-VIDEO
S-VIDEO
NORTH BRIDGE
Calistoga
PG 35
LVDS X1
LCD Panel
PG 7,8,9,10,11,12
PG 32
DDRII 533,667 MHz
DDRII-SODIMM2
DMI LINK
32.768KHz
PCI-E 4X
PCLK_ICH
USB 2.0
USB PORT 4,5,6,7

Camera,Bluetooth,Mini
Card,New CardPG 23
14M_ICH
SATA 150MB
SATA - HDD
PG 33
PG 40
BATT CHARGER
MAX8724
PG 37
DISCHARGE
PG 36
PCLK_5C832
SBLINKCLK, SBLINKCLK#
SOUTH BRIDGE
ICH7-M
PG 38
SYSTEM POWER MAX8632

(1.8VSUS/0.9V SMDDR_VREF)
PG 14,15
PG 23
IDE - CDROM
DDRII-SODIMM1
PG 14,15
INTEGRADED VGA FUNCTION
CRT
USB PORT 0,1,2,3
DDRII 533,667 MHz
1466P BGA
PG 20
CRT
SYSTEM MAX8734
POWER(3/5V)
PCLK_541
PG 35
PG 4
CLK_PCIE_3GPLL, CLK_PCIE_3GPLL#
CLK_PCIE_NEW_C,
CLK_PCIE_NEW_C#
CLK_PCIE_MINI,
CLK_PCIE_MINI#
PCLK_TPM
DVI
PG 41
DREFSSCLK, DREFSSCLK#
HOST BUS
33MHZ, 3.3V PCI

24.576MHz
Azalia
652P BGA
PATA 66/100/133
CARDREADER / IEEE 1394

CONTROLLER/CF
Azalia
PG 33
PG 16,17,18,19
CX20549
32.768KHz
RICOH 5C832
3.3V LPC, 33MHz
TPM (1.2)
32.768KHz
DIB_DATAN
DIB_DATAP
PG 35
PCLK_541
Express Card x1
NEW CARD
PC87541V
TQFP 176
MINI-Card
GigaLAN
Intel
82573E
PG 34
PG 34
SMARTDAA
MODEM,
CX20548
PG 27,28
PG 30
PG 26
PG 32
Keyboard
PG 31
PG 31
PG 24
CARD READER
SD/MMC,MS
MS-PRO
PG 23
RJ45
JACK
FLASH
PG 26
PG 30
PROJECT : DW1
Quanta Computer Inc.
Size
Document Number
Custom
BLOCK DIAGRAM
Date:
PG 22
D
PG 25
PG 27
1
1394
CONN
AUDIO
JACK
RJ11
Touchpad
3 IN 1
AMP
TPA0312
GMT1427
25MHz
FAN
PG 21,22,23
PG 24
PCI-Express
Tuesday, November 29, 2005

7
Rev
1A
Sheet
of
8
42
INDEX
Pg#
Description
Label
Schematic Block Diagram

System Information
System Power Block Diagram
CLOCK GENERATOR
5-6
Intel Yonah CPU
7-12
Calistoga-GM
13
DDR II SO-DIMM
16-19
ICH7-M
CARD Reader(R5C832)
23
CARD Reader/USB Port
26
27-28
LCD CONNECTOR / LCD PWR
21-22
24-25
Control
Signal
Description
VIN
S0, S3, S4, S5
AC ADAPTER (19V)
MBAT
S0, S3, S4, S5
MAIN BATTERY + (10~17V)
VCCRTC
S0, S3, S4, S5
RTC & KBC POWER
+15V
S0, S3, S4, S5
+15V
CPU_CORE
S0
CPU CORE POWER (1.25/1.15V)
VRON
+1.05V
S0
FSB POWER (1.05V)
VRON
+3V
S0
MAIND
3VSUS
S0, S3
SUSON
3V_S5
S0, S3, S4, S5
3VPCU
S0, S3, S4, S5
(3_3V)
S5_ON
ALWAYS POWER (3V)
+5V
S0
MAIND
AUDIO CODEC / AUDIO JACK
5VSUS
S0, S3
SUSON
MODEM(DAA)
5V_S5
S0, S3, S4, S5
S5_ON
GIGA-LAN 82573E
29
LED/Switch
30
KBC
31
Bluetooth/Touch Pad/Key board
32
FAN/CRT Port
33
SATA HDD / CD-ROM
34
NEW CARD/MINI CARD
35
TPM/DVI Port/S-Video
36
DISCHARGE
37
CHARGE
38
SYSTEM POWER(3V/5V)
39
SYSTEM POWER(1.05V/1.5V)
40
SYSTEM POWER(1.8V/0.9V)
41
CPU POWER(ISL6260/6280)
42
CPU Operation State
5VPCU
S0, S3, S4, S5
+1.5V
S0
ALWAYS POWER (5V)

MAIND
1.5V_S5
S0, S3, S4, S5
1.8VSUS
S0, S3
+2.5V
S0
S5_ON
SUSON
DDR CORE POWER
MAINON
SMDDR_VTERM
S0
DDR COMMAND & CONTROL PULL UP POWER
MAINON
SMDDR_VREF
S0, S3
DDR REF POWER
SUSON
VDDA
S0
AUDIO ANALOG POWER (5V)
MAINON
B
GND
PCI DEVICES IRQ ROUTING

A
ACTIVE
DVI Bridge
14-15
20
Power & Ground
NOTE
DEVICE
IDSEL # REQ/GNT # PCI_INT
Ricoh 5C832
AD25
E,F
PCB STACK UP
LAYER 1 : TOP
LAYER 2 : GND
LAYER 3 : IN1
LAYER 4 : IN2
LAYER 5 : GND
LAYER 6 : IN3
LAYER 7 : VCC
LAYER 8 : BOT
ALL PAGES
DIGITAL GROUND
AGND
AUDIO GND
T-GND
AUDIO JACK GND
6260AGND
CPU ANALOG GROUND
SM BUS
ADDRESS
DEVICE
BUS
CLOCK GENERATOR
D2H
(ICH6)PCLK_SMB, PCLK_SMB
DDR II
A0H
(ICH6)PCLK_SMB, PCLK_SMB
LCD EDID
TBD
CHARGER
16H
(KBC) MBDATA,MBCLK
CPU THERMAL SENSOR
98H
(KBC) MBDATA,MBCLK
GMCH
PROJECT : DW1
Size
Document Number
Custom
System Information
Date:
Rev
1A
Sheet
1
of
42
S5_ON
S.W
SYSTEM POWER BLOCK DIAGRAM
3V_S5
MOS-FET
MAINON
SC4215
S.W
Adaptor
MOS-FET
+2.5V
MAIND
VIN
+3V
S.W
3VPCU
ALWAYS
MOS-FET
3VSUS
SUSD
MAX8734
MAIND
5VPCU
ALWAYS
VIN
S.W
+5V
MOS-FET
5VSUS
SUSD
S5_ON
+15V
S.W
3V_S5
MOS-FET
CHARGER
MAX8724
MAINON
1.05V
VIN
MAINON
5VPCU
MAX8632
SMDDR_VTERM
1.8VSUS
MAX1540
SUSON
+1.5V
MAINON
BATTERY
S.W
MOS-FET
VRON
VIN
CPU_VID[0..5]
MAX8771
CPU_CORE
HWPG
DPRSLPVR
STP_CPU#
PROJECT : DW1
5
Size
C
Document Number
Date:
Rev
1A
System Power block diagram

Sheet
1
of
42
100
33
133
100
33
166
100
33
200
100
33
266
100
33
333
100
33
400
100
33
200
100
33
5,9,11,13,14,15,16,17,18,19,20,24,29,30,31,32,33,34,35,36,38
33P
33P
L15
1T2012-121JT
C264
0.1U
2.2/F
C260
0.1U
C252
0.1U
18
C267
10U
XTAL_IN
CG_XOUT
R187
*10K
49
XTAL_OUT
VR_PWRGD_CK410#
PM_STPPCI#
PM_STPCPU#
10
55
54
Vtt_PwrGd#/PD
PCI/SRC_STOP#
CPU_STOP#
CLKUSB_48
R186
33
CLK_BSEL0
CLK_BSEL1
CLK_BSEL2
R191
2.2K
R162
4.7K
VDD_A
C256
0.1U
VDD_REF
VDD_SRC_CPU
C258
10U
VDD_PCI
25 mils
VDD_PCI
C240
0.1U
120 ohms@100Mhz
R158
2.2/F
C226
0.1U
C230
10U
C246
0.1U
C233
10U
R200
12
16
53
FSA/USB_48MHz
FSB/TEST_MODE
FSC/REF1
48
42
VDD_REF
VDD_CPU
21
28
34
VDD_SRC0
VDD_SRC1
VDD_SRC2
VDD_48
11
VDD_48
475/F IREF
39
IREF
RP37
9
9
DREFCLK
DREFCLK#
DREFCLK
DREFCLK#
VDD_48
1
3
2
4
R_DOT96
R_DOT96#
14
15
14M_REF
CPU0
CPU0#
44
43
RHCLK_CPU
RHCLK_CPU#
CPU1
CPU1#
41
40
CPU2_ITP/SRC7
CPU2#_ITP/SRC7#
36
35
SRC6
SRC6#
33
32
SRC5
SRC5#
31
30
SRC4_SATA
SRC4#_SATA
26
27
SRC3
SRC3#
24
25
SRC2
SRC2#
22
23
SRC1
SRC1#
19
20
SRC0/DREFSSCLK
SRC0#/DREFSSCLK#
17
18
PCI5
PCI4
PCI3
PCI2
PCIF1/100_96M#
PCIF0/ITP_EN
5
4
3
56
9
8
DOT96MHz
DOT96MHz#
33X2
R173
RP38
1
3
RP42
RHCLK_MCH
1
RHCLK_MCH#
3
52
RP47
1
3
RP51
RSRC_MCH
1
RSRC_MCH#
3
RP53
RSRC_SATA
3
RSRC_SATA#
1
RP49
RSRC_NEW
3
RSRC_NEW#
1
RP46
RSRC_ICH
3
RSRC_ICH#
1
RP44
RSRC_LAN
3
RSRC_LAN#
1
RP41
RDREFSSCLK
3
RDREFSSCLK#
1
33
R_PCLK_541
R_PCLK_5C832
R_PCLK_TPM
R_PCLK_DBP
R_PCLK_ICH
R_PCLK_SIO
14M_ICH 18
2 33X2
4
CLK_CPU_BCLK 5
CLK_CPU_BCLK# 5
2 33X2
4
CLK_MCH_BCLK 7
CLK_MCH_BCLK# 7
T194
T195
RSRC_MINI
RSRC_MINI#
2 33X2
4
CLK_PCIE_MINI 34
CLK_PCIE_MINI# 34
2 33X2
4
CLK_PCIE_3GPLL 9
CLK_PCIE_3GPLL# 9
4 33X2
2
CLK_PCIE_SATA 16
CLK_PCIE_SATA# 16
4 33X2
2
CLK_PCIE_NEW 34
CLK_PCIE_NEW# 34
4 33X2
2
CLK_PCIE_ICH 17
CLK_PCIE_ICH# 17
4 33X2
2
CLK_PCIE_LAN 27
CLK_PCIE_LAN# 27
4 33X2
2
R176
R171
R159
R155
R183
10K
R185
*10K
R175
10K
R202
+1.05V
5 CPU_BSEL1
R211
1K
MCH_BSEL0 9
*1K
*1K
R214
R207
*0
R154
*1K
R172
R177
*0
R212
C239 *10P
1K
C241 *10P
RP39
CLK_CPU_BCLK
CLK_CPU_BCLK#
RP43
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_PCIE_3GPLL RP54
CLK_PCIE_3GPLL#
CLK_PCIE_SATA# RP52
CLK_PCIE_SATA
RP50
CLK_PCIE_MINI
CLK_PCIE_MINI#
RP45
CLK_PCIE_ICH#
CLK_PCIE_ICH
CLK_PCIE_NEW_C RP48
CLK_PCIE_NEW_C#
RP40
DREFSSCLK#
DREFSSCLK
RP36
DREFCLK#
DREFCLK
B Stage:
Change Q9,Q10 footprint.
18,27,34 PDAT_SMB
CLK_BSEL1
PCLK_ICH
Place these termination to close CK410M.
R188
10K
R196
CLK_BSEL0
C223 *10P
To check intel reference circuit default setting.

100MHZ? or 96MHZ?
EMI problem?
56/F
*0
PCLK_TPM
+3V
+3V
R194
C232 *10P
PCLK_5C832 C225 *10P
14M_ICH
FSB frequency will be selected by CPU internal.
5 CPU_BSEL0
PCLK_541
+3V
C244
10U
R206
33MHZ
14.318MHZ
R184
DREFSSCLK Frequency Select.

"0" : 96MHz
"1" : 100MHz
+1.05V
CLKUSB_48 C245 *10P
PCLK_541 30
PCLK_5C832 21
PCLK_TPM 35
PCLK_DBP 34
PCLK_ICH 17
VDD_REF
C248
0.1U
48MHZ
DREFSSCLK 9
DREFSSCLK# 9
33
33
33
33
33
SMbus address D2 /IDT

R179
EMI
ICS954206AG-T
13
51
2
6
29
45
+3V
Iref=5mA,
Ioh=4*Iref
SCLK
SDATA
VDD_PCI_1
VDD_PCI_2
VDD_SRC_CPU
Place these termination to close CK410M.

REF0
CK-410M
46
47
1
7
L14
1T2012-121JT
U9
50
CGCLK_SMB
CGDAT_SMB
14,15,34 CGCLK_SMB
14,15,34 CGDAT_SMB
25 mils
VDD_SRC_CPU
CG_XIN
CL=20 - 22P
Y2
14.318MHZ
18,41 VR_PWRGD_CK410#
18 PM_STPPCI#
18 PM_STPCPU#
R216
VDD_A
Close to IC <500mils
C228
+3V
C257
0.1U
+1.05V
Default
C227
120 ohms@100Mhz
+3V
+3V
5,6,7,10,11,16,19,36,39 +1.05V
38
100
GNDA
37
+3V
PCI
VDDA
SRC
GND_48
GND_REF
GND_PCI_1
GND_PCI_2
GND_SRC
GND_CPU
CPU
FSC FSB FSA
R192
10K
CGDAT_SMB
Q9
2N7002E
MCH_BSEL1 9
+3V
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
49.9/FX2
49.9/FX2
49.9/FX2
49.9/FX2
49.9/FX2
49.9/FX2
49.9/FX2
49.9/FX2
49.9/FX2
1
+1.05V
18,27,34 PCLK_SMB
5 CPU_BSEL2
CLK_BSEL2
R160
1K
CGCLK_SMB
Q10
2N7002E
MCH_BSEL2 9
PROJECT : DW1
Size
Document Number
Custom
Date:
Rev
1A
CLOCK GENERATOR
Sheet
E
of
42
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
K3
H2
K2
J3
L5
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
16
H_A20M#
H_FERR#
H_IGNNE#
R99
H_STPCLK#
16
16
16
H_INTR
H_NMI
H_SMI#
T170
T9
T171
T11
T15
T22
T16
T12
T177
T19
T192
H_A20M#
H_FERR#
H_IGNNE#
A6
A5
C4
A20M#
FERR#
IGNNE#
H_STPCLK_R#
H_INTR
H_NMI
H_SMI#
D5
C6
B4
A3
STPCLK#
LINT0
LINT1
SMI#
TP_A32#
TP_A33#
TP_A34#
TP_A35#
TP_A36#
TP_A37#
TP_A38#
TP_A39#
TP_APM0#
TP_APM1#
AA1
AA4
AB2
AA3
M4
N5
T2
V3
B2
C3
RSVD[01]#
RSVD[02]#
RSVD[03]#
RSVD[04]#
RSVD[05]#
RSVD[06]#
RSVD[07]#
RSVD[08]#
RSVD[09]#
RSVD[10]#
TP_HFPLL
B25
RSVD[11]#
CONTROL
XDP/ITP SIGNALS
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
ADSTB[1]#
H5
F21
E1
H_DEFER#
H_DRDY#
H_DBSY#
H_ADS#
H_BNR#
H_BPRI#
+1.05V
H_DEFER# 7
H_DRDY# 7
H_DBSY# 7
F1
H_BREQ#0
IERR#
INIT#
D20
B3
IERR#
H_INIT#
LOCK#
H4
H_LOCK#
H_CPURST#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
B1
F3
F4
G3
G2
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
HIT#
HITM#
G6
E4
H_HIT#
H_HITM#
BR0#
+1.05V
7
7
7
H_D#[63:0]
H_D#[63:0]
U28B
Near to MCH <500mils

H_INIT#
16
H_LOCK# 7
H_CPURST# 7
H_RS#[2:0] 7
H_TRDY# 7
H_HIT#
7
H_HITM# 7
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
SYS_RST#
PROCHOT
THERMDA
THERMDC
D21
A24
A25
H_PROCHOT#
H_THERMDA
H_THERMDC
T6
T13
T176
T10
T175
7
7
7
SYS_RST# 18
R135
56/F
C7
PM_THRMTRIP# 9,16
BCLK[0]
BCLK[1]
A22
A21
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
RSVD[12]#
T22
TP_EXTBREF
TP_SPARE0
TP_SPARE1
TP_SPARE2
TP_SPARE3
TP_SPARE4
TP_SPARE5
TP_SPARE6
TP_SPARE7
H_DSTBN#0
H_DSTBP#0
H_DINV#0
+1.05V
R164
1K/F
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
H_D#16
N22
H_D#17
K25
H_D#18
P26
H_D#19
R23
H_D#20
L25
H_D#21
L22
H_D#22
L23
H_D#23
M23
H_D#24
P25
H_D#25
P22
H_D#26
P23
H_D#27
T24
H_D#28
R24
H_D#29
L26
H_D#30
T25
H_D#31
N24
H_DSTBN#1 M24
H_DSTBP#1 N25
H_DINV#1 M26
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
W24
Y25
V23
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
COMP[0]
COMP[1]
COMP[2]
COMP[3]
R26
U26
U1
V1
COMP0
COMP1
COMP2
COMP3
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
E5
B5
D24
D6
D7
AE6
ICH_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGD
H_CPUSLP#
PSI#
H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
H_D#[63:0]
T20
T21
T18
T172
T173
T71
T73
T69
7
7
7
H_DSTBN#1
H_DSTBP#1
H_DINV#1
H_GTLREF
Layout note: 0.5" max

for GTLREF
T76
H_D#0
E22
H_D#1
F24
H_D#2
E26
H_D#3
H22
H_D#4
F23
H_D#5
G25
H_D#6
E25
H_D#7
E23
H_D#8
K24
H_D#9
G24
H_D#10
J24
H_D#11
J23
H_D#12
H26
H_D#13
F26
H_D#14
K22
H_D#15
H25
H_DSTBN#0 H23
H_DSTBP#0 G22
H_DINV#0
J26
H_D#[63:0]
+1.05V
THERMTRIP#
D2
F6
D3
C1
AF1
D22
C23
C24
4,6,7,10,11,16,19,36,39
H_BREQ#0 7
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
RSVD[13]#
RSVD[14]#
RSVD[15]#
RSVD[16]#
RSVD[17]#
RSVD[18]#
RSVD[19]#
RSVD[20]#
+1.05V
R137
56/F
THERM
16
16
16
H_ADSTB#1
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1
V4
H_ADS#
H_BNR#
H_BPRI#
R41 populate for Yonah B

stepping.
R166
*1K/F
R167
51
AD26
R165
2K/F
4
4
4
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
GTLREF
C26
TEST1
D25
TEST2
B22
B23
C21
BSEL[0]
BSEL[1]
BSEL[2]
PZ47903-2741-01
DATA GRP 1
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADSTB#1
DEFER#
DRDY#
DBSY#
H1
E2
G5
H CLK
H_A#[31:3]
ADS#
BNR#
BPRI#
DATA GRP 2
J4
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
L2
DATA GRP 0
H_ADSTB#0
H_REQ#[4:0]
T48
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
ADDR GROUP 0
7
7
U28A
H_A#[31:3]
RESERVED
DATA GRP 3
MISC
Resistor placed within 0.5" of

processor pin for all compensation
resistor and routing as 27.4 and 55
ohm impedance.
H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7
R169
R170
R49
R50
27.4/F
54.9/F
27.4/F
54.9/F
ICH_DPRSTP# 16,41
H_DPSLP# 16
H_DPWR# 7
H_PWRGD 16
H_CPUSLP# 7,16
PSI#
41
PZ47903-2741-01
+3V
+3V
+3V
R199
10K
R138
SYS_RST#
*54.9/F
+1.05V
30,37
BDATA
1
+3V
+1.05V
+3V
THDAT_SMB
Q12
2N7002E
Populate when ITP700FLEX debug port not used.
R190
10K
+1.05V
R42
R44
R45
R54
R46
R142
*330
150/F
39.2/F
*54.9/F
54.9/F
56
H_PROCHOT#
XDP_TCK
XDP_TRST#
R47
R43
R163
100
27.4/F
680
VR_TT# 41
Q8
*MMBT3904
If PROCHOT# is not used, then it must be

terminated with a 56 pull-up resistor to
VCCP.
BCLK
THCLK_SMB
H/W MONITOR
C238
0.1U
3
30,37
Q11
2N7002E
XDP_TDI
XDP_TMS
XDP_TDO
H_CPURST#
XDP_BPM#5
38
6657VCC
VCC
SMCLK
THCLK_SMB
H_THERMDA
DXP
SMDATA
THDAT_SMB
C231
2200P/50V
H_THERMDC
DXN
-ALT
THERM_ALERT#
-OVT
GND
SYS_SHDN#
H/W Shutdown
U8
MAX6657/GMT-781
THERM_ALERT# 18
ICH_THRM#
To SB --> System throttling
PROJECT : DW1
Size
Document Number
Custom
Date:
5
Rev
1A
CPU HOST BUS (1 OF 2 )
Sheet
1
of
42
VCC_CORE
VCC_CORE
C137
10U
C148
10U
C151
10U
C157
10U
C176
10U
C136
10U
C184
10U
C212
10U
C199
10U
C204
10U
C211
10U
C175
10U
C183
10U
C198
10U
C203
10U
C208
10U
C207
10U
C185
10U
C213
10U
C201
10U
C200
10U
C177
10U
C191
10U
C156
10U
C150
10U
C153
10U
C147
10U
C158
10U
C180
10U
C152
10U
C168
10U
C149
10U
B stage:
Change to 10UF/X6S material(105C).
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
VCC[001]
VCC[68]
VCC[002]
VCC[69]
VCC[003]
VCC[70]
VCC[004]
VCC[71]
VCC[005]
VCC[72]
VCC[006]
VCC[73]
VCC[007]
VCC[74]
VCC[008]
VCC[75]
VCC[009]
VCC[76]
VCC[010]
VCC[77]
VCC[011]
VCC[78]
VCC[012]
VCC[79]
VCC[013]
VCC[80]
VCC[014]
VCC[81]
VCC[015]
VCC[82]
VCC[016]
VCC[83]
VCC[017]
VCC[84]
VCC[018]
VCC[85]
VCC[019]
VCC[86]
VCC[020]
VCC[87]
VCC[021]
VCC[88]
VCC[022]
VCC[89]
VCC[023]
VCC[90]
VCC[024]
VCC[91]
VCC[025]
VCC[92]
VCC[026]
VCC[93]
VCC[027]
VCC[94]
VCC[028]
VCC[95]
VCC[029]
VCC[96]
VCC[030]
VCC[97]
VCC[031]
VCC[98]
VCC[032]
VCC[99]
VCC[033] VCC[100]
VCC[034]
VCC[035] VCCP[01]
VCC[036] VCCP[02]
VCC[037] VCCP[03]
VCC[038] VCCP[04]
VCC[039] VCCP[05]
VCC[040] VCCP[06]
VCC[041] VCCP[07]
VCC[042] VCCP[08]
VCC[043] VCCP[09]
VCC[044] VCCP[10]
VCC[045] VCCP[11]
VCC[046] VCCP[12]
VCC[047] VCCP[13]
VCC[048] VCCP[14]
VCC[049] VCCP[15]
VCC[050] VCCP[16]
VCC[051]
VCC[052]
VCCA
VCC[053]
VCC[054]
VCC[055]
VID[0]
VCC[056]
VID[1]
VCC[057]
VID[2]
VCC[058]
VID[3]
VCC[059]
VID[4]
VCC[060]
VID[5]
VCC[061]
VID[6]
VCC[062]
VCC[063]
VCC[064]
VCC[065] VCCSENSE
VCC[066]
VCC[067] VSSSENSE
+1.05V
VCC_CORE
+1.5V
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
+1.05V
4,5,7,10,11,16,19,36,39
VCC_CORE 36,41
+1.5V
11,17,19,34,36,39
+1.05V
V6
G21
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
+
C234
330U/2.5V/ESR-9/POS
+1.5V
R178
B26
AD6
AF5
AE5
AF4
AE3
AF2
AE2
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID0
VID1
VID2
VID3
VID4
VID5
VID6
41
41
41
41
41
41
41
C229
0.01U
C242
10U/X6S
R415
100/F
VCCSENSE 41
Connect to PWM , special layout
VSSSENSE 41
PZ47903-2741-01
R413
100/F
+1.05V
C145
0.1U
C178
0.1U
C237
0.1U
VCC_CORE
AF7
AE7
C209
0.1U
C146
0.1U
C179
0.1U
U28D
VCC_CORE
U28C
C210
0.1U
C51
0.1U
A4
A8
A11
A14
A16
A19
A23
A26
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF24
PZ47903-2741-01
recommend by EMI
PROJECT : DW1
Size
B
Document Number
Date:
Rev
1A
CPU POWER/GND (2 OF 2 )
Sheet
1
of
42
+1.05V
H_D#[63:0]
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
R130
54.9/F
H_XSCOMP
H_XRCOMP
R131
24.9/F
15 mils/10mils
+1.05V
R125
54.9/F
C
H_YSCOMP
H_YRCOMP
R127
24.9/F
15 mils/10mils
+1.05V
R129
221/F
H_XSWING
R128
100/F
C197
0.1U
+1.05V
R124
221/F
H_YSWING
R123
100/F
C196
0.1U
F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8
H_XRCOMP
H_XSCOMP
H_XSWING
E1
E2
E4
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
Y1
U1
W1
H_YRCOMP
H_YSCOMP
H_YSWING
CLK_MCH_BCLK AG2
CLK_MCH_BCLK# AG1
4 CLK_MCH_BCLK
4 CLK_MCH_BCLK#
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
Short Stub < 100mils

extract from same point
4,5,6,10,11,16,19,36,39
H_A#[31:3] 5
U27A
+1.05V
HOST
5
D
+1.05V
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_VREF_0
H_BNR#
H_BPRI#
H_BREQ#0
H_CPURST#
H_DBSY#
H_DEFER#
H_DPWR#
H_DRDY#
H_VREF_1
E8
B9
C13
J13
C6
F6
C7
B7
A7
C3
J9
H8
K13
H_ADS#
H_ADSTB#0
H_ADSTB#1
J7
W8
U3
AB10
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
K4
T7
Y5
AC4
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
K3
T6
AA5
AC5
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_HIT#
H_HITM#
H_LOCK#
D3
D4
B3
H_HIT#
H_HITM#
H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
D8
G8
B8
F8
A8
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#_0
H_RS#_1
H_RS#_2
B4
E6
D6
H_RS#0
H_RS#1
H_RS#2
H_SLPCPU#
H_TRDY#
E3
E7
H_CPUSLP#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_CLKIN
H_CLKIN#
H_BNR#
H_BPRI#
H_BREQ#0
H_CPURST#
H_DBSY#
H_DEFER#
H_DPWR#
H_DRDY#
+1.05V
C
R100
100/F
H_ADS# 5
H_ADSTB#0 5
H_ADSTB#1 5
H_VREF
H_BNR# 5
H_BPRI# 5
H_BREQ#0 5
H_CPURST# 5
H_DBSY# 5
H_DEFER# 5
H_DPWR# 5
H_DRDY# 5
C142
0.1U
< 0.1", Use 1% R

H_VREF :10 mils/20 mils space
R92
200/F
H_DINV#[3:0] 5
C128
0.1U
H_DSTBN#[3:0] 5
H_DSTBP#[3:0] 5
H_HIT#
5
H_HITM# 5
H_LOCK# 5
H_REQ#[4:0] 5
H_RS#[2:0] 5
H_CPUSLP# 5,16
H_TRDY# 5
Calistoga
PROJECT : DW1
Size
Document Number
Custom
Date:
5
Rev
1A
GMCH HOST(1 OF 6 )
Sheet
1
of
42
15 M_B_DQ[0..63]
M_A_BS#0
M_A_BS#1
M_A_BS#2
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
AY13
AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4
M_A_CAS#
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5
AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
AW14
AK23
AK24
AY14
M_A_RAS#
TP_MA_RCVENIN#
TP_MA_RCVENOUT#
M_A_WE#
U27E
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_A_BS#0 14,15
M_A_BS#1 14,15
M_A_BS#2 14,15
M_A_CAS# 14,15
M_A_DM[0..7] 15
M_A_DQS[0..7] 15
M_A_DQS#[0..7] 15
M_A_A[0..13] 14,15
M_A_RAS# 14,15
T23
T17
M_A_WE# 14,15
Calistoga
AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
AU12
AV14
BA20
MEMORY
SA_BS_0
SA_BS_1
SA_BS_2
SYSTEM
MEMORY
SYSTEM
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
DDR
AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8
U27D
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
DDR
15 M_A_DQ[0..63]
SB_BS_0
SB_BS_1
SB_BS_2
AT24
AV23
AY28
M_B_BS#0
M_B_BS#1
M_B_BS#2
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
AR24
AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4
M_B_CAS#
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5
AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
AU23
AK16
AK18
AR27
M_B_RAS#
TP_MB_RCVENIN#
TP_MB_RCVENOUT#
M_B_WE#
M_B_BS#0 14,15
M_B_BS#1 14,15
M_B_BS#2 14,15
M_B_CAS# 14,15
M_B_DM[7:0] 15
M_B_DQS[0..7] 15
M_B_DQS#[0..7] 15
M_B_A[0..13] 14,15
M_B_RAS# 14,15
T31
T26
M_B_WE# 14,15
Calistoga
PROJECT : DW1
Size
Document Number
Custom
Date:
5
Rev
1A
GMCH DDR(2 OF 6)
Sheet
1
of
42
17
RST IN# MCH
R400
100/F
PLT_RST-R#
AW35
AT1
AY7
AY40
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3
AU20
AT20
BA29
AY29
M_CKE0
M_CKE1
M_CKE2
M_CKE3
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
AW13
AW12
AY21
AW21
M_CS#0
M_CS#1
M_CS#2
M_CS#3
SM_OCDCOMP_0
SM_OCDCOMP_1
AL20
AF10
M_OCDCOMP_0
M_OCDCOMP_1
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
BA13
BA12
AY20
AU21
M_ODT0
M_ODT1
M_ODT2
M_ODT3
SM_RCOMP#
SM_RCOMP
AV9
AT9
SM_VREF_0
SM_VREF_1
AK1
AK41
15
15
15
15
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
M_CKE0
M_CKE1
M_CKE2
M_CKE3
14,15
14,15
14,15
14,15
M_CS#0
M_CS#1
M_CS#2
M_CS#3
14,15
14,15
14,15
14,15
Place within 500 mils of GMCH
20
20
15
15
15
15
20
20
EDIDCLK
EDIDDATA
T1
DISP_ON
20
R398
1.5K/F
20
20
TXLCLKOUTTXLCLKOUT+
20
20
20
14,15
14,15
14,15
14,15
R104
*40.2/F
TXLOUT0TXLOUT1TXLOUT2-
M_RCOMP#
M_RCOMP
SMDDR_VREF
D32
J30
H30
H29
G26
G25
B38
C35
F32
C33
C32
L_BKLTCTL
L_BKLTEN
L_CLKCTLA
L_CLKCTLB
L_DDC_CLK
L_DDC_DATA
L_IBG
L_VBG
L_VDDEN
L_VREFH
L_VREFL
TXLCLKOUTTXLCLKOUT+
A33
A32
E27
E26
LA_CLK#
LA_CLK
LB_CLK#
LB_CLK
TXLOUT0TXLOUT1TXLOUT2-
C37
B35
A37
LA_DATA#_0
LA_DATA#_1
LA_DATA#_2
R71
*40.2/F
20
20
20
TXLOUT0+
TXLOUT1+
TXLOUT2+
TXLOUT0+
TXLOUT1+
TXLOUT2+
Layout as short as passable

NC from WW45
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
G_CLKIN#
G_CLKIN
D_REFCLKIN#
D_REFCLKIN
D_REFSSCLKIN#
D_REFSSCLKIN
AF33
AG33
A27
A26
C40
D41
CLK_PCIE_3GPLL#
CLK_PCIE_3GPLL
DREFCLK#
DREFCLK
DREFSSCLK#
DREFSSCLK
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
AE35
AF39
AG35
AH39
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
AC35
AE39
AF35
AG39
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
AE37
AF41
AG37
AH41
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
AC37
AE41
AF37
AG41
CLK_PCIE_3GPLL# 4
CLK_PCIE_3GPLL 4
DREFCLK# 4
DREFCLK 4
DREFSSCLK# 4
DREFSSCLK 4
DMI_TXN[3:0] 17
35
35
R25
100K
S-CVBS
S-YD
S-CD
S-CVBS
S-YD
S-CD
R411
R412
R414
150/F
150/F
75/F
TVIREF
4.99K/F
R68
DMI_TXP[3:0] 17
DMI_RXN[3:0] 17
B37
B34
A36
LA_DATA_0
LA_DATA_1
LA_DATA_2
G30
D30
F29
LB_DATA#_0
LB_DATA#_1
LB_DATA#_2
F30
D29
F28
LB_DATA_0
LB_DATA_1
LB_DATA_2
A16
C18
A19
TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT
J20
B16
B18
B19
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC
E23
D23
C22
B22
A21
B21
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
C26
C25
G23
J22
H23
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_IREF
CRT_VSYNC
< 0.1" . 15mils/15mils space
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
32
CRT_B
32
CRT_G
32
CRT_R
CRT_B
CRT_G
CRT_R
150/F
150/F
150/F
R409
R406
R408
32
32
DDCCLK
DDCDAT
DMI_RXP[3:0] 17
32
Calistoga
32
HSYNC
VSYNC
R33
39/F
HSYNC1
R64
255/F
CRTIREF
R34
39/F
VSYNC1
R399
10K/F
PM_EXTTS#0
R397
*10K/F
PM_EXTTS#1
24.9/F
EXP_A_COMPI
EXP_A_COMPO
EXP_A_RXN_0
EXP_A_RXN_1
EXP_A_RXN_2
EXP_A_RXN_3
EXP_A_RXN_4
EXP_A_RXN_5
EXP_A_RXN_6
EXP_A_RXN_7
EXP_A_RXN_8
EXP_A_RXN_9
EXP_A_RXN_10
EXP_A_RXN_11
EXP_A_RXN_12
EXP_A_RXN_13
EXP_A_RXN_14
EXP_A_RXN_15
F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38
EXP_A_RXP_0
EXP_A_RXP_1
EXP_A_RXP_2
EXP_A_RXP_3
EXP_A_RXP_4
EXP_A_RXP_5
EXP_A_RXP_6
EXP_A_RXP_7
EXP_A_RXP_8
EXP_A_RXP_9
EXP_A_RXP_10
EXP_A_RXP_11
EXP_A_RXP_12
EXP_A_RXP_13
EXP_A_RXP_14
EXP_A_RXP_15
D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38
EXP_A_TXN_0
EXP_A_TXN_1
EXP_A_TXN_2
EXP_A_TXN_3
EXP_A_TXN_4
EXP_A_TXN_5
EXP_A_TXN_6
EXP_A_TXN_7
EXP_A_TXN_8
EXP_A_TXN_9
EXP_A_TXN_10
EXP_A_TXN_11
EXP_A_TXN_12
EXP_A_TXN_13
EXP_A_TXN_14
EXP_A_TXN_15
F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
C34
C25
C32
C27
*0.1U
*0.1U
*0.1U
*0.1U
EXP_A_TXP_0
EXP_A_TXP_1
EXP_A_TXP_2
EXP_A_TXP_3
EXP_A_TXP_4
EXP_A_TXP_5
EXP_A_TXP_6
EXP_A_TXP_7
EXP_A_TXP_8
EXP_A_TXP_9
EXP_A_TXP_10
EXP_A_TXP_11
EXP_A_TXP_12
EXP_A_TXP_13
EXP_A_TXP_14
EXP_A_TXP_15
D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
C35
C26
C33
C28
*0.1U
*0.1U
*0.1U
*0.1U
EXP_RXN2
EXP_RXN2 13
EXP_RXP2
EXP_RXP2 13
SDVOB_RED- 13
SDVOB_GREEN- 13
SDVOB_BLUE- 13
SDVOB_CLK- 13
SDVOB_RED+ 13
SDVOB_GREEN+ 13
SDVOB_BLUE+ 13
SDVOB_CLK+ 13
+3V
R26
R27
10K/F
10K/F
SMDDR_VREF
GMCH Strap pin need to check

MCH_CFG_5
R82
*2.2K
1.MCH_CFG_5 Low = DMI X2, High=DMIX4
MCH_CFG_6
R103
*2.2K
2.MCH_CFG_6 DDR : Low =Moby Dick, High= Calistoga (Default)
M_RCOMP#
MCH_CFG_7
R17
*2.2K
3.MCH_CFG_7 CPU Strap Low=RSVD, High=Mobile CPU
M_RCOMP
MCH_CFG_9
R77
*2.2K
4.MCH_CFG_9 PCI Exp Graphics Lane: Low =Reserved,High=Mobility
MCH_CFG_10
R108
*2.2K
5.MCH_CFG_10 Host PLL VCC Select: Low=Reserved, High=Mobility
MCH_CFG_11
R109
*2.2K
6.MCH_CFG_11: Low=Calistoga, High=Reserved
MCH_CFG_12
R105
*2.2K
MCH_CFG_13
R95
*2.2K
MCH_CFG_16
R75
*2.2K
MCH_CFG_19
R396
*1K/F
+3V
MCH_CFG_18
R59
*1K
+3V
MCH_CFG_20
R41
*1K/F
+3V
R106
80.6/F
R107
80.6/F
A
C190
0.1U
C38
2.2U
Place close ball AK1/AK41
00 = Partial CLK gating disable

10 = All Z mode enabled
01 = XOR mode enabled

11 = Normal operation (Default)
7.MCH_CFG_16 FSB Dynmic ODT: Low=Dynamic ODT Disabled,

High=Dynamic ODT Enabled.
8.MCH_CFG_19 DMI LANE Reversal:Low=Normal,
High=LANES Reversed.
9.MCH_CFG_18 VCC Select: LOW=1.05V, High=1.5V
PROJECT : DW1
10.MCH_CFG_20 PCIE Backward interpoerability mode: Low= only

SDVO or PCIE x1 is operational (defaults) ,High=SDVO and PCIE x1
are operation simultaneously via the PEG port.
Size
Document Number
Custom
Date:
R15
Calistoga
L_CLKCTLA
L_CLKCTLB
1.8VSUS
EXP_A_COMPX
D40
D38
< 0.1" . 15mils/15mils space

use 1% R
+3V
15mils/10mils
DPST_PWM
LCD_BLON
15mils/15mils
M_ODT0
M_ODT1
M_ODT2
M_ODT3
+V1.5_PCIE
U27C
DPST_PWM
LCD_BLON
L_CLKCTLA
L_CLKCTLB
EDIDCLK
EDIDDATA
L_IBG
L_VBG
DISP_ON
L_VREFH
L_VREFL
GRAPHICS
MUXING
DDR
SM_CK#_0
SM_CK#_1
SM_CK#_2
SM_CK#_3
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
VGA
AY35
AR1
AW7
AW40
+V1.5_PCIE 11
+3V
4,5,11,13,14,15,16,17,18,19,20,24,29,30,31,32,33,34,35,36,38
SMDDR_VREF 15,40
1.8VSUS 10,15,36,40
TV
T185
T160
T184
T162
T164
T166
T180
T182
T183
T157
T181
T158
T188
T159
T189
T163
T178
T165
T179
D1
C41
C1
BA41
BA40
BA39
BA3
BA2
BA1
B41
B2
AY41
AY1
AW41
AW1
A40
A4
A39
A3
SDVO_CTRLCLK
SDVO_CTRLDATA
LT_RESET#
NC
TP_MCH_NC0
TP_MCH_NC1
TP_MCH_NC2
TP_MCH_NC3
TP_MCH_NC4
TP_MCH_NC5
TP_MCH_NC6
TP_MCH_NC7
TP_MCH_NC8
TP_MCH_NC9
TP_MCH_NC10
TP_MCH_NC11
TP_MCH_NC12
TP_MCH_NC13
TP_MCH_NC14
TP_MCH_NC15
TP_MCH_NC16
TP_MCH_NC17
TP_MCH_NC18
H28
H27
K28
PM_BMBUSY#
PM_EXTTS#_0
PM_EXTTS#_1
PM_THRMTRIP#
PWROK
RSTIN#
MISC
SDVO_CtrlClk
SDVO_CtrlData
MCH_ICH_SYNC
13 SDVO_CtrlClk
13 SDVO_CtrlData
17 MCH_ICH_SYNC
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
SM_CK_0
SM_CK_1
SM_CK_2
SM_CK_3
+V1.5_PCIE
+3V
SMDDR_VREF
1.8VSUS
LCD_BLON
CLK
T36
DMI
G28
F25
H26
G6
AH33
AH34
T40
T35
LVDS
PM_BMBUSY#
18 PM_BMBUSY#
PM_EXTTS#0
14,15 PM_EXTTS#0
PM_EXTTS#1
14,18 PM_EXTTS#1
5,16 PM_THRMTRIP#
18,41 DELAY_VR_PWRGOOD
T29
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM
K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26
MCH_BSEL0
MCH_BSEL1
MCH_BSEL2
T28
T45
T37
CFG
MCH_BSEL0
MCH_BSEL1
MCH_BSEL2
MCH_CFG_3
MCH_CFG_4
MCH_CFG_5
MCH_CFG_6
MCH_CFG_7
MCH_CFG_8
MCH_CFG_9
MCH_CFG_10
MCH_CFG_11
MCH_CFG_12
MCH_CFG_13
MCH_CFG_14
MCH_CFG_15
MCH_CFG_16
MCH_CFG_17
MCH_CFG_18
MCH_CFG_19
MCH_CFG_20
4
4
4
RSVD
CLK_MCH_OE#
MCH_RSVD_1
MCH_RSVD_2
MCH_RSVD_3
MCH_RSVD_4
MCH_RSVD_5
MCH_RSVD_6
MCH_RSVD_7
MCH_RSVD_8
TV_DCONSEL0
TV_DCONSEL1
MCH_RSVD_11
MCH_RSVD_12
MCH_RSVD_13
MCH_RSVD_14
MCH_RSVD_15
T4
T3
T2
T186
T52
T41
T44
T49
T25
T5
T8
T161
T167
T168
T7
T14
U27B
H32 RSVD_0
T32 RSVD_1
R32 RSVD_2
F3 RSVD_3
F7 RSVD_4
AG11 RSVD_5
AF11 RSVD_6
H7 RSVD_7
J19 RSVD_8
K30 RSVD_9
J29 RSVD_10
A41 RSVD_11
A35 RSVD_12
A34 RSVD_13
D28 RSVD_14
D27 RSVD_15
PCI-EXPRESS
Rev
1A
GMCH DMI VEDIO(3 OF 6)
Sheet
1
of
42
U27G
C478
330U/2.5V/ESR-9/POS
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110
+1.05V
+
VCC
VCC_SM_0
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_SM_37
VCC_SM_38
VCC_SM_39
VCC_SM_40
VCC_SM_41
VCC_SM_42
VCC_SM_43
VCC_SM_44
VCC_SM_45
VCC_SM_46
VCC_SM_47
VCC_SM_48
VCC_SM_49
VCC_SM_50
VCC_SM_51
VCC_SM_52
VCC_SM_53
VCC_SM_54
VCC_SM_55
VCC_SM_56
VCC_SM_57
VCC_SM_58
VCC_SM_59
VCC_SM_60
VCC_SM_61
VCC_SM_62
VCC_SM_63
VCC_SM_64
VCC_SM_65
VCC_SM_66
VCC_SM_67
VCC_SM_68
VCC_SM_69
VCC_SM_70
VCC_SM_71
VCC_SM_72
VCC_SM_73
VCC_SM_74
VCC_SM_75
VCC_SM_76
VCC_SM_77
VCC_SM_78
VCC_SM_79
VCC_SM_80
VCC_SM_81
VCC_SM_82
VCC_SM_83
VCC_SM_84
VCC_SM_85
VCC_SM_86
VCC_SM_87
VCC_SM_88
VCC_SM_89
VCC_SM_90
VCC_SM_91
VCC_SM_92
VCC_SM_93
VCC_SM_94
VCC_SM_95
VCC_SM_96
VCC_SM_97
VCC_SM_98
VCC_SM_99
VCC_SM_100
VCC_SM_101
VCC_SM_102
VCC_SM_103
VCC_SM_104
VCC_SM_105
VCC_SM_106
VCC_SM_107
C463
0.47U
AU41
AT41 VCC_SM1
C464
0.47U
AM41VCC_SM2
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
+
BA30
PC152
C469
AY30
10U/X6S
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
C89
BA22
0.47U
AY22
AW22
AV22
place Cap on
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
C120
AW15
0.47U
AV15
AU15
AT15
place Cap on
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
AR6
AP6
AN6
AL6
AK6
AJ6
0.47U
AV1 VCC_SM106 C483
AJ1 VCC_SM107
C484
0.47U
330U/2.5V/ESR-9/POS
AA33
W33
P33
N33
L33
J33
AA32
Y32
W32
V32
P32
N32
M32
L32
J32
AA31
W31
V31
T31
R31
P31
N31
M31
AA30
Y30
W30
V30
U30
T30
R30
P30
N30
M30
L30
AA29
Y29
W29
V29
U29
R29
P29
M29
L29
AB28
AA28
Y28
V28
U28
T28
R28
P28
N28
M28
L28
P27
N27
M27
L27
P26
N26
L26
N25
M25
L25
P24
N24
M24
AB23
AA23
Y23
P23
N23
M23
L23
AC22
AB22
Y22
W22
P22
N22
M22
L22
AC21
AA21
W21
N21
M21
L21
AC20
AB20
Y20
W20
P20
N20
M20
L20
AB19
AA19
Y19
N19
M19
L19
N18
M18
L18
P17
N17
M17
N16
M16
L16
330U/2.5V/ESR-9/POS
+1.05V
C486
C193
C194
C143
10U/X6S 10U/X6S 1U
C79
0.1U
1.8VSUS
C465
10U/X6S
C154
0.47U
U27F
C73
0.1U
C124
0.1U
BA23 Ball
C45
0.1U
C82
0.1U
C105
0.1U
AD27
AC27
AB27
AA27
Y27
W27
V27
U27
T27
R27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
AD19
V19
U19
T19
AD18
AC18
AB18
AA18
Y18
W18
V18
U18
T18
VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72
VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17
VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57
AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15
+1.5V_AUX
NCTF
BA15 Ball
11
+1.5V_AUX
4,5,6,7,11,16,19,36,39
+1.05V
9,15,36,40 1.8VSUS
+1.5V_AUX
+1.05V
1.8VSUS
PROJECT : DW1
Size
Document Number
Custom
Date:
Calistoga
Calistoga
5
Rev
1A
GMCH POWER(4 OF 6)
Sheet
1
10
of
42
+1.5V
L10
+V3.3_TVDAC
+V1.5_DPLLA
L11
FCM2012C-121
10uH/0805
+1.05V
+V3.3_ATVBG
C61
0.1U
+V3.3_ATVBG
C36
10U/X6S
10U/X6S
+2.5V
+V3.3_ATVBG
+V1.5_DPLLB
+V1.5_PCIE
+2.5V
AJ41
AB41
Y41
V41
R41
N41
L41
AC33
G41
H41
+V3.3_ATVBG
10uH/0805
C109
0.1U
+V1.5_3GPLL
C87
0.022U
C39
0.1U
+ C22
C41
0.1U
470U_2.5V_12mOhm
+V1.5_HPLL
L13
C205
22U
C462
10U/X6S
+V3.3_ATVBG
FCM2012C-121
C110
0.1U
+V2.5_CRTDAC
C99
0.022U
C192
0.1U
C90
0.1U
+V3.3_ATVBG
+V1.5_MPLL
L12
C50
0.1U
+V3.3_ATVBG
C91
0.022U
+V1.5_DPLLA
+V1.5_DPLLB
+V1.5_HPLL
+V3.3_ATVBG
FCM2012C-121
B stage:
Change C103/C22 heigh to 1.9mm
C171
0.1U
C44
0.01U
C42
0.1U
+V1.5_MPLL
+V3.3_ATVBG
R78
10
25mils
VCCGFOLLOW
D4
PDZ5.6B
1
2
+3V
+V1.5_PCIE
C85
0.022U
+V3.3_ATVBG
+1.5V
+1.5V
+1.5V
R389
0
C468
10U/X6S
PCIE_L
C83
0.1U
C215
0.1U
C78
10U/X6S
+V1.5_TVDAC
C461
10U/X6S
+ C458
220U/4V/ESR=15
C457
10U/X6S
+3V
40mils
+V1.5_3GPLL
L28
1uH
+V1.5_QTVDAC
+1.5V_AUX
+1.5V
R392
0.5/F
R393
0
3GPLL_FB_R
3GPLL_FB_L
+1.5V_AUX
+1.5V
R122
0
+V1.5_TVDAC
+1.5V
L32
V15_TVDAC_R
C94
0.1U
R410
FCM2012C-121
+1.5V
30mils
V1_5SFOLLOW
0.1U
R405
FCM2012C-121
+3V
10
C472
0.022U
+V1.5_QTVDAC
PDZ5.6B
+V3.3_TVDAC
C88
L33
D1
1
C475
C473
0.022U
0.1U
RC0805
R407
+1.05V
+1.5V
+V1.5_PCIE
+2.5V
+3V
VCC_TXLVDS0
VCC_TXLVDS1
VCC_TXLVDS2
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
B26
C39
AF1
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
A38
B39
VCCA_LVDS
VSSA_LVDS
AF2
VCCA_MPLL
H20
G20
VCCA_TVBG
VSSA_TVBG
E19
F19
C20
D20
E20
F20
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
AH1
AH2
VCCD_HMPLL0
VCCD_HMPLL1
A28
B28
C28
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
D21
VCCD_TVDAC
A23
B23
B25
VCC_HV0
VCC_HV1
VCC_HV2
H19
VCCD_QTVDAC
+V3.3_ATVBG
C101
0.1U
+V3.3_ATVBG
L27
100nH
VTT_0
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VTT_26
VTT_27
VTT_28
VTT_29
VTT_30
VTT_31
VTT_32
VTT_33
VTT_34
VTT_35
VTT_36
VTT_37
VTT_38
VTT_39
VTT_40
VTT_41
VTT_42
VTT_43
VTT_44
VTT_45
VTT_46
VTT_47
VTT_48
VTT_49
VTT_50
VTT_51
VTT_52
VTT_53
VTT_54
VTT_55
VTT_56
VTT_57
VTT_58
VTT_59
VTT_60
VTT_61
VTT_62
VTT_63
VTT_64
VTT_65
VTT_66
VTT_67
VTT_68
VTT_69
VTT_70
VTT_71
VTT_72
VTT_73
VTT_74
VTT_75
VTT_76
+1.05V
+V2.5_CRTDAC
L29
FCM2012C-121
+1.05V
VCCSYNC
F21
E21
G21
+2.5V
C202
22U
+2.5V
C30
B30
A30
+1.05V
4,5,6,7,10,16,19,36,39
+1.5V
6,17,19,34,36,39
+V1.5_PCIE 9
+2.5V
13,35,36,39
+3V
4,5,9,13,14,15,16,17,18,19,20,24,29,30,31,32,33,34,35,36,38
AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14
AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AD12
POWER
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40
C485
AC14
AB14
W14
V14
T14
R14
P14
N14
M14
L14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1
C155
2.2U
C59
0.1U
C57
10U/X6S
+1.05V
C122
0.22U
C93
0.47U
C86
0.47U
+2.5V
C58
0.1U
C64
4.7U
C164 0.47U
C172 0.22U
C195 0.47U
Need to check.
HF: Two 0402 @ 0.22 F (one cap placed at
the Edge pin location D2, one cap placed at
power corridor); Two 0603 @ 0.47 F (placed
at Edge pin locations AB1 and A6)
A
PROJECT : DW1
Size
Document Number
Custom
Calistoga
4
C135
4.7U
C173
0.22U
Date:
5
330U/2.5V/ESR-9/POS
+ C103
L7
U27H
H22
C112
C80
0.1U
470U_2.5V_12mOhm
+2.5V
Rev
1A
GMCH POWER (5 OF 6)
Sheet
1
11
of
42
U27I
AC41
AA41
W41
T41
P41
M41
J41
F41
AV40
AP40
AN40
AK40
AJ40
AH40
AG40
AF40
AE40
B40
AY39
AW39
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
Y39
W39
V39
T39
R39
P39
N39
M39
L39
J39
H39
G39
F39
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
AB37
AA37
Y37
W37
V37
T37
R37
P37
N37
M37
L37
J37
H37
G37
F37
D37
AY36
AW36
AN36
AH36
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AB35
AA35
Y35
W35
V35
T35
R35
P35
N35
M35
L35
J35
H35
G35
F35
D35
AN34
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
U27J
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS
AK34
AG34
AF34
AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21
AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
J11
D11
B11
AV10
AP10
AL10
AJ10
AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1
Calistoga
PROJECT : DW1
Calistoga
Size
Document Number
Custom
Date:
Rev
1A
GMCH GND(6 OF 6)
Sheet
1
12
of
42
GMCH SDVO Signal to DVI Signal Bridge

SDVOB_RED+
SDVOB_RED-
9 SDVOB_RED+
9 SDVOB_RED-
SDVOB_GREEN+
SDVOB_GREEN-
9 SDVOB_GREEN+
9 SDVOB_GREEN-
SDVOB_BLUE+
SDVOB_BLUE-
9 SDVOB_BLUE+
9 SDVOB_BLUE-
SDVOB_CLK+
SDVOB_CLK-
9 SDVOB_CLK+
9 SDVOB_CLK-
Intel has released the sighting to change R13,R14 value

(2.2K~5.6K as appropriate) for SDVO I2C bus.
R13
*4.7K
+2.5V
R14
*4.7K SDVO_CtrlData
AS (Address Select)
Default is PH, PD for differnt application
such as dual transmitter.
SDVO_CtrlClk
+2.5V
+3V
L5
*BLM11A601S
2
R12
DVI_AVDD_PLL
17,18,27,33,34,35 PLTRST#
+2.5V
C18
*10U/10V
L8
*BLM11A601S
1
2
9 SDVO_CtrlClk
9 SDVO_CtrlData
DVI_DVDD
C40
*0.1U
DVI_DAT
DVI_CLK
INT+
C31
*0.1U
AVDD_PLL
RESET*
AS
SPC
SPD
AGND_PLL
DGND1
SD_PROM
SC_PROM
SD_DDC
SC_DDC
DVDD1
C43
*10U/10V
AVDD1
SDVOB_STALLSDVOB_STALL+
SDVOB_INTSDVOB_INT+
AGND1
DGND2
HPDET
DVDD2
ATPG
SCEN
VSWING
DVI_AVDD
36
35
34
33
32
31
30
29
28
27
26
25
C14
*0.1U
INTINT+
C21
*0.1U
C15
*0.1U
L6
*BLM11A601S
2
+2.5V
L9
*BLM11A601S
2
+3V
C13
*10U/10V
CH_DVI_DETECT 35
PROM2
PROM1
R16
R18
*10K
*10K
R19
*1.2K
DVI_TVDD
C46
*0.1U
+3V
35 CH_TMDS_CLK35 CH_TMDS_CLK+
C9
*0.1U
R7
*4.7K
R6
*4.7K
U1
1
2
3
A0
A1
A2
8
4
VCC
GND
SCL
SDA
6
5
WP
SD2_CLK
SD2_DAT
35 CH_TMDS_TX035 CH_TMDS_TX0+
*CH7307
13
14
15
16
17
18
19
20
21
22
23
24
C37
*0.1U
35
35
U2
*100K
1
PLTRST#
2
3
SDVO_CtrlClk 4
SDVO_CtrlData 5
6
7
SD2_DAT
8
SD2_CLK
9
DVI_DAT
10
DVI_CLK
11
12
*0.1U
EXP_RXN2 9
EXP_RXP2 9
TLC*
TLC
TVDD1
TDC0*
TDC0
TGND1
TDC1*
TDC1
TVDD2
TDC2*
TDC2
TGND2
C12
*0.1U
*10KR11
C29
48
47
46
45
44
43
42
41
40
39
38
37
+2.5V
AVDD3
SDVOB_CLKSDVOB_CLK+
AGND3
SDVOB_BSDVOB_B+
AVDD2
SDVOB_GSDVOB_G+
AGND2
SDVOB_RSDVOB_R+
INT-
C47
*0.1U
C49
*10U/10V
CH_TMDS_CLKCH_TMDS_CLK+
CH_TMDS_TX0CH_TMDS_TX0+
CH_TMDS_TX0CH_TMDS_TX1CH_TMDS_TX2CH_TMDS_CLK-
R22
R23
R24
R21
*330
*330
*330
*330
CH_TMDS_TX0+
CH_TMDS_TX1+
CH_TMDS_TX2+
CH_TMDS_CLK+
*AT24C08AN-10SI-2.7
PROJECT : DW1
Size
Document Number
Custom
GMCH SDVO
Date:
1

7
Rev
1A
Signal to DVI Signal Bridge

Sheet
13
8
of
42
DDRII DUAL CHANNEL A,B

DDRII A CHANNEL
DDRII B CHANNEL
M_A_A[0..13]
SMDDR_VTERM
M_A_A[0..13] 8,15
SMDDR_VTERM 36,40
M_B_A[0..13]
1.8VSUS
+3V
SMDDR_VTERM
M_B_A[0..13] 8,15
1.8VSUS 9,10,15,36,40
+3V
4,5,9,11,13,15,16,17,18,19,20,24,29,30,31,32,33,34,35,36,38
SMDDR_VTERM
SMDDR_VTERM
C71
0.1U
C144
0.1U
C133
0.1U
C140
0.1U
C98
0.1U
C56
0.1U
C63
0.1U
C102
0.1U
C126
0.1U
C119
0.1U
C77
0.1U
C75
0.1U
C81
0.1U
C60
0.1U
C139
0.1U
C129
0.1U
C97
0.1U
C62
0.1U
C65
0.1U
C117
0.1U
C138
0.1U
C131
0.1U
C68
0.1U
C127
0.1U
C104
0.1U
C130
0.1U
Layout note: Place one cap close to every 2 pullup resistors terminated to SMDDR_VTERM
9,15
M_ODT0
9,15
8,15
8,15
9,15
9,15
M_CKE1
M_A_BS#0
M_A_BS#1
M_ODT1
M_CS#1
M_A_A13
M_ODT0
M_A_A8
M_A_A5
M_A_A3
M_A_A1
RP31
M_A_A6
M_CKE1
M_A_A10
M_A_BS#0
M_A_A7
M_A_A11
M_A_A2
M_A_A0
RP11
M_A_BS#1
M_A_A4
M_A_A12
M_A_A9
M_ODT1
M_CS#1
RP22
RP17
RP21
RP24
RP14
RP18
RP13
RP33
1
3
1
3
1
3
2 56X2
4
2 56X2
4
2 56X2
4
1
3
1
3
1
3
1
3
2
4
2
4
2
4
2
4
1
3
1
3
1
3
2 56X2
4
2 56X2
4
2 56X2
4
8,15
M_B_BS#1
SMDDR_VTERM
56X2
M_B_BS#1
M_B_A0
M_B_A5
M_B_A3
M_B_A12
M_B_A8
RP23
M_B_A2
M_B_A4
M_B_A9
M_B_A1
M_B_A6
M_B_A7
M_CKE2
M_B_BS#2
RP20
M_B_A13
M_CS#2
M_B_WE#
M_B_CAS#
M_B_A10
M_B_BS#0
RP30
RP19
RP12
56X2
56X2
56X2
SMDDR_VTERM
SMDDR_VTERM
9,15
8,15
M_CKE2
M_B_BS#2
8,15
9,15
8,15
8,15
M_B_A13
M_CS#2
M_B_WE#
M_B_CAS#
8,15
M_B_BS#0
RP15
RP16
RP8
RP29
RP25
1
3
1
3
1
3
2 56X2
4
2 56X2
4
2 56X2
4
1
3
1
3
1
3
1
3
2
4
2
4
2
4
2
4
1
3
1
3
1
3
2 56X2
4
2 56X2
4
2 56X2
4
SMDDR_VTERM
56X2
56X2
56X2
56X2
SMDDR_VTERM
SMDDR_VTERM
+3V
R422
*200/F
SMB Address?
C487
*0.1U
CGCLK_SMB
4,15,34 CGDAT_SMB
CGDAT_SMB
9,15 PM_EXTTS#0
9,18 PM_EXTTS#1
PM_EXTTS#1
PM_EXTTS#0
R424
*0
SCLK
VCC
SDA
DXP
ALERT#
DXN
OVERT#
GND
LM86_3V
Q21
*MMBT3904
DDR_THERMDA2
C490
*2200P/50V
DDR_THERMDC
4,15,34 CGCLK_SMB
U29
9,15
8,15
9,15
9,15
9,15
8,15
8,15
8,15
M_CS#0
M_A_RAS#
M_ODT3
M_CS#3
M_ODT2
M_B_RAS#
M_A_WE#
M_A_CAS#
9,15
8,15
9,15
M_CKE3
M_A_BS#2
M_CKE0
M_CS#0
M_A_RAS#
M_ODT3
M_CS#3
M_ODT2
M_B_RAS#
M_A_WE#
M_A_CAS#
M_B_A11
M_CKE3
M_A_BS#2
M_CKE0
RP27
RP32
RP26
RP28
RP9
RP10
1
3
1
3
1
3
1
3
1
3
1
3
2
4
2
4
2
4
2
4
2
4
2
4
56X2
56X2
56X2
56X2
56X2
56X2
SMDDR_VTERM
*MAX6657/GMT781
D
PROJECT : CT6
Size
B
Document Number
Date:
Rev
1A
DDR RES. ARRAY

7
Sheet
14
of
8
42
SMDDR_VREF
T169
4,5,9,11,13,14,16,17,18,19,20,24,29,30,31,32,33,34,35,36,38
9,10,36,40
SMDDR_VREF
1.8VSUS
1.8VSUS
CN20
1 VREF
VSS46 2
M_A_DQ4
3 VSS47
DQ4 4
M_A_DQ1
M_A_DQ0
5 DQ0
DQ5 6
M_A_DQ5
7 DQ1
VSS15 8
M_A_DM0
9 VSS37
DM0 10
M_A_DQS#0
11 DQS#0
12
VSS5
M_A_DQ7
M_A_DQS0
13 DQS0
DQ6 14
M_A_DQ6
15 VSS48
DQ7 16
M_A_DQ2
17 DQ2
18
VSS16
M_A_DQ3
M_A_DQ13
19 DQ3
DQ12 20
M_A_DQ14
21 VSS38
22
DQ13
M_A_DQ12
23 DQ8
24
VSS17
M_A_DQ8
M_A_DM1
25 DQ9
DM1 26
27 VSS49
VSS53 28
M_CLK_DDR0
M_A_DQS#1
29 DQS#1
CK0 30
M_CLK_DDR#0
M_A_DQS1
31 DQS1
CK0# 32
33 VSS39
34
VSS41
M_A_DQ10
M_A_DQ9
35 DQ10
36
DQ14
M_A_DQ15
M_A_DQ11
37 DQ11
DQ15 38
39 VSS50
VSS54 40
M_A_DQ21
M_A_DQ17
M_A_DQS#2
M_A_DQS2
M_A_DQ23
M_A_DQ19
M_A_DQ24
M_A_DQ25
M_A_DM3
M_A_DQ26
M_A_DQ27
9,14
8,14
M_CKE0
M_CKE0
M_A_BS#2
M_A_BS#2
M_A_A12
M_A_A9
M_A_A8
T174
M_A_A5
M_A_A3
M_A_A1
8,14
8,14
M_A_BS#0
M_A_WE#
8,14
9,14
M_A_CAS#
M_CS#1
9,14
M_ODT1
M_A_A10
M_A_BS#0
M_A_WE#
M_A_CAS#
M_CS#1
M_ODT1
M_A_DQ37
M_A_DQ35
M_A_DQS#4
M_A_DQS4
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DM5
M_A_DQ42
M_A_DQ46
M_A_DQ48
M_A_DQ49
M_A_DQS#6
M_A_DQS6
M_A_DQ50
M_A_DQ51
M_A_DQ56
M_A_DQ60
D
M_A_DM7
M_A_DQ62
M_A_DQ58
CGDAT_SMB
CGCLK_SMB
T190
T191
+3V
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VSS18
DQ16
DQ17
VSS1
DQS#2
DQS2
VSS19
DQ18
DQ19
VSS22
DQ24
DQ25
VSS23
DM3
NC4
VSS9
DQ26
DQ27
VSS4
CKE0
VDD7
NC1
A16_BA2
VDD9
A12
A9
A8
VDD5
A5
A3
A1
VDD10
A10/AP
BA0
WE#
VDD2
CAS#
S1#
VDD3
ODT1
VSS11
DQ32
DQ33
VSS26
DQS#4
DQS4
VSS2
DQ34
DQ35
VSS27
DQ40
DQ41
VSS29
DM5
VSS51
DQ42
DQ43
VSS40
DQ48
DQ49
VSS52
NCTEST
VSS30
DQS#6
DQS6
VSS31
DQ50
DQ51
VSS33
DQ56
DQ57
VSS3
DM7
VSS34
DQ58
DQ59
VSS14
SDA
SCL
VDD(SPD)
VSS20
DQ20
DQ21
VSS6
NC3
DM2
VSS21
DQ22
DQ23
VSS24
DQ28
DQ29
VSS25
DQS#3
DQS3
VSS10
DQ30
DQ31
VSS8
CKE1
VDD8
A15
A14
VDD11
A11
A7
A6
VDD4
A4
A2
A0
VDD12
BA1
RAS#
S0#
VDD1
ODT0
A13
VDD6
NC2
VSS12
DQ36
DQ37
VSS28
DM4
VSS42
DQ38
DQ39
VSS55
DQ44
DQ45
VSS43
DQS#5
DQS5
VSS56
DQ46
DQ47
VSS44
DQ52
DQ53
VSS57
CK1
CK1#
VSS45
DM6
VSS32
DQ54
DQ55
VSS35
DQ60
DQ61
VSS7
DQS#7
DQS7
VSS36
DQ62
DQ63
VSS13
SA0
SA1
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
M_A_DM[0..7] 8
M_A_DQ[0..63] 8
M_A_DQS[0..7] 8
M_A_DQS#[0..7] 8
M_A_A[0..13] 8,14
T156
1.8VSUS
M_B_DQ0
M_B_DQ5
M_B_DQS#0
M_B_DQS0
M_B_DQ7
M_B_DQ3
M_B_DQ9
M_B_DQ8
M_B_DQS#1
M_B_DQS1
M_CLK_DDR0 9
M_CLK_DDR#0 9
M_B_DQ11
M_B_DQ10
M_B_DQ20
M_B_DQ17
M_A_DQ20
M_A_DQ16
M_B_DQS#2
M_B_DQS2
PM_EXTTS#0
M_A_DM2
M_B_DQ19
M_B_DQ23
M_A_DQ18
M_A_DQ22
M_B_DQ29
M_B_DQ28
M_A_DQ29
M_A_DQ28
M_B_DM3
M_A_DQS#3
M_A_DQS3
M_B_DQ31
M_B_DQ30
M_A_DQ30
M_A_DQ31
M_CKE1
M_CKE1
9,14
M_CKE2
8,14
M_B_BS#2
M_CKE2
9,14
M_B_BS#2
M_B_A12
M_B_A9
M_B_A8
M_A_A11
M_A_A7
M_A_A6
M_B_A5
M_B_A3
M_B_A1
M_A_A4
M_A_A2
M_A_A0
M_A_BS#1
M_A_RAS#
M_CS#0
M_A_BS#1 8,14
M_A_RAS# 8,14
M_CS#0 9,14
M_ODT0
M_A_A13
M_ODT0
9,14
8,14
8,14
M_B_BS#0
M_B_WE#
8,14
9,14
M_B_CAS#
M_CS#3
9,14
M_B_A10
M_B_BS#0
M_B_WE#
M_B_CAS#
M_CS#3
M_ODT3
M_ODT3
M_B_DQ37
M_B_DQ33
M_A_DQ32
M_A_DQ36
M_B_DQS#4
M_B_DQS4
M_A_DM4
M_A_DQ33
M_A_DQ34
M_B_DQ39
M_B_DQ35
M_A_DQ44
M_A_DQ45
M_B_DQ41
M_B_DQ40
M_A_DQS#5
M_A_DQS5
M_B_DM5
M_B_DQ46
M_B_DQ43
M_A_DQ43
M_A_DQ47
M_B_DQ53
M_B_DQ49
M_A_DQ52
M_A_DQ53
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 9
M_CLK_DDR#1 9
M_B_DQS#6
M_B_DQS6
M_A_DM6
M_B_DQ51
M_B_DQ54
M_A_DQ54
M_A_DQ55
M_B_DQ60
M_B_DQ57
M_A_DQ61
M_A_DQ57
M_B_DM7
M_A_DQS#7
M_A_DQS7
M_B_DQ58
M_B_DQ59
M_A_DQ59
M_A_DQ63
R144
R145
CGDAT_SMB
CGCLK_SMB
4,14,34 CGDAT_SMB
4,14,34 CGCLK_SMB
+3V
10K
10K
CLOCK 0,1
CKE 0,1 H 6.75
2
1.8VSUS
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VREF
VSS47
DQ0
DQ1
VSS37
DQS#0
DQS0
VSS48
DQ2
DQ3
VSS38
DQ8
DQ9
VSS49
DQS#1
DQS1
VSS39
DQ10
DQ11
VSS50
VSS46
DQ4
DQ5
VSS15
DM0
VSS5
DQ6
DQ7
VSS16
DQ12
DQ13
VSS17
DM1
VSS53
CK0
CK0#
VSS41
DQ14
DQ15
VSS54
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VSS18
DQ16
DQ17
VSS1
DQS#2
DQS2
VSS19
DQ18
DQ19
VSS22
DQ24
DQ25
VSS23
DM3
NC4
VSS9
DQ26
DQ27
VSS4
CKE0
VDD7
NC1
A16_BA2
VDD9
A12
A9
A8
VDD5
A5
A3
A1
VDD10
A10/AP
BA0
WE#
VDD2
CAS#
S1#
VDD3
ODT1
VSS11
DQ32
DQ33
VSS26
DQS#4
DQS4
VSS2
DQ34
DQ35
VSS27
DQ40
DQ41
VSS29
DM5
VSS51
DQ42
DQ43
VSS40
DQ48
DQ49
VSS52
NCTEST
VSS30
DQS#6
DQS6
VSS31
DQ50
DQ51
VSS33
DQ56
DQ57
VSS3
DM7
VSS34
DQ58
DQ59
VSS14
SDA
SCL
VDD(SPD)
VSS20
DQ20
DQ21
VSS6
NC3
DM2
VSS21
DQ22
DQ23
VSS24
DQ28
DQ29
VSS25
DQS#3
DQS3
VSS10
DQ30
DQ31
VSS8
CKE1
VDD8
A15
A14
VDD11
A11
A7
A6
VDD4
A4
A2
A0
VDD12
BA1
RAS#
S0#
VDD1
ODT0
A13
VDD6
NC2
VSS12
DQ36
DQ37
VSS28
DM4
VSS42
DQ38
DQ39
VSS55
DQ44
DQ45
VSS43
DQS#5
DQS5
VSS56
DQ46
DQ47
VSS44
DQ52
DQ53
VSS57
CK1
CK1#
VSS45
DM6
VSS32
DQ54
DQ55
VSS35
DQ60
DQ61
VSS7
DQS#7
DQS7
VSS36
DQ62
DQ63
VSS13
SA0
SA1
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
2-1734073-2
DDR2_SODIMM
FSC required for

easily accessible.
SMDDR_VREF 9,40
CN19
PC4800 DDR2
SDRAM SO-DIMM
(200P)
+3V
1.8VSUS
PC4800 DDR2
SDRAM SO-DIMM
(200P)
+3V
1.8VSUS
M_B_DM[0..7] 8
M_B_DQ[0..63] 8
M_B_DQS[0..7] 8
M_B_DQS#[0..7] 8
M_B_A[0..13] 8,14
Place these Caps near So-Dimm1.
M_B_DQ4
M_B_DQ1
C471
2.2U
M_B_DM0
CKE 2,3 H 11
4
C466
2.2U
1.8VSUS
M_B_DQ12
M_B_DQ13
M_B_DM1
M_CLK_DDR3
M_CLK_DDR#3
C121
0.1U
M_CLK_DDR3 9
M_CLK_DDR#3 9
C470
0.1U
C95
0.1U
C92
0.1U
M_B_DQ14
M_B_DQ15
+3V
SMDDR_VREF
M_B_DQ16
M_B_DQ21
PM_EXTTS#1
M_B_DM2
C7
0.1U
PM_EXTTS#0 9,14
C10
2.2U
C217
2.2U
C218
0.1U
M_B_DQ18
M_B_DQ22
M_B_DQ24
M_B_DQ25

No Vias Between the Trace of PIN to
CAP.
M_B_DQS#3
M_B_DQS3
M_B_DQ26
M_B_DQ27
M_CKE3
M_CKE3
9,14
1.8VSUS
M_B_A11
M_B_A7
M_B_A6
C118
2.2U
C84
2.2U
C74
2.2U
M_B_A4
M_B_A2
M_B_A0
1.8VSUS Place
M_B_BS#1
M_B_RAS#
M_CS#2
these Caps near So-Dimm1.
M_B_BS#1 8,14
M_B_RAS# 8,14
M_CS#2 9,14
M_ODT2
M_B_A13
C76
0.1U
M_ODT2 9,14
C72
0.1U
C125
0.1U
M_B_DQ32
M_B_DQ36
C96
0.1U
+3V
SMDDR_VREF
M_B_DM4
M_B_DQ34
M_B_DQ38
C8
0.1U
M_B_DQ44
M_B_DQ45
C11
2.2U
C216
2.2U
C219
0.1U
M_B_DQS#5
M_B_DQS5

No Vias Between the Trace of PIN to
CAP.
M_B_DQ47
M_B_DQ42
M_B_DQ52
M_B_DQ48
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR2 9
M_CLK_DDR#2 9
M_B_DM6
M_B_DQ55
M_B_DQ50
M_B_DQ56
M_B_DQ61
M_B_DQS#7
M_B_DQS7
M_B_DQ62
M_B_DQ63
R143
R146
10K
10K
PROJECT : DW1
Size
Document Number
Custom
SMbus address A4
Date:
3
C467
2.2U
M_B_DQ2
M_B_DQ6
+3V
CLOCK 3,4
SMbus address A0
1.8VSUS

7
Rev
1A
DDR SO-DIMM(200P)
Sheet
15
8
of
42
RTC
VCCRTC
C347
1U/16V
VCCRTC
3VPCU
D14
CH500H-40
R310
20K
CKL:C1/C2: 18pF -> CL:12.5pF

C1/C: 10pF -> CL Value = 8.5pF
G1 Place under Mini-card or Dram door
VCCRTC_5
1
D13
CH500H-40
C376
1U/16V
R304
1M
Y6
VCCRTC_4
CLK_32KX1
C367
18P
G1
SHORT_ PAD1
2
1
R290
1K
R328
10M
RTXC1
RTCX2
RTCRST#
AA3
RTCRST#
SM_INTRUDER#
ICH_INTVRMEN
R311
*1.2KVCCRTC_1
*1K VCCRTC_3
R305
Q17
3
LAN_EEP_CS
W1
LAN_EEP_SK
Y1
LAN_EEP_DOUT Y2
LAN_EEP_DIN
W3
1
*MMBT3904
R312
27
*4.7K
27
27
27
R306
*15K
27
27
27
24
24
BIT_CLK
SYNC
24
AC_RESET#
24
SDDATA_IN
LAN_JCLK
27 LAN_RSTSYNC
VCCRTC_2
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
29
C382
*10P
C383
*10P
C381
*10P
C507
*10P
33
33
33
33
R315
332K/F
ICH_INTVRMEN
Disable
LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
U5
V4
T5
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
U7
V6
V7
LAN_TXD0
LAN_TXD1
LAN_TXD2
R335
39
ACZ_RST#
R5
ACZ_RST#
SDDATA_IN
ACZ_SDIN1
ACZ_SDIN2
T2
T3
T1
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
ACZ_SDOUT
39
10K
SATA_LED#
C277
C278
C354
C353
SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0
3900P
3900P
3900P
3900P
24.9/F
ACZ_SDOUT
AF3
AE3
AG2
AH2
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA_RXN2_C
SATA_RXP2_C
SATA_TXN2_C
SATA_TXP2_C
AF7
AE7
AG6
AH6
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AF1
AE1
SATA_CLKN
SATA_CLKP
SATA_BIAS
AH10
AG10
AC3
AA5
LDRQ#0
LDRQ#1
LFRAME#
AB3
LFRAME#
A20GATE
A20M#
AE22
AH28
GATEA20
H_A20M#
33
33
33
33
33
33
PDIOR#
PDIOW#
PDDACK#
IRQ14
PDIORDY
PDDREQ
PDIOR#
PDIOW#
PDDACK#
IRQ14
PDIORDY
PDDREQ
AF15
AH15
AF16
AH16
AG16
AE15
LAD0
LAD1
LAD2
LAD3
30,34,35
30,34,35
30,34,35
30,34,35
LDRQ#0
T139
30
CPUSLP#
AG27
TP_H_CPUSLP#
R235
*0
AF24
AH25
H_DPRSTP#_R
H_DPSLP#_R
R252
R247
0
0
FERR#
AG26
H_FERR#
GPIO49/CPUPWRGD
AG24
H_PWRGD_R
IGNNE#
INIT3_3V#
INIT#
INTR
AG22
AG21
AF22
AF25
H_IGNNE#
RCIN#
AG23
RCIN#
NMI
SMI#
AH24
AF23
H_NMI
H_SMI#_R
STPCLK#
AH22
H_STPCLK#
THERMTRIP#
AF26
H_THERMTRIP_R
SATARBIASN
SATARBIASP
DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ
DA0
DA1
DA2
AH17
AE17
AF17
PDA0
PDA1
PDA2
DCS1#
DCS3#
AE16
AD16
PDCS1#
PDCS3#
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
IDE
R260
R259
R287
R289
10K
10K
4.7K
8.2K
R251
*56/F
+1.05V
R254
*56/F
H_CPUSLP# 5,7
R243
56/F
ICH_DPRSTP# 5,41
H_DPSLP# 5
H_FERR# 5
R258
H_PWRGD 5
C
H_IGNNE# 5
T108
H_INIT#
H_INTR
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
+1.05V
GATEA20 30
H_A20M# 5
TP1/DPRSTP#
TP2/DPSLP#
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
RCIN#
GATEA20
PDIORDY
IRQ14
LFRAME# 30,34,35
R253
H_INIT#
H_INTR
5
5
RCIN#
30
H_NMI
H_SMI#
5
5
+1.05V
R240
56/F
H_STPCLK# 5
R241
SATALED#
SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C
CLK_PCIE_SATA#
CLK_PCIE_SATA
R292
T4
AF18
LDRQ0#
LDRQ1#/GPIO23
Place within 500 mils of ICH7
INTVRMEN
1
LAN_CLK
U3
ACZ_BIT_CLK
ACZ_SYNC
VCCRTC
Enable
(default)
V3
LAN_RSTSYNC
U1
R6
4 CLK_PCIE_SATA#
4 CLK_PCIE_SATA
STATUS
LAN_JCLK
ACZ_BCLK
ACZ_SYNC
R334
+3V R284
SATA_LED#
LAD0
LAD1
LAD2
LAD3
LAD0
LAD1
LAD2
LAD3
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
39
T130
T133
T134
T135
ICH7 internal VR
enable strap
INTRUDER#
INTVRMEN
R333
T142
T151
SDATA_OUT
Y5
W4
RTC
LPC
CLK_32KX2
AA6
AB5
AC4
Y6
AC-97/AZALIA
C372
18P
AB1
AB2
LAN
CPU
3
4
U30A
5VPCU
+3V
32.768KHZ
BT1
BAT_CONN
24
To confirm what stepping will support?
SATA
24.9/F
PM_THRMTRIP# 5,9
Should be 2" close ICH7
PDD[0..15] 33
PDA[0..2]
33
PDCS1#
PDCS3#
33
33
ICH7-M
R314
*0
+1.05V
3V_S5
Populate for 82562GX/GZ
R236
*1K
LANVCC
*3.6K
U31
LANVCC
LAN_EEP_CS
LAN_EEP_SK
LAN_EEP_DOUT
LAN_EEP_DIN
1
2
3
4
CS
SK
DI
DO
VCC
NC
NC
GND
8
7
6
5
R346
*0
C389
0.1U
PM_THRMTRIP#
THERM_CPUDIE_L#
R237
THERM_CPUDIE# 30
Q16
*MMBT3904
GND
93C46-3GR
R238
10K
R338
PROJECT : DW1
Size
Document Number
Custom
Date:
5
Rev
1A
ICH7-M HOST (1 OF 4)
Sheet
1
16
of
42
27
27
27
27
For 82573 GigaLAN
C502
C503
PCIE_RXN2
PCIE_RXP2
PCIE_TXN2
PCIE_TXP2
C500
C501
0.1U
0.1U
0.1U
0.1U
T92
T100
T93
T94
R342
10K
R337
10K
R451
10K
T88
T105
T90
T87
T149
T146
23
23
USBOC0#
USBOC1#
T143
T147
T152
T144
T201
T200
PERn1
PERp1
PETn1
PETp1
PCIE_TXN1_C
PCIE_TXP1_C
H26
H25
G28
G27
PERn2
PERp2
PETn2
PETp2
PCIE_TXN2_C
PCIE_TXP2_C
PCIE_RXN3
PCIE_RXP3
PCIE_TXN3
PCIE_TXP3
PCIE_RXN4
PCIE_RXP4
PCIE_TXN4
PCIE_TXP4
T91
T98
T97
T99
+3V
PCIE_TXN0_C
PCIE_TXP0_C
PCIE_RXN5
PCIE_RXP5
PCIE_TXN5
PCIE_TXP5
K26
K25
J28
J27
PERn3
PERp3
PETn3
PETp3
M26
M25
L28
L27
PERn4
PERp4
PETn4
PETp4
P26
P25
N28
N27
PERn5
PERp5
PETn5
PETp5
T25
T24
R28
R27
PERn6
PERp6
PETn6
PETp6
PCI-Express
PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1
0.1U
0.1U
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
V26
V25
U28
U27
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
Y26
Y25
W28
W27
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
AB26
AB25
AA28
AA27
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AD25
AD24
AC28
AC27
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
AE28
AE27
CLK_PCIE_ICH#
CLK_PCIE_ICH
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
SPI_SCLK
SPI_CE#
SPI_ARB
R2
P6
P1
SPI_CLK
SPI_CS#
SPI_ARB
SPI_SI
SPI_SO
P5
P2
SPI_MOSI
SPI_MISO
USBOC0#
USBOC1#
USBOC2#
USBOC3#
USBOC4#
USBOC5#
USBOC6#
USBOC7#
D3
C4
D5
D4
E5
C3
A2
B3
OC0#
OC1#
OC2#
OC3#
OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
SPI
For EXPRESS CARD (NEW CARD)
34
34
34
34
C504
C505
F26
F25
E28
E27
USB
For MINI CARD PCI-E
PCIE_RXN0
PCIE_RXP0
PCIE_TXN0
PCIE_TXP0
Direct Media Interface
U30D
34
34
34
34
C25
D25
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3
USBRBIAS#
USBRBIAS
D2
D1
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
9
9
9
9
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
9
9
9
9
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
9
9
9
9
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
9
9
9
9
+3V
RP57
REQ2#
REQ1#
FRAME#
STOP#
+3V
6
7
8
9
10
5
4
3
2
1
REQ4#
TRDY#
DEVSEL#
REQ3#
8.2KX8
D
+3V
RP58
SERR#
LOCK#
PERR#
+1.5V
+3V
CLK_PCIE_ICH# 4
CLK_PCIE_ICH 4
6
7
8
9
10
5
4
3
2
1
INTE#
REQ5#
INTG#
8.2KX8
R242
24.9/F
DRI_IRCOMP_R
+3V
Place within 500 mils of ICH7
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
23
23
23
23
23
23
27
27
20
20
31
31
34
34
34
34
RP59
INTH#
IRDY#
INTF#
INTC#
USB 0~3 : USB PORT
+3V
6
7
8
9
10
5
4
3
2
1
REQ0#
INTD#
INTB#
INTA#
8.2KX8
USB 4 : Camera
3VSUS
USB 5 : Bluetooth Module
RP60
USBOC2#
USBOC3#
USBOC0#
USBOC4#
USB 6 : Mini PCI-E

USB 7 : NEW CARD
3VSUS
USB_RBIAS_PN
6
7
8
9
10
5
4
3
2
1
USBOC1#
USBOC5#
USBOC7#
USBOC6#
8.2KX8
ICH7-M
Place within 500

mils of ICH7
U30B
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
INTA#
INTB#
INTC#
INTD#
E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
TP_ICH_RSVD1
TP_ICH_RSVD2
TP_ICH_RSVD3
TP_ICH_RSVD4
TP_ICH_RSVD5
REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4#/GPIO22
GNT4#/GPIO48
GPIO1/REQ5#
GPIO17/GNT5#
D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8
REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4#
GNT4#
REQ5#
GNT5#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
B15
C12
D12
C15
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
A7
E10
B18
A12
C9
E11
B10
F15
F14
F16
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
LOCK#
SERR#
STOP#
TRDY#
FRAME#
PLTRST#
PCICLK
PME#
C26
A9
B19
PLT_RST-R#
PCLK_ICH
PCI_PME#
G8
F7
F8
G7
INTE#
INTF#
INTG#
INTH#
AE9
AG8
AH8
F21
AH20
TP_ICH_RSVD6
TP_ICH_RSVD7
TP_ICH_RSVD8
RSVD9
Interrupt I/F
A3
B4
C5
B5
PIRQA#
PIRQB#
PIRQC#
PIRQD#
AE5
AD5
AG4
AH4
AD9
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]
GPIO2/PIRQE#
GPIO3/PIRQF#
GPIO4/PIRQG#
GPIO5/PIRQH#
MISC
T137
T138
T141
T140
T127
PCI
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
MCH_SYNC#
REQ0#
GNT0#
21
21
T115
T114
T119
T116
T123
T122
ICH7 Boot BIOS select
C/BE0#
C/BE1#
C/BE2#
C/BE3#
21
21
21
21
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
21
21
21
21
21
SERR#
STOP#
TRDY#
FRAME#
21
21
21
21
R448
10K
R449
*1K
R302
*1K
R303
10K
+3V
ICH7 Boot BIOS select

STRAP
LPC
SPI
+3V
GNT4#
1
0
GNT5#
1
1
(default)
PLT_RST-R# 9
PCLK_ICH 4
PCI_PME# 21
INTE#
INTF#
+3V
21
21
C281
0.1U
T126
T132
T131
MCH_ICH_SYNC
AD[0..31]
PLT_RST-R#
Don't connect to PCI device / Express card
ICH7-M
R229
*1K/F
2
4
21
CKL use 10Kohm

R453
22.6/F
PLTRST# 13,18,27,33,34,35
PROJECT : DW1
U14
TC7SH08FU
Size
Document Number
Custom
Date:
Rev
1A
ICH7-M PCI E (2 OF 4)
Sheet
1
17
of
42
3V_S5
+3V
3V_S5
PCLK_SMB
PDAT_SMB
PCIE_WAKE#
BATLOW#_R
R256
R444
R239
R273
3V_S5
2.2K
2.2K
1K
8.2K
SMB_LINK_ALERT#
SMLINK0
SMLINK1
R439
R440
R441
10K
10K
10K
CLKRUN#
R282
8.2K
10K
SERIRQ
R269
8.2K
10K
RUNTIME_SCI#_R
R288
10K
R438
10K
RSMRST#
R347
10K
R280
10K
DNBSWON#
R248
10K
SYS_RST#-1
R445
SMB_ALERT#
R443
RI#
SWI#
For EMI Perofmance

+3V
U30C
+3V
35
5
R270
*10K/F
R276
*10K/F
RI#
RI#
SUS_STAT#
SYS_RST#
A19
A27
0 SYS_RST#-1 A22
SYS_RST# R446
R286
9 PM_BMBUSY#
T102
R274
R264
AB18
SMB_ALERT# B23
27 SMB_ALERT#
4 PM_STPPCI#
4 PM_STPCPU#
A28
0
0
PM_STPPCI_ICH#
PM_STPCPU_ICH#
Remove RF_OFF# from GPIO26
A21
T205
B21
E23
T106
T95
+3V
CLKRUN#
21,30,35 CLKRUN#
Board_ID2 T111
R271
10K/F
AG18
AC19
0
U2
R504
PCIE_WAKE#
SERIRQ
27,34 PCIE_WAKE#
21,30,35 SERIRQ
5 THERM_ALERT#
VR_PWRGD_CK410
30
30
T223
0
RUNTIME_SCI#_R
0
SMI#_R
R285
R267
SCI#
SMI#
AC20
AF21
SATA
GPIO
GPIO21/SATA0GP
GPIO19/SATA1GP
GPIO36/SATA2GP
GPIO37/SATA3GP
Clocks
21
SMB
T196
T197
T198
SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1
RI#
SPKR
SUS_STAT#
SYS_RST#
GPIO0/BM_BUSY#
GPIO11/SMBALERT#
SYS
GPIO
Power MGT
PCLK_SMB
C22
PDAT_SMB
B22
SMB_LINK_ALERT# A26
SMLINK0
B25
SMLINK1
A25
4,27,34 PCLK_SMB
4,27,34 PDAT_SMB
*1K/F
ACZ_SPKR
14M_ICH
R452
*10
R450
*33
C508
*10P
C509
*10P
R447
R447
No stuff-->boot
Stuff-->No boot
24
CLKUSB_48
GPIO18/STPPCI#
GPIO20/STPCPU#
GPIO26
GPIO27
GPIO28
CLK14
CLK48
AC1
B2
SUSCLK
C20
SLP_S3#
SLP_S4#
SLP_S5#
B24
D23
F22
PWROK
AA4
WAKE#
SERIRQ
THRM#
AD22
VRMPWRGD
AC21
AC18
E21
GPIO6
GPIO7
GPIO8
14M_ICH 4
CLKUSB_48 4
T107
R442
R249
100/F
100/F
R265
PM_DPRSLPVR_R
BATLOW#_R
PWRBTN#
C23
DNBSWON#
R268
*100/F
LAN_RST#
C19
RSMRST#
Y4
PM_RSMRST#_R
E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20
SWI#
GPIO
ICH7-M
30
30
C
ICH_PWROK
C21
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35
GPIO38
GPIO39
SUSB#
SUSC#
T103
AC22
GPIO33/AZ_DOCK_EN#
GPIO34/AZ_DOCK_RST#
Board_ID0 and Board_ID1 swap
14M_ICH
CLKUSB_48
TP0/BATLOW#
GPIO16/DPRSLPVR
GPIO32/CLKRUN#
F20
AH21
AF20
0 Board_ID1
AF19 R502
0 Board_ID0
AH18 R503
AH19 Board_ID3
T204
Board_ID4
AE19
T112
R263
R262
R272
PM_DPRSLPVR 41
*100K
100/F
BATLOW# 30
T96
DNBSWON# 30
RSMRST# 30
100/F
AMP_BEEP
PM_EXTTS#1 9,14
PLTRST# 13,17,27,33,34,35
R332
100/F
SWI#
T199
T118
T113
T136
T101
T229
T206
T231
T109
T110
Lan_RST#
1. If use 82573E (PCI-E), Lan_RST# tie to RSMRST#.
2. If use 82562GX/GZ (LCI), Lan_RST# tie to PLTRST#.
RSMRST#
30
Remove BT_OFF# from GPIO25
+3V
U15
1
2
3
5
4 VR_PWRGD_CK410
BOARD ID Selection
NL17SZ14DFT2G
PWM require 6.9K
+3V
R278
10K
Board_ID0
C350
0.047U
R275
*10K
30
ICH_PWROK
+3V
+3V
R279
*10K
Board_ID2
R281
10K
R492
*10K
Board_ID3
R277
10K
R493
*10K
Board_ID4
R494
*10K
R495
*10K
ICH_PWROK 27
PWROK
R317
100K
R283
*10K
Board_ID1
R327
6.8K/F
C5310.1U
+3V
3VSUS
Change to 6.8K
+3V
+3V
U17
TC7SH08FU
R325
10K
Board_ID0
Board_ID1
Board_ID2
PROJECT : DW1
Board_ID0 30
Board_ID1 30
Board_ID2 30
Size
Document Number
Custom
Date:
Rev
1A
ICH7-M GPIO (3 OF 4)
Sheet
1
18
of
42
+5V
+3V
+1.05V
U30F
V5REF_Sus
C377
1U
PAD1
C375
0.1U
1
+1.5V
+1.5V_PCIE_ICH
L18
BK1608HS800-T
+ C284
220U
C294
0.1U
C296
0.1U
C287
0.1U
+3V
C289
0.1U
+1.5V
R220
1
L44
1uH
AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23
B27
GPLL_R
C506
0.01U
AG28
VccDMIPLL
+1.5V
AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5
Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]
AD2
VccSATAPLL
C499
10U/X6S
C343
1U
C355
0.1U
+3V
+1.5V
C320
0.1U
C323
1U
3V_S5
+1.5V
AH11
Vcc3_3[2]
AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9
Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]
E3
C357
0.1U
C1
T153
T128
TPVCCSUSLAN1
TPVCCSUSLAN2
AA2
Y7
V5
V1
W2
W7
Vcc3_3/VccHDA
U6
VccSus3_3/VccSusHDA
R7
VccSus3_3[19]
V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]
AE23
AE26
AH26
Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]
AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19
Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]
A5
B13
B16
B7
C10
D15
F9
G11
G12
G16
VccRTC
W5
VccSus3_3[1]
P7
VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]
A24
C24
D19
D22
G19
VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]
K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7
Vcc1_5_A[19]
Vcc1_5_A[20]
AB17
AC17
Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]
T7
F17
G17
Vcc1_5_A[24]
Vcc1_5_A[25]
AB8
AC8
VccSus1_05[1]
VccUSBPLL
VccSus1_05[2]
VccSus1_05[3]
VccSus1_05/VccLAN1_05[1]
VccSus1_05/VccLAN1_05[2]Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]
ICH7-M
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
Vcc3_3[1]
GPLL_R_L
+1.5V
C330
0.1U
Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]
IDE
D15
PDZ5.6B
R339
10
PCI
C328
0.1U
C305
1U
CORE
F6
Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
VCC PAUX Vcc1_05[20]
ATX
V5REF[2]
ARX
P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27
V5REF_SUS
V5REF[1]
AD17
VCCA3GP
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
3VPCU
USB
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
5VPCU
U30E
A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27
D12
PDZ5.6B
R291
100/F
G10
USB CORE
V5REF(1)
+ C279
330U/2.5V/ESR-9/POS
C316
0.1U
C326
0.1U
C325
0.1U
C319
0.1U
C308
0.1U
C303
0.1U
C314
0.1U
C309
0.1U
C312
0.1U
C315
0.1U
C304
0.1U
3V_S5
+3V
C356
0.1U
3V_S5
C340
0.1U
C339
0.1U
+1.05V
+3V
C292
0.1U
C311
0.1U
C301
4.7U/10V
C318
0.1U
C
+3V
C317
0.1U
C324
0.1U
C313
0.1U
C310
0.1U
VCCRTC
3V_S5
C338
0.1U
C299
0.1U
C342
0.1U
C302
0.1U
3V_S5
C345
0.1U
C344
0.1U
+1.5V
+1.5V
C307
0.1U
+1.5V
C306
0.1U
K7
TP_ICHVCCSUS1
C28
G20
TP_ICHVCCSUS2
TP_ICHVCCSUS3
A1
H6
H7
J6
J7
T129
C329
0.1U
C333
0.1U
T89
T104
+1.5V
C346
0.1U
ICH7-M
PROJECT : DW1
Size
Document Number
Custom
Date:
5
Rev
1A
ICH7-M POWER (4 OF 4)
Sheet
1
19
of
42
LCD_CON30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
34
33
32
31
CN4
+3V
PANEL VCC CONTROL
VIN_BLIGHT
LCDVCC
+3V
EDIDDATA_1
EDIDCLK_1
R141
+3V
C460
0.1U
+3V
LCDVCC
3.3K
R387
*10K
LIGHT_SENOR 30
C438
0.1U
U26
6
VADJ_R
R140
4.7K
DISP_ON
TXLOUT0+ 9
TXLOUT0- 9
TXLOUT1+
TXLOUT1-
TXLOUT2+ 9
TXLOUT2- 9
TXLCLKOUT+
TXLCLKOUT-
IN
GND
ON/OFF
GND
AAT4280_OUT
C452
0.1U
C456
22U/16V/1206
C444
0.01U
C443
0.1U
C450
4.7U/10V
R388
10K
VADJ_R
BLON
EDIDDATA_1
EDIDCLK_1
TXLOUT1+ 9
TXLOUT1- 9
TXLOUT2+
TXLOUT2-
OUT
IN
AAT4280-1
Reserve for EMI.

TXLOUT0+
TXLOUT0-
L25
FBM2125HM330
C441
*0.1U
C442
*0.1U
C449
0.1U
C439
0.1U
TXLCLKOUT+ 9
TXLCLKOUT- 9
+PWR_SRC
L26
FBM2125HM330
C451
0.1U/50V
C447
0.1U/50V
VIN_BLIGHT
C440
10U/25V
+3V
5VSUS
*0
USBP4USBP4+
1
4
C529
0.1U
1
2
3
4
5
USBP4-1
USBP4+1
2
3
*WCM2012-90
R3 COM-CHOKE-WCM2012-4P
*0
C4
*0.1U
C530 0.1U
17
17
5VSUS
CN1
L3
VADJ_R
*CAMERA
2
4
U33
TC7SH08FU
B stage:
Change CN1 footprint.
R379
1K
R380
*0
3VPCU
BRIGHTNESS 30
DPST_PWM 9
1 BLON
R385
10K
R2
C
D21
9
R382
LCD_BLON
1K
LID#
29,30
1SS355
C455
*10P
Q19
1
EDIDCLK
R383
10K
R384
10K
2N7002E
3
EDIDDATA
+3V
EDIDCLK_1
BLON# (MR)
Default High, Backlight turn on.
When MR off, D28 turn on, Backlight turn off.
Q20
2N7002E
PROJECT : DW1
EDIDDATA_1
Size
B
Document Number
Date:
Rev
1A
LCD CONN
7
Sheet
20
of
8
42
3VSUS
3VSUS
3VSUS
U19B
C420
10U
C362
0.01U
C385
0.1U
C418
0.01U
C423
10U
C408
0.01U
C398
0.01U
VCC_ROUT_832
C417
0.01U
C419
0.01U
C359
0.47U
C393
0.47U
10
20
27
32
41
128
VCC_PCI1
VCC_PCI2
VCC_PCI3
VCC_PCI4
VCC_PCI5
VCC_PCI6
61
VCC_RIN
16
34
64
114
120
VCC_3V
C387
0.01U
PowerOnReset for VccCore

3
When GRESET# is controlled by system,

the pull-up resistor(R353) and
capacitor(C400) do not need to apply.
3VSUS
R353
10K
CBUS_REST#_1
C400
*0.1U
17
17
17
17
17
17
17
17
17
17
17
17
17
17
PCI_CLK_5C832
R326
*22
30 CBUS_REST#
C358
*22P
17
Ground guard
PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
REQ0#
GNT0#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
AD25
D18
CBUS_REST# 1
PCIRST#
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
R343
100
RB500
2
125
126
127
1
2
3
5
6
9
11
12
14
15
17
18
19
36
37
38
39
40
42
43
44
46
47
48
49
50
51
52
53
33
7
21
35
45
8
REQ0#
GNT0#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
124
123
23
24
25
26
29
30
31
REQ#
GNT#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
CBUS_REST#_1
PCIRST#
71
119
GBRST#
PCIRST#
PCI_CLK_5C832 121
4 PCLK_5C832
R5C832_PME#
CLKRUN#
18,30,35 CLKRUN#
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
IDSEL
70
117
86
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
4
13
22
28
54
62
63
68
118
122
AGND1
AGND2
AGND3
AGND4
AGND5
99
102
103
107
111
3VSUS
3VSUS
R362
10K
When HWSPND# is
controlled by system, the
pull-up resistor(R232)
dose not need to apply.
R474
*100K
3VSUS
3VSUS
3VSUS
* NOT Use EEPROM :

R231 : installed
R233,U15,C316 : NOT installed
* Use EEPROM :
R233,U15,C316 : installed
R231 : NOT installed
R473
100K
PCI / OTHER
AD[0..31]
C410
10U
VCC_ROUT1
VCC_ROUT2
VCC_ROUT3
VCC_ROUT4
VCC_ROUT5
VCC_MD
17
67
HWSPND#
69
MSEN
58
XDEN
55
HWSPND#
R370
10K
R369
10K
R367
10K
R475
10K
3VSUS
Serial EEPROM
C429
0.01U
UDIO5
57
UDIO3
UDIO4
65
59
UDIO2
56
UDIO1
60
UDIO0/SRIRQ#
72
SERIRQ
INTA#
115
INTE#
INTB#
116
INTF#
TEST
66
U24
8
7
6
5
SCL
SDA
VCC
NC
SCL
SDA
A0
A1
A3
GND
1
2
3
4
24C02
SERIRQ 18,30,35
INTE#
17
INTF#
17
PCICLK
PME#
CLKRUN#
3VSUS
CLKRUN#
CoreLogic CLOCKRUN#
When CLKRUN# is controlled
by system, the pull-down
resistor(R244) dose not need
to apply.
RI#
R356
*0
R5C832T_V00
This part needs to populate?
R358
10K
R319
*100K
R5C832_PME#
18
PCI_PME# 17
Q18
2N7002E
PROJECT : DW1
Size
Document Number
Custom
R5C832
Date:
Rev
1A
PCI CONNECTOR
Sheet
E
21
of
42
3VSUS
1394_AVCC
L20
FBM1608
C361
10U
U19A
TPBIAS0
113
C363
0.001U
AS CLOSE AS POSSIBLE TO 1394 CONNECTOR.
R63
TPB0N
TPB0P
1394_XIN
94
R320
56.2/F
1394_XOUT 95
XO
FIL0_PWR 96
10K/F REXT
101
FIL0
REXT
IEEE1394/SD
R318
R321
56.2/F
TPBN0
104
TPB0N
TPBP0
105
TPB0P
2
3
TPAN0
108
TPA0N
TPAP0
109
TPA0P
R53
TPB0N_C
TPB0P_C
CN18
1394_CONN
L30
TPA0N
TPA0P
1
4
GND Shields
R39
2
3
TPA0N_C
TPA0P_C
*WCM2012-90
COM-CHOKE-WCM2012-4P
0
C341 270P
R322
56.2/F
C351 0.01U VREF_PWR 100
1
4
C352 0.01U
GND Shields
C366 0.01U
C360 0.33uF
*WCM2012-90
R58
0
XI
Y5
24.576MHz
C371 22P
TPBIAS0
C379 22P
0
L31
5
6
98
106
110
112
C365
0.01U
5
6
AVCC_PHY1
AVCC_PHY2
AVCC_PHY3
AVCC_PHY4
C364
0.1U
VREF
R323
56.2/F
R309
5.11K/F
GUARD GND
MDIO17
87
MDIO16
92
MDIO15
89
MDIO14
91
MDIO13
90
MDIO13
MDIO12
93
MDIO12
MDIO11
81
MDIO11
MDIO10
82
MDIO10
MDIO05
75
MDIO08
88
MDIO19
83
MDIO18
85
MDIO02
78
MDIO03
77
MDIO03
MDIO00
80
SD_CDZ
MDIO01
79
MS_CDZ
MDIO09
84
MDIO09
MDIO04
76
MC_PWR_CTRL_0
MDIO06
74
T154
97
RSV
MDIO07
MDIO08
MDIO13 23
MDIO12 23
2
MDIO11 23
MDIO10 23
MDIO08 23
3VSUS
Close to CHIP
MDIO03 23
MDIO09 23
D16
2
RB500
1
2
D17
1
RB500
R478
10K
GUARD GND
MC_PWR_CTRL_0 23
SD_CDZ
MS_CDZ
SD_CDZ 23
MS_CDZ 23
73
PROJECT : DW1
R5C832T_V00
Size
Document Number
Custom
Date:
A
Rev
1A
IEEE1394
Sheet
E
22
of
42
VCC_XD
VCC_XD
R294
C332
2.2U
22
22
22
22
22
22
22
22
22
SD_CDZ
MS_CDZ
MDIO03
MDIO13
MDIO12
MDIO11
MDIO10
MDIO08
MDIO09
SD_CDZ
MS_CDZ
MDIO03
MDIO13
MDIO12
MDIO11
MDIO10
MDIO08
MDIO09
R295
R297
R296
R300
R301
R298
R299
56/F
56/F
56/F
56/F
56/F
56/F
56/F
SD_WP
MS_D3_SD_D3
MS_D2_SD_D2
MS_D1_SD_D1
MS_D0_SD_D0
MS_BS_SD_CMD
MS_SD_CLK
C327
0.1U
150K
C336
0.1U
C334
0.1U
C335
0.1U
3 IN1 CARD READER

VCC_XD
CN9
MS_D3_SD_D3
MS_BS_SD_CMD
18
15
12
10
7
4
3
2
20
21
23
1
22
MS_SD_CLK
MS_D0_SD_D0
MS_D1_SD_D1
MS_D2_SD_D2
SD_CDZ
SD_WP
VCC_XD
SD-1(DAT3)
SD-2(CMD)
SD-3(VSS)
SD-4(VCC)
SD-5(CLK)
SD-6(VSS)
SD-7(DAT0)
SD-8(DAT1)
SD-9(DAT2)
SD-CD1
SD-CD2(G)
SD-WP1
SD-WP-COM
(VSS)MS-1
(BS)MS-2
(DAT1)MS-3
(DAT0)MS-4
(DAT2)MS-5
(INS)MS-6
(DAT3)MS-7
(SCLK)MS-8
(VCC)MS-9
(VSS)MS-10
5
6
8
9
11
13
14
16
17
19
MS_BS_SD_CMD
MS_D1_SD_D1
MS_D0_SD_D0
MS_D2_SD_D2
MS_CDZ
MS_D3_SD_D3
MS_SD_CLK
3VSUS
C331
U16
1U
MC_PWR_CTRL_0
22 MC_PWR_CTRL_0
24
25
26
VCC_XD
5
3
IN OUT
NC
EN GND
C337
10U
G5240
NAIL1
NAIL2
NAIL3
Memory Card Power Supply
3IN1_DFHD23MS166
5VSUS
5VSUS
U25
IN
OUT
ON# SET
GND
USB3PWR
40 mils Iout=1A
1
OC1
OC2
8
5
100U/10V
R5
0
CN14
L4
USB2PWR
TI2062
1
2nd source AL000546005.
B stage:
Change to H=1.9mm.
USB2PWR
C290
17
17
USBP2USBP2+
2
1
1
2
3
4
USBP2-1
USBP2+1
3
4
COM-CHOKE-ILS0405-01-4P
GND
GND
GND
GND
8
7
6
5
Suyin_020151MR004S523ZU
100U/10V
R4
C300
470P/50V
B stage:
Change to H=1.9mm.
G5240
C321
C349
470P/50V
USBOC0# 17
USBOC1# 17
100U/10V
C6
*Clamp-Diode
USB 3
EN1
EN2
GND
C434
C433
470P/50V
R376
6.8K/F
3
4
1
OUT1
OUT2
C435
1U
USB1PWR
VCC
7
6
U11
2
USB1PWR
C498
1U
C5
*Clamp-Diode
USB1PWR
R307
0
CN28
L19
17
17
1
4
USBP0USBP0+
USBP0-1
USBP0+1
2
3
*WCM2012-90
R293
0
1
2
3
4
GND
GND
GND
GND
8
7
6
5
USB 1
Suyin_020173MR004G552ZR
C348
*Clamp-Diode
C322
*Clamp-Diode
USB2PWR
R244
0
CN26
L16
4
1
USBP1USBP1+
USBP1-1
USBP1+1
3
2
*WCM2012-90
R250
0
1
2
3
4
GND
GND
GND
GND
8
7
6
5
USB 2
PROJECT : DW1
Suyin_020173MR004G552ZR
17
17
C293
*Clamp-Diode
C297
*Clamp-Diode
Size
Document Number
Custom
Date:
Rev
1A
CARD READER CONN,USB x 3
Sheet
E
23
of
42
+3V
3V_DVDD
AVDD
2
BLM11A601S
1
C391
0.1U
C388
0.1U
C412
0.1U
C513
0.1U
C517
0.1U
Vout
C514
10U/10V
+5V
L22
5V_AVDD
Vin
C396
0.1U
1
C397
0.047U
2
BLM11A601S
C394
1U
C386
0.1U
C390
10U/10V
C399
10U/10V
U20
GMT_G910T21U
L23
1
GND
BIT_CLK
VDDIO is used in determining which HD Audio bus voltage
is present on the system. When VDDIO is +1.5V, the
device will use 1.5v signaling on the HDA interface pins;
when VDDIO is +3.3v, the device will use 3.3v signaling
on the HDA interface pins.
26
26
18
BITCLK
33
SDI
DIBP_HS
DIBP_HS
R355
DIBP
DIBN_HS
DIBN_HS
R354
DIBN
ACZ_SPKR
ACZ_SPKR
25
33
SPDIF
C392
0.1U
PCBEEP
SPDIF
EAPD
T155
3V_DVDD
R363
237K/F
RCOSC
RESET#
5
9
7
4
BIT_CLK
SYNC
SDI
SDO
44
43
DIBP
20
31
37
MIC_BIAS_L
MIC_BIAS_R
MIC_L
MIC_R
INT_MICBIAS_L
INT_MICBIAS_R
INT_MIC_L
INT_MIC_R
LINEOUT_L
LINEOUT_R
35
36
LINEOUT_L
LINEOUT_R
PORT-A_BIAS_L
PORT-A_BIAS_R
PORT-A_L
PORT-A_R
33
34
38
39
PORT-B_BIAS_L
PORT-B_BIAS_R
PORT-B_L
PORT-B_R
14
15
23
24
CD_L
CD_GND
CD_R
17
18
19
SENSE
13
VREF_HI
VREF_LO
VC_REFA
26
27
28
DIBN
11
PCBEEP
48
SPDIF
47
EAPD
1
2
16
NC_1
NC_2
NC_16
41
RCOSC
CX20549-12
INT_MICBIAS_R
INT_MICBIAS_L
Internal MIC
LINEOUT_L 25
LINEOUT_R 25
B stage:
R377
2.2K
Speaker
R378
2.2K
CN2
INT_MIC_R
C436
10U
INT_MIC_L
C437
10U
INT_MIC_R_1
1
2
3
4
INT_MIC_L_1
MICBIAS_B
MICBIAS_B 25
MIC
MIC
MIC
MIC IN
AGND
25
SENSE
VREF_HI
VREF_LO
VC_REFA
R464
R467
R461
C516 1U
5.11K/F
5.11K/F
10K/F
AGND
AVDD
SENSE_PORT_A 25
SENSE_PORT_B 25
C515 1U
AVSS_12
AVSS_25
AVSS_32
AVSSHP
BIT_CLK
R457
SYNC
SDDATA_IN R348
SDATA_OUT
Internal MIC
29
30
21
22
12
25
32
40
BIT_CLK
SYNC
SDDATA_IN
SDATA_OUT
DVSS
16
16
16
16
10
AC_RESET#
VSSIO_42
VSSIO_46
For associated Line Side

Device portion of this
design
see Conexant RD02-D450
reference schematic
AC_RESET#
42
46
Reserve for EMI
16
AVDD_20
AVDD_31
AVDDHP
C510
*22P
DVDD
DVDDM
VDDIO
U22
8
45
AGND
R455
*22
AGND
AGND
R508
R465
R364
*0
R456
*0
R462
*0
R330
*0
R481
*0
DIGITAL
ANALOG
AGND
PROJECT : DW1
Size
B
Document Number
Date:
Rev
1A
Azalia CTRL_CONEXANT20549
Sheet
E
24
of
42
INT. SPEAKER
L46
BK1608LL121
+5VAMP
C519
100P
C532
0.1U_16V
C533
1U_10V
2
SPK
C534
0.1U_16V
C518
100P
BLM21PG600SN1D
1
1
4
3
2
1
R_SPK+1
L50
2
R_SPK+
+5VAMP
+5V
CN11
L47
BK1608LL121
Audio amplifier
R_SPK-1
R_SPK-
L48
BK1608LL121
10
7
L_SPK+
L_SPKR_SPKR_SPK+
23
GND
22
/SHDN
6
3
16
19
21
PVDDL
PGNDL
PVDDR
PGNDR
VBIAS
12
+5VAMP
C537
0.1U_16V
GAIN_SEL
C538
0.1U_16V
MAX9755AETI
B
AGND
+5VAMP
10.5
C541
1U_10V
AGND
R517
10K
C539
10U_10V
2
24
4
5
17
18
HPR
OUTL+
OUTLOUTROUTR+
15
8
C1N
CPVDD
VDD
HPVDD
C1P
HP_OUT_R
NC
NC
R516
1K
HP_OUT_L
27
C540
1U_10V
MODE MODE
HPL
13
RB500
HP
HPS
14
SPK_SHUTDOWN#
20
11
MUTE#
INR
HPS
AGND
30
GAIN1
R514
100K_0402
D25
GAIN1 SPKR
R513
*100K_NC
INL
VSS
R512
*100K_NC
2
C536 1U_10V
+5VAMP
R515
*1K_NC
2
CPVSS
C524
100P
AGND
28
+5VAMP
GAIN1
RRIN-1
2 RIN-1
CPGND
2 LIN-1
AGND
U34
C535 1U_10V
RLIN-1
1
2
26
24 LINEOUT_R
C520
100P
24 LINEOUT_L
L_SPK-1
L_SPK-
R511
R510
1
25
AGND
L49
BK1608LL121
GND
AGND L_SPK+1
L_SPK+
HPS
3
AGND
AGND
Q30
+5V
SPDIF
220
2N7002E
SPDIF_1
24
R349
SENSE_LINEOUT_A#
HEADPHONE OUT/SPDIF
AGND
R350
*110
C511
0.1U
C395
*100P
MIC JACK
CN31
9
8
7
R520
L51
1
L52
1
HP_R_1
HP_OUT_R
HP_L_1
HP_OUT_L
R521
BLM11A601S
2
BLM11A601S
2
HP_R_2
IC
24
1
3
2
4
5
HP_L_2
0
C413
180P
DRIVE
C404
180P
AVDD
CN29
24
audio/spdif
MIC
C384
10U
L21
MIC1
FCM1608K221
R331
*1K
AGND
C369
100P
Shall install 1k ?
10K
1
2
6
3
4
5
MIC2
AGND
AGND
SENSE_LINEOUT_A#
*10K
R341
2.2K
11
10
6
AGND
R340
MICBIAS_B
MICBIAS_B
R519
8
2SJ-S351-001
+5V
AGND
+5VAMP
C542
24 SENSE_PORT_B
AGND
AGND
SENSE_PORT_B
AGND
0.1u/10V
24 SENSE_PORT_A
SENSE_PORT_A 4
U35
AHCT1G125DCH
AGND
PROJECT : DW1
Size
Document Number
Custom
Date:

7
Rev
1A
JACK,AMP_TPA6211
Sheet
25
of
8
42
CN10
12
11
10
9
8
7
6
5
4
3
2
1
24 DIBP_HS
24 DIBN_HS
12
11
10
9
8
7
6
5
4
3
2
1
AMC Connector
RJ11 CONNECTOR
CN24
CN7
B stage:
1
2
1
2
3
4
TIP_1
RING_1
MDC
C266
470P
NC GND
RING
TIP
NC GND
5
6
RJ11
C262
470P
PROJECT : DW1
Size
Document Number
Custom
Date:
5
Rev
1A
MODEM (DAA)
Sheet
1
26
of
42
U5A
R101
R93
3.3K
R98
*3.3K
*3.3K
DOCK_IND
AUX_PRESENT
R31
R30
619
649
R32
populate R93 for D3 wake up.

R89
18 SMB_ALERT#
*0
R96
18 ICH_PWROK
SMB_ALRT#/ASF_PWRGOOD
*3.3K
4,18,34 PCLK_SMB
4,18,34 PDAT_SMB
*0
22P
1
C70
C69
22P
SMB_ALRT#/ASF_PWRGOOD--NC
SMB_CLK-NC
SMB_DATA-NC
T24
T33
T30
T32
A8
B8
C8
C7
SDP0--NC
SDP1--NC
SDP2--NC
SDP3--NC
XTAL1
XTAL2
K14
J14
XTAL1--X1
XTAL1--X2
T
A5
A6
D3
LED0#--SPDLED
LED1#--ACTLED
LED2#--LILED
B11
C11
A12
JTAG_TMS--NC
JTAG_TDI--NC
JTAG_TCK--NC
JTAG_TDO--NC
N4
P4
N5
P6
R90
R81
R102
*0
*3.3K
*3.3K
Populate R308 to disable SPI NVM protection.

Populate R309 - Use SPI FLASH
Populate R311 - Sahre SPI with ICH7-M.
C52
*0.01U
C53
*0.01U
R394 *54.9/F
N11
P11
M11
NVM_CS#
NVM_SK
NVM_SI
NVM_SO
54.9/F
PHY_TSTPT--RBIAS10
PHY_HSDACn-RBIAS100
PHY_HSDACp-TOUT
ALT_CLK125--NC
47
47
47
*0
54.9/F
B14
B13
B12
N10
NVM_PROT--NC
NVM_TYPE--NC
NVM_SHARED--NC_D3
R70
R76
R79
R97
R261
TEST_EN--TEST_EN
NC--ISOL_TEX
PHY_REF--ISOL_TI
NC--ISOL_TCK
DOCK_IND--NC
AUX_PRESENT--NC
THERMn--NC
THERMp--NC
B10
C9
A9
B9
B4
R257
A13
D10
D12
D14
C3
C6
L2
L3
NVM_CS#--NC
NVM_SK--NC
NVM_SI--NC
NVM_SO--NC
NVM_REQ--NC
Enternet Port
LAN_PWR_GOOD--NC
DEVICE_OFF#--ADV10/LAN_DIS_N
T50
T51
Y1
25MHZ
PE_RST#--NC
PE_WAKE#--NC
Place temination resistors and caps as

close to LAN controller as possible
TX0P
TX0N
TX1P
TX1N
TX2P
TX2N
TX3P
TX3N
54.9/F
LAN_TEST-TEST_EN
LAN_EXEC_R
LAN_TI_R
LAN_TCK_R
LANVCC
P5
L7
TX0P
TX0N
TX1P
TX1N
TX2P
TX2N
TX3P
TX3N
54.9/F
ICH_PWROK
LAN_ADV10
C13
C14
E13
E14
F13
F14
H13
H14
R221
P7
P10
MDI0p--TDP
MDI0n--TDN
MDI1p--RDP
MDI1n--RDN
MDI2p--NC
MDI2n--NC
MDI3p--NC
MDI3n--NC
R181
PLTRST#
13,17,18,33,34,35 PLTRST#
18,34 PCIE_WAKE#
PE_CLKp--NC
PE_CLKn--NC
Control
NVM/EEPROM
4 CLK_PCIE_LAN
4 CLK_PCIE_LAN#
PE_T0p--NC
PE_T0n--NC
G1
G2
LEDs
CLK_PCIE_LAN
CLK_PCIE_LAN#
D1
C1
SMBus
PCIE_RXP2_C
PCIE_RXN2_C
JTAG 82570EI
0.1U
0.1U
LAN Connect Interface
C162
C161
PCIE_RXP2
PCIE_RXN2
PE_R0p--NC
PE_R0n--NC
Test
PCIE_RXP2
PCIE_RXN2
F2
F1
PCI Express
17
17
PCIE_TXP2
PCIE_TXN2
SDP Pins
Thermal
Monitoring
PCIE_TXP2
PCIE_TXN2
Crystal
17
17
R391 *54.9/F
R390 *54.9/F
R266 *54.9/F
C54
*0.01U
C55
*0.01U
LINK_100_LED#
LINK_ACT_LED#
LINK_1000--LINK_UP_LED#
JTAG_TMS
JTAG_TDI
JTAG_TCK
JTAG_TDO
573E populated 49.4

562GZ/GX populated 54.9
T42
T38
T34
T27
LANVCC
C
NC--LAN_RXD[2]
NC--LAN_RXD[1]
NC--LAN_RXD[0]
M12
N13
P13
R74
R65
R69
0
0
0
CLK_VIEW--LAN_TXD[2]
NC--LAN_TXD[2]
NC--LAN_TXD[0]
L14
L13
M14
R35
R38
R51
0
0
0
NC--LAN_RSTSYNC
M13
R56
NC--LAN_CLK
N14
R60
82562GZ/GX
LAN_RXD2 16
LAN_RXD1 16
LAN_RXD0 16
C100
*0.1U
U4
LAN_TXD2 16
LAN_TXD1 16
LAN_TXD0 16
R72
LAN_RSTSYNC 16
LANVCC
*8.2K
NVM_CS#
NVM_SK
NVM_SI
NVM_SO
R28
*3.3K
1
6
5
2
3
LAN_JCLK 16
CE#
SCK
SI
SO
VDD
HOLD#
WP#
VSS
R73
*3.3K
*SST25LF080A
T : Stuffed for 82573E(10/100/1000)

E : Stuffed for 82856GZ/GX(10/100)
Stuff for full

power down
mode,
82562GX/GZ
LANVCC
For 10/100/100 option
LANVCC
LINK_100_LED#
LINK_100_LED#
LANVCC
R88
10K
30 LAN_DISABLE#
R80
*1K LAN_RST#_R
MODE2
R67
*470
Stuff for 82562

only, not for
82562
enhanced
mode
LAN_ISOL
3
LANVCC
LANVCC
R55
R37
R61
R48
*100
*100
*100
*100
LAN_TI_R
LAN_TCK_R
LAN_EXEC_R
LAN_TEST-TEST_EN
TX0P
TX0N
2
R52
*200/F
T
R62
*4.99K/F
LAN
TX1P
TX1N
TX2P
TX2N
TX3P
TX3N
LAN_ADV10
1000_LINK#
100_LINK#
82573E = 3.3K
82562GZ = 200
R86
*1K
LAN LED
CN17
Resistor value:
0
150
*0
0
0
*0
*150
R40 R66 R36 R57

200/F 200/F *200/F *200/F
Q2
*RHU002N06
R84
R496
R497
R498
R499
R500
R501
USB3
17
17
USBP3+
USBP3-
USB_P3+
USB_P3-
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
Close to CN17
LANVCC LAN_2.5V 5VSUS
LINK_ACT_LED#
1000_LINK#
100_LINK#
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
LANVCC
LAN_2.5V
5VSUS
0.1U
*22P
PROJECT : DW1
Size
Document Number
Custom
Date:
C20
0.1U
CAPSLED 30
B stage:
1. Populate Q2 (A-test lose)
2. ChangeR52 value to 200 ohm.
4
C16
0.1U
C19
EIC 3760-30-01
C17
Rev
1A
LAN 82573E/82562GZ
Sheet
1
27
of
42
LANVCC
C141
*0.1U
C132
*4.7U
CTRL_2.5
*MMJT9435T1
Q5
LAN_2.5V
2
4
C182
*10U
C181
*10U
C159
*0.1U
C160
*0.1U
F4
F5
F6
F7
F8
F9
F10
F11
VSS--VSS_F4
VSS--VSS_F5
VSS--VSS_F6
VSS--VSS_F7
VSS--VSS_F8
VSS--VSS_F9
VSS--VSS_F10
VSS--VSS_F11
G4
G7
G8
G9
G10
G11
G14
H9
H10
K2
K12
L6
L11
M6
N1
N12
P8
VSS--NC_G4
VSS--VSS_G7
VSS--VSS_G8
VSS--VSS_G9
VSS--VSS_G10
VSS--VSS_G11
VSS--VSS_G14
VSS--VSS_H9
VSS--VSS_H10
VSS--VSS_K2
NC--VSS_K12
NC--VSS_L6
NC--VSS_L11
NC--VSS_M6
VSS--VSS_N1
VSS--VSS_N12
VSS--VSS_P8
VCC Pins
VSS--NC_A1
VSS--VSS_B3
NC--VSS_B7
VSS--NC_C2
VSS--VSS_C10
VSS--VSS_C12
VSS--NC_D2
VSS--VSS_D4
VSS--VSS_D5
VSS--VSS_D6
VSS--VSS_D7
VSS--VSS_D8
VSS--VSS_D13
VSS--VSS_E2
VSS--VSS_E4
VSS--VSS_E5
VSS--VSS_E6
VSS--VSS_E7
VSS--VSS_E8
VSS--VSS_E9
VSS--VSS_E10
VSS Pins
U5B
A1
B3
B7
C2
C10
C12
D2
D4
D5
D6
D7
D8
D13
E2
E4
E5
E6
E7
E8
E9
E10
LANVCC
TEST0--NC
TEST1--NC
TEST2--NC
TEST3--NC
TEST4--NC
TEST5--NC
TEST6--NC
TEST7--NC
TEST8--NC
TEST9--NC
TEST10--NC
TEST11--NC
TEST12--NC
TEST13--NC
TEST14--NC
TEST15--NC
TEST16--NC
NC--NC_D11
NC--NC_J13
NC--NC_L8
NC--NC_M5
NC--NC_M7
NC--NC_M9
NC--NC_N9
NC--NC_P14
C166
*1U
C167
*4.7U
*MMJT9435T1
Q4
H1
H2
H3
J1
J2
J3
K1
L1
M1
M3
N2
P1
N3
M8
P9
E3
A14
D11
J13
L8
M5
M7
M9
N9
P14
CTRL_1.2
VCC1.2--NC-A10
VCC1.2--NC-C5
VCC1.2--NC-C4
VCC1.2--NC-F12
VCC1.2--VCC3.3_G6
VCC1.2--NC-G12
VCC1.2--VCC3.3_G13
VCC1.2--VCC3.3_H6
VCC1.2--VCC3.3_H7
VCC1.2--VCC3.3_H8
VCC1.2--VCC3.3_H11
VCC1.2--NC_H12
VCC1.2--VCC3.3_J6
VCC1.2--VCC3.3_J7
VCC1.2--VCC3.3_J8
VCC1.2--VCC3.3_J9
VCC1.2--VCC3.3_J10
VCC1.2--VCC3.3_J11
VCC1.2--VCC_K3
VCC1.2--VCC_K4
VCC1.2--VCC3.3_K5
VCC1.2--VCC3.3_K6
VCC1.2--VCC3.3_K7
VCC1.2--VCC3.3_K8
VCC1.2--VCC3.3_K9
VCC1.2--VCC3.3_K10
VCC1.2--VCC3.3_K11
VCC1.2--VCC3.3_L5
VCC1.2--VCC3.3_L9
VCC1.2--VCC3.3_L10
A10
C5
C4
F12
G6
G12
G13
H6
H7
H8
H11
H12
J6
J7
J8
J9
J10
J11
K3
K4
K5
K6
K7
K8
K9
K10
K11
L5
L9
L10
IREG2.5_IN--NC_A2
IREG2.5_IN-A3
VCC3.3--VCC_A7
VCC3.3--NC_D9
NC--VCC_E1
NC--VCCT_E11
NC--VCCT_E12
VCC3.3--NC_F3
VCC3.3--NC_J4
NC--VCC_L4
FUSEV--NC
VCC3.3--NC_M10
VCC3.3--VCC_N6
VCC3.3--VCC_N8
VCC3.3--VCC_P2
VCC3.3--VCC_P12
A2
A3
A7
D9
E1
E11
E12
F3
J4
L4
M2
M10
N6
N8
P2
P12
VCC2.5--VCC_A11
VCC2.5--NC_B6
VCC2.5--NC_G3
VCC2.5--VCCR_G5
VCC2.5--NC_H4
VCC2.5--VCCR_H5
VCC2.5--VCC3.3_J5
VCC2.5--NC_J12
VCC2.5--VCC_K13
VCC2.5--NC_L12
VCC2.5--NC_M4
VCC2.5--NC_N7
A11
B6
G3
G5
H4
H5
J5
J12
K13
L12
M4
N7
VCC2.5_OUT--NC_B1
VCC2.5_OUT--NC_B2
CTRL_1.2--NC
CTRL_2.5--NC
EN2.5REG--NC_B5
C66
0.1U
C106
0.1U
C174
0.1U
R113
R117
*0
LANVCC
LAN_1.2V
C169
4.7U
LANVCC
C
C170
10U
C134
10U
C163
0.1U
C113
0.1U
C116
0.1U
C108
0.1U
C114
0.1U
C67
0.1U
C115
0.1U
C123
4.7U
R94
R114
*0
C165
4.7U
LANVCC
LAN_2.5V
LANVCC
LAN_2.5V
R83
*3.3K
B1
B2
P3
A4
B5
CTRL_1.2
CTRL_2.5
T47
T46
PD - To disable internal 2.5V regulator.

PH - To enable internal 2.5V regulator.
It's just for 82573E using.
R87
*3.3K
82562GZ/GX
2
4
LAN_1.2V
R132
*2
R119
*2
LANVCC
C187
*4.7U
C186
*10U
C188
*0.1U
C189
*0.1U
R91
*10K
R1
R85
*10K
R2
To enable clocks for Tekoa-M,
stuff R1, Unstuff R2
PROJECT : DW1
Size
Document Number
Custom
Date:
5
Rev
1A
LAN Power
Sheet
1
28
of
42
30 PowerLED_AMBER#
Q28
DTC144EUA
AC Present (Orange)
5VPCU
B stage:
Can change to S3 power plane to
save power consumption
R486
150/F
LED4
1
Q29
DTC144EUA LED ORANGE/BLUE
System power (Blue)
5VSUS
+3V
LED HSMD-C112 BLUE

2
30 PowerLED_BLUE#
5VPCU
R485
150/F
LED3
1
R484
150/F
LED1
2
34
RF_LED#
Q26
Q25
DTC144EUA
LED LTST-S110UBKT-Q BLUE
30 BATLED_AMBER#
B stage:
Change color from blue to orange
DTC144EUA
+3V
2
Status:
1. Charge - ON
2. Discharge - OFF
31
5
1
3
TP_R#
TP_R#
R482
150/F
LED2
SW2
TC901-AA1G-A160T
16 SATA_LED#
6
2
4
Q27
DTC144EUA
SW1
TC901-AA1G-A160T
31
5
1
3
TP_L#
TP_L#
6
2
4
+5V
HOLE14
H-C197D197N
HOLE23
H-C315BC236D83P2
HOLE17
H-C315D83P2
HOLE22
H-S236D83P2
HOLE5
H-TS393BC276D83P2
HOLE15
H-TS393BC276D83P2
HOLE4
H-TS393BC276D83P2
HOLE3
H-TS393BC276D83P2
HOLE19
H-BC236D43P2
CPU Thermal Module lock HOLE.
3VPCU
30,31 MX3
HOLE20
H-BC236D43P2
HOLE25
H-DW1D83P2
HOLE11
H-C256D142P2
HOLE9
H-C256D142P2
HOLE8
H-C256D142P2
HOLE10
H-C256D142P2
HOLE21
H-C276D43P2
HOLE18
H-C276D43P2
HOLE24
H-R394X413BC276D83D10P2
POWER BOARD
AGND
HOLE12
H-TS393BC315D177P2
HOLE13
H-TS393BC315D177P2
HOLE2
H-C276D83P2
HOLE1
H-C236BC197D83P2
MDC HOLE.
AGND
30,31 MX4
30,31
30,31
30,31
30,31
30
30
MY0
MX0
MX1
MX2
NUMLED
NBSWON#
20,30 LID#
MX3
PowerLED_AMBER#
MX4
PowerLED_BLUE#
MY0
MX0
MX1
MX2
NUMLED
NBSWON#
RF_LED#
LID#
RP18
6
4
2
RP28
6
4
2
RP38
6
4
2
7
5
3
1
7
5
3
1
7
5
3
1
MX4_1
P_LED
AC_PRE
MX3_1
MX2_1
MX1_1
MX0_1
MY0_1
LID#_1
RFLED#
N_LED
SW_ON#
MX3_1
AC_PRE
MX4_1
P_LED
MY0_1
MX0_1
MX1_1
MX2_1
N_LED
SW_ON#
RFLED#
LID#_1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LFBR32164M241
LFBR32164M241
+5V
LFBR32164M241
3VPCU
C446
0.1U
5VPCU
C445
0.1U
C30
0.1U
CN3
A
MINI-PCIE Card lock HOLE.
PROJECT : DW1
Need to apply Nut part number for Thermal,

MDC and Mini-card module.
Size
Document Number
Custom
Date:
5
Rev
1A
LED, Hole, TP SW, SW/B
Sheet
1
29
of
42
3VPCU
3VPCU
3VPCU
10K
3VPCU
18
16,34,35 LFRAME#
16,34,35 LAD0
16,34,35 LAD1
16,34,35 LAD2
16,34,35 LAD3
R182
4 PCLK_541
2
D8
SMI#
18
SCI#
SCI#
16
16
3VPCU
R198
470K 541RESET#
2
D6
GATEA20
RCIN#
29,31
29,31
29,31
29,31
29,31
31
31
31
C250
0.1U
MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7
29,31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
R161
3VPCU
10K
4.7K
4.7K
TPCLK
TPDATA
2
4
6
8
MSCLK1
MSDAT1
KBCLK
KBDAT
1
3
5
7
B
7
8
9
15
14
13
10
18
19
22
PWUREQ# 23
1
RB500
GATEA20
RCIN#
MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7
31
31
27
29
8P4R-10K
R226
TPCLK
TPDATA
CAPSLED
NUMLED
20M
IOPD3/ECSCI
5
6
GA20/IOPB5
KBRST/IOPB6
49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68
Host interface
TINT-
105
106
107
108
109
TINT
TCK
TDO
TDI
TMS
110
111
114
115
116
117
118
119
PSCLK1/IOPF0
PSDAT1/IOPF1
PSCLK2/IOPF2
PSDAT2/IOPF3
PSCLK3/IOPF4
PSDAT3/IOPF5
PSCLK4/IOPF6
PSDAT4/IOPF7
32KX1/32KCLKOUT
541_32KX2
160
32KX2
21 CBUS_REST#
25
MUTE#
18
D9
RB500
DNBSWON#
36
S5_ON
36,40
SUSON
36,39,40 MAINON
36 LAN_POWER
36,41
VRON
1
18
RSMRST#
18
PWROK
S5_ON
SUSON
MAINON
LAN_POWER
VRON
DNBSWON#591
RSMRST#_EC
PWROK
CS#
173
174
47
T85
T56
IOPM0/D8
IOPM1/D9
IOPM2/D10
IOPM3/D11
IOPM4/D12
IOPM5/D13
IOPM6/D14
IOPM7/D15
PORTJ-2
*0
NBSWON#
IOPH0/A0/ENV0
IOPH1/A1/ENV1
IOPH2/A2/BADDR0
IOPH3/A3/BADDR1
IOPH4/A4/TRIS
IOPH5/A5/SHBM
IOPH6/A6
IOPH7/A7
124
125
126
127
128
131
132
133
ENV0
ENV1
BADDR0
BADDR1
TRIS
SHBM
A6
A7
IOPI0/D0
IOPI1/D1
IOPI2/D2
IOPI3/D3
IOPI4/D4
IOPI5/D5
IOPI6/D6
IOPI7/D7
138
139
140
141
144
145
146
147
D0
D1
D2
D3
D4
D5
D6
D7
IOPJ0/RD
IOPJ1/WR0
150
151
RD#
WR#
SELIO
152
SELIO#
IOPD4
IOPD5
IOPD6
IOPD7
41
42
54
55
SCROLED#
CELL_SET
D/C#
BL/C#
IOPK0/A8
IOPK1/A9
IOPK2/A10
IOPK3/A11
IOPK4/A12
IOPK5/A13/BE0
IOPK6/A14/BE1
IOPK7/A15/CBRD
143
142
135
134
130
129
121
120
A8
A9
A10
A11
A12
A13
A14
A15
IOPL0/A16
IOPL1/A17
IOPL2/A18
IOPL3/A19
IOPL4/WR1
113
112
104
103
48
A16
A17
A18
A19
PORT-D-2
PORT-L
17
35
46
122
159
167
137
R509
2
44
24
25
PORT-K
SEL0
SEL1
CLK
R208
10K
R213
BADDR1
*10K
R215
SHBM
10K
R217
153
154
162
163
164
165
SUSB#
ACIN
LID#
R233
R232
4.7K
4.7K
BCLK
BDATA
R490
R491
4.7K
4.7K
SCLK
SDATA
5VPCU
PowerLED_BLUE# 29
PowerLED_AMBER# 29
BATLED_AMBER# 29
BCLK
5,37
BDATA
5,37
T226
U13
8
7
6
5
BCLK
BDATA
18
37
20,29
VCC
NC
SCL
SDA
A0
A1
A3
GND
NBSWON# 29
T218
T219
CLKRUN# 18,21,35
8Mbit (1M Byte), TSSOP40

U12
Pin 24 if no pull-high,
will can't reboot.
T202
ENV0
ENV1
BADDR0
BADDR1
TRIS
SHBM
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
CS#
RD#
WR#
22
24
9
CE#
OE#
WE#
D0
D1
D2
D3
D4
D5
D6
D7
25
26
27
28
32
33
34
35
RESET#/NC
RY/BY#/NC
NC1
NC2
NC3
10
12
29
38
11
VCC
VCC
31
30
R153
100K
3VPCU
B
C221
*0.1U
3VPCU
C280
0.1U
GND
GND
CELL_SET 37
D/C#
37
BL/C#
37
23
39
ST Micro M29W008AB/AMD-29LV081B/SST39VF080
1.AMD-29LV081B require MAX 500nS Tready

for it's hardware reset.And MAX6326_UR29
has >100mS reset timing.So we can tie it's
reset# pin to +3VALW directly.
2.SIO has internal 20 mS delay of
VCC1_PWROK
AMD :Pin 10 is RESET# ; Pin12 is RY/BY#
SST :Pin10,12 are NC
T59
Pin 103 internal is

"A19",Can't use to
GPIO
PROJECT : DW1
Size
Document Number
Custom
Date:
D0
D1
D2
D3
D4
D5
D6
D7
T220
1U/16V
C283
*0.1U
R218
10K
C247
1
2
3
4
*24LC08
BATLOW# 18
T227
T228
T217
FANSIG
31
BRIGHTNESS 20
3VPCU
T82
THERM_CPUDIE# 16
SUSB#
ACIN
LID#
CLKRUN#
PC87541V
5VPCU
37
T64
T213
PWM_FAN 31
BT_ON# 31
RF_ON# 34
T62
T214
LAN_DISABLE# 27
IOPE4/SWIN
IOPE5/EXWINT40
IOPE6/LPCPD/EXWIN45
IOPE7/CLKRUN/EXWINT46
PORT-M
GND1
GND2
GND3
GND4
GND5
GND6
GND7
148
149
155
156
3
4
27
28
IOPJ2/BST0
IOPJ3/BST1
IOPJ4/BST2
IOPJ5/PFS
IOPJ6/PLI
IOPJ7/BRKL_RSTO
0
0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
D11 2
SWI#
62
63
69
70
75
76
PWM_FAN
R224
R225
30
PORT-I
AGND
18
FANLESS#
HWPG
SUSC#
SWI#_EC
R149
0
MUTE#
10K
BADDR0
I/O Address
Index
BADDR1-0
Data
0 0
2E
2F
0 1
4E
4F
1 0
(HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1
1 1
Reserved
TEMP_MBAT 37
MBAT_V 37
LIGHT_SENOR 20
T224
Board_ID0 18
Board_ID1 18
Board_ID2 18
T61
T209
T210
CC_SET
T222
T211
T212
26
PS2 interface
158
CC_SET
IOPD2/EXWINT24
PORT-J-1
T187
38,39,40,41 HWPG
18
SUSC#
1 RB500
32
33
36
37
38
39
40
43
TEMP_MBAT
MBAT_V
LIGHT_SENOR
SBAT_V
R505
*0 Board_ID0
R506
*0 Board_ID1
R507
*0 Board_ID2
PR_INSERT#
IOPD0/RI1/EXWINT20
PORT-H
120K
C285
4.7P
99
100
101
102
PORT-D-1 IOPD1/RI2/EXWINT21 29
11
12
20
21
85
86
91
92
97
98
C282 Y4
4.7P
R227
81
82
83
84
87
88
89
90
93
94
IOPC0
IOPC1/SCL2
IOPC2/SDA2
IOPC3/TA1
IOPC4/TB1/EXWINT22
IOPC5/TA2
IOPC6/TB2/EXWINT23
IOPC7/CLKOUT
PORT-C
96
4 541_32KX3
3
PowerLED_BLUE#
PowerLED_AMBER#
BATLED_AMBER#
BCLK
BDATA
PCIRST#
D24
RB500
168 BATLOW#_1 1
2
SCLK
169
SDATA
170
171
FANSIG
172
BRIGHTNESS
175
176
THERM_CPUDIE#
1
Key matrix scan
541_32KX1
ENV1
IOPB0/URXD
IOPB1/UTXD
IOPB2/USCLK
IOPB3/SCL1
IOPB4/SDA1
IOPB7/RING/PFAIL
PORT-B
JTAG debug port
C271
0.1U
SHBM=1: Enable shared memory with host BIOS
IOPA0/PWM0
IOPA1/PWM1
IOPA2/PWM2
IOPA3/PWM3
IOPA4/PWM4
IOPA5/PWM5
IOPA6/PWM6
IOPA7/PWM7
PWM or
PORT-A
PORT-E
C270
0.1U
Should have a 0.1uF capacitor close to every

GND-VCC pair + one larger cap on the
supply.
DA0
DA1
DA2
DA3
32.768KHZ
1
2
R223
DA output
KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15
16,19
C269
0.1U
RESERVE FOR 87541
AD0
AD1
AD2
AD3
IOPE0AD4
IOPE1/AD5
IOPE2/AD6
IOPE3/AD7
DP/AD8
DN/AD9
AD Input
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MSCLK1
MSDAT1
KBCLK
KBDAT
TPCLK
TPDATA
CAPSLED
NUMLED
95
34
45
123
136
157
166
SERIRQ
LDRQ
LFRAME
LAD0
LAD1
LAD2
LAD3
LCLK
LREST
SMI
PWUREQ
31
71
72
73
74
77
78
79
80
T70
T68
T74
T75
+5V
R197
R203
RN1
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
SERIRQ
LDRQ#
LFRAME#
LAD0
LAD1
LAD2
LAD3
PCLK_541
541RESET#
SMI#541
1
RB500
T79
VCCRTC
C254
0.1U
18,21,35 SERIRQ
U7
LDRQ#
*0
VBAT
*0
R222
AVCC
LDRQ#0
R209
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
16
LDRQ#0
VDD
10U/10V
16
LDRQ#(pin 8) internal is no use
C220
C253
0.1U
C222
0.1U
0.1U
C214
161 VBAT_951
+3V
KBC-NS87541L
VCCRTC
3VPCU
Rev
1A
KBC PCU-87541L; LPC CONN
Sheet
1
30
of
42
KEYBOARD CONNECTOR
24
KEYBOARD
TOUCH PAD CONNECTOR

25 mils
5VSUS
L41
BK1608HS800-T
5VSUS_TP C491
0.1U
B Stage:
Change to P-TWO DFFC12FR234
CN6
30
TPDATA
30
TPCLK
L42
L43
SBK160808T-221
12
11
10
9
8
7
6
5
4
3
2
1
TPDATA-1
TPCLK-1
SBK160808T-221
C492
*10P
C493
*10P
29
TP_L#
29
TP_R#
MY15
MY14
MY13
MY12
MY11
MY10
MY9
MY7
MY6
MX0
MX1
MX2
MX3
MY8
MY3
MY5
MX4
MX5
MX6
MX7
MY2
MY4
MY1
MY0
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
12
UP CONTACT
30
30
30
30
30
30
30
30
30
29,30
29,30
29,30
29,30
30
30
30
29,30
30
30
30
30
30
30
29,30
UP CONTACT
3VPCU
A
RP35
10
9
8
7
6
MY4
MY5
MY6
MY7
MY3
MY2
MY1
MY0
1
2
3
4
5
MY15
MY14
MY13
MY12
10KX8
RP34
MY8
MY9
MY10
MY11
10
9
8
7
6
10KX8
CN5
88241-1201
1
2
3
4
5
P-TWO
DFHS24FR358
BLUETOOTH
3VSUS
3VSUS
CP3
2
4
6
8
220PX4
1
3
5
7
MY11
MY10
MY9
MY7
CP2
2
4
6
8
220PX4
1
3
5
7
MX3
MY8
MY3
MY5
CP4
2
4
6
8
220PX4
1
3
5
7
MY2
MY4
MY1
MY0
CP6
2
4
6
8
220PX4
1
3
5
7
MX4
MX5
MX6
MX7
CP5
2
4
6
8
220PX4
1
3
5
7
MY15
MY14
MY13
MY12
CP1
2
4
6
8
220PX4
1
3
5
7
R454
4.7K
MY6
MX0
MX1
MX2
Q24
IRLML5103
Q22
DTC144EUA
BTV
USBP5+
USBP5-
BT_ON#
C525
10U/10V
C522
0.1U
BLUELED
USBP5+
USBP5-
17
17
FAN CONTROL
BLUELED 34
CN30
R470 *0
1
2
3
4
5
6
7
8
Support Wireless 2200

Pin6: Ch_Data(BC0EX1)
Pin7: Ch_Clk(BC0EX2)
R471 *0
USBP5+
USBP5BLUELED
BBC0EX1
BBC0EX2
R386
2
5
1A
2A
1
7
1OE#
2OE#
1B
2B
3
6
VCC
GND
8
4
T203
BC0EX1
BC0EX2
BC0EX1
BC0EX2
34
34
CN16
FAN_PWR1
+5V
30
1
2
3
4
PWM_FAN
5VSUS
Bluetooth 8P
C459
10U/10V
C453
0.1U
+3V
FAN
R381
10K
5VSUS
U32
FSTD3306MTCX_NL
FANSIG
VFAN_1
R459
10K
C454
0.1U
3
+3V
R458
10K
BT_ON#
BT_ON#
1
D23
2
1SS355
Q23
2N7002E
PROJECT : DW1
30
Size
Document Number
Custom
Date:
1
30
C448
100P

7
Rev
1A
BLUETOOTH/TP/KEY/BTB
Sheet
31
8
of
42
F1
2
+5V
FUSE1A6V_POLY
35 JVGA_R
Route to DVI-I first and then route to D-SUB15
35 JVGA_G
*0
R416
*0
R419
*0
RB501H
C489
0.1U
CRT PORT
16
35 JVGA_B
R421
CRT_R
CRT_G
CRT_B
CRT_R
L40
39nH
CRT_R1
L39
110nH
CRT_R2
CRT_G
L35
39nH
CRT_G1
L34
110nH
CRT_G2
CRT_B
L38
39nH
CRT_B1
L37
110nH
CRT_B2
R417
150/F
R423
150/F
C482
18P
C480
18P
6
1
7
2
8
3
9
4
10
5
T230
C488
18P
CN23
*CRT_CONN
Need to change footprint.

T225
11
DDCDAT2
12
13
CRT_HSYNC
14
CRT_VSYNC
15
DDCCLK2
17
R420
150/F
5V_CRT
D22
1
C496
*10P
C495
*10P
C497
*10P
C235
*10P
For EMI
5V_CRT
+3V
ESD PROTECTION
C494
0.1U
C236
0.1U
U6
1
2
3
4
5
6
7
8
VCC_SYNC
VCC_VIDEO
VIDEO_1
VIDEO_2
VIDEO_3
GND
VCC_DDC
BYP
SYNC_OUT2
SYNC_IN2
SYNC_OUT1
SYNC_IN1
DDC_OUT2
DDC_IN2
DDC_IN1
DDC_OUT1
16
15
14
13
12
11
10
9
HSYNC_R
HSYNC
VSYNC_R
VSYNC
DDCCLK1
DDCCLK
DDCDAT
DDCDAT1
R430
R428
39
39
CRT_HSYNC
HSYNC
VSYNC
R429
0 DDCCLK2
DDCCLK
DDCDAT
9
9
R168
0 DDCDAT2
35
CRT_VSYNC 35
CM2009
DDCCLK2 35
C224
0.22U
R425
2.2K
R426
2.2K
R156
2.2K
+3V
R427
2.2K
DDCDAT2 35
+5V
PROJECT : DW1
Size
B
Document Number
Date:
Rev
1A
CRT, DVI-I
Sheet
1
32
of
42
CD-ROM
PLTRST#
R403
16
PDA[0..2]
16
PDD[0..15]
16
16
16
16
16
16
16
16
PDIOW#
PDDREQ
PDIORDY
PDIOR#
IRQ14
PDDACK#
PDCS1#
PDCS3#
47
IDERST#
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0
IDERST#
PDA[0..2]
PDD[0..15]
PDIOW#
PDDREQ
PDIORDY
PDIOR#
IRQ14
PDDACK#
PDCS1#
PDCS3#
PDIOW#
PDIORDY
IRQ14
PDA1
PDA0
PDCS1#
CDVCC
CSEL
C
R418
470
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
B stage:
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDDREQ
PDIOR#
PDDACK#
IOCS16#
DIAG#
PDA2
PDCS3#
T39
T43
CDVCC
60 mils
L36
PBY201209T-4A
+5V
CDVCC
C479
0.1U
C481
0.1U
C477
0.1U
C476
0.1U
C474
10U/10V
C
51
52
13,17,18,27,34,35 PLTRST#
51
52
CN21
CD-ROM
SATA CONNECTOR
CN27
GND1
TXP
TXN
GND2
RXN
RXP
GND3
22
21
20
19
18
17
16
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
RSVD
GND
12V
12V
12V
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SATA_TXP0 16
SATA_TXN0 16
SATA_RXN0 16
SATA_RXP0 16
+3VSATA
+3V
HDD_VDD
HDD_VDD
R245
+5V
T117
T121
T120
T124
4.7U/10V
HDD_VDD
C291
C288
C16659-12204-L
0.1U
C286
+3VSATA
4.7U/10V
B stage:
Change CN27 net.
R234
C295
C298
22U
0.1U
PROJECT : DW1
Size
Document Number
Custom
Date:
5
Rev
1A
SATA HDD, CD-ROM
Sheet
1
33
of
42
+3V
Mini PCI-E Card

3VSUS
+3V
+3V
+1.5V
+3V
+1.5V
3VSUS
R522
R230
CN25
C268
0.1U
C276
10U/10V
C274
C275
0.01U/50V 0.1U
C265
10U/10V
17
17
17
17
4
PCIE_TXP0
PCIE_TXN0
R437
R436
PCIE_RXP0
PCIE_RXN0
PCIE_RXP0_C
PCIE_RXN0_C
0
0
R435
PCLK_DBP
3VSUS
4 CLK_PCIE_MINI
4 CLK_PCIE_MINI#
CLK_MINI_OE#
CCI_DATA
CCI_CLK
T80
18,27 PCIE_WAKE#
RF LED control.
1
Q13
DTC144EUA
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
Reserved
Reserved
15
13
11
9
7
5
3
1
GND
REFCLK+
REFCLKGND
CLKREQ#
Reserved
Reserved
WAKE#
+3.3V
GND
+1.5V
LED_WPAN#
LED_WLAN#
LED_WWAN#
GND
USB_D+
USB_DGND
SMB_DATA
SMB_CLK
+1.5V
GND
+3.3Vaux
PERST#
Reserved
GND
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
Reserved
Reserved
Reserved
Reserved
Reserved
+1.5V
GND
+3.3V
16
14
12
10
8
6
4
2
USBP6+
USBP6-
R228
D10
LAD0_1
LAD1_1
LAD2_1
LAD3_1
PLTRST# 13,17,18,27,33,35
RF_ON# 30
LAD1_1 RP56
1
LAD0_1
3
LAD3_1 RP55
1
LAD2_1
3
R219
2 0X2
4
2 0X2
4
0
LAD1
LAD0
LAD3
LAD2
LFRAME#
LAD1
16,30,35
LAD0
16,30,35
LAD3
16,30,35
LAD2
16,30,35
LFRAME# 16,30,35
LPC Debug
R434
R431
*0
BC0EX1
R432
R433
31
C
*0
BC0EX2
31
RF_LED# 29
NEWCARD (PCIEXPRESS*1 + USB*1)
3V_NEWCARD
3VAUX
1.5V_NEWCARD
DTC144EUA
1
DTC144EUA
+3V
1 RB500
Q15
10K
2
+3V
CCI_CLK
BLUELED 2
RF_LINK
CGDAT_SMB 4,14,15
CGCLK_SMB 4,14,15
#8,#10,#12,#14,#16,#19 For Debug port use
Q14
17
17
T53
CCI_DATA
RF_LINK
Q31
IRLML5103
T81
67910-0002
RF_LED#
BLUELED
0
RF_LINK#
R231
67910-0002
BLUELED
31 BLUELED
10K
10K
1
C273
1U/10V
C272
0.1U
R255
C380
0.1U
C373
0.1U
C370
0.1U
C368
0.1U
C374
0.1U
C378
0.1U
L17
17
17
1
4
USBP7+
USBP7-
USBP7+1
USBP7-1
2
3
+3V
*WCM2012-90
R246 COM-CHOKE-WCM2012-4P
0
Internal Pull-High to 3VAUX

CPUSB#
R344
*10K
CPPE#
R345
*10K
2231_SHDN#
R324
*10K
2231_STBY#
R329
*10K
3V_NEWCARD
CN8
1.5V_NEWCARD
PCIE_WAKE#
3VAUX
CLK_NEW_OE#
CPPE#
CLK_PCIE_NEW_C#
CLK_PCIE_NEW_C
T125
4 CLK_PCIE_NEW#
4 CLK_PCIE_NEW
17 PCIE_RXN1
17 PCIE_RXP1
17
17
R308
R313
PERST#
0
0
PCIE_RXN1_C
PCIE_RXP1_C
PCIE_TXN1
PCIE_TXP1
GND_1
USBUSB+
CPUSB#
RSV_0
RSV_1
SMBCLK
SMBDATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V_1
+3.3V_2
CLKREQ#
CPPE#
REFCLKREFCLK+
GND_2
PERn0
PERp0
GND_3
PETn0
PETp0
GND_4
Tyco 1759011-1
U18
2231_STBY#
3V_S5
3VAUX
T145
T148
1
17
15
PLTRST#
6
CPPE#
10
CPUSB#
9
PERST#
8
2231_SHDN# 20
RCLKEN
18
OC#
19
7
STBY#
3.3VIN
AUXIN
3.3VIN
AUXOUT
SYSRST# 1.5VIN
CPPE#
1.5VIN
CPUSB#
PERST# 3.3VOUT
SHDN# 3.3VOUT
RCLKEN
1.5VOUT
OC#
1.5VOUT
GND
12
14
+1.5V
3
5
3V_NEWCARD
11
13
1.5V_NEWCARD
PROJECT : DW1
Date:
+3V
R5538
Size
Document Number
Custom
2
4
NC1
NC2
PCLK_SMB
PDAT_SMB
4,18,27 PCLK_SMB
4,18,27 PDAT_SMB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
USBP7-1
USBP7+1
CPUSB#
Rev
1A
NEW CARD, MINI CARD
Sheet
E
34
of
42
B stage:
CN12
Change to 4 pins connector. wait

for ME to confirm connector.
B stage:
Change U10 footprint.
TPM (1.2)
+3V
PCLK_TPM
LAD0
LAD1
LAD2
LAD3
PCLK_TPM
16,30,34
LAD0
16,30,34
LAD1
16,30,34
LAD2
16,30,34
LAD3
4
PCLK_TPM
R204
*33
D
LFRAME#
PLTRST#
SUS_STAT#
SERIRQ
16,30,34 LFRAME#
13,17,18,27,33,34 PLTRST#
18 SUS_STAT#
18,21,30 SERIRQ
C251
*10P
U10
26
23
20
17
21
LAD0
LAD1
LAD2
LAD3
LCLK
22
16
28
27
LFRAME#
LRESET#
LPCPD#
SERIRQ
9
CLKRUN#
18,21,30 CLKRUN#
FOR EMI
+3V
CLKRUN#
1
3
12
NC
NC
NC
R210
*4.7K
10
19
24
5
GND
GND
GND
GND
4
11
18
25
GPIO
GPIO2
TEST/BADD
15
VDD
VDD
VDD
VSB
PP
TESTI
XTALI/32K IN
XTALO
C255
*0.1U
HIGH
LOW
TV-CD
C259
*0.1U
S-YD
C243
*0.1U
R374
150/F
C430
5.6P
S-YD
L24
SBK201209T-151Y-S
C1
5.6P
C431
5.6P
R189
*4.7K
TVGND
2
TVGND
7
8
*0
*0
TVGND
S-VIDEO
TVGND
R195
R201
C432
5.6P
R375
150/F
TVGND TVGND
TVGND
+3V
R180
*4.7K
TPM_XIN
TPM_XOUT
R193
*4.7K
R373
Y3
*32.768KHZ
1
2
C263
*12P
C261
*12P
TVGND
(default)
+2.5V
+2.5V
D3
C
D5
3 S-CD
3 S-YD
C
2
*DA204U
+5V
TV-YD
L2
SBK201209T-151Y-S
TVGND
*SLB9635
BADD
4EH/4F
2EH/2FH
S-CD
Address
R205
*4.7K
C249
*0.1U
R174
*4.7K
6
2
13
14
S-CD
+3V
*DA204U
+5V
R111
*8.2K
DVI-I Port
R115
*8.2K
CN22
TMDS_TX232
DDCCLK2
32
DDCDAT2
13
DVI_DAT
13
DVI_CLK
R116
DVI_CLK1
R120
DVI_DAT1
R118
R112
DVI_DAT1
TMDS_TX1-
TMDS_TX0-
Don't need to PH due to DDCCCLK2 and

DDCDAT2 already pull up to 5V.
1
3
5
7
9
11
13
15
17
19
21
23
TMDS_CLK+
32
32
CRT_HSYNC
32
CRT_VSYNC
13 CH_TMDS_TX2-
R110
39
JVGA_HS
R139
39
JVGA_VS
CH_TMDS_TX2-
R152
TMDS_TX2-
CH_TMDS_TX2+
R157
TMDS_TX2+
CH_TMDS_TX1-
R150
TMDS_TX1-
CH_TMDS_TX1+
R151
TMDS_TX1+
CH_TMDS_TX0-
R148
TMDS_TX0-
JVGA_G
TMDS2GND2
TMDS4+
DDC_DAT
TMDS1GND3
TMDS3+
GND
TMDS0GND5
TMDS5+
TMDS_CLK+
26
28
C2
C4
C6
JVGA_G
JVGA_HS
B stage:
Change to 39 ohm to match impedance.
TMDS2+
TMDS4DDC_CLK
VSYNC
TMDS1+
TMDS3VCC5
HP_Detect
TMDS0+
TMDS5GNDC
TMDS_CLK-
2
4
6
8
10
12
14
16
18
20
22
24
25
27
RED
BLUE
GNDA
25
27
C1
C3
C5
26
28
GREEN
HSYNC
C6
+5V
DVI_CLK1
JVGA_VS
TMDS_TX1+
DVI_DET
TMDS_TX0+
C206
0.1U
+5V
TMDS_CLK-
JVGA_R
JVGA_B
JVGA_R
JVGA_B
32
32
DVI_070939FR029SX01PU
+3V
13 CH_TMDS_TX2+
TMDS_TX2+
+3V
DVI DETECT
R126
1K
R136
1K
13 CH_TMDS_CLK13 CH_TMDS_CLK+
R147
TMDS_TX0+
DVI_DET
R133
TMDS_CLK-
CH_TMDS_CLK+ R134
TMDS_CLK+
CH_TMDS_CLK-
Q7
MMBT3904
CH_TMDS_TX0+
R121
10K
13 CH_TMDS_TX0+
2
2
Q6
MMBT3904
1
CH_DVI_DETECT 13
13 CH_TMDS_TX0-
PROJECT : DW1
Size
Document Number
Custom
Date:
Rev
1A
TPM
Sheet
1
35
of
42
+PWR_SRC
SMDDR_VTERM
+2.5V
+5V
+1.5V
+3V
15V
PR43
22C
PR176
1M
PR168
22C
PR167
22C
PR41
22C
PR46
22C
PR171
1M
MAINON_G
MAIND
MAIND
38
Z2707
Z2706
PC147
2200P
PQ45
2N7002E-G
PQ40
2N7002E-G
PQ41
2N7002E-G
PQ44
DTC144EUA
1
Z2705
PR175
1M
30,39,40 MAINON
Z2704
Z2725
PQ1
2N7002E-G
PQ2
2N7002E-G
PQ49
2N7002E-G
3V_S5
72mA
modify from 2N7002E TO 2M7002E-G

+PWR_SRC
3V_S5
15V
S0-S5
3VPCU
PR148
22C
PR151
1M
1
2
5
6
PR146
1M
S5_OND
S5_ONG
B
3
30
S5_ON 2
S5_ON
PQ31
SI3456DV
Z2712
PR145
1M
PC123
2200P
PC124
0.01U
1.8VSUS
3VSUS
5VSUS
15V
+PWR_SRC
PQ28
DTC144EUA
3V_S5
PQ29
2N7002E-G
PR147
1M
PR227
22C
PR152
22C
PR153
22C
PR149
1M
38
SUSD
Z2710
SUSON 2
SUSON
PC125
2200P
PQ30
DTC144EUA
1
30,40
SUSD
SUSON_G
Z2709
PQ32
2N7002E-G
PR150
1M
PQ59
2N7002E-G
PQ34
2N7002E-G
PQ35
2N7002E-G
PQ33
2N7002E-G
3VPCU
VCC_CORE
+1.05V
+PWR_SRC
LANVCC
50mils
15V
1
2
5
6
+PWR_SRC
LAN_ON
PR86
22C
PR84
22C
PR79
22C
PR80
1M
LAN_POWER_G
3
Z2713
Z2722
Z2721
LANVCC
LAN_ON
Z2720
LANVCC
PQ9
SI3456DV
PR76
1M
4
PR87
1M
PR85
1M
30 LAN_POWER
PC43
0.1U
PC41
2200P
2
2
PQ13
2N7002E-G
1
PQ11
2N7002E-G
PQ14
2N7002E-G
PROJECT : DW1
PQ8
2N7002E-G
Size
Document Number
Custom
Date:
PQ10
DTC144EUA
1
PQ12
DTC144EUA
VRON
30,41
PR81
1M
Rev
1A
DISCHARGE
Sheet
5
36
of
42
PD14 AND PD15 MODIFY FROM SSM24PT TO SBM1040
Iinput =(V CLS / V REF)*(0.075/ RS1)
+
PC29
10U/25V
0.1U_50V
PC27
0.1U_50V
2
8724_3D3_LDO
VA
5
6
7
8
PR57 100K
CELL-SET
PC25
1000P/50V
ACIN
PR77
15K_6
VA2
23
8724LX
11
ACOK
DLO
21
8724DL
9
28
8
ICHG
IINP
SHDN
PGND
20
CSIP
CSIN
19
18
CCV
CCI
BATT
CCS
REF
CLS
PC37
0.01U_50V
1
2
1
2
3
4
2
2
1
LX
29
PC38
0.01U_50V
REFIN
8
7
6
5
PC31
0.1U_50V
1 D1
G1 8
2 D1
S1/D2 7
3 G2
4 S2
10uH 30% 4.4A(SIL104R-100PF)L-F

PR71
0.015
PL10
8724LXR
1
V_CHG
PQ47 SI4914DY-T1-E3
5VPCU
R1
PR74
13.3K_6
R2
3VPCU
PC36
1U_10V_0603
1
3
3VPCU
PR173
100K/F
P331
MBAT_V
PR39
330
30
BCLK
5,30
PROJECT : DW1
Size
Document Number
Custom
Date:
30
PQ4
2N7002E-G
PD2
ZD5.6V
MODIFY FROM 2N7002E TO 2M7002E-G

1
BL/C#
PD1
ZD5.6V
P332
PR47
100K
1
PC158
0.1U_50V
BCLK
30
MODIFY FROM 2N7002E TO 2M7002E-G
PR174
14K/F
BDATA
D/C#
PR51
332K/F
4
PU2
LMV331
PR38
330
D/C#
PQ3
2N7002E-G
PC151
0.1U_50V
G2
BDATA
PR50
475K/F
TEMP_MBAT 30
PD3
SW1010
2
5
4
3
2
1
PR45
100K
2
300mil
I2C_CLK
I2C_DATA
TEMP
GND1
GND2
V_CHG
7
6
PR40
10K
PL11
3216-800T40
G1
G2
ACOK-2
PWR1
PWR2
5,30
PQ5
2N7002K
3VPCU
CN15
1827654-1
2
PD4
RB500
20,36,38,39,40,41 +PWR_SRC
G1
PR54
100K
16,19,20,29,30,31,36,38,39,40 3VPCU
+PWR_SRC
3VPCU
PC146
10U/25V
16,19,29,30,38,39,40 5VPCU
PR68
20K/B_6
PR66
*0
+
PC145
10U/25V
ICHG =(V ICTL / V REFIN)*(0.075/ RS2)
PR69
20K/B_6
ACOK
1M_6
PC148
0.1U_50V
CSIP
CSIN
16 V_CHG
PU3
MAX8724
5V_AL
1U_8
12
GND
PD6
SW1010C
PC39
0.1U_50V
PR73
2N7002K
PR67
100K
ACOK#
PQ7
8724DH
ICTL
VAD-5
25
VCTL
13
PR72
1K_6
PC35
DHI
15
30
ACOK#
PR75
10K
PC30
PC26
1000P/50V 0.1U_50V
24
CC_SET
30
BST
PR44
100K/F
8724LDO
8724_3D3_LDO
PQ46
PD5
SW1010C
1P
PR172
200K/F_6
SI4835BDY-T1-E3
DLOV
ACIN
PQ6
2N7002E
PC28
1U_10V_0603
8724DLOV
PR62
8724BST
22
GND
28724LDO
14
ACOK
10
PC21
0.1U_50V
CELL_SET 30
Q3
DTA124EU
2 CELL_SET
LDO
17
PC34
1U_8
CELLS
1.33K_6
+PWR_SRC
1 = 3 CELL
DCIN
33_6
PR60
PC24
1U_10V_0603
CSSP
CSSN
PC157
0.01U_50V
27
26
PR56
0 = 4 CELL
PR59
0
PR64
10K
SI4835BDY-T1-E3
8724_3D3_LDO
PR61 825_6
0.1U
PR58
100K
PD9
RB500
PR63
75K_6
PQ48
PC23
PC22
1U_8
For ESD Proection

VA
10K/F
3
PL8
FBJ3216HS480NT_1206
Q1
DTA124EU
PC221
PC220
0.1U_50V
PR52
300mil
4
3
2
1
1P
1
PC132
+ 10U/25V
PC134
0.1U
PR154
0
+PWR_SRC
PL1
FBJ3216HS480NT_1206
R3
1
PC126
0.1U
POWER_JACK
3
2
PR1
10K
PC133
0.01U
2P
CN13
PR65
RL3720WT-R010-GN(CYNTEC)
1
2VA2
2P
PL9
FBJ3216HS480NT_1206
VA2
VA1
PD24
SBM1040
1
VA
1
2
3
4
5
A2 TEST TO B TEST
Rev
1A
CHARGE
Sheet
5
37
of
42
DC-DC(MAX8734A)
Need create L-F

Part number.
PC63
1000P/50V
PR112
3VPCU
+PWR_SRC
PL2
10
0805/5A
PGOOD
LX3
27
ON3
DH3
26
ON5
LDO3
25
ILIM3
DL3
24
SHDN-
GND
23
FB3
OUT3
22
REF
OUT5
21
3
2
1
5
6
7
8
LX3
DH3
PQ22
RSS090N03
18
VCC
17
PR139 *0
13
TON
DH5
16
LX5
15
PR137
0
14
8
DH5
BST5
LX5
MAX8734A
PR131
EC10QS04
PC222
+ PC98
0.1U/50V
220U/6.3V/25m
PC223 PC115
0.1U/50V 0.1U/50V
6A
3VSUS
PC119
+3V
PC109
0.1U_50V
1
2
BST5
2
PR138
0
PD8
PQ18
RSS090N03
LDO5
SKIP-
PQ26
SI4804BDY-T1-E3
5VPCU
ILIM5
12
PL6
PC60
10U/25V
2.5UH_7.5A/SIL-104R-2R5PF L-F
11
1000P/50V
5V_AL
PC58
DL5
19
2 PR144
*0
REF2V_1999
PR125
0
1
20
DL5
FB5
8734ILIM5
100K
PR141
0
V+
PRO-
10
FB5 9
PR136
FB3
5
6
7
8
FB5
PC114
0.1U/50V
5
6
7
8
1U PC122
1 REF2V_8734 8
3VPCU
PR123
*2.7R
0.1U/50V
PC234
0.1U/50V
PC235
0.1U/50V
PC224 PC225 PC108

0.1U/50V 0.1U/50V 0.1U/50V
PR142
*15K
5A
3
2
1
FB3 7
PR130
*6.49K
PD17
EC10QS04
PC97
220U/4V/25m
PC79
0.1U/50V
PC100
*0.01U
DL3
8734ILIM3
BST3
3VPCU
2.5UH_7.5A/SIL-104R-2R5PF L-F
PR117
*2.7R
0 BST3
5V_AL
3VPCU
N.C
PL5
3
2
1
5VPCU
2 PC104
0.1U_50V
PU7
28 PR122
2
1
30,39,40,41 HWPG
PR134
100K
PC57
10U/25V
0.01U
PQ17
RSS090N03
3V_AL
PC96
4.7U/10V
2
1
2
1
PR111
100K
PC89
4.7U/25V
PC59
10U/25V
+3V
PC83
*0.1U
PC66
390K
1
PR110
5
6
7
8
D
*10K
R316
SYS_SHDN#
SUSD
VCC
REF2V_8734
PR140
33.2K/F
8734ILIM3
15mil
8734ILIM5
15mil
*0.01U
47
+
PC91
1U
5VPCU
+
PC90
4.7U/10V
PR143
100K/F
PD16
2
PR135
100K/F
PC110
36
MAIND
5V_AL
1
PR133
53.6K/F
PQ24
RSS090N03
3
2
1
PD19
CHP202U
PR116
36
2 PC106
0.01U
5VPCU
10V
CHN217
PC111
0.1U/50V
PC99
1U
MAIND 4
5VPCU
5
6
7
8
1
+
PR120
PD18
SUSD
2 PC105
0.01U
10V
+5V
PQ25
RSS090N03
3
2
1
5
6
7
8
2
PC116
0.1U/50V
15V
PR132
PC118
CHN217
5VSUS
PC117
0.1U_50V
0.1U/16V
PROJECT : DW1
Size
Document Number
Custom
Date:
PC215
PC120
1U
PC121
0.1U/16V
0.1U_50V
3
2
1
PQ36
RSS090N03
PC214
0.1U_50V
Rev
1A
3V/5V
Sheet
1
38
of
42
+PWR_SRC
+PWR_SRC
PL15
FBJ3216HS480NT_1206
PQ23
PR107
22
LX1
27
8743LX1
CS2
DL1
24
8743DL1
15
OUT2
CS1
28
14
FB2
1
2
3
PQ15
AO4422
1.05V/ 8A
PL12
PC72
1.5UH_SIL104R-1R5_10A/8.1 mohm *220U/6.3V_ 25m H=1.9
1
2
PC68
0.1U_50V
ON2
FB1
TON
ILIM2
8743ILIM1 3
ILIM1
PC78
*0.01U
8743REF
REF
10
SKIP
GND
23
PR103
*0
PD11
PC71
*10U/10V
SBM1040-13-F(40V/10A SCHOTTKY)EU
PC155
470U/6.3V_25m H=1.9
PR105
1K/F
Rc
PC51
0.22U/10V
PR89
0
MAINON
8743VCC
PR106
*2.7R
PQ21
FDS6676AS_NL(30V,14.5A)
MAX8743EEI+
UVP
8743ILIM213
PR97
0
ON1
OVP
PR98
0
OUT1
PGOOD
8743FB2
8743AGND
8743FB1
PR102
20K/F
PR101
*0
8743AGND
MAINON
8743AGND
PC61
0.01U
+1.05V
DH2
11
PR94
*0
26
16
AO4422
PR95
20K/F
DH1
8743DH1
18
12
Rb
8743BST1
8743DH2
8743PG
PD7
PC156
PC54
330U/2.5V_25m H=1.9
SBM1040-13-F(40V/10A SCHOTTKY)EU *0.01U
25
LX2
PQ16
PR93
10K/F
BST1
17
EC-A14
Ra
PC76
PC74
10U/10V
0.1U_50V
21
8743LX2
PC62
10U/25V
0.1U_50V
0.1U_50V
PR104
*2.7R
PC55
10U/25V
3
2
1
3.8UH_SIL104R_6A/13mohm
+
DL2
10
VDD
3
2
1
20
1
2
3
PL7
BST2
VCC
8743DL2
PC52
PC56
*10U/10V *220U/6.3V_25m H=1.9
8
7
6
5
PC49
0.1U_50V
PC227
PU5
19
V+
PC73
0.1U_50V
8743BST2
+1.5V
PC67
10U/25V
8743VDD
8743VCC
1.5V/ 8A
PC65
1000P/50V
5
6
7
8
PR99
0
PR113
0
5
6
7
8
AO4422
4
PC226
PL14
FBJ3216HS480NT_1206
8743AGND
3
PC88
1000P/50V
5VPCU
PD13
DAP202UT106
8743VCC
PC87
10U/25V
8
7
6
5
PC86
10U/25V
+PWR_SRC
EC-C?
1U
2
PC77
Rd
8743AGND
8743REF
Vout=(1+Ra/Rb)*1
3VPCU
PR100
0
PJ2 SHORT
PR92
*10K
8743ILIM2
PR90
*10K/F
8743AGND
Vout=(1+Rc/Rd)*1
PR96
2K/F
8743ILIM1
8743AGND
8743PG
PR91
HWPG
HWPG
30,38,40,41
PR88
100K/F
8743AGND
8743AGND
EN_4215
3VPCU
3
4
VIN
GND0
NC1
GND1
+2.5V
PC48
PC45
PC44
10U/6.3V
0.1U_50V
0.1U_50V
A2 TEST TO B TEST MODIFY PC47 CH61001KA94
11,13,35,36
PC236
2.5V
1.1A
PU4
SC4215 L-F
4215FB
PC217
+2.5V
PC47
PC46
0.1U/16V
PC216
0.1U_50V
6
0.1U_50V
VO
0.1U_50V
NC2
0.1U/16V
PC229
EN
10U/6.3V
PC228
NC0
10U/6.3V
ADJ
PC42
*0.1U
PR78
30,36,40 MAINON
8743AGND
R1
PR83
*4.12K/F
PR82
10K/F
A2 TEST TO B TEST
MODIFY PC45 ANDPC48
CH61001KA94
S0
D
R2
PROJECT : DW1
Vo=0.8(R1+R2)/R2
Size
Document Number
Custom
Date:
1
Rev
1A
MAX8743 1.5VS_5/+1.05V/2.5V
Sheet
5
39
of
42
+PWR_SRC
5VPCU
PR179
0_0402
BST
0.1U_50V
1.8V_DH
18
DH
1.8V_LX
19
LX
1.8_DL
21
1
2
53
SHDN
27
SUSON
30,36
STBY
MAINON
30,36,39
13
REFIN
14
PGND2
11
1
1
DL
HWPG
23
PGND1
16
OUT
30,38,39,41
PR182
PC167
0.1U_50V
20/F_0402
PC169
0.1U_50V
1.8VSUS
PC168
10U_6.3V
Design current 1.05A

Peak current 1.5A
POK2
MAX8632ETI+ VTTI
+ PC165
220U/2.5V/ESR15
220U/2.5V/ESR15
17
PQ51
FDS7088SN3
VIN
POK1
20
PR181
1.8V_DH
1.8_DL
0.1U_50V
PR180
100K_0402
1.8V_BST
AVDD
0_0603
IND SMD XFMR 1.5UH+-30% 10A(SIL104R-1R5PF)

PL16
+ PC164
+PWR_SRC
26
22
VDD
OVP/UVP
PC163
PU8
RQW130N03FD5
1.8VSUS
PC166
3VPCU
1U_10V
*0_NC
1
PC162
PR178
PC161
PD21 4.7U_10V
CH501
PQ50
A2 TEST TO B TEST
MODIFY PL16 FROM
3.3UH TO 1.5UH
C
SUSON
A2 TEST TO B TEST
MODIFY HISIDE MOS
RQW130N03FD5 AND
LOWSIDE MOS FDS7088
10_0603
1 8632VDD
2
PR177
2
2
1
10U_25V
1
2
10U_25V
PC160
PC159
PC173
*10U_6.3V_NC
2
1
2
PC172
10U_6.3V
PC174
2
SS
GND
PC171
10U_6.3V
1U_10V
PC176
1000P_50V
1.8V_LIM
0.22U_25V
PC170
0.1U_50V
PC175
2
Freq=300K
SMDDR_VTERM
SMDDR_VREF
PR187
100K/F_0402
PR186
*63.4KF_NC
VTTR
10
REF
ILIM
12
9
24
8632REF
VTT
VTTS
FB
TON
SKIP
25
15
TP0
*0_NC
2
28
PR184
1
0_0402
2
PR185
1
8632VDD
1
2
3
PR183
*100K/F_NC
PR189 0
PR188
110K/F_0402
*0_NC
2
GND_DDR
PR190
8632VDD 1
PR191
0_0402
PROJECT : DW1
Size
Document Number
Custom
Date:
5
Rev
1A
1.8V/0.9V
Sheet
1
40
of
42
+PWR_SRC
PC178
2.2U_10V
8771BST1
+CPU_PWR_SRC
BST1
30
28
8771LX1
29
8771DH1
DL1
26
8771DL1
PGND1
27
8771DH2
DL2
24
8771DL2
LX2
22
8771LX2
BST2
20
BST2_R
PGND2
23
PC209
3
2
1
VCC_CORE
PQ56
RQA180N03FD5
PQ57
RQA180N03FD5
PC210
4
0.22U_25V
1
PC205
330UF_2V_7mohm PC206
*1nF_NC
PR220
2.1K/F
PC207
330UF_2V_7mohm
PC208
0.01U_25V
*330UF_2V_7mohm_NC
PC211
0.1U_10V
PL18
0.45_25A_20%_MPC1040LR45
1
PR219
0_0603
PR221
0_0603
POUT
8771BST2
PR222
3
2
1
2
PR218
10K
5 VR_TT#
PC202
10U_25V
X6S_1206
POUT
PC201
10U_25V
8771CSP2
21
PC200
2200P_50V
14
DH2
PC199
CSP2
PC198
2200P_50V
MAX8771
PC197
0.1U_50V
X6S_1206
PR214
*100_NC
1000P_50V
VRHOT
8771CSN12
15
RQA130N03FD5
CSN12
PQ55
VSSSENSE 6
8/11 change
PC204
8771CSP1
THRM
16
GND
EP
5VSUS
PR217
56
13
CSP1
REF
6
PR216
*NTC 10K_6-B4.25K_NC
GNDS
18
41
PR215 10K/F
1
2
TIME
+CPU_PWR_SRC
0.1U_50V
VCC_CORE
PR213
100_4
20K
8771VCC
8771CSN12
PC233
0.1U_50V
0.22U_10V
1 8771REF 11
2
PC194
470P
71.5K/F
DELAY_VR_PWRGOOD
PC232
0.1U_50V
CCI
CCV
8/11 change
PR207
*100_NC
PR211
10
DPRSLPVR
PR209 0.22U_25V
0
2
1
DPRSTP
39
7
PC203
2
40
PR212
PC193
1000P
8771CSP1
VCCSENSE 6
3.48K/F
2
0
470P
2
PC192
12
SHDN
NTC 10K_6-B4.25K
4.02K/F
PD23
RB751V
Add layout note on pins 22 and 28 of MAX8771

controller. These nets have large voltage swings.
Need to route them away from the sensitive areas that
are trying to detect small changes in voltage, such as
the voltage sense VccSense VssSense lines.
5VSUS
PR223
3
2
1
PC195
100P_50V
FB
PSI
PC196
1
PR201
4.02K/F
PR206
1
PR210
2
18 PM_DPRSLPVR
3
2
1
PR203
3
38
5,16 ICH_DPRSTP#
0
2
PC186
PR200
PR204
100
PR202
1
PSI#
PC189
0.01U_25V
PC188
330UF_2V_7mohm
PC187
330UF_2V_7mohm
*330UF_2V_7mohm_NC
PR198
2.1K/F
3
2
1
PR199 PC191
*3.48K/F_NC *4700P_NC
1
2
30,38,39,40 HWPG
PR208
1
100K/F
2
2
PQ54
RQA180N03FD5
PQ53
RQA180N03FD5
PC190
4
*1nF_NC
PR205
1
D0
D1
D2
D3
D4
D5
D6
1
2
LX1
CLKEN
VCC_CORE
PL17
0.45_25A_20%_MPC1040LR45
2
1
VRON
31
32
33
34
35
36
37
VID0
VID1
VID2
VID3
VID4
VID5
VID6
PC185
10U_25V
X6S_1206
6
6
6
6
6
6
6
PC184
10U_25V
X6S_1206
8771BST1_R
DH1
PWRGD
PC183
2200P_50V
PHASEGD
PC182
0.1U_50V
RQA130N03FD5
2
8
PC181
2200P_50V
0.1U_50V
25
TON
PC180
3
2
1
PQ52
PC179
0.22U_25V
17
PHASEGD
VDD
VCC
PU9
19
PR197
10K
PR196
1.91K/F
PR195
10K
PR193
0_0603
PR194
200K/F
+CPU_PWR_SRC
5VSUS
30,36
PD22
RB751V
PC218 PC219
0.1U_50V 0.1U_50V
1
2
1
PC177
2.2U_10V
8771VCC
PC213
0.1U_10V
PR226
1K
A2 TEST TO B TEST DELETE JUMPER
PR192
10
*0
PR225
5VSUS
PQ58
2N7002E-G
NTC 10K_6-B4.25K
distribute evenly between N side and S

side, preferably on secondary side.
PC212
8771CSP2
Sense lines are 18 mil wide, Z0=27.4 Ohm.

Use differential routing with 7 mil spacing.
Route external layer with solid GND reference
(no split planes).
Use 25 mil separation from any other signal.
2
0.22U_25V
8771CSN12
PR224
2
0
1
PROJECT : DW1
A
Size
C
Document Number
Date:
Rev
1A
max8771
Sheet
41
H
of
42
IMVP Spec. Rev. 0.8

(Nom.)
Yonah-2M
Meron
HFM
1.2875 V
1.1500 V
LFM
0.8375 V
0.8375 V
Deeper
0.7625 V
0.7625 V
VBOOT
1.2000 V
1.2000 V
SLOPE
-2.1 mV/A
-2.1 mV/A
(Max.)
Yonah-2M
CCM : Continuous Conduction Mode

DCM : Dis-Continuous Mode
Active Mode
A
Meron
HFM
36
LFM
9.5 A
12.5 A
Deeper
3.5 A
5.5
27
34.5 A
26
32
44
PSI# : H
DPRSTP# : H
DPRSLPVR : L
FCCM : H
Dynamic
TDC
Active Mode
VID change
up or down
CCM
PSI# : H
DPRSTP# : H
DPRSLPVR : L
FCCM : H
CCM
A
Mode change
Vo
VID6 VID5 VID4 VID3 VID2 VID1 VID0
---------------------------------------------1.5000
0
0
0
0
0
0
0
---------------------------------------------1.4375
0
0
0
0
1
0
1
---------------------------------------------1.4000
0
0
0
1
0
0
0
---------------------------------------------1.3000
0
0
1
0
0
0
0
---------------------------------------------1.2875
0
0
1
0
0
0
1
---------------------------------------------1.2000
0
0
1
1
0
0
0
---------------------------------------------1.1500
0
0
1
1
1
0
0
---------------------------------------------1.1000
0
1
0
0
0
0
0
---------------------------------------------1.0000
0
1
0
1
0
0
0
---------------------------------------------0.9625
0
1
0
1
0
1
1
---------------------------------------------0.9000
0
1
1
0
0
0
0
---------------------------------------------0.8375
0
1
1
0
1
0
1
---------------------------------------------0.8000
0
1
1
1
0
0
0
---------------------------------------------0.7625
0
1
1
1
0
1
1
---------------------------------------------0.7500
0
1
1
1
1
0
0
---------------------------------------------0.7000
1
0
0
0
0
0
0
---------------------------------------------0.6000
1
0
0
1
0
0
0
---------------------------------------------0.5000
1
0
1
0
0
0
0
---------------------------------------------0.3000
1
1
0
0
0
0
0
----------------------------------------------
Deeper Sleep
Mode
PSI# : L
DPRSTP# : L
DPRSLPVR : H
FCCM : L
Mode change
with
VID change
up
DCM
Active Mode
PSI# : H
DPRSTP# : H
DPRSLPVR : L
FCCM : H
CCM
Mode change
without VID change
or
with VID change
down
Active Mode
PSI# : H
DPRSTP# : H
DPRSLPVR : L
FCCM : L
DCM
A
PROJECT : DW1
5
Size
C
Document Number
Date:
Rev
1A
CPU_Operation State
Sheet
1
42
of
42

Yonah / Calistoga / ICH7-M

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1

DW1 BLOCK DIAGRAM

SYSTEM POWER MAX8743

CPU CORE MAX8771

DDRII 533,667 MHz

USB PORT 4,5,6,7

SYSTEM POWER MAX8632

INTEGRADED VGA FUNCTION

USB PORT 0,1,2,3

DDRII 533,667 MHz

33MHZ, 3.3V PCI

CARDREADER / IEEE 1394

Tuesday, November 29, 2005

Schematic Block Diagram

System Power Block Diagram

Intel Yonah CPU

CARD Reader/USB Port

LCD CONNECTOR / LCD PWR

S0, S3, S4, S5

S0, S3, S4, S5

MAIN BATTERY + (10~17V)

S0, S3, S4, S5

RTC & KBC POWER

S0, S3, S4, S5

CPU CORE POWER (1.25/1.15V)

FSB POWER (1.05V)

S0, S3, S4, S5

S0, S3, S4, S5

AUDIO CODEC / AUDIO JACK

S0, S3, S4, S5

Bluetooth/Touch Pad/Key board

SATA HDD / CD-ROM

NEW CARD/MINI CARD

CPU Operation State

S0, S3, S4, S5

ALWAYS POWER (5V)

S0, S3, S4, S5

DDR CORE POWER

DDR COMMAND & CONTROL PULL UP POWER

DDR REF POWER

AUDIO ANALOG POWER (5V)

PCI DEVICES IRQ ROUTING

Power & Ground

IDSEL # REQ/GNT # PCI_INT

AUDIO JACK GND

CPU ANALOG GROUND

CPU THERMAL SENSOR

Tuesday, November 29, 2005

SYSTEM POWER BLOCK DIAGRAM

Tuesday, November 29, 2005

System Power block diagram

Place these termination to close CK410M.

To check intel reference circuit default setting.

PCLK_5C832 C225 *10P

FSB frequency will be selected by CPU internal.

DREFSSCLK Frequency Select.

CLKUSB_48 C245 *10P

SMbus address D2 /IDT

Place these termination to close CK410M.

FSC FSB FSA

Tuesday, November 29, 2005

Near to MCH <500mils

Layout note: 0.5" max