CLK-DOWN-TESTBENCH:

Note: Here we assume that b=4.

POST-ROUTE-SIMULATION:
CLK-DOWN-VHDL CODE:
//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clk_div_with_50per_duty_cycle is
Port ( clk,rst : in STD_LOGIC;
clk_div : out STD_LOGIC);
end clk_div_with_50per_duty_cycle;

architecture Behavioral of clk_div_with_50per_duty_cycle is

signal clk_out:STD_LOGIC;
signal q:STD_LOGIC:='0';
signal qbar:STD_LOGIC:='1';

begin
process(clk)
variable a,b,c:integer;
begin
if clk ='1' and clk'event then
a:=a+1;b:=33554432;c:=a rem b;
if c =0 then clk_out<='1';
else clk_out<='0';
end if;
end if;
end process;
process(clk_out,rst)
variable t:STD_LOGIC:='1';
variable d:STD_LOGIC:='0';
begin
if rst='1' then q<='0';qbar<='1';
else
if clk_out ='1' and clk_out'event then
d:=t xor q;q<=d;qbar<=not d;
clk_div<=d;
end if;
end if;
end process;

end Behavioral;

//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.

Design Statistics:

//----------------------------------------------------------------------------------//
Minimum period: 14.330ns (Maximum Frequency: 69.785MHz)
Minimum input arrival time before clock: 3.144ns
Maximum output required time after clock: 6.216ns
Maximum combinational path delay: No path found
//----------------------------------------------------------------------------------//
Implementation User constrain file using Spartan-3 FPGA kit
//----------------------------------------------------------------------------------//
INPUT = "clk" LOC = "T9";
INPUT = "rst" LOC = "g12";
INPUT = "rst" LOC = "h14";
OUTPUT = "clk_div" LOC = "k12";
//----------------------------------------------------------------------------------//

Conclusion: “clk_div” is connected to led of spartan3 FPGA kit. It will blink(On/Off) ,we can visualase it.
Hence we can conclude that the program is ok.
T-FLIP-FLOP-TESTBENCH:

POST-ROUTE-SIMULATION:

CIRCUIT-DIAGRAM-OF-T-FLIP-FLOP:
T-FLIP-FLOP-VHDL CODE:
//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity T_FF is
Port ( t,clk,rst : in STD_LOGIC;
q,qbar : out STD_LOGIC);
end T_FF;

architecture Behavioral of T_FF is

signal qx,qbarx:STD_LOGIC;

begin
process(t,clk,rst)
variable d:STD_LOGIC:='0';
begin
if rst='1' then qx<='0';qbarx<='1';
else
if clk ='0' and clk'event then
d:=t xor qx;qx<=d;qbarx<=not d;
end if;
end if;
q<=qx;qbar<=qbarx;
end process;
end Behavioral;
//----------------------------------------------------------------------------------//
NOTE: Our Spartan3 FPGA kit has clk frequency of 50 MHz. To verify our T flip-Flop we have to
integrate the clk down circuit of 1 Mz.
//----------------------------------------------------------------------------------//
T-FLIP-FLOP-VHDL CODE MODIFIED:
//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity T_FF_with_clk_down is
Port ( t,clk,rst : in STD_LOGIC;
q,qbar : out STD_LOGIC);
end T_FF_with_clk_down;

architecture Behavioral of T_FF_with_clk_down is

signal clk_divx:STD_LOGIC;

component T_FF is
Port ( t,clk,rst : in STD_LOGIC;
q,qbar : out STD_LOGIC);
end component;

component clk_div_with_50per_duty_cycle is
Port ( clk,rst : in STD_LOGIC;
clk_div : out STD_LOGIC);
end component;

begin
L1: clk_div_with_50per_duty_cycle port map(clk,rst,clk_divx);
L2: T_FF port map(t,clk_divx,rst,q,qbar);

end Behavioral;

//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.

Design Statistics:

//----------------------------------------------------------------------------------//
Minimum period: 14.330ns (Maximum Frequency: 69.785MHz)
Minimum input arrival time before clock: 3.178ns
Maximum output required time after clock: 6.306ns
Maximum combinational path delay: No path found

//----------------------------------------------------------------------------------//
Implementation User constrain file using Spartan-3 FPGA kit
//----------------------------------------------------------------------------------//
INPUT = "t" LOC = "f12"; INPUT = "rst" LOC = "g12";
INPUT = "clk" LOC = "h14";
OUTPUT = "q" LOC = "k12";OUTPUT = "qbar" LOC = "p14";
//----------------------------------------------------------------------------------//
Truth table verification:

Truth table of T-FLIP-FLOP Corresponding I/O mapping to LOC

J K q0 q0bar F12 G12 K12 P14
0 0 q0 q0bar Off Off Off(q0=0) On(q0=0)
1 1 q0bar q0 On On On(q0=0) Off(q0=0)

Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC.

Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “T-FLIP-FLOP”.
JK-FLIP-FLOP-TESTBENCH:

POST-ROUTE-SIMULATION:

CIRCUIT-DIAGRAM-OF-JK-FLIP-FLOP:
JK-FLIP-FLOP-VHDL CODE:
//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity JK_FF is
Port ( clk,rst,j,k : in STD_LOGIC;
q,qbar : out STD_LOGIC);
end JK_FF;

architecture Behavioral of JK_FF is

signal jx,kx:STD_LOGIC:='0';

begin
process(clk,j,k,rst)
variable d:STD_LOGIC;
begin
if rst='1' then jx<='0';kx<='1';
else
if clk='1' and clk'event then
d:=(j and (not jx))or ((not k) and jx);
jx<= d;kx<=not d;
end if;
end if;
q<=jx;qbar<=kx;
end process;
end Behavioral;

//----------------------------------------------------------------------------------//
NOTE: Our Spartan3 FPGA kit has clk frequency of 50 MHz. To verify our JK flip-Flop we have to
integrate the clk down circuit of 1 Mz.
//----------------------------------------------------------------------------------//

JK-FLIP-FLOP-VHDL CODE MODIFIED:

//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity jk_ff_with_clk_div is
Port ( j,k,rst,clk : in STD_LOGIC;
q,qbar : out STD_LOGIC);
end jk_ff_with_clk_div;

architecture Behavioral of jk_ff_with_clk_div is

signal clk_divx:STD_LOGIC;

component JK_FF is
Port ( clk,rst,j,k : in STD_LOGIC;
q,qbar : out STD_LOGIC);
end component;
component clk_div_with_50per_duty_cycle is
Port ( clk,rst : in STD_LOGIC;
clk_div : out STD_LOGIC);
end component;

begin
L1:clk_div_with_50per_duty_cycle port map(clk,rst,clk_divx);
L2:JK_FF port map(j,k,rst,clk,q,qbar);

end Behavioral;
//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.

Design Statistics:

//----------------------------------------------------------------------------------//
Minimum period: 2.449ns (Maximum Frequency: 408.330MHz)
Minimum input arrival time before clock: 2.791ns
Maximum output required time after clock: 7.271ns
Maximum combinational path delay: No path found
Maximum practical path delay:4.7ns
//----------------------------------------------------------------------------------//
//----------------------------------------------------------------------------------//
Implementation User constrain file using Spartan-3 FPGA kit
//----------------------------------------------------------------------------------//
INPUT = "J" LOC = "f12"; INPUT = "K" LOC = "g12";
INPUT = "rst" LOC = "h14";INPUT = "clk" LOC = "T9";

OUTPUT = "q" LOC = "k12";OUTPUT = "qbar" LOC = "p14";

//----------------------------------------------------------------------------------//
Truth table verification:

Truth table of JK-FLIP-FLOP Corresponding I/O mapping to LOC

J K q0 q0bar F12 G12 K12 P14
0 0 q0 q0bar Off Off Off(q0=0) On(q0=0)
0 1 0 1 Off On Off On
1 0 1 0 On Off On Off
1 1 q0bar q0 On On On(q0=0) Off(q0=0)

Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC.

Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “JK-FLIP-FLOP”.
DECADE-COUNTER-TESTBENCH:

POST-ROUTE-SIMULATION:

CIRCUIT-DIAGRAM-OF DECADE COUNTER:

DECADE-COUNTER-VHDL CODE:
//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decade_counter is
Port ( clkt: in STD_LOGIC;
q0,q1,q2,q3 : inout STD_LOGIC);
end decade_counter;

architecture Behavioral of decade_counter is

signal q0x,q1x,q2x,q3x:STD_LOGIC:='0';
signal rstx:STD_LOGIC;

component JK_FF is
Port ( clk,rst,j,k : in STD_LOGIC;
q,qbar : out STD_LOGIC);
end component;

component and_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end component;

begin

L1:JK_FF port map(clk,rstx,'1','1',q0,open);

q0x<=q0;
L2:JK_FF port map(q0x,rstx,'1','1',q1,open);
q1x<=q1;
L3:JK_FF port map(q1x,rstx,'1','1',q2,open);
q2x<=q2;
L4:JK_FF port map(q2x,rstx,'1','1',q3,open);
q3x<=q3;
L5: and_gate port map(q1x,q3x,rstx);

end Behavioral;
//----------------------------------------------------------------------------------//
//----------------------------------------------------------------------------------//
NOTE: Our Spartan3 FPGA kit has clk frequency of 50 MHz. To verify our DECADE-COUNTER we
have to integrate the clk down circuit of 1 Mz.
//----------------------------------------------------------------------------------//
DECADE-COUNTER-CIRCUIT DIAGRAM MODIFIED:
DECADE-COUNTER -VHDL CODE MODIFIED:
//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decade_counter_with_clk_down is
Port ( clk : in STD_LOGIC;
q0,q1,q2,q3 : inout STD_LOGIC);
end decade_counter_with_clk_down;

architecture Behavioral of decade_counter_with_clk_down is

signal q0x,q1x,q2x,q3x:STD_LOGIC:='0';
signal rstx,clk_out:STD_LOGIC;

component JK_FF is
Port ( clk,rst,j,k : in STD_LOGIC;
q,qbar : out STD_LOGIC);
end component;

component and_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end component;

component clk_div_with_50per_duty_cycle is
Port ( clk,rst : in STD_LOGIC;
clk_div : out STD_LOGIC);
end component;

begin

L0:clk_div_with_50per_duty_cycle port map(clk,clk_out);

L1:JK_FF port map(clk_out,rstx,'1','1',q0,open);

q0x<=q0;
L2:JK_FF port map(q0x,rstx,'1','1',q1,open);
q1x<=q1;
L3:JK_FF port map(q1x,rstx,'1','1',q2,open);
q2x<=q2;
L4:JK_FF port map(q2x,rstx,'1','1',q3,open);
q3x<=q3;
L5: and_gate port map(q1x,q3x,rstx);

end Behavioral;

//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.
//----------------------------------------------------------------------------------//
//----------------------------------------------------------------------------------//
Design Statistics:

//----------------------------------------------------------------------------------//
Implementation User constrain file using Spartan-3 FPGA kit
//----------------------------------------------------------------------------------//
INPUT = "clk" LOC = "T9
OUTPUT = "q0" LOC = "k12";OUTPUT = "q1" LOC = "p14";
OUTPUT = "q2" LOC = "l12"; OUTPUT = "q3" LOC = "n14";
//----------------------------------------------------------------------------------//
Truth table verification:

Truth table of DECADE-COUNTER Corresponding I/O mapping to LOC

clk q3 q2 q1 q0 T9 N14 L12 P14 K12
1 0 0 0 0 on off off off off
1 0 0 0 1 on off off off on
1 0 0 1 0 on off on on off
1 0 0 1 1 on off on on on
1 0 1 0 0 on on off off off
1 0 1 0 1 on on off off on
1 0 1 1 0 on on on on off
1 0 1 1 1 on on on on on
1 1 0 0 0 on off off off off
1 1 0 0 1 on off off off on

Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC.

Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “decade-counter”.
MOD8-UP-DOWN-COUNTER-TESTBENCH:

POST-ROUTE-SIMULATION:

CIRCUIT-DIAGRAM-OF- MOD8-UP-DOWN-COUNTER:
MOD8-UP-DOWN-COUNTER -VHDL CODE:
//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity up_down_counter is
Port ( sel_up_dn,clk : in STD_LOGIC;
q0,q1,q2: inout STD_LOGIC;
q0b,q1b,q2b: inout STD_LOGIC);
end up_down_counter;

architecture Behavioral of up_down_counter is

signal q0x,q0bx,q1x,q1bx,downx,s0x,s1x,s2x,s3x,s4x,s5x:STD_LOGIC:='0';
---------------------------------
component not_gate is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC);
end component;
---------------------------------
component or_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end component;
---------------------------------
component JK_FF is
Port ( clk,rst,j,k : in STD_LOGIC;
q,qbar : out STD_LOGIC);
end component;
---------------------------------
component and_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end component;
---------------------------------
begin
L1: JK_FF port map(clk,'0','1','1',q0,q0b );
q0x<=q0;q0bx<=q0b;
L2: not_gate port map(sel_up_dn,downx);
L3: and_gate port map(sel_up_dn,q0x,s0x);
L4: and_gate port map(downx,q0bx,s1x);
L5: or_gate port map(s0x,s1x,s2x);
L6: JK_FF port map(clk,'0',s2x,s2x,q1,q1b );
q1x<=q1;q1bx<=q1b;
L7: and_gate port map(q1x,s0x,s3x);
L8: and_gate port map(q1bx,s1x,s4x);
L9: or_gate port map(s3x,s4x,s5x);
L10: JK_FF port map(clk,'0',s5x,s5x,q2,q2b );

end Behavioral;
//----------------------------------------------------------------------------------//
//----------------------------------------------------------------------------------//
NOTE: Our Spartan3 FPGA kit has clk frequency of 50 MHz. To verify our MOD8-UP-DOWN-
COUNTER we have to integrate the clk down circuit of 1 Mz.
//----------------------------------------------------------------------------------//

MOD8-UP-DOWN-COUNTER -VHDL CODE MODIFIED:

//----------------------------------------------------------------------------------//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity up_down_counter_with_clk_down is
Port ( sel_up_dn,clk : in STD_LOGIC;
q0,q1,q2: inout STD_LOGIC;
q0b,q1b,q2b: inout STD_LOGIC);
end up_down_counter_with_clk_down;

architecture Behavioral of up_down_counter_with_clk_down is

signal q0x,q0bx,q1x,q1bx,downx,s0x,s1x,s2x,s3x,s4x,s5x,clk_div:STD_LOGIC:='0';

---------------------------------
component not_gate is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC);
end component;
---------------------------------
component or_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end component;
---------------------------------
component JK_FF is
Port ( clk,rst,j,k : in STD_LOGIC;
q,qbar : out STD_LOGIC);
end component;
---------------------------------
component and_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end component;
---------------------------------
component clk_div_with_50per_duty_cycle is
Port ( clk,rst : in STD_LOGIC;
clk_div : out STD_LOGIC);
end component;
---------------------------------
begin
L0:clk_div_with_50per_duty_cycle port map(clk,clk_div);
L1: JK_FF port map(clk_div,'0','1','1',q0,q0b );
q0x<=q0;q0bx<=q0b;
L2: not_gate port map(sel_up_dn,downx);
L3: and_gate port map(sel_up_dn,q0x,s0x);
L4: and_gate port map(downx,q0bx,s1x);
L5: or_gate port map(s0x,s1x,s2x);
L6: JK_FF port map(clk,'0',s2x,s2x,q1,q1b );
q1x<=q1;q1bx<=q1b;
L7: and_gate port map(q1x,s0x,s3x);
L8: and_gate port map(q1bx,s1x,s4x);
L9: or_gate port map(s3x,s4x,s5x);
L10: JK_FF port map(clk,'0',s5x,s5x,q2,q2b );

end Behavioral;

//----------------------------------------------------------------------------------//
//-----------------------------------Synthesis Report---------------------------//
Partition Report: No Partitions were found in this design.
//----------------------------------------------------------------------------------//
Design Statistics:

//----------------------------------------------------------------------------------//
Minimum period: 14.330ns (Maximum Frequency: 69.785MHz)
Minimum input arrival time before clock: 3.721ns
Maximum output required time after clock: 6.388ns
Maximum combinational path delay: No path found
//----------------------------------------------------------------------------------//
Implementation User constrain file using Spartan-3 FPGA kit
//----------------------------------------------------------------------------------//
INPUT = "clk" LOC = "T9; INPUT = "sel" LOC = "G12”
OUTPUT = "q0" LOC = "k12";OUTPUT = "q1" LOC = "p14";
OUTPUT = "q2" LOC = "l12";
//----------------------------------------------------------------------------------//
Truth table verification:

Truth table of MOD8-UP-DOWN- Corresponding I/O mapping to LOC

COUNTER
sel q2 q1 q0 G12 L12 P14 K12
1 0 0 0 on off off off
1 0 0 1 on off off on
1 0 1 0 on on on off
1 0 1 1 on on on on
1 1 0 0 on off off off
1 1 0 1 on off off on
1 1 1 0 on on on off
1 1 1 1 on on on on
0 0 0 0 off off off off
0 1 1 1 off on on on
0 1 1 0 off on on off
0 1 0 1 off on off on
0 1 0 0 off on off off
0 0 1 1 off off on on
0 0 1 0 off off on off
0 0 0 1 off off off on

Note:Off -> 0 STD_LOGIC, On -> 1 STD_LOGIC.

Input port are mapped with switch and output port are mapped with LED of Spartan 3 FPGA kit.
Conclusion: The Experimental result exactily matches with the Truth Tables of “MOD8-UP-DOWN-
COUNTER”.