-------------------------------------------------------------------------------- File : decoder24.

vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo

gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.librar
y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log
ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc
h\
-------------------------------------------------------------------------------- File : decoder24.vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo
gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.librar
y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log
ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc
h
-------------------------------------------------------------------------------- File : decoder24.vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo
gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.librar
y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log
ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc
h
-------------------------------------------------------------------------------- File : decoder24.vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo
gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER---------------------------------------------------------------

------------------The IEEE standard 1164 package, declares std_logic, etc.librar

y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log
ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc
h
-------------------------------------------------------------------------------- File : decoder24.vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo
gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.librar
y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log
ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc
h
-------------------------------------------------------------------------------- File : decoder24.vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo
gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.librar
y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log
ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc
h
-------------------------------------------------------------------------------- File : decoder24.vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo
gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.librar
y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log
ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc

h
-------------------------------------------------------------------------------- File : decoder24.vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo
gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.librar
y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log
ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc
h
-------------------------------------------------------------------------------- File : decoder24.vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo
gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.librar
y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log
ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc
h
-------------------------------------------------------------------------------- File : decoder24.vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo
gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.librar
y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log
ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc
h
-------------------------------------------------------------------------------- File : decoder24.vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo
gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.librar

y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log

ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc
h
-------------------------------------------------------------------------------- File : decoder24.vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo
gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.librar
y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log
ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc
h
-------------------------------------------------------------------------------- File : decoder24.vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo
gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.librar
y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log
ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc
h
-------------------------------------------------------------------------------- File : decoder24.vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo
gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.librar
y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log
ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc
h

-------------------------------------------------------------------------------- File : decoder24.vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo

gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.librar
y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log
ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc
h
-------------------------------------------------------------------------------- File : decoder24.vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo
gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.librar
y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log
ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc
h
-------------------------------------------------------------------------------- File : decoder24.vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo
gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.librar
y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log
ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc
h
-------------------------------------------------------------------------------- File : decoder24.vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo
gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.librar
y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log

ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc
h
-------------------------------------------------------------------------------- File : decoder24.vhd-- Entity : decoder24-------------------------------------------------------------------------------- University : Vishweswaraia Technolo
gical UniversityBelgaum,Karnataka-- Simulators : Mentor Graphics Modelsim Or Act
ive HDL-- Synthesizers : Xilinx ISE-- Target Device : XC4000 Series-------------------------------------------------------------------------------- Description
: 2 to 4 DECODER--------------------------------------------------------------------------------The IEEE standard 1164 package, declares std_logic, etc.librar
y IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_log
ic_unsigned.all;---------------------------------- Entity Declarations ------------------------entity decoder24 isgeneric(N: INTEGER :=2;M: INTEGER :=4 );port
(EN : in STD_LOGIC;SEL: in STD_LOGIC_VECTOR (N-1 downto 0);D: out STD_LOGIC_VECT
OR (M-1 downto 0) );end decoder24;architecture decoder24_arch of decoder24 issig
nal aux: INTEGER;beginaux<=conv_integer(SEL);process(EN,aux)beginif (EN='1') the
nfor i in 0 to M-1 loopif aux=i thenD(i)<='1' ;elseD(i)<='0' ;end if;end loop;el
sefor i in 0 to M-1 loopD(i)<='0' ;end loop;end if;end process;end decoder24_arc
h