VHDL 101: Everything you Need to Know to Get Started

Table of Contents

Cover Image

Front Matter

Copyright

Preface

About the Author

Acknowledgments

Chapter 1. Introduction and Background

1.1. VHDL

1.2. Brief History of VHDL

1.3. FPGA Architecture

Chapter 2. Overview of the Process of Implementing an FPGA Design

2.1. Design Entry

2.2. Synthesis

2.3. Simulation

2.4. Implementation

2.5. Bitstream Generation

Chapter 3. Loop 1 – Going with the Flow

3.1. The Shape of VHDL

Chapter 4. Loop 2 – Going Deeper

4.1. Introducing Processes, Variables, and Sequential Statements

4.2. Tool Perspectives – Synthesis Options and Constraints

Chapter 5. Loop 3

5.1. Introducing Concept of Reuse

5.2. Flexibility Using Generics and Constants

5.3. Generate Statements

5.4. Functions and Procedures

5.5. Attributes

5.6. Packages

5.7. Commonly Used Libraries

Appendix. A Quick Reference

Index

Front Matter

VHDL 101

Everything you need to know to get started

William Kafig

AMSTERDAM • BOSTON • HEIDELBERG • LONDON • NEW YORK OXFORD • PARIS • SAN DIEGO • SAN FRANCISCO SINGAPORE • SYDNEY • TOKYO

Newnes is an imprint of Elsevier

Copyright © 2011 Elsevier Inc.. All rights reserved.

Copyright

Newnes is an imprint of Elsevier

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First edition 2011

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A catalogue record for this book is available from the British Library

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A catalog record for this book is available from the Library of Congress

ISBN: 978-1-85617-704-7

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Preface

VHDL, as with so many other languages, is difficult to teach as each part of the language requires the understanding of some other part of the language to make sense. This makes the traditional linear approach very difficult as it requires the reader to read the book from start to finish in order to have a sufficient grasp of the language to become useful. This book is experimenting with a different approach – it covers various aspects of the material multiple times! Each loop builds upon the previous and introduces new material along with practical application.

The introduction provides a context to the reader into the overall architecture of a generic FPGA and the big picture of how code becomes a working design. The reader then enters the first loop which introduces the reader to the shape and flavor of VHDL – rudimentary structures, signals, and a number of things that can be done to a signal in the concurrent (simultaneous) realm. A lab (worked out design that the user can run on his/her own) is provided to show the reader how to play along with the book and practice using the various constructs. Specific tools or tool versions are not referenced here as the tools tend to change appearance quite often and explicit instructions may serve only to confuse the reader. A website is provided with the source code and other documents to assist the student in building the reference design used throughout this book.

The second iteration builds upon the understanding gained of simple concurrent statements and delves into one of the most commonly used control structures – the process.

The third and final loop of this book emphasizes code reuse through a construct known as a package. The powerful generic and generate statements as well as functions and procedures are demonstrated to give the reader the tools to create dynamic, flexible packages for future use to expedite custom designs. Salient points from the second iteration are driven home so that the reader is fully confident with the material. The final lab leaves the reader with a custom package for future designs.

Within the industry there is a small number of FPGA manufacturers – Xilinx, Altera, Lattice, SiliconBlue, and a few others. As I have first-hand experience designing with the two major manufacturers, Xilinx and Altera, I've seen the good, the bad, and the ugly with both vendors. That said, my strong preference is Xilinx, which conveniently is also the industry leader, so, even though VHDL is vendor agnostic, we have to pick one FPGA vendor as I have neither the time, nor inclination to write the labs to support every synthesis, simulation, and implementation tool currently available.

Xilinx offers a set of free tools (with no time-out or degradation in capabilities), which includes a decent text editor, synthesis engine, and simulator, as well as the implementation tools. This is not a watered down, limited capability, but rather the full-featured tool set. The basic difference between the WebPack (free) and the full price tools is that the full price tools support every current Xilinx device and the WebPack only supports the more commonly selected devices (which is still quite a number of FPGAs and CPLDs!). The other limitation is that the simulation tool (ISIM) limits the total number of lines that can be simulated. We're not getting anywhere near this limit for the labs presented in this book. Please download the latest WebPack for the labs, from www.xilinx.com.

Other things you should know…

This book targets Electrical Engineers wishing to break into FPGA design. It is assumed that the readers have a basic knowledge of digital design and at least a year's experience with the engineering process, that is, the flow of engineering that takes an idea and turns it into reality.

Why is this book written this way?

1) Many readers have neither the time, nor desire to read through an academic stylebook. Often the readers are faced with an immediate need to use or understand VHDL. To meet this perceived need, the book is organized into three sections and an introduction – understanding the FPGA development process with a light introduction to VHDL; commands and data management which covers many of the VHDL language constructs, intrinsic data types, and some of the commonly used IEEE standard data types. This final section focuses on design reuse.

2) This book dovetails with FPGA 101: Getting Started which is a User Guide on how to successfully develop an FPGA design. FPGA 101: Getting Started focuses on the process and Xilinx tools, but not on any specific language. VHDL 101: Getting Started elaborates on the language concepts introduced in its sister book.

3) A number of small designs are presented in this book, which serves as the beginning of a cookbook of techniques and functions which may be commonly used in many designs. Each design is fully commented and includes a thorough explanation of why certain coding practices were selected.

4) A quick reference guide to both the VHDL language (those items covered in the book) and the common IEEE libraries is provided and cross-referenced to the text of the book.

5) A light, conversational tone is used throughout this book to improve reader comprehension and not to come off as dry as the Mojave in August.

Some familiarity with programming languages is a plus, because, even though this is a book about hardware in an FPGA, how we describe the circuit to the FPGA looks and tastes a lot like programming a microprocessor.

Although simulation is covered in this book, it only scratches the surface. Many simulation concepts, such as self-checking test benches, TEXTIO, and others, are deferred to both existing and future texts and are outside the scope of beginner.

The bulk of the commonly used VHDL concepts and structures will be covered with enough detail to enable the beginning FPGA designer to accomplish his task, there are; however, certain structures, such as the configuration statement that will also be deferred to a more advanced book.

About the Author

Mr. Kafig escaped from the University of Maryland with a BSEE in 1986 and has been in hiding ever since. Believing that the statute of limitations has been reached, he is climbing out from under his rock where he has been practicing electrical engineering for the last 24 years. During his incarceration in college and immediately afterward, he had the opportunity to work for the Department of the Army at the Harry Diamond Laboratories (now the US Army Research Laboratory) for 16 years working on everything from security systems, to airborne radar systems, to cover tracking technologies, to stuff that really can't be talked about – and of course lots of programmable logic and microprocessors! Concerned that that much government service would leave irreparable psychic scarring, Mr. Kafig moved into the private sector building railway electronics and experiencing design in real world. Eventually an opening became available as a Field Applications Engineer where he, once again, became infatuated with Xilinx FPGAs.

Family issues brought him to, under the cover of darkness, St. Louis where he consulted on a number of projects from High-Performance Graphics Hardware Compositors, to a Team Leader for a phase-array antenna prototype, to traveling North America teaching the joys of Xilinx Programmable Logic.

Currently Mr. Kafig is employed by Xilinx as a Curriculum Developer, and, since Xilinx prefers him to build FPGAs course content rather than write books, he has taken it upon himself to write this minor tome.

Acknowledgments

My parents – who provided the safe, supportive environment for me to cause my mischief without blowing up too much. And let's not forget that TRS-80 got me started programming! Oh, and I'm sorry about all those partially reassembled things I took apart decades ago. I'll put them back together real soon – promise!

John Speulstra – you earned my sincere appreciation when, those many years ago, you took a young man into the lab and showed him the value of real hands-on training in the tradition of a true mentor – the skills you taught me on the bench have made me a far better engineer and saved the lives of countless pieces of test equipment. Your teaching style and skills have been passed on to many a novice engineer over the years. Whenever I mentor a junior engineer or create educational material – you are there.

Chapter 1. Introduction and Background

1.1. VHDL

VHDL. Four little letters. So much to understand.

There are many approaches to learning the Very-High-Speed Integrated Circuit Hardware Description Language (VHDL). These range from the academic – where each piece is looked at, turned upside down and inside out, and fully understood at an atomic level, yet only a few understand how to actually USE the language to implement a design; to OJT¹ where an engineer may be handed either poorly written code (or in rare cases a well written piece of code), or nothing at all and told that they are now responsible for the Field Programmable Gate Array (FPGA) in the system.

¹On-The-Job-Training, most often this is a sink-or-swim scenario. Without a framework, engineers who learn in this style often code inefficiently.

Somewhere in between lays a happy medium – a way to learn VHDL and be productive as quickly as possible.

I have a strong background in the Japanese Martial Art of Aikido. Like so many Martial Arts there are beginning techniques, intermediate techniques, and advanced techniques, yet all of them are built on certain fundamental ideas of movement. It would be a disservice to a student to spend hundreds of hours on wrist techniques alone without covering falling techniques (one way to avoid harm), or posture, or any number of other important aspects of the Art.

We start out simply, get a rough idea of what we're in for – sort of a sampling of the various aspects, but none in any great detail.

Now that the student has an idea of what he's in for, he² has a better idea of what lies ahead so that the next iteration of falling, arm techniques, wrist techniques, knee work, etc., there is a context in which to place the learning. In this fashion, an upward spiral of success is achieved.

²I use he instead of the awkward he/she or the more encompassing he/she/he–she/she–he/it. This is not out of sexism, but out of long tradition, in virtually every language, of using the third person masculine for when the gender of the reader is unknown (as opposed to indeterminate).

I'd like to take you on this same path in VHDL. We'll start out by traversing the general process of developing an FPGA. ³ During this process you will encounter forward references, that is, references to aspects of VHDL that we haven't covered yet. Currently, there is no known way to avoid this problem except through a highly academic, atomic view of the language, with no references or context relative to other aspects or commands of the language. This is exactly what we are attempting to AVOID. When you see a new construct, there will be a brief conceptual description of what it does and the details will be provided later.

³Although the focus of this book is VHDL, I believe that a brief overview of the entire flow helps create a context in which to place this learning.

Once we've made our first loop through the material, we'll revisit the initial concepts and statement and begin adding to it and exploring the capabilities of the language. We'll also begin looking at some of the synthesis tool's capabilities and how to verify that the code is behaving properly prior to testing it in silicon (i.e. simulation).

The focus of this book is on VHDL which is one of the primary FPGA languages, but who wants to work in a vacuum? References to various tools and other languages are made to help the reader better understand the landscape into which he is entering. The Xilinx tools will only be covered to the extent that they are required to produce a viable netlist and for simulation. Other books, websites and classes from the FPGA vendors delve into great detail as to how the various tools can be effectively applied.

This book is, by no means, the end-all, be-all reference for VHDL. The intention is to convey the basic principles of VHDL with a smattering of FPGA techniques so that the VHDL has relevance and so that you can get started coding quickly. In that vein neither every aspect of VHDL is covered, nor are the covered aspects detailed to the nth degree – but they are covered enough to get you coding for FPGAs very quickly.

There are a number of very good, extremely detailed books out there – look for anything written by Peter Ashenden.

1.2. Brief History of VHDL

Way back, in the BEFORE TIME, say around 1981, the US Department of Defense began writing the specifications for the Very-High-Speed Integrated Circuit (VHSIC) program. The intent was to be able to accurately and thoroughly describe the behavior of circuits for documentation, simulation, and (later) synthesis purposes. This initiative was known as VHDL. July of 1983 saw Intermetics, IBM, and Texas Instruments begin developing the first version of VHDL, which was finally released in August of 1985.

Just to flesh out the timeline, Xilinx invented the first FPGA in 1984, began shipping parts in 1985, and was supporting VHDL shortly thereafter using a third-party synthesis tool.

Due to the popularity of the language, the Institute of Electrical and Electronics Engineers (IEEE) convened a committee to formalize the language. This task was completed in 1987 and the standard became known as IEEE 1076-1987. This standard has been revisited a number of times (1993 and 2000) since then, and the current standard IEEE 1076-2008 is known informally as VHDL-2008. As this latest standard has not yet been ratified (at the time of writing), we will use the IEEE 1076-2000 standard which tends to be a superset of previous versions.

VHDL is a large, complex, and powerful language. Although the language is feature-rich, many designs only require a small subset of the total capabilities.

As a Department of Defense (DoD) project where, quite literally, lives were at stake, no aspect of VHDL would be assumed and it was deigned to be a strongly typed language, sharing many concepts and features with the programming language Ada.

VHDL gained very rapid acceptance (as it was mandated by DoD of their agencies and contractors), initially on the East Coast. This is in contrast to Verilog, another FPGA programming language, which began its life as a programming language for Application Specific Integrated Circuits (ASICs) and is particularly strong on the West Coast.

VHDL's history still weighs on the current implementation, most notably in the process sensitivity list used for simulation. At the time that VHDL was developed, the then brand new PC class machines were running at 5 MHz and 640 KB of memory. Processor cycles were very expensive! So, in order not to waste processor time, the process sensitivity list was examined to see if key signals had changed since the last iteration. If so, the block of code was executed, otherwise it was skipped. This is one of the places where some problems of today can occur as the synthesis tools ignore the process sensitivity list and we encounter an error known as simulation mismatch.

1.2.1. Coding Styles: Structural vs. Behavioral vs. RTL

You may hear several adjectives used with VHDL – Structural VHDL, Behavioral VHDL, RTL coding, etc. These are not separate languages, but rather different approaches to coding. These methods are not mutually exclusive, but may be mixed freely within a project or even a single module.

Structural VHDL or structural coding is a very low-level style of coding. This practice involves instantiating, or calling out explicitly, specific instances of primitives or previously defined modules